Datasheet PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H Datasheet

PIC32MX3XX/4XX Family

Data Sheet

64/100-Pin General Purpose and USB

32-Bit Flash Microcontrollers

© 2009 Microchip Technology Inc. Preliminary DS61143F

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
Omniscient Code Generation, PICC, PICC-18, PICkit,
PICDEM, PICDEM.net, PICtail, PIC

32

logo, REAL ICE, rfLAB,
Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS61143F-page ii Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller

64/100-Pin General Purpose and USB

High-Performance 32-bit RISC CPU:

•MIPS32® M4K™ 32-bit Core with 5-Stage Pipeline

• 80 MHz Maximum Frequency

• 1.56 DMIPS/MHz (Dhrystone 2.1) Performance
at 0 Wait State Flash Access

• Single-Cycle Multiply and High-Performance
Divide Unit

• MIPS16e™ Mode for Up to 40% Smaller Code
Size

• Two Sets of 32 Core Register Files (32-bit) to
Reduce Interrupt Latency

• Prefetch Cache Module to Speed Execution from
Flash

Microcontroller Features:

• Operating Voltage Range of 2.3V to 3.6V

• 32K to 512K Flash Memory (plus an additional
12KB of Boot Flash)

• 8K to 32K SRAM Memory

• Pin-Compatible with Most PIC24/dsPIC

• Multiple Power Management Modes

• Multiple Interrupt Vectors with Individually
Programmable Priority

• Fail-Safe Clock Monitor Mode

• Configurable Watchdog Timer with On-Chip
Low-Power RC Oscillator for Reliable Operation

®

Devices

Peripheral Features:

• Atomic SET, CLEAR and INVERT Operation on
Select Peripheral Registers

• Up to 4-Channel Hardware DMA with Automatic
Data Size Detection

• USB 2.0 Compliant Full Speed Device and
On-The-Go (OTG) Controller

• USB has a Dedicated DMA Channel

• 10 MHz to 40 MHz Crystal Oscillator

• Internal 8 MHz and 32 kHz Oscillators

• Separate PLLs for CPU and USB Clocks

•Two I

• Two UART Modules with:

• Parallel Master and Slave Port (PMP/PSP) with

• Hardware Real-Time Clock/Calendar (RTCC)

• Five 16-bit Timers/Counters (two 16-bit pairs com-

• Five Capture Inputs

• Five Compare/PWM Outputs

• Five External Interrupt Pins

• High-Speed I/O Pins Capable of Toggling at Up to

• High-Current Sink/Source (18 mA/18 mA) on

• Configurable Open-Drain Output on Digital I/O

2

C™ Modules

- RS-232, RS-485 and LIN 1.2 support

-IrDA

8-bit and 16-bit Data and Up to 16 Address Lines

bine to create two 32-bit timers)

80 MHz

All I/O Pins

Pins

®

with On-Chip Hardware Encoder and

Decoder

Debug Features:

• Two Programming and Debugging Interfaces:

- 2-Wire Interface with Unintrusive Access and
Real-time Data Exchange with Application

- 4-wire MIPS
interface

• Unintrusive Hardware-Based Instruction Trace

• IEEE Std 1149.2 Compatible (JTAG) Boundary
Scan

®

Standard Enhanced JTAG

Analog Features:

• Up to 16-Channel 10-bit Analog-to-Digital
Converter:

- 1000 ksps Conversion Rate

- Conversion Available During Sleep, Idle

• Two Analog Comparators

• 5V Tolerant Input Pins (digital pins only)

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 1

PIC32MX3XX/4XX

TABLE 1: PIC32MX GENERAL PURPOSE – FEATURES

GENERAL PURPOSE

2

C™

(2)

Device

PIC32MX320F032H 64 40 32 + 12

PIC32MX320F064H 64 80 64 + 12

PIC32MX320F128H 64 80 128 + 12

PIC32MX340F128H 64 80 128 + 12

PIC32MX340F256H 64 80 256 + 12

PIC32MX340F512H 64 80 512 + 12

PIC32MX320F128L 100 80 128 + 12

PIC32MX340F128L 100 80 128 + 12

PIC32MX360F256L 100 80 256 + 12

PIC32MX360F512L 100 80 512 + 12

Pins

MHz

Trace

VREG

Channels

Program Memory (KB)

Data Memory (KB)

(1)

8 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PT, MR

(1)

16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PT, MR

(1)

16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PT, MR

(1)

32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes PT, MR

(1)

32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes PT, MR

(1)

32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes PT, MR

(1)

16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PT

(1)

32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes PT

(1)

32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes PT

(1)

32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes PT

Programmable DMA

Timers/Capture/Compare

EUART/SPI/I

Legend: PT = TQFP MR = QFN

Note 1: This device features 12 KB Boot Flash memory.

2: See Legend for an explanation of the acronyms. See Section 29.0 “Packaging Information” for details.

TABLE 2: PIC32MX USB – FEATURES

USB

JTAG

PMP/PSP

Comparators

10-bit A/D (ch)

Packages

C™

Device

Pins

MHz

Program Memory (KB)

PIC32MX420F032H 64 80 32 + 12

PIC32MX440F128H

PIC32MX440F256H

PIC32MX440F512H

64 80 128 + 12

64 80 256 + 12

64 80 512 + 12

PIC32MX440F128L 100 80 128 + 12

PIC32MX460F256L 100 80 256 + 12

PIC32MX460F512L 100 80 512 + 12

2

Trace

Data Memory (KB)

Channels

Programmable DMA

VREG

Channels

Dedicated USB DMA

EUART/SPI/I

10-bit A/D (ch)

Comparators

PMP/PSP

Timers/Capture/Compare

(1)

8 5/5/5 0 2 Yes No 2/1/2 16 2 Yes Yes PT, MR

(1)

32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes

(1)

32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes

(1)

32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes

(1)

32 5/5/5 4 2 Yes No 2/2/2 16 2 Yes Yes PT

(1)

32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes PT

(1)

32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes PT

(2)

JTAG

Packages

PT, MR

PT, MR

PT, MR

Legend: PT = TQFP MR = QFN

Note 1: This device features 12 KB Boot Flash memory.

2: See Legend for an explanation of the acronyms. See Section 29.0 “Packaging Information” for details.

DS61143F-page 2 Preliminary © 2009 Microchip Technology Inc.

PIN DIAGRAM: 64-PIN QFN – GENERAL PURPOSE

64-Pin QFN (General Purpose)

64 63 62 61 60 59 58 57 56 55

22 23 24 25 26 27 28 29 30 31

3

40
39
38
37
36
35
34
33

4
5

7
8
9
10
11

1
2

42
41

6

32

43

54

14
15
16

12
13

17

18 1920 21

45
44

47
46

48

53

52 51 50 49

PIC32MX3XXH

= Pins are up to 5V tolerant

Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to

V

SS externally.

CN15/RD6

PMRD/CN14/RD5

PMWR/OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

V

CAP/VDDCORE

PMD0/RE0

RF1

CN16/RD7

ENVREG

PMD5/RE5
PMD6/RE6
PMD7/RE7

PMA5/SCK2/CN8/RG6

V

DD

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1

/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGEC1/AN1/V

REF-/CVREF-/CN3/RB1

PGED1/PMA6/AN0/V

REF+/CVREF+/CN2/RB0

PMA2/SS2

/CN11/RG9

MCLR

VSS

SOSCI/CN1/RC13
OC1/RD0

IC3/PMCS2/PMA15/INT3/RD10
IC2/U1CTS

/INT2/RD9

IC1/RTCC/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15
OSC1/CLKI/RC12
V

DD

SCL1/RG2

U1RTS

/BCLK1/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3

SDA1/RG3

SOSCO/T1CK/CN0/RC14

Vss

AVDD

U2CTS/C1OUT/AN8/RB8

PMA7/C2OUT/AN9/RB9

TMS/CV

REFOUT/PMA13/AN10/RB10

TDO/PMA12/AN11/RB11

V

DD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

PMA8/U2TX/SCL2/CN18/RF5

PMA9/U2RX/SDA2/CN17/RF4

TCK/PMA11/AN12/RB12

TDI/PMA10/AN13/RB13

PMALH/PMA1/U2RTS

/BCLK2/AN14/RB14

PMALL/PMA0/AN15/OCFB/CN12/RB15

V

SS

AVSS

PIC32MX3XX/4XX

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 3

PIC32MX3XX/4XX

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

2244242526272829303132

PIC32MX3XXH

1

46

45

23

43

42

41

40

39

CN15/RD6

PMRD/CN14/RD5

PMWR/OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

V

CAP/VDDCORE

SOSCI/CN1/RC13

OC1/RD0

IC3/PMCS2/PMA15/INT3/RD10

IC2/U1CTS

/INT2/RD9

IC1/RTCC/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

V

DD

SCL1/RG2

U1RTS

/BCLK1/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

SDA1/RG3

SOSCO/T1CK/CN0/RC14

AVDD

U2CTS/C1OUT/AN8/RB8

PMA7/C2OUT/AN9/RB9

TMS/CV

REFOUT/PMA13/AN10/RB10

TDO/PMA12/AN11/RB11

V

DD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

PMA8/U2TX/SCL2/CN18/RF5

PMA9/U2RX/SDA2/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

PMA5/SCK2/CN8/RG6

V

DD

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1

/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGEC1/AN1/VREF-/CVREF-/CN3/RB1

PGED1/PMA6/AN0/VREF+/CVREF+/CN2/RB0

PMA2/SS2

/CN11/RG9

MCLR

TCK/PMA11/AN12/RB12

TDI/PMA10/AN13/RB13

PMALH/PMA1/U2RTS

/BCLK2/AN14/RB14

PMALL/PMA0/AN15/OCFB/CN12/RB15

PMD0/RE0

RF1

CN16/RD7

VSS

VSS

Vss

ENVREG

636261596058575654555352514950

38

37

34

36

35

33

17

192021

18

AV

SS

64

64-Pin TQFP (General Purpose)

= Pins are up to 5V tolerant

PIN DIAGRAM: 64-PIN TQFP – GENERAL PURPOSE

DS61143F-page 4 Preliminary © 2009 Microchip Technology Inc.

PIN DIAGRAM: 100-PIN TQFP – GENERAL PURPOSE

9294939190898887868584838281807978

20

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

65
64
63
62
61
60
59

56

45

44

43

42

41

40

39

2829303132333435363738

17
18
19

21

22

95

1

76

77

72
71
70
69
68
67
66

75
74
73

58
57

24

23

25

969897

99

27

464748

49

55
54
53
52
51

100

PMRD/CN14/RD5

PMWR/OC5/CN13/RD4

PMD13/CN19/RD13

PMD12/IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

PMD11/RF0

SOSCI/CN1/RC13
OC1/RD0

IC3/PMCS2/PMA15/RD10
IC2/RD9
IC1/RTCC/RD8

IC4/PMCS1/PMA14/RD11

INT4/RA15
INT3/RA14

OSC2/CLKO/RC15
OSC1/CLKI/RC12
V

DD

SCL1/RG2

SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8

SDA1/RG3

U1RX/RF2
U1TX/RF3

V

SS

SOSCO/T1CK/CN0/RC14

PMA6/VREF+/CVREF+/RA10

PMA7/V

REF-/CVREF-/RA9

AV

DD

AVSS

C1OUT/AN8/RB8

C2OUT/AN9/RB9

CV

REFOUT/PMA13/AN10/RB10

PMA12/AN11/RB11

V

DD

U2CTS/RF12

U2RTS

/BCLK2/RF13

CN20/U1CTS

/RD14

U1RTS

/BCLK1/CN21/RD15

V

DD

VSS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

PMA8/U2TX/CN18/RF5

PMA9/U2RX/CN17/RF4

PMD5/RE5
PMD6/RE6
PMD7/RE7

T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4

PMA5/SCK2/CN8/RG6

V

DD

TMS/RA0
INT1/RE8
INT2/RE9

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1

/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0

V

DD

RG15

PMA2/SS2

/CN11/RG9

MCLR

PMA11/AN12/RB12

PMA10/AN13/RB13

PMALH/PMA1/AN14/RB14

PMALL/PMA0/AN15/OCFB/CN12/RB15

PMD9/RG1

PMD10/RF1

ENVREG

PMD14/CN15/RD6

TDO/RA5

SDA2/RA3
SCL2/RA2

V

SS

VSS

VSS

VCAP/VDDCORE

TDI/RA4

TCK/RA1

100-Pin TQFP (General Purpose)

50

26

PMD15/CN16/RD7

PIC32MX3XXL

= Pins are up to 5V tolerant

PIC32MX3XX/4XX

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 5

PIC32MX3XX/4XX

64-Pin QFN (USB)

= Pins are up to 5V tolerant

Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to

V

SS externally.

PIC32MX4XXH

PMD5/RE5

PMD6/RE6
PMD7/RE7

PMA5/SCK2/CN8/RG6

V

DD

VBUSON/C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/ RB4

C2IN+/AN3/CN5/ RB3

C2IN-/AN2/CN4/ RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/EMUD1/PMA6/AN0/V

REF

+/CV

REF

+/CN2/RB0

PMA2/SS2/CN11/RG9

MCLR

V

SS

64 63 62 61 6059 58 57 56 55

22 23 24 25 26 27 28 29 30 31

3

40
39
38
37
36
35
34
33

4
5

7
8

9
10
11

1

2

42
41

6

32

43

54

14
15
16

12
13

17

18 19 20 21

45
44

47
46

48

53

52 51 50 49

AV

DD

U2CTS/C1OUT/AN8/RB8

PMA7/C2OUT/AN9/RB9

TMS/CV

REFOUT

/PMA13/AN10/RB10

TDO/PMA12/AN11/RB11

V

DD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

PMA8/U2TX/SCL2/ CN18/RF5

PMA9/U2RX/SDA2/CN17/RF4

TCK/PMA11/AN12/RB12

TDI/PMA10/AN13/RB13

PMALH/PMA1/U2RTS

/BCLK2/AN14/RB14

PMALL/PMA0/AN15/ OCFB/CN12/RB15

V

SS

AV

SS

CN15/RD6

PMRD/CN14/RD5

PMWR/OC5/IC5/CN13/RD4

OC4/U1TX/RD3

OC3/U1RX/RD2

OC2/U1RTS

/BCLK1/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

V

CAP

/V

DDCORE

PMD0/RE0

RF1

CN16/RD7

ENVREG

SOSCI/CN1/RC13

OC1/INT0/RD0

IC3/PMCS2/PMA15/INT3/SCL1/RD10

IC2/U1CTS

//INT2/SDA1/RD9

IC1/RTCC/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

V

DD

D+/RG2

VUSB

VBUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIN DIAGRAM: 64-PIN QFN – USB

DS61143F-page 6 Preliminary © 2009 Microchip Technology Inc.

PIN DIAGRAM: 64-PIN TQFP – USB

64-Pin TQFP (USB)

CN15/RD6

PMRD/CN14/RD5

PMWR/OC5/IC5/CN13/RD4

OC4/U1TX/RD3

OC3/U1RX/RD2

OC2/U1RTS

/BCLK1/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

V

CAP/VDDCORE

SOSCI/CN1/RC13

OC1/INT0/RD0

IC3/PMCS2/PMA15/INT3/SCL1/RD10

IC2/U1CTS

//INT2/SDA1/RD9

IC1/RTCC/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

V

DD

D+/RG2

VUSB

VBUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

AVDD

U2CTS/C1OUT/AN8/RB8

PMA7/C2OUT/AN9/RB9

TMS/CV

REFOUT/PMA13/AN10/RB10

TDO/PMA12/AN11/RB11

V

DD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

PMA8/U2TX/SCL2/CN18/RF5

PMA9/U2RX/SDA2/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

PMA5/SCK2/CN8/RG6

V

DD

VBUSON/C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/EMUD1/PMA6/AN0/V

REF

+/CV

REF

+/CN2/RB0

PMA2/SS2

/CN11/RG9

MCLR

TCK/PMA11/AN12/RB12

TDI/PMA10/AN13/RB13

PMALH/PMA1/U2RTS

/BCLK2/AN14/RB14

PMALL/PMA0/AN15/OCFB/CN12/RB15

PMD0/RE0

RF1

CN16/RD7

V

SS

VSS

Vss

ENVREG

AV

SS

= Pins are up to 5V tolerant

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

2244242526272829303132

PIC32MX4XXH

1

46

45

23

43

42

41

40

39

636261596058575654555352514950

38

37

34

36

35

33

17

192021

18

64

PIC32MX3XX/4XX

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 7

PIC32MX3XX/4XX

PMRD/CN14/RD5

PMWR/OC5/CN13/RD4

PMD13/CN19/RD13

PMD12/IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

PMD11/RF0

SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0

IC3/SCK1/PMCS2/PMA15/RD10
IC2/SS1

/RD9

IC1/RTCC/RD8

IC4/PMCS1/PMA14/RD11

SDA1/INT4/RA15
SCL1/INT3/RA14

OSC2/CLKO/RC15
OSC1/CLKI/RC12
V

DD

D+/RG2

VUSB
VBUS
U1TX/RF8

D-/RG3

U1RX/RF2
USBID/RF3

V

SS

SOSCO/T1CK/CN0/RC14

PMA6/VREF+/CVREF+/RA10

PMA7/V

REF-/CVREF-/RA9

AV

DD

AVSS

C1OUT/AN8/RB8

C2OUT/AN9/RB9

CV

REFOUT/PMA13/AN10/RB10

PMA12/AN11/RB11

V

DD

U2CTS/RF12

U2RTS

/BCLK2/RF13

CN20/U1CTS

/RD14

U1RTS

/BCLK1/CN21/RD15

V

DD

VSS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

PMA8/U2TX/CN18/RF5

PMA9/U2RX/CN17/RF4

PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3

SDI1/T5CK/RC4

PMA5/SCK2/CN8/RG6

V

DD

TMS/RA0
INT1/RE8
INT2/RE9

VBUSON/C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0

V

DD

RG15

PMA2/SS2

/CN11/RG9

MCLR

PMA11/AN12/RB12

PMA10/AN13/RB13

PMALH/PMA1/AN14/RB14

PMALL/PMA0/AN15/OCFB/CN12/RB15

PMD9/RG1

PMD10/RF1

ENVREG

PMD14/CN15/RD6

TDO/RA5

SDA2/RA3
SCL2/RA2

V

SS

VSS

VSS

VCAP/VDDCORE

TDI/RA4

TCK/RA1

100-Pin TQFP (USB)

PMD15/CN16/RD7

= Pins are up to 5V tolerant

20

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

65
64
63
62
61
60
59

56

45

44

43

42

41

40

39

2829303132333435363738

17
18
19

21

22

1

72
71
70
69
68
67
66

75
74
73

58
57

24

23

25

27

464748

49

55
54
53
52
51

50

26

PIC32MX4XXL

92949391908988878685848382818079789576

77

969897

99

100

PIN DIAGRAM: 100-PIN TQFP – USB

DS61143F-page 8 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

Table of Contents

High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose and USB ..................................... 1

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 15

3.0 PIC32MX MCU........................................................................................................................................................................... 19

4.0 Memory Organization................................................................................................................................................................. 25

5.0 Flash Program Memory.............................................................................................................................................................. 55

6.0 Resets ........................................................................................................................................................................................ 57

7.0 Interrupt Controller ..................................................................................................................................................................... 59

8.0 Oscillator Configuration.............................................................................................................................................................. 63

9.0 Prefetch Cache........................................................................................................................................................................... 65

10.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 67

11.0 USB On-The-Go (OTG).............................................................................................................................................................. 69

12.0 I/O Ports ..................................................................................................................................................................................... 71

13.0 Timer1 ........................................................................................................................................................................................ 73

14.0 Timers 2, 3, 4, 5 ......................................................................................................................................................................... 75

15.0 Input Capture.............................................................................................................................................................................. 77

16.0 Output Compare......................................................................................................................................................................... 79

17.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 81

18.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................... 83

19.0 Universal Asynchronous Receiver Transmitter (UART) ............................................................................................................. 85

20.0 Parallel Master Port (PMP)......................................................................................................................................................... 89

21.0 Real-Time Clock and Calendar (RTCC)..................................................................................................................................... 91

22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................... 93

23.0 Comparator ................................................................................................................................................................................ 95

24.0 Comparator Voltage Reference (CVref) ..................................................................................................................................... 97

25.0 Power-Saving Features.............................................................................................................................................................. 99

26.0 Special Features ...................................................................................................................................................................... 101

27.0 Instruction Set .......................................................................................................................................................................... 113

28.0 Development Support............................................................................................................................................................... 121

28.0 Electrical Characteristics .......................................................................................................................................................... 119

29.0 Packaging Information.............................................................................................................................................................. 157

INDEX ................................................................................................................................................................................................ 167

Worldwide Sales and Service ............................................................................................................................................................ 170

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 9

PIC32MX3XX/4XX

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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DS61143F-page 10 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

Note 1: Some features are not available on all device variants.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

UART 1,2

Comparators

PORTA

PORTD

PORTE

PORTF

PORTG

PORTB

CN1-22

JTAG

Priority

DMAC

ICD

MIPS 32® M4K® CPU Core

IS DS

EJTAG INT

Bus Matrix

Prefetch

Data RAM

Peripheral Bridge

128

128-bit wide

Flash

32

32

32

32

32

Peripheral Bus Clocked by PBCLK

Program Flash Memory

Controller

32

32

Module

32

32

Interrupt

Controller

BSCAN

PORTC

PMP

I2C 1,2

SPI 1,2

IC 1-5

PWM

OC 1-5

OSC1/CLKI

OSC2/CLKO

V

DD,

Timing

Generation

V

SS

MCLR

Power-up

Timer

Oscillator

Start-up Ti me r

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VDDCORE/VCAP

ENVREG

OSC/SOSC

Oscillators

PLL

DIVIDERS

SYSCLK

PBCLK

Peripheral Bus Clocked by SYSCLK

USB

PLL-USB

USBCLK

32

RTCC

10-bit ADC

Timer1-5

32

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features of

the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
appropriate section of the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32)

FIGURE 1-1: BLOCK DIAGRAM

(1,2)

This document contains device-specific information for
the PIC32MX3XX/4XX devices.

Figure 1-1 shows a general block diagram of the core
and peripheral modules in the PIC32MX3XX/4XX fam­ilies of devices.

Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 11

PIC32MX3XX/4XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN15 I Analog Analog input channels.

CLKI

CLKO

OSC1

OSC2

SOSCI
SOSCO

CN0-CN21 I ST Change notification inputs.

IC1-IC5 I ST Capture inputs 1-5.

OCFA
OC1-OC5
OCFB

INT0
INT1
INT2
INT3
INT4

RA0-RA15 I/O ST PORTA is a bidirectional I/O port.

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC0-RC15 I/O ST PORTC is a bidirectional I/O port.

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RE0-RE15 I/O ST PORTE is a bidirectional I/O port.

RF0-RF15 I/O ST PORTF is a bidirectional I/O port.

RG0, RG1,
RG4-RG15

RG2, RG3 I ST PORTG input pins.

T1CK
T2CK
T3CK
T4CK
T5CK

U1CTS
U1RTS
U1RX
U1TX

U2CTS
U2RTS
U2RX
U2TX

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer

Pin

Typ e

I/O

O

I/O ST PORTG is a bidirectional I/O port.

O

O

O

O

Buffer

Type

IOST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.

I

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.

IOST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.

32.768 kHz low-power oscillator crystal output.

Can be software programmed for internal weak pull-ups on all inputs.

I

I

I
I
I
I
I

I
I
I
I
I

I

I

I

I

ST

—

ST

ST
ST
ST
ST
ST

ST
ST
ST
ST
ST

ST

—

ST

—

ST

—

ST

—

Compare Fault A input.
Compare outputs 1 through 5.
Output Compare Fault B Input.

External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.

Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.

UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.

UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.

Description

DS61143F-page 12 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

SCK1
SDI1
SDO1
SS1

SCK2
SDI2
SDO2
SS2

SCL1
SDA1

TMS
TCK
TDI
TDO

RTCC O — Real-Time Clock Alarm Output.

CVREF–
CVREF+
CVREFOUT

C1IN-
C1IN+
C1OUT

C2IN­C2IN+
C2OUT

PMA0

PMA1

PMA2-PMPA15
PMENB
PMCS1
PMCS2
PMD0-PMD15

PMRD
PMWR
PMALL

PMALH

PMRD/PMWR

PMALL

PMALH

PMRD/PMWR

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer

Pin

Typ e

I/O

O

I/O

I/O

O

I/O

I/O
I/O

O

O

O

O

I/O

I/O

O
O
O
O

I/O

O
O
O

O

O

O

O

O

Buffer

Type

ST

I

I

I
I
I

I
I

I
I

I
I

ST

ST

ST
ST

ST

STSTSynchronous serial clock input/output for I2C1.

ST
ST
ST

ANA
ANA
ANA

ANA
ANA

ANA
ANA

TTL/ST

TTL/ST

TTL/ST

Synchronous serial clock input/output for SPI1.
SPI1 data in.

—

SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for SPI2.
SPI2 data in.

—

SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.

Synchronous serial data input/output for I2C1.

JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.

—

JTAG test data output pin.

Comparator Voltage Reference (low).
Comparator Voltage Reference (high).
Comparator Voltage Reference Output.

Comparator 1 Negative Input.
Comparator 1 Positive Input.

—

Comparator 1 Output.

Comparator 2 Negative Input.
Comparator 2 Positive Input.

—

Comparator 2 Output.

Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output
(Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output
(Master modes).

—

Parallel Master Port Address (Demultiplexed Master Modes).

—

Parallel Master Port Enable Strobe (Master mode 1).

—

Parallel Master Port Chip Select 1 Strobe.

—

Parallel Master Port Chip Select 2 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/Data
(Multiplexed Master modes).

—

Parallel Master Port Read Strobe.

—

Parallel Master Port Write Strobe.

—

Parallel Master Port Address Latch Enable low-byte (Multiplexed Master
modes).

—

Parallel Master Port Address Latch Enable high-byte (Multiplexed Master
modes).

—

Parallel Master Port Read/Write Strobe (Master mode 1).

—

Parallel Master Port Address Latch Enable low-byte (Multiplexed Master
modes).

—

Parallel Master Port Address Latch Enable high-byte (Multiplexed Master
modes).

—

Parallel Master Port Read/Write Strobe (Master mode 1).

Description

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 13

PIC32MX3XX/4XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

VBUS
VUSB
VBUSON
D+
D–
USBID

ENVREG I ST Enable for On-Chip Voltage Regulator.

TRCLK
TRD0-TRD3

PGED1
PGEC1
PGED2
PGEC2

MCLR I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

AVdd P P Positive supply for analog modules. This pin must be connected at all times.

AVss P P Ground reference for analog modules.

Vdd P — Positive supply for peripheral logic and I/O pins.

Vcap/Vddcore P — CPU logic filter capacitor connection.

Vss P — Ground reference for logic and I/O pins.

REF+ I Analog Analog voltage reference (high) input.

V

V

REF- I Analog Analog voltage reference (low) input.

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer

Pin

Typ e

O
I/O
I/O

O

O

I/O

I/O

Buffer

Type

I

P

I

I

I

ANA

—

—
ANA
ANA

ST

—

—

ST
ST
ST
ST

USB Bus Power Monitor.
USB Internal Transceiver Supply.
USB Host and OTG Bus Power Control Output.
USB D+.
USB D–.
USB OTG ID Detect.

Trace Clock.
Trace Data Bits 0-3

Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.

Description

DS61143F-page 14 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS

Note: This data sheet summarizes the features of

the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” for a detailed
description of the PIC32MX MCU.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).

2.1 Basic Connection Requirements

Getting started with the PIC32MX3XX/4XX family of
32-bit Microcontrollers (MCU) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:

DD and VSS pins

• All V

(see Section 2.2)

• All AV

•V

•MCLR

• PGECx/PGEDx pins used for In-Circuit Serial

• OSC1 and OSC2 pins when external oscillator

Additionally, the following pins may be required:

•V

DD and AVSS pins (regardless if ADC module

is not used)
(see Section 2.2)

CAP/VDDCORE

(see Section 2.3)

pin

(see Section 2.4)

Programming™ (ICSP™) and debugging purposes
(see Section 2.5)

source is used
(see Section 2.8)

REF+/VREF- pins used when external voltage

reference for ADC module is implemented

Note: The AVDD and AVSS pins must be

connected independent of ADC use and
ADC voltage reference source.

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of
power supply pins, such as V
AVSS is required. See Figure 2-1.

Consider the following criteria when using decoupling
capacitors:

• Value and type of capacitor: Recommendation

of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within one­quarter inch (6 mm) in length.

• Handling high frequency noise: If the board is

experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout

from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.

DD, VSS, AVDD, and

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 15

PIC32MX3XX/4XX

PIC32MX

VDD

VSS

VDD

VSS

VSS

VDD

AVDD

AVSS

VDD

VSS

C

R

V

DD

MCLR

0.1 µF
Ceramic

VCAP/VDDCORE

10 Ω

R1

CBP

0.1 µF
Ceramic
C

BP

0.1 µF
Ceramic
C

BP

0.1 µF
Ceramic
C

BP

0.1 µF
Ceramic
C

BP

Note 1: R ≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the MCLR
pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR

from the external capacitor C, in the

event of MCLR

pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR

pin

V

IH and VIL specifications are met.

3: The capacitor can be sized to prevent uninten-

tional resets from brief glitches or to extend the
device reset period during POR.

C

R1

R

V

DD

MCLR

PIC32MX

JP

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device
functions:

• Device Reset

• Device Programming and Debugging

Pulling The MCLR pin low generates a device reset.
Figure 2-2 shows a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR
levels (V

IH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.

For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR
operations.

Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR

FIGURE 2-2: EXAMPLE OF MCLR PIN

pin. Consequently, specific voltage

pin during programming and debugging

pin.

CONNECTIONS

2.3 Capacitor on Internal Voltage
Regulator (V

2.3.1 INTERNAL REGULATOR MODE

A low-ESR (< 5 Ohms) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the
internal voltage regulator output. The V
pin must not be connected to VDD, and must have a
10 µF capacitor, with at least a 6V rating, connected to
ground. The type can be ceramic or tantalum. Refer to
Section 28.0 "Electrical Characteristics" for
additional information. This mode is enabled by
connecting the ENVREG pin to V

2.3.2 EXTERNAL REGULATOR MODE

In this mode the core voltage is supplied externally
through the VDDCORE pin. A low-ESR capacitor of
10 µF is recommended on the VDDCORE pin. This mode
is enabled by grounding the ENVREG pin.

The placement of this capacitor should be close to the

CAP/VDDCORE. It is recommended that the trace

V
length not exceed one-quarter inch (6 mm). Refer to
Section 26.3 "On-Chip Voltage Regulator" for
details.

DS61143F-page 16 Preliminary © 2009 Microchip Technology Inc.

CAP/VDDCORE)

DD.

CAP/VDDCORE

PIC32MX3XX/4XX

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur­poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi­cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternately, refer to the AC/DC characteristics and tim­ing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits and pin input voltage high (V

IH)

and input low (VIL) requirements.

Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB

®

ICD 2, MPLAB® ICD 3, or MPLAB® REAL

ICE™.

For more information on ICD 2, ICD 3, and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.

®

• “MPLAB

ICD 2 In-Circuit Debugger User's

Guide” DS51331

®

• “Using MPLAB

• “MPLAB

®

• “Using MPLAB

ICD 2” (poster) DS51265

ICD 2 Design Advisory” DS51566

®

ICD 3” (poster) DS51765

• “MPLAB® ICD 3 Design Advisory” DS51764

®

• “MPLAB

REAL ICE™ In-Circuit Debugger

User's Guide” DS51616

®

• “Using MPLAB

REAL ICE™” (poster) DS51749

2.6 JTAG

Pull-up resistors, series diodes, and capacitors on the
TMS, TDO, TDI, and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete compo­nents are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternately, refer to the AC/DC characteris­tics and timing requirements information in the respec­tive device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (V

IH) and input low (VIL) requirements.

2.7 Trace

The trace pins can be connected to a hardware-trace­enabled programmer to provide a compress real time
instruction trace. When used for trace the TRD3,
TRD2, TRD1, TRD0, and TRCLK pins should be dedi­cated for this use. The trace hardware requires a 22
Ohm series resistor between the trace pins and the
trace connector.

2.8 External Oscillator Pins

Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 "Oscillator
Configuration" for details).

The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.

The TMS, TDO, TDI, and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR
CIRCUIT

trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 17

PIC32MX3XX/4XX

2.9 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins by setting all bits in the
ADPCFG register.

The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.

If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
ADPCFG register during initialization of the ADC
module.

When MPLAB ICD 2, ICD 3, or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the ADPCFG register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic '0', which may affect user application
functionality.

2.10 Unused I/Os

Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.

Alternately, inputs can be reserved by connecting the
pin to V
the pin as an input.

SS through a 1k to 10k resistor and configuring

DS61143F-page 18 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

Dual Bus I/F

System

Coprocessor

MDU

FMT

TAP

EJTAG

Power

Mgmt

Off-Chip

Debug I/F

Execution

Core

(RF/ALU/Shift)

Bus Matrix

Trace

Trace I/F

Bus Interface

3.0 PIC32MX MCU

Note: This data sheet summarizes the features of

the PIC32MX3XX/4XX Family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX

Family Reference Manual” Section 2.
“MCU” (DS61113) for a detailed description

of the PIC32MX MCU. The manual is
available from the Microchip web site
(www.Microchip.com/PIC32). Resources for
the MIPS32
available at www.mips.com/prod­ucts/cores/32-bit-cores/ mips32-m4k/#.

The MCU module is the heart of the PIC32MX3XX/4XX
Family processor. The MCU fetches instructions,
decodes each instruction, fetches source operands,
executes each instruction, and writes the results of
instruction execution to the proper destinations.

3.1 Features

• 5-stage pipeline

• 32-bit Address and Data Paths

• MIPS32 Enhanced Architecture (Release 2)

- Multiply-Accumulate and Multiply-Subtract
Instructions

- Targeted Multiply Instruction

- Zero/One Detect Instructions

- WAIT Instruction

- Conditional Move Instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

- Atomic interrupt enable/disable

- GPR shadow registers to minimize latency
for interrupt handlers

- Bit field manipulation instructions

®

M4K® Processor Core are

• MIPS16e™ Code Compression

- 16-bit encoding of 32-bit instructions to
improve code density

- Special PC-relative instructions for efficient
loading of addresses and constants

- SAVE & RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines

- Improved support for handling 8 and 16-bit
data types

• Simple Fixed Mapping Translation (FMT)
mechanism

• Simple Dual Bus Interface

- Independent 32-bit address and data busses

- Transactions can be aborted to improve

interrupt latency

• Autonomous Multiply/Divide Unit

- Maximum issue rate of one 32x16 multiply

per clock

- Maximum issue rate of one 32x32 multiply

every other clock

- Early-in iterative divide. Minimum 11 and

maximum 34 clock latency (dividend (rs) sign
extension-dependent)

• Power Control

- Minimum frequency: 0 MHz

- Low-Power mode (triggered by WAIT

instruction)

- Extensive use of local gated clocks

• EJTAG Debug and Instruction Trace

- Support for single stepping

- Virtual instruction and data address/value

- breakpoints

- PC tracing with trace compression

FIGURE 3-1: MCU BLOCK DIAGRAM

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 19

PIC32MX3XX/4XX

3.2 Architecture Overview

The PIC32MX3XX/4XX Family core contains several
logic blocks working together in parallel, providing an
efficient high performance computing engine. The fol­lowing blocks are included with the core:

• Execution Unit

• Multiply/Divide Unit (MDU)

• System Control Coprocessor (CP0)

• Fixed Mapping Translation (FMT)

• Dual Internal Bus interfaces

• Power Management

• MIPS16e Support

• Enhanced JTAG (EJTAG) Controller

3.2.1 EXECUTION UNIT

The PIC32MX3XX/4XX Family core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit general purpose registers used for
integer operations and address calculation. One addi­tional register file shadow set (containing thirty-two reg­isters) is added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.

The execution unit includes:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction
address

• Logic for branch determination and branch target
address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when
executing instructions streams where data
producing instructions are followed closely by
consumers of their results

• Leading Zero/One detect unit for implementing the
CLZ and CLO instructions

• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations

• Shifter and Store Aligner

3.2.2 MULTIPLY/DIVIDE UNIT (MDU)

The PIC32MX3XX/4XX Family core includes a multi­ply/divide unit (MDU) that contains a separate pipeline
for multiply and divide operations. This pipeline oper­ates in parallel with the integer unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows
MDU operations to be partially masked by system stalls
and/or other integer unit instructions.

The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.

The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.

Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16­bit-wide rs, 15 iterations are skipped, and for a 24-bit­wide rs, 7 iterations are skipped. Any attempt to issue
a subsequent MDU instruction while a divide is still
active causes an IU pipeline stall until the divide oper­ation is completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (num­ber of cycles until a result is available) for the PIC32MX
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.

DS61143F-page 20 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

TABLE 3-1: PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER

MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate

MULT/MULTU, MADD/MADDU,

MSUB/MSUBU

MUL 16 bits 2 1

DIV/DIVU 8 bits 12 11

The MIPS architecture defines that the result of a mul­tiply or divide operation be placed in the HI and LO reg­isters. Using the Move-From-HI (MFHI) and Move­From-LO (MFLO) instructions, these values can be
transferred to the general purpose register file.

In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination registers, the throughput of multiply-inten­sive operations is increased.

Two other instructions, multiply-add (MADD) and multi­ply-subtract (MSUB), are used to perform the multiply­accumulate and multiply-subtract operations. The
MADD instruction multiplies two numbers and then adds

TABLE 3-2: COPROCESSOR 0 REGISTERS

Register

Number

0-6 Reserved Reserved in the PIC32MX3XX/4XX Family core

10 Reserved Reserved in the PIC32MX3XX/4XX Family core

12 Status

12 IntCtl

12 SRSCtl

12 SRSMap

13 Cause

14 EPC

15 PRId Processor identification and revision

15 EBASE Exception vector base register

16 Config Configuration register

16 Config1 Configuration register 1

16 Config2 Configuration register 2

16 Config3 Configuration register 3

Register
Name

7 HWREna Enables access via the RDHWR instruction to selected hardware registers

8 BadVAddr

9 Count

11 Compare

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

Function

Reports the address for the most recent address-related exception

Processor cycle count

Timer interrupt control

Processor status and control

Interrupt system status and control

Shadow register set status and control

Provides mapping from vectored interrupt to a shadow set

Cause of last general exception

Program counter at last exception

16 bits 1 1

32 bits 2 2

32 bits 3 2

16 bits 19 18

24 bits 26 25

32 bits 33 32

the product to the current contents of the HI and LO
registers. Similarly, the MSUB instruction multiplies two
operands and then subtracts the product from the HI
and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.

3.2.3 SYSTEM CONTROL COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the vir­tual-to-physical address translation, the exception con­trol system, the processor’s diagnostics capability, the
operating modes (kernel, user, and debug), and
whether interrupts are enabled or disabled. Configura­tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0 reg­isters, listed in Table 3-2.

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 21

PIC32MX3XX/4XX

TABLE 3-2: COPROCESSOR 0 REGISTERS (CONTINUED)

Register

Number

17-22 Reserved Reserved in the PIC32MX3XX/4XX Family core

23 Debug

24 DEPC

25-29 Reserved Reserved in the PIC32MX3XX/4XX Family core

30 ErrorEPC

31 DESAVE

Note 1: Registers used in exception processing.

Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events, or program errors. Table 3-3
shows the exception types in order of priority.

TABLE 3-3: PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES

Exception Description

DDBL / DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)

Register
Name

(2)

(2)

(1)

(2)

Function

Debug control and exception status

Program counter at last debug exception

Program counter at last error

Debug handler scratchpad register

2: Registers used during debug.

Reset Assertion MCLR or a Power-On Reset (POR)

DSS EJTAG Debug Single Step

DINT EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the

EjtagBrk bit in the ECR register

NMI Assertion of NMI signal

Interrupt Assertion of unmasked hardware or software interrupt signal

DIB EJTAG debug hardware instruction break matched

AdEL Fetch address alignment error

Fetch reference to protected address

IBE Instruction fetch bus error

DBp EJTAG Breakpoint (execution of SDBBP instruction)

Sys Execution of SYSCALL instruction

Bp Execution of BREAK instruction

RI Execution of a Reserved Instruction

CpU Execution of a coprocessor instruction for a coprocessor that is not enabled

CEU Execution of a CorExtend instruction when CorExtend is not enabled

Ov Execution of an arithmetic instruction that overflowed

Tr Execution of a trap (when trap condition is true)

AdEL Load address alignment error

Load reference to protected address

AdES Store address alignment error

Store to protected address

DBE Load or store bus error

DDBL EJTAG data hardware breakpoint matched in load data compare

DS61143F-page 22 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

3.3 Power Management

The PIC32MX3XX/4XX Family core offers a number of
power management features, including low-power
design, active power management, and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during idle periods.

3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT

The mechanism for invoking power-down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 25.0
“Power-Saving Features”.

3.3.2 LOCAL CLOCK GATING

The majority of the power consumed by the
PIC32MX3XX/4XX Family core is in the clock tree and
clocking registers. The PIC32MX family uses extensive
use of local gated-clocks to reduce this dynamic power
consumption.

3.4 EJTAG Debug Support

The PIC32MX3XX/4XX Family core provides for an
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard user mode and kernel modes of
operation, the PIC32MX3XX/4XX Family core provides
a Debug mode that is entered after a debug exception
(derived from a hardware breakpoint, single-step
exception, etc.) is taken and continues until a debug
exception return (DERET) instruction is executed.
During this time, the processor executes the debug
exception handler routine.

The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring test data in and out of the
PIC32MX3XX/4XX Family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define what
registers are selected and how they are used.

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 23

PIC32MX3XX/4XX

NOTES:

DS61143F-page 24 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

4.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features of

the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX

Family Reference Manual” Section 3.
“Memory Organization” (DS61115 ) f o r a

detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).

PIC32MX3XX/4XX microcontrollers provide 4 GB of
unified virtual memory address space. All memory
regions including program, data memory, SFRs, and
Configuration registers reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX3XX/4XX to
execute from data memory.

Key Features:

• 32-bit native data width

• Separate User and Kernel mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and

program space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept

runaway code.

• Simple memory mapping with Fixed Mapping

Translation (FMT) unit

• Cacheable and non-cacheable address regions

4.1 PIC32MX3XX/4XX Memory Layout

PIC32MX3XX/4XX microcontrollers implement two
address spaces: Virtual and Physical. All hardware
resources such as program memory, data memory, and
peripherals are located at their respective physical
addresses. Virtual addresses are exclusively used by
the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
peripherals such as DMA and Flash controller that
access memory independently of CPU.

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 25

PIC32MX3XX/4XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD008000

0xBD007FFF

Program Flash

(2)

0xBD000000

Reserved

0xA0002000

0xA0001FFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC02FF0

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FEF

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D008000 0x1F800000

0x9D007FFF

Program Flash

(2)

Reserved

0x9D000000 0x1D008000

Reserved

Program Flash

(2)

0x1D007FFF

0x80002000

0x80001FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00002000

Reserved RAM

(2)

0x00001FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX320F032H, PIC32MX420F032H

DEVICES

(1)

DS61143F-page 26 Preliminary © 2009 Microchip Technology Inc.

PIC32MX3XX/4XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC02FF0

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FEF

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D010000

Reserved

Program Flash

(2)

0x1D00FFFF

0x80004000

0x80003FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM

(2)

0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICES

(1)

© 2009 Microchip Technology Inc. Preliminary DS61143F-page 27

PIC32MX3XX/4XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC02FF0

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FEF

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D020000

Reserved

Program Flash

(2)

0x1D01FFFF

0x80004000

0x80003FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM

(2)

0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX320F128H, PIC32MX320F128L

DEVICES

(1)

DS61143F-page 28 Preliminary © 2009 Microchip Technology Inc.