Datasheet PIC32MX120F064H, PIC32MX130F128H, PIC32MX130F128L, PIC32MX230F128H, PIC32MX230F128L Datasheet

PIC32MX1XX/2XX/5XX 64/100-PIN

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with

Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Operating Conditions

• 2.3V to 3.6V, -40ºC to +105ºC (DC to 40 MHz),

-40ºC to +85ºC (DC to 50 MHz)

Core: 50 MHz/83 DMIPS MIPS32® M4K

• MIPS16e® mode for up to 40% smaller code size

• Code-efficient (C and Assembly) architecture

• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply

®

Clock Management

• 0.9% internal oscillator

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer

• Fast wake-up and start-up

Power Management

• Low-power management modes (Sleep and Idle)

• Integrated Power-on Reset, Brown-out Reset, and High
Voltage Detect

• 0.5 mA/MHz dynamic current (typical)

•44 μA IPD current (typical)

Audio/Graphics/Touch HMI Features

• External graphics interface with up to 34 PMP pins

• Audio data communication: I2S, LJ, RJ, USB

• Audio data control interface: SPI and I2C™

• Audio data master clock:

- Generation of fractional clock frequencies

- Can be synchronized with USB clock

- Can be tuned in run-time

• Charge Time Measurement Unit (CTMU):

- Supports mTouch™ capacitive touch sensing

- Provides high-resolution time measurement (1 ns)

Advanced Analog Features

• ADC Module:

- 10-bit 1 Msps rate with one Sample and Hold (S&H)

- Up to 48 analog inputs

- Can operate during Sleep mode

• Flexible and independent ADC trigger sources

• On-chip temperature measurement capability

• Comparators:

- Three dual-input Comparator modules

- Programmable reference with 32 voltage points

Timers/Output Compare/Input Capture

• Five General Purpose Timers:

- Five 16-bit and up to two 32-bit Timers/Counters

• Five Output Compare (OC) modules

• Five Input Capture (IC) modules

• Peripheral Pin Select (PPS) to allow function remap

• Real-Time Clock and Calendar (RTCC) module

Communication Interfaces

• USB 2.0-compliant Full-speed OTG controller

• Up to five UART modules (12.5 Mbps):

- LIN 1.2 protocols and IrDA® support

• Four 4-wire SPI modules (25 Mbps)

•Two I2C modules (up to 1 Mbaud) with SMBus support

• PPS to allow function remap

• Parallel Master Port (PMP) with dual read/write buffers

• Controller Area Network (CAN) 2.0B Compliant with
DeviceNet™ addressing support

Direct Memory Access (DMA)

• Four channels of hardware DMA with automatic data
size detection

• 32-bit Programmable Cyclic Redundancy Check (CRC)

• Two additional channels dedicated to USB

• Two additional channels dedicated to CAN

Input/Output

• 10 mA or 15 mA source/sink for standard VOH/VOL and
up to 22

• 5V-tolerant pins

• Selectable open drain, pull-ups, and pull-downs

• External interrupts on all I/O pins

mA for non-standard VOH

1

Qualification and Class B Support

• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-circuit and in-application programming

•4-wire MIPS® Enhanced JTAG interface

• Unlimited program and six complex data breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

Packages

Type QFN TQFP TFBGA (see Note 1)

Pin Count 64 64 100 100 100

I/O Pins (up to) 53 53 85 85 85

Contact/Lead Pitch 0.50 mm 0.50 mm 0.40 mm 0.50 mm 0.65 mm

Dimensions 9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 7x7x1.2 mm

Note 1: Please contact your local Microchip Sales Office for information regarding the availability of devices in the 100-pin TFBGA package.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 1

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1: PIC32MX1XX/2XX/5XX 64/100-PIN CONTROLLER FAMILY FEATURES

Remappable Peripherals

(1)

(4)

Device

PIC32MX120F064H 64

PIC32MX130F128H 64

PIC32MX130F128L

PIC32MX230F128H 64

PIC32MX230F128L

PIC32MX530F128H 64

PIC32MX530F128L

PIC32MX150F256H 64

PIC32MX150F256L

PIC32MX250F256H 64

PIC32MX250F256L

PIC32MX550F256H 64

PIC32MX550F256L

PIC32MX170F512H 64

PIC32MX170F512L

PIC32MX270F512H 64

PIC32MX270F512L

PIC32MX570F512H 64

PIC32MX570F512L

Note 1: All devices feature 3 KB of Boot Flash memory.

2: Four out of five timers are remappable.
3: Four out of five external interrupts are remappable.
4: Please contact your local Microchip Sales Office for information regarding the availability of devices in the 100-pin TFBGA package.

Pins

Packages

QFN,

TQFP

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

QFN,

TQFP

100 TQFP

100 TFBGA

Data Memory (KB)

Program Memory (KB)

64+38375/5/5435283N0Y2YY4/053YN

128+3 16 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y N

128+3 16 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y Y

128+3 16 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y N

128+3 16 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y

128+3 16 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y N

128+3 16 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y Y

256+3 32 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y N

256+3 32 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y Y

256+3 32 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y N

256+3 32 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 4/2 81 Y Y

256+3 32 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y N

256+3 32 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y Y

512+3 64 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y N

512+3 64 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y Y

512+3 64 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y N

512+3 64 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 4/2 81 Y Y

512+3 64 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y N

512+3 64 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y Y

Remappable Pins

(2)

(3)

S

2

UART

SPI/I

External Interrupts

Timers/Capture/Compare

Analog Comparators

10-bit 1 Msps ADC (Channels)

CAN

USB On-The-Go (OTG)

CTMU

2

C™
I

PMP

RTCC

DMA Channels (Programmable/Dedicated)

4/2

JTAG

I/O Pins

81 Y Y

Trace

DS60001290C-page 2 Preliminary  2014 Microchip Technology Inc.

1

64

64-PIN QFN

(4)

AND TQFP (TOP VIEW)

PIC32MX120F064H
PIC32MX130F128H
PIC32MX150F256H

64

1

M

TQFP

QFN

(4)

PIC32MX170F512H

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Device Pin Tables

TABLE 2: PIN NAMES FOR 64-PIN GENERAL PURPOSE DEVICES

Pin # Full Pin Name Pin # Full Pin Name

AN22/RPE5/PMD5/RE5

1

2 AN23/PMD6/RE6 34 RPF2/RF2

AN27/PMD7/RE7

3

4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 SDA1/RG3

AN17/C1INC/RPG7/PMA4/RG7

5

6 AN18/C2IND/RPG8/PMA3/RG8 38 VDD

MCLR

7

8 AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15

9 VSS 41 VSS

10 VDD 42 RPD8/RTCC/RD8

11 AN5/C1INA/RPB5/RB5 43 RPD9/RD9

12 AN4/C1INB/RB4 44 RPD10/PMA15/RD10

13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMA14/RD11

14 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 46 RPD0/RD0

15 PGEC1/VREF-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13

16 PGED1/VREF+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14

17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1

18 PGED2/AN7/RPB7/CTED3/RB7 50 AN25/RPD2/RD2

AVDD

19

20 AV SS 52 RPD4/PMWR/RD4

AN8/RPB8/CTED10/RB8

21

22 AN9/RPB9/CTED4/PMA7/RB9 54 C3INC/RD6

TMS/CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10

23

24 TDO/AN11/PMA12/RB11 56 VCAP

VSS

25

26 VDD 58 C3INA/RPF0/RF0

27 TCK/AN12/PMA11/RB12 59 TRCLK/RPF1/RF1

28 TDI/AN13/PMA10/RB13 60 TRD0/PMD0/RE0

29 AN14/RPB14/SCK3/CTED5/PMA1/RB14 61 TRD1/PMD1/RE1

30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 TRD2/AN20/PMD2/RE2

31 RPF4/SDA2/PMA9/RF4 63 TRD3/RPE3/CTPLS/PMD3/RE3

32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.
2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

RPF3/RF3

33

RPF6/SCK1/INT0/RF6

35

SCL1/RG2

37

OSC1/CLKI/RC12

39

AN26/C3IND/RPD3/RD3

51

RPD5/PMRD/RD5

53

C3INB/RD7

55

VDD

57

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 3

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

1

64

64-PIN QFN

(4)

AND TQFP (TOP VIEW)

PIC32MX530F128H
PIC32MX250F256H

PIC32MX270F512H

64

1

M

TQFP

QFN

(4)

PIC32MX550F256H
PIC32MX570F512H

PIC32MX230F128H

TABLE 3: PIN NAMES FOR 64-PIN USB DEVICES

Pin # Full Pin Name Pin # Full Pin Name

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

AN22/RPE5/PMD5/RE5

1

2 AN23/PMD6/RE6 34 VBUS

AN27/PMD7/RE7

3

4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 D-

AN17/C1INC/RPG7/PMA4/RG7

5

6 AN18/C2IND/RPG8/PMA3/RG8 38 VDD

MCLR

7

8 AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15

9 VSS 41 VSS

10 VDD 42 RPD8/RTCC/RD8

11 AN5/C1INA/RPB5/VBUSON/RB5 43 RPD9/SDA1/RD9

12 AN4/C1INB/USBOEN/RB4 44 RPD10/SCL1/PMA15/RD10

13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMA14/RD11

14 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 46 RPD0/INT0/RD0

15 PGEC1/VREF-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13

16 PGED1/VREF+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14

17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1

18 PGED2/AN7/RPB7/CTED3/RB7 50 AN25/RPD2/SCK1/RD2

AVDD

19

20 AV SS 52 RPD4/PMWR/RD4

AN8/RPB8/CTED10/RB8

21

22 AN9/RPB9/CTED4/PMA7/RB9 54 C3INC/RD6

TMS/CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10

23

24 TDO/AN11/PMA12/RB11 56 VCAP

VSS

25

26 VDD 58 C3INA/RPF0/RF0

27 TCK/AN12/PMA11/RB12 59 TRCLK/RPF1/RF1

28 TDI/AN13/PMA10/RB13 60 TRD0/PMD0/RE0

29 AN14/RPB14/SCK3/CTED5/PMA1/RB14 61 TRD1/PMD1/RE1

30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 TRD2/AN20/PMD2/RE2

31 RPF4/SDA2/PMA9/RF4 63 TRD3/RPE3/CTPLS/PMD3/RE3

32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4

Select” for restrictions.

2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS externally.

USBID/RPF3/RF3

33

VUSB3V3

35

D+

37

OSC1/CLKI/RC12

39

AN26/C3IND/RPD3/RD3

51

RPD5/PMRD/RD5

53

C3INB/RD7

55

VDD

57

DS60001290C-page 4 Preliminary  2014 Microchip Technology Inc.

TABLE 4: PIN NAMES FOR 100-PIN GENERAL PURPOSE DEVICES

1

100

100-PIN TQFP (TOP VIEW)

PIC32MX130F128L
PIC32MX170F512L

PIC32MX150F256L

Pin # Full Pin Name Pin # Full Pin Name

AN28/RG15

1

2VDD 37 VDD

AN22/RPE5/PMD5/RE5

3

4 AN23/PMD6/RE6 39 AN34/RPF13/SCK3/RF13

AN27/PMD7/RE7

5

6 AN29/RPC1/RC1 41 AN12/PMA11/RB12

AN30/RPC2/RC2

7

8 AN31/RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14

9 RPC4/CTED7/RC4 44 AN15/RPB15/OCFB/CTED6/PMA0/RB15

10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 V

11 AN17/C1INC/RPG7/PMA4/RG7 46 VDD

12 AN18/C2IND/RPG8/PMA3/RG8 47 AN36/RPD14/RD14

13 MCLR 48 AN37/RPD15/SCK4/RD15

14 AN19/C2INC/RPG9/PMA2/RG9

SS 50 RPF5/PMA8/RF5

15 V

V

DD

16

TMS/CTED1/RA0

17

18 AN32/RPE8/RE8 53 AN39/RPF8/RF8

AN33/RPE9/RE9

19

20 AN5/C1INA/RPB5/RB5

AN4/C1INB/RB4

21

22 PGED3/AN3/C2INA/RPB3/RB3

PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2

23

24 PGEC1/AN1/RPB1/CTED12/RB1

25 PGED1/AN0/RPB0/RB0

26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5

27 PGED2/AN7/RPB7/CTED3/RB7 62 V

28 VREF-/PMA7/RA9 63 OSC1/CLKI/RC12

REF+/PMA6/RA10 64 OSC2/CLKO/RC15

29 V

30 AV

DD 65 VSS

31 AVSS 66 RPA14/RA14

32 AN8/RPB8/CTED10/RB8

33 AN9/RPB9/CTED4/RB9

CV

REFOUT/AN10/RPB10/CTED11/PMA13/RB10

34

35 AN11/PMA12/RB11

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.
2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.

3: Shaded pins are 5V tolerant.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

SS

V

36

TCK/CTED2/RA1

38

AN35/RPF12/RF12

40

AN13/PMA10/RB13

42

SS

49 RPF4/PMA9/RF4

RPF3/RF3

51

AN38/RPF2/RF2

52

RPF7/RF7

54

55 RPF6/SCK1/INT0/RF6

SDA1/RG3

56

57 SCL1/RG2

SCL2/RA2

58

59 SDA2/RA3

60 TDI/CTED9/RA4

DD

67 RPA15/RA15

68 RPD8/RTCC/RD8

RPD9/RD9

69

70 RPD10/PMA15/RD10

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 5

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

1

100

100-PIN TQFP (TOP VIEW)

PIC32MX130F128L
PIC32MX170F512L

PIC32MX150F256L

TABLE 4: PIN NAMES FOR 100-PIN GENERAL PURPOSE DEVICES (CONTINUED)

Pin # Full Pin Name Pin # Full Pin Name

71 RPD11/PMA14/RD11 86 VDD

72 RPD0/RD0 87 AN44/C3INA/RPF0/PMD11/RF0

SOSCI/RPC13/RC13

73

74 SOSCO/RPC14/T1CK/RC14

V

SS

75

76 AN24/RPD1/RD1

77 AN25/RPD2/RD2

78 AN26/C3IND/RPD3/RD3 93 AN46/PMD0/RE0

79 AN40/RPD12/PMD12/RD12 94 AN47/PMD1/RE1

80 AN41/PMD13/RD13

81 RPD4/PMWR/RD4 96 TRD1/RG12

RPD5/PMRD/RD5

82

83 AN42/C3INC/PMD14/RD6 98 AN20/PMD2/RE2

84 AN43/C3INB/PMD15/RD7

CAP 100 AN21/PMD4/RE4

85 V

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.

3: Shaded pins are 5V tolerant.

AN45/RPF1/PMD10/RF1

88

89 RPG1/PMD9/RG1

RPG0/PMD8/RG0

90

91 TRCLK/RA6

92 TRD3/CTED8/RA7

95 TRD2/RG14

TRD0/RG13

97

99 RPE3/CTPLS/PMD3/RE3

DS60001290C-page 6 Preliminary  2014 Microchip Technology Inc.

TABLE 5: PIN NAMES FOR 100-PIN USB DEVICES

1

100

100-PIN TQFP (TOP VIEW)

PIC32MX530F128L
PIC32MX250F256L

PIC32MX270F512L

PIC32MX550F256L
PIC32MX570F512L

PIC32MX230F128L

Pin # Full Pin Name Pin # Full Pin Name

AN28/RG15

1

2VDD 37 VDD

AN22/RPE5/PMD5/RE5

3

4 AN23/PMD6/RE6 39 AN34/RPF13/SCK3/RF13

AN27/PMD7/RE7

5

6 AN29/RPC1/RC1 41 AN12/PMA11/RB12

AN30/RPC2/RC2

7

8 AN31/RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14

9 RPC4/CTED7/RC4 44 AN15/RPB15/OCFB/CTED6/PMA0/RB15

10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 V

11 AN17/C1INC/RPG7/PMA4/RG7 46 VDD

12 AN18/C2IND/RPG8/PMA3/RG8 47 AN36/RPD14/RD14

13 MCLR 48 AN37/RPD15/SCK4/RD15

14 AN19/C2INC/RPG9/PMA2/RG9

SS 50 RPF5/PMA8/RF5

15 V

V

DD

16

TMS/CTED1/RA0

17

18 AN32/RPE8/RE8 53 AN39/RPF8/RF8

AN33/RPE9/RE9

19

20 AN5/C1INA/RPB5/VBUSON/RB5 55 VUSB3V3

AN4/C1INB/USBOEN/RB4

21

22 PGED3/AN3/C2INA/RPB3/RB3 57 D+

PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2

23

24 PGEC1/AN1/RPB1/CTED12/RB1

25 PGED1/AN0/RPB0/RB0

26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5

27 PGED2/AN7/RPB7/CTED3/RB7 62 V

28 VREF-/PMA7/RA9 63 OSC1/CLKI/RC12

REF+/PMA6/RA10 64 OSC2/CLKO/RC15

29 V

30 AV

DD 65 VSS

31 AVSS 66 RPA14/SCL1/RA14

32 AN8/RPB8/CTED10/RB8

33 AN9/RPB9/CTED4/RB9

CV

REFOUT/AN10/RPB10/CTED11/PMA13/RB10

34

35 AN11/PMA12/RB11

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.
2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.
3: Shaded pins are 5V tolerant.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 7

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

SS

V

36

TCK/CTED2/RA1

38

AN35/RPF12/RF12

40

AN13/PMA10/RB13

42

SS

49 RPF4/PMA9/RF4

USBID/RPF3/RF3

51

AN38/RPF2/RF2

52

V

BUS

54

D-

56

SCL2/RA2

58

59 SDA2/RA3

60 TDI/CTED9/RA4

DD

67 RPA15/SDA1/RA15

68 RPD8/RTCC/RD8

RPD9/RD9

69

70 RPD10/SCK1/PMA15/RD10

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

1

100

100-PIN TQFP (TOP VIEW)

PIC32MX530F128L
PIC32MX250F256L

PIC32MX270F512L

PIC32MX550F256L
PIC32MX570F512L

PIC32MX230F128L

TABLE 5: PIN NAMES FOR 100-PIN USB DEVICES (CONTINUED)

Pin # Full Pin Name Pin # Full Pin Name

71 RPD11/PMA14/RD11 86 VDD

72 RPD0/INT0/RD0 87 AN44/C3INA/RPF0/PMD11/RF0

SOSCI/RPC13/RC13

73

74 SOSCO/RPC14/T1CK/RC14

V

SS

75

76 AN24/RPD1/RD1

77 AN25/RPD2/RD2

78 AN26/C3IND/RPD3/RD3 93 AN46/PMD0/RE0

79 AN40/RPD12/PMD12/RD12 94 AN47/PMD1/RE1

80 AN41/PMD13/RD13

81 RPD4/PMWR/RD4 96 TRD1/RG12

RPD5/PMRD/RD5

82

83 AN42/C3INC/PMD14/RD6 98 AN20/PMD2/RE2

84 AN43/C3INB/PMD15/RD7

CAP 100 AN21/PMD4/RE4

85 V

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.

3: Shaded pins are 5V tolerant.

AN45/RPF1/PMD10/RF1

88

89 RPG1/PMD9/RG1

RPG0/PMD8/RG0

90

91 TRCLK/RA6

92 TRD3/CTED8/RA7

95 TRD2/RG14

TRD0/RG13

97

99 RPE3/CTPLS/PMD3/RE3

DS60001290C-page 8 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 25

3.0 CPU............................................................................................................................................................................................ 35

4.0 Memory Organization ................................................................................................................................................................. 39

5.0 Interrupt Controller ..................................................................................................................................................................... 51

6.0 Flash Program Memory .............................................................................................................................................................. 61

7.0 Resets ........................................................................................................................................................................................ 67

8.0 Oscillator Configuration .............................................................................................................................................................. 71

9.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 83

10.0 USB On-The-Go (OTG)............................................................................................................................................................ 103

11.0 I/O Ports ................................................................................................................................................................................... 127

12.0 Timer1 ...................................................................................................................................................................................... 157

13.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 161

14.0 Watchdog Timer (WDT) ........................................................................................................................................................... 167

15.0 Input Capture............................................................................................................................................................................ 171

16.0 Output Compare....................................................................................................................................................................... 175

17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 179

18.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 189

19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 197

20.0 Parallel Master Port (PMP)....................................................................................................................................................... 205

21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 219

22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 229

23.0 Controller Area Network (CAN) ................................................................................................................................................ 241

24.0 Comparator .............................................................................................................................................................................. 277

25.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 281

26.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 285

27.0 Power-Saving Features ........................................................................................................................................................... 291

28.0 Special Features ...................................................................................................................................................................... 297

29.0 Instruction Set .......................................................................................................................................................................... 309

30.0 Development Support............................................................................................................................................................... 311

31.0 40 MHz Electrical Characteristics............................................................................................................................................. 315

32.0 50 MHz Electrical Characteristics............................................................................................................................................. 359

33.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 365

34.0 Packaging Information.............................................................................................................................................................. 367

The Microchip Web Site ..................................................................................................................................................................... 383

Customer Change Notification Service .............................................................................................................................................. 383

Customer Support.............................................................................................................................................................................. 383

Product Identification System ............................................................................................................................................................ 384

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 9

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

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[e-mail]. We welcome your feedback.

http://www.microchip.com

DS60001290C-page 10 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Referenced Sources

This device data sheet is based on the following

individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as

the general reference for the operation of a particular
module or device feature.

Note: To access the documents listed below,

browse to the documentation section of
the Microchip web site
(www.microchip.com).

• Section 1. “Introduction” (DS60001127)

• Section 2. “CPU” (DS60001113)

• Section 3. “Memory Organization” (DS60001115)

• Section 5. “Flash Program Memory” (DS60001121)

• Section 6. “Oscillator Configuration” (DS60001112)

• Section 7. “Resets” (DS60001118)

• Section 8. “Interrupt Controller” (DS60001108)

• Section 9. “Watchdog Timer and Power-up Timer” (DS60001114)

• Section 10. “Power-Saving Features” (DS60001130)

• Section 12. “I/O Ports” (DS60001120)

• Section 13. “Parallel Master Port (PMP)” (DS60001128)

• Section 14. “Timers” (DS60001105)

• Section 15. “Input Capture” (DS60001122)

• Section 16. “Output Compare” (DS60001111)

• Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)

• Sect i o n 19 . “Comparator” (DS60001110)

• Section 20. “Comparator Voltage Reference (CV

• Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)

• Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)

• Section 24. “Inter-Integrated Circuit™ (I

• Section 27. “USB On-The-Go (OTG)” (DS60001126)

• Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)

• Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)

• Section 32. “Configuration” (DS60001124)

• Section 33. “Programming and Diagnostics” (DS60001129)

• Section 34. “Controller Area Network (CAN)” (DS60001123)

• Section 37. “Charge Time Measurement Unit (CTMU)” (DS60001167)

REF)” (DS60001109)

2

C™)” (DS60001116)

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 11

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

NOTES:

DS60001290C-page 12 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Note: Not all features are available on all devices. Refer to TABLE 1: “PIC32MX1XX/2XX/5XX 64/100-pin Controller

Family Features” for the list of features by device.

UART1-5

Comparators

PORTA/CNA

PORTD/CND

PORTE/CNE

PORTF/CNF

PORTG/CNG

PORTB/CNB

JTAG

Priority

DMAC ICD

MIPS32

®

M4K® CPU Core

IS DS

EJTAG INT

Bus Matrix

Data RAM

Peripheral Bridge

128

128-bit wide

Flash

32

32

32

32

Peripheral Bus Clocked by PBCLK

Program Flash Memory

Controller

32

32

32

Interrupt

Controller

BSCAN

PORTC/CNC

PMP

I2C1,2

SPI1-4

IC1-5

PWM

OC1-5

OSC1/CLKI

OSC2/CLKO

V

DD,

Timing

Generation

V

SS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VCAP

OSC/SOSC

Oscillators

PLL

DIVIDERS

SYSCLK

PBCLK

Peripheral Bus Clocked by SYSCLK

USB

PLL-USB

USBCLK

32

RTCC

10-bit ADC

Timer1-5

32

32

Remappable

Pins

CTMU

1-3

CAN

32

1.0 DEVICE OVERVIEW

This document contains device-specific information for
PIC32MX1XX/2XX/5XX 64/100-pin devices.

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100­pin family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to the related section of

Figure 1-1 illustrates a general block diagram of the

core and peripheral modules in the PIC32MX1XX/2XX/
5XX 64/100-pin family of devices.

Table 1-1 lists the functions of the various pins shown

in the pinout diagrams.

the “PIC32 Family Reference Manual”,

which is available from the Microchip

site (www.microchip.com/PIC32).

web

FIGURE 1-1: PIC32MX1XX/2XX/5XX 64/100-PIN BLOCK DIAGRAM

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 13

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

AN0 16 25 I Analog

AN1 15 24 I Analog

AN2 14 23 I Analog

AN3 13 22 I Analog

AN4 12 21 I Analog

AN5 11 20 I Analog

AN6 17 26 I Analog

AN7 18 27 I Analog

AN8 21 32 I Analog

AN9 22 33 I Analog

AN10 23 34 I Analog

AN11 24 35 I Analog

AN12 27 41 I Analog

AN13 28 42 I Analog

AN14 29 43 I Analog

AN15 30 44 I Analog

AN16 4 10 I Analog

AN17 5 11 I Analog

AN18 6 12 I Analog

AN19 8 14 I Analog

AN20 62 98 I Analog

AN21 64 100 I Analog

AN22 1 3 I Analog

AN23 2 4 I Analog

AN24 49 76 I Analog

AN25 50 77 I Analog

AN26 51 78 I Analog

AN27 3 5 I Analog

AN28 — 1 I Analog

AN29 — 6 I Analog

AN30 — 7 I Analog

AN31 — 8 I Analog

AN32 — 18 I Analog

AN33 — 19 I Analog

AN34 — 39 I Analog

AN35 — 40 I Analog

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

Pin

Type

Buffer

Type

Description

Analog input channels.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 14

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

AN36 — 47 I Analog

AN37 — 48 I Analog

AN38 — 52 I Analog

AN39 — 53 I Analog

AN40 — 79 I Analog

AN41 — 80 I Analog

AN42 — 83 I Analog

AN43 — 84 I Analog

AN44 — 87 I Analog

AN45 — 88 I Analog

AN46 — 93 I Analog

AN47 — 94 I Analog

CLKI 39 63 I ST/CMOS

CLKO 40 64 O —

OSC1 39 63 I ST/CMOS

OSC2 40 64 O —

SOSCI 47 73 I ST/CMOS

SOSCO 48 74 O — 32.768 kHz low-power oscillator crystal output.

IC1 PPS PPS I ST

IC2 PPS PPS I ST

IC3 PPS PPS I ST

IC4 PPS PPS I ST

IC5 PPS PPS I ST

OC1 PPS PPS O ST Output Compare Output 1

OC2 PPS PPS O ST Output Compare Output 2

OC3 PPS PPS O ST Output Compare Output 3

OC4 PPS PPS O ST Output Compare Output 4

OC5 PPS PPS O ST Output Compare Output 5

OCFA PPS PPS I ST Output Compare Fault A Input

OCFB 30 44 I ST Output Compare Fault B Input

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

Pin

Type

Buffer

Type

Description

Analog input channels.

External clock source input. Always associated with OSC1 pin
function.

Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes. Always associated with the OSC2 pin
function.

Oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.

Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes.

32.768 kHz low-power oscillator crystal input; CMOS
otherwise.

Capture Input 1-5

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 15

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

INT0 35

INT1 PPS PPS I ST External Interrupt 1

INT2 PPS PPS I ST External Interrupt 2

INT3 PPS PPS I ST External Interrupt 3

INT4 PPS PPS I ST External Interrupt 4

RA0 — 17 I/O ST

RA1 — 38 I/O ST

RA2 — 58 I/O ST

RA3 — 59 I/O ST

RA4 — 60 I/O ST

RA5 — 61 I/O ST

RA6 — 91 I/O ST

RA7 — 92 I/O ST

RA9 — 28 I/O ST

RA10 — 29 I/O ST

RA14 — 66 I/O ST

RA15 — 67 I/O ST

RB0 16 25 I/O ST

RB1 15 24 I/O ST

RB2 14 23 I/O ST

RB3 13 22 I/O ST

RB4 12 21 I/O ST

RB5 11 20 I/O ST

RB6 17 26 I/O ST

RB7 18 27 I/O ST

RB8 21 32 I/O ST

RB9 22 33 I/O ST

RB10 23 34 I/O ST

RB11 24 35 I/O ST

RB12 27 41 I/O ST

RB13 28 42 I/O ST

RB14 29 43 I/O ST

RB15 30 44 I/O ST

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

(1)

, 46

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

(2)55(1)

, 72

Pin

Type

(2)

Buffer

Type

I ST External Interrupt 0

PORTA is a bidirectional I/O port

PORTB is a bidirectional I/O port

Description

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 16

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC1 — 6 I/O ST

RC2 — 7 I/O ST

RC3 — 8 I/O ST

RC4 — 9 I/O ST

RC12 39 63 I/O ST

RC13 47 73 I/O ST

RC14 48 74 I/O ST

RC15 40 64 I/O ST

RD0 46 72 I/O ST

RD1 49 76 I/O ST

RD2 50 77 I/O ST

RD3 51 78 I/O ST

RD4 52 81 I/O ST

RD5 53 82 I/O ST

RD6 54 83 I/O ST

RD7 55 84 I/O ST

RD8 42 68 I/O ST

RD9 43 69 I/O ST

RD10 44 70 I/O ST

RD11 45 71 I/O ST

RD12 — 79 I/O ST

RD13 — 80 I/O ST

RD14 — 47 I/O ST

RD15 — 48 I/O ST

RE0 60 93 I/O ST

RE1 61 94 I/O ST

RE2 62 98 I/O ST

RE3 63 99 I/O ST

RE4 64 100 I/O ST

RE5 1 3 I/O ST

RE6 2 4 I/O ST

RE7 3 5 I/O ST

RE8 — 18 I/O ST

RE9 — 19 I/O ST

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

Pin

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port

PORTD is a bidirectional I/O port

PORTE is a bidirectional I/O port

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 17

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

64-pin

QFN/

TQFP

100-pin

TQFP

Pin

Type

RF0 58 87 I/O ST

RF1 59 88 I/O ST

RF2 34

(3)

52 I/O ST

RF3 33 51 I/O ST

RF4 31 49 I/O ST

RF5 32 50 I/O ST

RF6 35

(1)

RF7 — 54

55

(1)
(4)

I/O ST

I/O ST

RF8 — 53 I/O ST

RF12 — 40 I/O ST

RF13 — 39 I/O ST

RG0 — 90 I/O ST

RG1 — 89 I/O ST

RG2 37

RG3 36

(1)
(1)

57

56

(1)
(1)

I/O ST

I/O ST

RG6 4 10 I/O ST

RG7 5 11 I/O ST

RG8 6 12 I/O ST

RG9 8 14 I/O ST

RG12 — 96 I/O ST

RG13 — 97 I/O ST

RG14 — 95 I/O ST

RG15 — 1 I/O ST

T1CK 48 74 I ST Timer1 External Clock Input

T2CK PPS PPS I ST Timer2 External Clock Input

T3CK PPS PPS I ST Timer3 External Clock Input

T4CK PPS PPS I ST Timer4 External Clock Input

T5CK PPS PPS I ST Timer5 External Clock Input

U1CTS

U1RTS

PPS PPS I ST UART1 Clear to Send

PPS PPS O — UART1 Ready to Send

U1RX PPS PPS I ST UART1 Receive

U1TX PPS PPS O — UART1 Transmit

U2CTS

U2RTS

PPS PPS I ST UART2 Clear to Send

PPS PPS O — UART2 Ready to Send

U2RX PPS PPS I ST UART2 Receive

U2TX PPS PPS O — UART2 Transmit

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

Buffer

Type

Description

PORTF is a bidirectional I/O port

PORTG is a bidirectional I/O port

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 18

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

64-pin

QFN/

TQFP

100-pin

TQFP

Pin

Type

U3CTS PPS PPS I ST UART3 Clear to Send

U3RTS

PPS PPS O — UART3 Ready to Send

U3RX PPS PPS I ST UART3 Receive

U3TX PPS PPS O — UART3 Transmit

U4CTS

U4RTS

PPS PPS I ST UART4 Clear to Send

PPS PPS O — UART4 Ready to Send

U4RX PPS PPS I ST UART4 Receive

U4TX PPS PPS O — UART4 Transmit

U5CTS

U5RTS

— PPS I ST UART5 Clear to Send

— PPS O — UART5 Ready to Send

U5RX — PPS I ST UART5 Receive

U5TX — PPS O — UART5 Transmit

SCK1 35

, 50

(2)55(1)

, 70

(2)

I/O ST Synchronous Serial Clock Input/Output for SPI1

(1)

SDI1 PPS PPS I — SPI1 Data In

SDO1 PPS PPS O ST SPI1 Data Out

SS1

PPS PPS I/O — SPI1 Slave Synchronization for Frame Pulse I/O

SCK2 4 10 I/O ST Synchronous Serial Clock Input/Output for SPI2

SDI2 PPS PPS I — SPI2 Data In

SDO2 PPS PPS O ST SPI2 Data Out

SS2

PPS PPS I/O — SPI2 Slave Synchronization for Frame Pulse I/O

SCK3 29 39 I/O ST Synchronous Serial Clock Input/Output for SPI3

SDI3 PPS PPS I — SPI3 Data In

SDO3 PPS PPS O ST SPI3 Data Out

SS3

PPS PPS I/O — SPI3 Slave Synchronization for Frame Pulse I/O

SCK4 — 48 I/O ST Synchronous Serial Clock Input/Output for SPI4

SDI4 — PPS I — SPI4 Data In

SDO4 — PPS O ST SPI4 Data Out

SS4

SCL1 37

SDA1 36

— PPS I/O — SPI4 Slave Synchronization for Frame Pulse I/O

(1)
(1)

, 44

, 43

(2)57(1)
(2)56(1)

, 66

, 67

(2)

I/O ST Synchronous Serial Clock Input/Output for I2C1

(2)

I/O ST Synchronous Serial Data Input/Output for I2C1

SCL2 32 58 I/O ST Synchronous Serial Clock Input/Output for I2C2

SDA2 31 59 I/O ST Synchronous Serial Data Input/Output for I2C2

TMS 23 17 I ST JTAG Test Mode Select Pin

TCK 27 38 I ST JTAG Test Clock Input Pin

TDI 28 60 I — JTAG Test Clock Input Pin

TDO 24 61 O — JTAG Test Clock Output Pin

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

Buffer

Type

Description

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 19

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RTCC 42 68 O — Real-Time Clock Alarm Output

CV

REFOUT 23 34 O Analog Comparator Voltage Reference (Output)

C1INA 11 20 I Analog

C1INB 12 21 I Analog

C1INC 5 11 I Analog

C1IND 4 10 I Analog

C2INA 13 22 I Analog

C2INB 14 23 I Analog

C2INC 8 14 I Analog

C2IND 6 12 I Analog

C3INA 58 87 I Analog

C3INB 55 84 I Analog

C3INC 54 83 I Analog

C3IND 51 78 I Analog

C1OUT PPS PPS O — Comparator 1 Output

C2OUT PPS PPS O — Comparator 2 Output

C3OUT PPS PPS O — Comparator 3 Output

PMALL 30 44 O TTL/ST Parallel Master Port Address Latch Enable Low Byte

PMALH 29 43 O TTL/ST Parallel Master Port Address Latch Enable High Byte

PMA0 30 44 O TTL/ST

PMA1 29 43 O TTL/ST

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

Pin

Type

Buffer

Type

Description

Comparator 1 Inputs

Comparator 2 Inputs

Comparator 3 Inputs

Parallel Master Port Address bit 0 Input (Buffered Slave
modes) and Output (Master modes)

Parallel Master Port Address bit 0 Input (Buffered Slave
modes) and Output (Master modes)

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 20

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

PMA2 8 14 O TTL/ST

PMA3 6 12 O TTL/ST

PMA4 5 11 O TTL/ST

PMA5 4 10 O TTL/ST

PMA6 16 29 O TTL/ST

PMA7 22 28 O TTL/ST

PMA8 32 50 O TTL/ST

PMA9 31 49 O TTL/ST

PMA10 28 42 O TTL/ST

PMA11 27 41 O TTL/ST

PMA12 24 35 O TTL/ST

PMA13 23 34 O TTL/ST

PMA14 45 71 O TTL/ST

PMA15 44 70 O TTL/ST

PMCS1 45 71 O TTL/ST

PMCS2 44 70 O TTL/ST

PMD0 60 93 I/O TTL/ST

PMD1 61 94 I/O TTL/ST

PMD2 62 98 I/O TTL/ST

PMD3 63 99 I/O TTL/ST

PMD4 64 100 I/O TTL/ST

PMD5 1 3 I/O TTL/ST

PMD6 2 4 I/O TTL/ST

PMD7 3 5 I/O TTL/ST

PMD8 — 90 I/O TTL/ST

PMD9 — 89 I/O TTL/ST

PMD10 — 88 I/O TTL/ST

PMD11 — 87 I/O TTL/ST

PMD12 — 79 I/O TTL/ST

PMD13 — 80 I/O TTL/ST

PMD14 — 83 I/O TTL/ST

PMD15 — 84 I/O TTL/ST

PMRD 53 82 O — Parallel Master Port Read Strobe

PMWR 52 81 O — Parallel Master Port Write Strobe

(2)

V

BUS

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

34 54 I Analog USB Bus Power Monitor

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

Pin

Type

Buffer

Type

Description

Parallel Master Port data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes)

Parallel Master Port data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes)

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 21

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

VUSB3V3

VBUSON

(2)

D+

(2)

D-

USBID

USBOEN 12 21 O TTL/ST USB D+, D- active status (see UOEMON bit in Register 10-20)

PGED1 16 25 I/O ST

PGEC1 15 24 I ST

PGED2 18 27 I/O ST

PGEC2 17 26 I ST

PGED3 13 22 I/O ST

PGEC3 14 23 I ST

TRCLK — 91 O — Trace clock

TRD0 — 97 O — Trace Data bit 0

TRD1 — 96 O — Trace Data bit 1

TRD2 — 95 O — Trace Data bit 2

TRD3 — 92 O — Trace Data bit 3

CTED1 — 17 I ST CTMU External Edge Input 1

CTED2 — 38 I ST CTMU External Edge Input 2

CTED3 18 27 I ST CTMU External Edge Input 3

CTED4 22 33 I ST CTMU External Edge Input 4

CTED5 29 43 I ST CTMU External Edge Input 5

CTED6 30 44 I ST CTMU External Edge Input 6

CTED7 — 9 I ST CTMU External Edge Input 7

CTED8 — 92 I ST CTMU External Edge Input 8

CTED9 — 60 I ST CTMU External Edge Input 9

CTED10 21 32 I ST CTMU External Edge Input 10

CTED11 23 34 I ST CTMU External Edge Input 11

CTED12 15 24 I ST CTMU External Edge Input 12

CTED13 14 23 I ST CTMU External Edge Input 13

C1RX PPS PPS I ST Enhanced CAN Receive

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

(2)

(2)

(2)

35 55 P —

11 20 O — USB Host and OTG bus power control Output

37 57 I/O Analog USB D+

36 56 I/O Analog USB D-

33 51 I ST USB OTG ID Detect

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

Pin

Type

Buffer

Type

Description

USB internal transceiver supply. If the USB module is not
used, this pin must be connected to V

Data I/O pin for Programming/Debugging Communication
Channel 1

Clock Input pin for Programming/Debugging Communication
Channel 1

Data I/O Pin for Programming/Debugging Communication
Channel 2

Clock Input Pin for Programming/Debugging Communication
Channel 2

Data I/O Pin for Programming/Debugging Communication
Channel 3

Clock Input Pin for Programming/Debugging Communication
Channel 3

DD.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 22

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

C1TX PPS PPS O ST Enhanced CAN Transmit

MCLR

DD 19 30 P P

AV

SS 20 31 P P Ground reference for analog modules

AV

DD

V

VCAP 56 85 P — Capacitor for Internal Voltage Regulator

SS 9, 25, 41

V

REF+ 16 29 P Analog Analog Voltage Reference (High) Input

V

V

REF- 15 28 P Analog Analog Voltage Reference (Low) Input

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.
3: This pin is not available on 64-pin devices with a USB module.
4: This pin is only available on 100-pin devices without a USB module.

64-pin

QFN/

TQFP

713IST

10, 26, 38, 572, 16, 37,

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

100-pin

TQFP

46, 62, 86

15, 36, 45,

65, 75

Pin

Type

Buffer

Type

Master Clear (Reset) input. This pin is an active-low Reset to
the device.

Positive supply for analog modules. This pin must be
connected at all times.

P — Positive supply for peripheral logic and I/O pins

P — Ground reference for logic and I/O pins

Description

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 23

NOTES:

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 24

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

2.0 GUIDELINES FOR GETTING STARTED WITH 32-BI T MCUS

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the

“PIC32 Family Reference Manual”, which

is available from the Microchip web
(www.microchip.com/PIC32).

2.1 Basic Connection Requirements

Getting started with the PIC32MX1XX/2XX/5XX 64/
100-pin family of 32-bit Microcontrollers (MCUs)
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names, which must always be
connected:

• All VDD and VSS pins (see 2.2 “Decoupling

Capacitors”)

• All AVDD and AVSS pins, even if the ADC module is

not used (see 2.2 “Decoupling Capacitors”)

•VCAP pin (see 2.3 “Capacitor on Internal Voltage

Regulator (VCAP)”)

• MCLR pin (see 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins, used for In-Circuit Serial

Programming (ICSP™) and debugging purposes

2.5 “ICSP Pins”)

(see

• OSC1 and OSC2 pins, when external oscillator

source is used (see

The following pins may be required:

VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented

Note: The AVDD and AVSS pins must be

connected, regardless of ADC use and
the ADC voltage reference source.

2.8 “External Oscillator Pins”)

site

.

2.2 Decoupling Capacitors

The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.

Figure 2-1.

See

Consider the following criteria when using decoupling
capacitors:

• Value and type of capacitor: A value of 0.1 µF

(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance
frequency in the range of 20
further recommended that ceramic capacitors be
used.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within one­quarter inch (6

• Handling high frequency noise: If the board is

experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout

from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.

mm) in length.

MHz and higher. It is

µF to 0.001 µF. Place this

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 25

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

PIC32

VDD

VSS

VDD

VSS

VSS

VDD

AVDD

AVSS

VDD

VSS

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

C

10K

V

DD

MCLR

0.1 µF
Ceramic

L1

(2)

R1

Note 1: If the USB module is not used, this pin must be

connected to V

DD.

2: As an option, instead of a hard-wired connection, an

inductor (L1) can be substituted between V

DD and

AV

DD to improve ADC noise rejection. The inductor

impedance should be less than 3Ω and the inductor
capacity greater than 10 mA.

Where:

f

FCNV

2

------------- -=

f

1

2π LC()

-----------------------=

L

1

2πfC()

--------------------- -





2

=

(i.e., ADC conversion rate/2)

Connect

(2)

VUSB3V3

(1)

VCAP

Tantalum or
ceramic 10 µF
ESR ≤ 3Ω

(3)

2: Aluminum or electrolytic capacitors should not be

used. ESR ≤ 3Ω from -40ºC to 125ºC @ SYSCLK
frequency (i.e., MIPS).

1K

0.1 µF

Note 1: 470Ω ≤ R1 ≤ 1Ω will limit any current flowing into

MCLR

from the external capacitor C, in the event of

MCLR

pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR

pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.

2: The capacitor can be sized to prevent unintentional

Resets from brief glitches or to extend the device
Reset period during POR.

3: No pull-ups or bypass capacitors are allowed on

active debug/program PGECx/PGEDx pins.

R1

(1)

10k

V

DD

MCLR

PIC32

1 kΩ

0.1 µF

(2)

PGECx

(3)

PGEDx

(3)

ICSP™

1
5
4
2
3
6

V

DD

VSS
NC

R

C

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

2.4 Master Clear (MCLR) Pin

The MCLR pin provides two specific device
functions:

• Device Reset

• Device programming and debugging

Pulling The MCLR pin low generates a device Reset.

Figure 2-2 illustrates a typical MCLR circuit. During

device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the
levels (V
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.

For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the
operations.

Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

MCLR pin. Consequently, specific voltage

IH and VIL) and fast signal transitions must

MCLR pin during programming and debugging

CONNECTIONS

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47
the device as possible.

2.3 Capacitor on Internal Voltage

2.3.1 INTERNAL REGULATOR MODE

A low-ESR (3 ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regu­lator output. The VCAP pin must not be connected to

DD, and must have a CEFC capacitor, with at least a

V
6V rating, connected to ground. The type can be
ceramic or tantalum. Refer to

Electrical Characteristics” for additional information

on CEFC specifications.

DS60001290C-page 26 Preliminary  2014 Microchip Technology Inc.

µF. This capacitor should be located as close to

Regulator (V

CAP)

Section 31.0 “40 MHz

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high

IH) and input voltage low (VIL) requirements.

(V

Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to

®

MPLAB

For more information on MPLAB ICD 3 and MPLAB
REAL ICE connection requirements, refer to the follow
ing documents that are available on the Microchip web
site.

• “Using MPLAB® ICD 3” (poster) DS50001765

• “MPLAB® ICD 3 Design Advisory” DS50001764

• “MPLAB® REAL ICE™ In-Circuit Debugger

• “Using MPLAB® REAL ICE™ Emulator” (poster)

ICD 3 or MPLAB REAL ICE™.

User’s Guide” DS50001616

DS50001749

-

-

-

2.7 Trace

The trace pins can be connected to a hardware
trace-enabled programmer to provide a compressed
real-time instruction trace. When used for trace, the
TRD3, TRD2, TRD1, TRD0 and TRCLK pins should
be dedicated for this use. The trace hardware
requires a 22 Ohm series resistor between the trace
pins and the trace connector.

2.8 External Oscillator Pins

Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to

Configuration” for details).

The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator cir­cuit close to the respective oscillator pins, not exceed­ing one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator,
on the same side of the board. Use a grounded copper
pour around the oscillator circuit to isolate them from
surrounding circuits. The grounded copper pour should
be routed directly to the MCU ground. Do not run any
signal traces or power traces inside the ground pour.
Also, if using a two-sided board, avoid any traces on
the other side of the board where the crystal is placed.
A suggested layout is illustrated in

FIGURE 2-3: SUGGESTED OSCILLATOR

CIRCUIT PLACEMENT

Section 8.0 “Oscillator

Figure 2-3.

2.6 JTAG

The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.

Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete
components are an application requirement, they
should be removed from the circuit during
programming and debugging. Alternatively, refer to the
AC/DC characteristics and timing requirements
information in the respective device Flash
programming specification for information on
capacitive loading limits and pin input voltage high (V
and input voltage low (VIL) requirements.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 27

IH)

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Crystal manufacturer recommended: C1 = C2 = 15 pF

Therefore:

C

LOAD = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 + COUT] }

+ estimated oscillator PCB stray capacitance

= {( [5 + 15][5 + 15] ) / [5 + 15 + 15 + 5] } + 2.5 pF

= {( [20][20]) / [40] } + 2.5
= 10 + 2.5 = 12.5 pF

Rounded to the nearest standard value or 13 pF in this example for
Primary Oscillator crystals “C1” and “C2”.

OSC2 OSC1

1M

Typical XT

(4-10 MHz)

Circuit A

C1

C2

OSC2 OSC1

Typical HS

(10-25 MHz)

Circuit B

C1

C2

Rs

OSC2

OSC1

1M

Typical XT/HS

(4-25 MHz)

Circuit C

C1

C2

1M

Rs

OSC2 OSC1

Not Recommended

Circuit D

Not Recommended

1M

Rs

OSC2

OSC1

Circuit E

2.8.1 CRYSTAL OSCILLATOR DESIGN
CONSIDERATION

The following example assumptions are used to
calculate the Primary Oscillator loading capacitor
values:

•CIN = PIC32_OSC2_Pin Capacitance = ~4-5 pF

•COUT = PIC32_OSC1_Pin Capacitance = ~4-5 pF

• C1 and C2 = XTAL manufacturing recommended

loading capacitance

• Estimated PCB stray capacitance, (i.e.,12 mm

length) = 2.5 pF

EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR

CALCULATION

The following tips are used to increase oscillator gain,
(i.e., to increase peak-to-peak oscillator signal):

• Select a crystal with a lower “minimum” power drive

rating

• Select an crystal oscillator with a lower XTAL

manufacturing “ESR” rating.

• Add a parallel resistor across the crystal. The smaller

the resistor value the greater the gain. It is recom
mended to stay in the range of 600k to 1M

• C1 and C2 values also affect the gain of the oscillator.

The lower the values, the higher the gain.

• C2/C1 ratio also affects gain. To increase the gain,

make C1 slightly smaller than C2, which will also help
start-up performance.

Note: Do not add excessive gain such that the

oscillator signal is clipped, flat on top of
the sine wave. If so, you need to reduce
the gain or add a series resistor, RS, as
shown in circuit “C” in

Figure 2-4. Failure

to do so will stress and age the crystal,
which can result in an early failure. Adjust
the gain to trim the max peak-to-peak to

DD-0.6V. When measuring the oscilla-

~V
tor signal you must use a FET scope
probe or a probe with ≤ 1.5 pF or the
scope probe itself will unduly change the
gain and peak-to-peak levels.

2.8.1.1 Additional Microchip References

• AN588 “PICmicro® Microcontroller Oscillator

• AN826 “Crystal Oscillator Basics and Crystal

• AN849 “Basic PICmicro® Oscillator Design”

DS60001290C-page 28 Preliminary  2014 Microchip Technology Inc.

Design Guide”

Selection for rfPIC™ and PICmicro® Devices”

FIGURE 2-4: PRIMARY CRYSTAL

OSCILLATOR CIRCUIT
RECOMMENDATIONS

-

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

PIC32

SOSCO

SOSCI

2.2 K

33 pF

33 pF

Note 1: P/N: Epson MC-306 32.7680K-A0:ROHS.

Crystal

(1)

2.9 Unused I/Os

Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.

Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.

2.10 SOSC Design Recommendation

Figure 2-5 shows the recommended Sosc circuit

design. All components should be as close as possible
to the SOSCI and SOSCO pins of the PIC32 device,
(≤ 8 mm) and the capacitors should be ceramic-type.

FIGURE 2-5: RECOMMENDED

OSCILLATOR CIRCUIT
PLACEMENT

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 29

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Current Flow

CPU LOGIC

TRIS

ANSEL

I/O IN

I/O OUT

VSS

PIC32

AN2/RB0

On/Off

PIC32

POWER

SUPPLY

Non-5V Tolerant

Pin Architecture

V

DD

Remote

0.3V dVIH d 3.6V

Remote

GND

Note: When VDD power is OFF.

2.11 Considerations When Interfacing to Remotely Powered Circuits

2.11.1 NON-5V TOLERANT INPUT PINS

A quick review of the absolute maximum rating section

31.0 “40 MHz Electrical Characteristics” will indi-

in
cate that the voltage on any non-5v tolerant pin may not
exceed AVDD/VDD + 0.3V. Figure 2-6 shows an exam-
ple of a remote circuit using an independent power
source, which is powered while connected to a PIC32
non-5V tolerant circuit that is not powered.

FIGURE 2-6: PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE

DS60001290C-page 30 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

External VDD

PIC32

PIC32 VDD

Opto Digital

ISOLATOR

IN1

VSS

REMOTE_IN

Digital Isolator

PIC32 VDD

VSS

PIC32

Conn

IN1

OUT1

R

EMOTE_IN

REMOTE_OUT

External VDD

REMOTE_IN

External VDD

PIC32

PIC32 V

DD

IN

VSS

Digital Isolator

Analog_IN1

Analog_OUT2

External_V

DD1

PIC32 VDD

VSS

PIC32

Conn

Analog_IN2

S

Analog Switch

Analog / Digital Isolator

ENB

ENB

Without proper signal isolation, on non-5V tolerant

TABLE 2-1: EXAMPLES OF DIGITAL/

pins, the remote signal can power the PIC32 device
through the high side ESD protection diodes.
Besides violating the absolute maximum rating
specification when V

DD of the PIC32 device is

restored and ramping up or ramping down, it can
also negatively affect the internal Power-on Reset
(POR) and Brown-out Reset (BOR) circuits, which
can lead to improper initialization of internal PIC32
logic circuits. In these cases, it is recommended to

Example Digital/Analog

Signal Isolation Circuits

implement digital or analog signal isolation as
depicted in

Figure 2-7, as appropriate. This is

indicative of all industry microcontrollers and not just
Microchip products.

ADuM7241 / 40 ARZ (1 Mbps) X — — —

ADuM7241 / 40 CRZ (25 Mbps) X — — —

ISO721 — X — —

LTV-829S (2 Channel) — — X —

LTV-849S (4 Channel) — — X —

FSA266 / NC7WB66 — — — X

FIGURE 2-7: DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS

ANALOG ISOLATORS WITH
OPTIONAL LEVEL
TRANSLATION

Inductive Coupling

Opto Coupling

Capacitive Coupling

Analog/Digital Switch

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 31

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

CPU LOGIC

TRIS

ANSEL

I/O IN

I/O OUT

VSS

PIC32

RG10

On/Off

PIC32

POWER

SUPPLY

5V Tolerant Pin

Architecture

V

DD

Remote

V

IH = 2.5V

Remote

GND

Floating Bus

Oxide BV = 3.6V

if V

DD < 2.3V

OXIDE

2.11.2 5V TOLERANT INPUT PINS

The internal high side diode on 5V tolerant pins are
bussed to an internal floating node, rather than being
connected to V
on these pins, if VDD < 2.3V, should not exceed
roughly 3.2V relative to VSS of the PIC32 device.
Voltage of 3.6V or higher will violate the absolute
maximum specification, and will stress the oxide
layer separating the high side floating node, which
impacts device reliability. If a remotely powered
“digital-only” signal can be guaranteed to always be
≤ 3.2V relative to Vss on the PIC32 device side, a
5V tolerant pin could be used without the need for a
digital isolator. This is assuming there is not a
ground loop issue, logic ground of the two circuits
not at the same absolute level, and a remote logic
low input is not less than V

FIGURE 2-8: PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE

DD, as shown in Figure 2-8. Voltages

SS - 0.3V.

DS60001290C-page 32 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

CTMU

Current Source

ADC

Microchip

mTouch™

Library

User

Application

Microchip

Graphics

Library

Read the Touch Sensors

Process Samples

Display Data

Parallel

Master

Port

LCD Controller

Frame

Buffer

Display

Controller

PMD<7:0>

LCD

Panel

PIC32MX1XX/2XX/5XX

To AN6 To AN7 To AN8 To AN11

C1

R3

C2

R2

R3

R1

C5

C5

C5

C1

R1

R1

R1

C3

R2

C3

R2

C1

R2

C2

R3

C2

R3

C3

AN0

AN1

AN11

To A N 0

To A N 1

To AN5

AN9

PMWR

To A N 9

R1

C4

R2

C4

R3

C4

Audio

Codec

Display

PMP

I

2

S

SPI

USB

USB

PMD<7:0>

3

3

Stereo Headphones

Speaker

PIC32MX1XX/2XX/5XX

Host

PMWR

MMC SD

3

SDI

REFCLKO

2.12 Typical Application Connection

Examples

Examples of typical application connections are shown
in Figure 2-9, Figure 2-10, and Figure 2-11.

FIGURE 2-9: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION

FIGURE 2-10: AUDIO PLAYBACK APPLICATION

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 33

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

LCD Display

PIC32MX1XX/2XX/5XX

SRAM

CTMU

Microchip mTouch™

DMA

PMP

ADC

Projected Capacitive
Touch Overlay

GFX Libraries

External Frame Buffer

ANx

FIGURE 2-11: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH

PROJECTED CAPACITIVE TOUCH

DS60001290C-page 34 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

CPU

MDU

Execution Core
(RF/ALU/Shift)

FMT

TAP

EJTAG

Bus Interface

Power

Management

System

Co-processor

Off-chip Debug Interface

Bus Matrix

Dual Bus Interface

3.0 CPU

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data

sheet, refer to Section 2. “CPU”
(DS60001113) in the “PIC32 Family
Reference Manual”, which is available

from the Microchip web

www.microchip.com/PIC32). Resources

(
for the MIPS32® M4K® Processor Core
are available at http://www.imgtec.com.

The the MIPS32® M4K® Processor Core is the heart of
the PIC32MX1XX/2XX/5XX 64/100-pin device proces­sor. The CPU fetches instructions, decodes each
instruction, fetches source operands, executes each
instruction and writes the results of instruction
execution to the proper destinations.

3.1 Features

• 5-stage pipeline

• 32-bit address and data paths

• MIPS32® Enhanced Architecture (Release 2):

- Multiply-accumulate and multiply-subtract
instructions

- Targeted multiply instruction

- Zero/One detect instructions

- WAIT instruction

- Conditional move instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

- Atomic interrupt enable/disable

- GPR shadow registers to minimize latency
for interrupt handlers

- Bit field manipulation instructions

site

• MIPS16e® Code Compression:

- 16-bit encoding of 32-bit instructions to
improve code density

- Special PC-relative instructions for efficient
loading of addresses and constants

- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines

- Improved support for handling 8 and 16-bit
data types

• Simple Fixed Mapping Translation (FMT)

Mechanism:

• Simple Dual Bus Interface:

- Independent 32-bit address and data buses

- Transactions can be aborted to improve
interrupt latency

• Autonomous Multiply/Divide Unit (MDU):

- Maximum issue rate of one 32x16 multiply
per clock

- Maximum issue rate of one 32x32 multiply
every other clock

- Early-in iterative divide. Minimum 11 and

maximum 33 clock latency (dividend (rs) sign

extension-dependent)

• Power Control:

- Minimum frequency: 0 MHz

- Low-Power mode (triggered by WAIT instruction)

- Extensive use of local gated clocks

• EJTAG Debug and Instruction Trace:

- Support for single stepping

- Virtual instruction and data address/value

- Breakpoints

FIGURE 3-1: MIPS32® M4K® PROCESSOR CORE BLOCK DIAGRAM

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 35

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

3.2 Architecture Overview

The MIPS32® M4K® processor core contains several
logic blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:

• Execution Unit

• Multiply/Divide Unit (MDU)

• System Control Coprocessor (CP0)

• Fixed Mapping Translation (FMT)

• Dual Internal Bus interfaces

• Power Management

• MIPS16e

• Enhanced JTAG (EJTAG) Controller

3.2.1 EXECUTION UNIT

The MIPS32® M4K® processor core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit General Purpose Registers (GPRs)
used for integer operations and address calculation.
One additional register file shadow set (containing
thirty-two registers) is added to minimize context
switching overhead during interrupt/exception process
ing. The register file consists of two read ports and one
write port and is fully bypassed to minimize operation
latency in the pipeline.

The execution unit includes:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction
address

• Logic for branch determination and branch target
address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results

• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions

• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations

• Shifter and store aligner

®

Support

-

3.2.2 MULTIPLY/DIVIDE UNIT (MDU)

The MIPS32® M4K® processor core includes a Multi­ply/Divide Unit (MDU) that contains a separate pipeline
for multiply and divide operations. This pipeline oper
ates in parallel with the Integer Unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows
MDU operations to be partially masked by system stalls
and/or other integer unit instructions.

The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown

(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt) oper

and to determine how many times the operation must
pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.

The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.

Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection

checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit
wide rs, 15 iterations are skipped and for a 24-bit wide
rs, 7 iterations are skipped. Any attempt to issue a sub

sequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles

until the operation can be reissued) and latency (num­ber of cycles until a result is available) for the PIC32
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.

-

-

-

TABLE 3-1: MIPS32® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/

DIVIDE UNIT LATENCIES AND REPEAT RATES

Op code Operand Size (mul rt) (div rs) Latency Repeat Rate

MULT/MULTU, MADD/MADDU,
MSUB/MSUBU

MUL 16 bits 2 1

DIV/DIVU 8 bits 12 11

DS60001290C-page 36 Preliminary  2014 Microchip Technology Inc.

16 bits 1 1
32 bits 2 2

32 bits 3 2

16 bits 19 18
24 bits 26 25
32 bits 33 32

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move­From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.

In addition to the HI/LO targeted operations, the
MIPS32® architecture also defines a multiply instruction,
MUL, which places the least significant results in the pri

­mary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple desti

-

3.2.3 SYSTEM CONTROL

COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura
tion information, such as presence of options like
MIPS16e
registers, listed in Ta bl e 3-2.

®

, is also available by accessing the CP0

nation registers, the throughput of multiply-intensive
operations is increased.

Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.

TABLE 3-2: COPROCESSOR 0 REGISTERS

Register
Number

0-6 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

7 HWREna Enables access via the RDHWR instruction to selected hardware registers.

8 BadVAddr

9 Count

10 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

11 Compare

12 Status

12 IntCtl

12 SRSCtl

12 SRSMap

13 Cause

14 EPC

15 PRId Processor identification and revision.

15 EBASE Exception vector base register.

16 Config Configuration register.

16 Config1 Configuration register 1.

16 Config2 Configuration register 2.

16 Config3 Configuration register 3.

17-22 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

23 Debug

24 DEPC

25-29 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

30 ErrorEPC

31 DESAVE

Note 1: Registers used in exception processing.

2: Registers used during debug.

Register

Name

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(2)

(2)

(1)

(2)

Function

Reports the address for the most recent address-related exception.

Processor cycle count.

Timer interrupt control.

Processor status and control.

Interrupt system status and control.

Shadow register set status and control.

Provides mapping from vectored interrupt to a shadow set.

Cause of last general exception.

Program counter at last exception.

Debug control and exception status.

Program counter at last debug exception.

Program counter at last error.

Debug handler scratchpad register.

-

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 37

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors.
the exception types in order of priority.

TABLE 3-3: MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES

Exception Description

Reset Assertion MCLR or a Power-on Reset (POR).

DSS EJTAG debug single step.

DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the

EjtagBrk bit in the ECR register.

NMI Assertion of NMI signal.

Interrupt Assertion of unmasked hardware or software interrupt signal.

DIB EJTAG debug hardware instruction break matched.

AdEL Fetch address alignment error. Fetch reference to protected address.

IBE Instruction fetch bus error.

DBp EJTAG breakpoint (execution of SDBBP instruction).

Sys Execution of SYSCALL instruction.

Bp Execution of BREAK instruction.

RI Execution of a reserved instruction.

CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.

CEU Execution of a CorExtend instruction when CorExtend is not enabled.

Ov Execution of an arithmetic instruction that overflowed.

Tr Execution of a trap (when trap condition is true).

DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).

AdEL Load address alignment error. Load reference to protected address.

AdES Store address alignment error. Store to protected address.

DBE Load or store bus error.

DDBL EJTAG data hardware breakpoint matched in load data compare.

Table 3-3 lists

3.3 Power Management

The MIPS® M4K® processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or Halting the clocks, which reduces
system power consumption during Idle periods.

3.3.1 INSTRUCTION-CONTROLLED
POWER MANAGEMENT

The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more

information on power management, see Section 27.0

“Power-Saving Features”.

3.3.2 LOCAL CLOCK GATING

The majority of the power consumed by the PIC32MX­1XX/2XX/5XX 64/100-pin family core is in the clock
tree and clocking registers. The PIC32MX family uses
extensive use of local gated-clocks to reduce this
dynamic power consumption.

DS60001290C-page 38 Preliminary  2014 Microchip Technology Inc.

3.4 EJTAG Debug Support

The MIPS® M4K® processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the soft­ware debug of application and kernel code. In addition
to standard User mode and Kernel modes of operation,
the M4K® core provides a Debug mode that is entered
after a debug exception (derived from a hardware
breakpoint, single-step exception, etc.) is taken and
continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.

The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans­ferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

4.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be a
comprehensive reference source.For

detailed information, refer to Section 3.
“Memory Organization” (DS60001115)
in the “PIC32 Family Reference Manual”,

which is available from the Microchip

site (www.microchip.com/PIC32).

web

PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers
provide 4 GB of unified virtual memory address space.
All memory regions, including program, data memory,
SFRs and Configuration registers, reside in this
address space at their respective unique addresses.
The program and data memories can be optionally par
titioned into user and kernel memories. In addition, the
data memory can be made executable, allowing
PIC32MX1XX/2XX/5XX 64/100-pin devices to execute
from data memory.

The key features include:

• 32-bit native data width

• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1) mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and
program space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept
runaway code

• Simple memory mapping with Fixed Mapping
Translation (FMT) unit

• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions

-

4.1 Memory Layout

PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers
implement two address schemes: virtual and physical.
All hardware resources, such as program memory,
data memory and peripherals, are located at their
respective physical addresses. Virtual addresses are
exclusively used by the CPU to fetch and execute
instructions as well as access peripherals. Physical
addresses are used by bus master peripherals, such as
DMA and the Flash controller, that access memory
independently of the CPU.

The memory maps for the PIC32MX1XX/2XX/5XX 64/
100-pin devices are illustrated in Figure 4-1 through

Figure 4-4.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 39

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF

Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF

Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0002000

0xA0001FFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved

Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D010000

Reserved

Program Flash

(2)

0x1D00FFFF

0x80002000

0x80001FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00002000

Reserved RAM

(2)

0x00001FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool
documentation for information).

KSEG1KSEG0

FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 64 KB OF PROGRAM MEMORY + 8 KB RAM

DS60001290C-page 40 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF

Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF

Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved

Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D020000

Reserved

Program Flash

(2)

0x1D01FFFF

0x80004000

0x80003FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM

(2)

0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool
documentation for information).

KSEG1KSEG0

FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 128 KB OF PROGRAM MEMORY + 16 KB RAM

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 41

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF

Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF

Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD040000

0xBD03FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved

Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D040000 0x1F800000

0x9D03FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D040000

Reserved

Program Flash

(2)

0x1D03FFFF

0x80008000

0x80007FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM

(2)

0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool
documentation for information).

KSEG1KSEG0

FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 256 KB OF PROGRAM MEMORY + 32 KB RAM

DS60001290C-page 42 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF

Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF

Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD080000

0xBD07FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0010000

0xA000FFFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved

Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D080000 0x1F800000

0x9D07FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D080000

Reserved

Program Flash

(2)

0x1D07FFFF

0x80010000

0x8000FFFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00010000

Reserved RAM

(2)

0x0000FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool
documentation for information).

KSEG1KSEG0

FIGURE 4-4: MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY + 64 KB RAM

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 43

DS60001290C-page 44 Preliminary  2014 Microchip Technology Inc.

4.2 Special Function Register Maps

TABLE 4-1: BUS MATRIX REGISTER MAP

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bits

Name

Register

(BF88_#)

Virtual Address

2000 BMXCON

2010 BMXDKPBA

2020 BMXDUDBA

2030 BMXDUPBA

2040 BMXDRMSZ

2050 BMXPUPBA

2060 BMXPFMSZ

2070 BMXBOOTSZ

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for more information.

(1)

(1)

(1)

(1)

(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 041F

— — — — — — — — —BMXWSDRM— — — BMXARB<2:0> 0047

15:0

31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDKPBA<15:0> 0000

31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUDBA<15:0> 0000

31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUPBA<15:0> 0000

31:16

15:0 xxxx

31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000

15:0 BMXPUPBA<15:0> 0000

31:16

15:0 xxxx

31:16

15:0 0000

BMXDRMSZ<31:0>

BMXPFMSZ<31:0>

BMXBOOTSZ<31:0>

All

xxxx

xxxx

0000

Resets

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

4.3 Control Registers

Register 4-1 through Register 4-8 are used for setting

the RAM and Flash memory partitions for data and
code.

REGISTER 4-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 R/W-1 U-0 U-0

— — — — —

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

BMX

ERRIXI

Bit

27/19/11/3

BMX

ERRICD

Bit

26/18/10/2

BMX

CHEDMA

BMX

ERRDMA

25/17/9/1

BMX

ERRDS

— — — — — — — —

U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1

—

BMX

WSDRM

— — — BMXARB<2:0>

Bit

24/16/8/0

— —

BMX

ERRIS

Bit

bit 31-27 Unimplemented: Read as ‘0’
bit 26 BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit

1 = Enable program Flash memory (data) cacheability for DMA accesses (requires cache to have data

caching enabled)

0 = Disable program Flash memory (data) cacheability for DMA accesses

(hits are still read from the cache, but misses do not update the cache)

bit 25-21 Unimplemented: Read as ‘0’
bit 20 BMXERRIXI: Enable Bus Error from IXI bit

1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus

bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit

1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD

bit 18 BMXERRDMA: Bus Error from DMA bit

1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA

bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)

1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access

bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)

1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access

bit 15-7 Unimplemented: Read as ‘0’
bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit

1 = Data RAM accesses from CPU have one wait state for address setup
0 = Data RAM accesses from CPU have zero wait states for address setup

bit 5-3 Unimplemented: Read as ‘0’
bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits

111 = Reserved (using these configuration modes will produce undefined behavior)

•

•

•

011 = Reserved (using these configuration modes will produce undefined behavior)
010 = Arbitration Mode 2
001 = Arbitration Mode 1 (default)
000 = Arbitration Mode 0

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 45

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 4-2: BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits

bit 9-0 BMXDKPBA<9:0>: Read-Only bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

When non-zero, this value selects the relative base address for kernel program space in RAM

Value is always ‘0’, which forces 1 KB increments

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

BMXDKPBA<15:8>

BMXDKPBA<7:0>

27/19/11/3

Bit

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

DS60001290C-page 46 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 4-3: BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits

bit 9-0 BMXDUDBA<9:0>: Read-Only bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

When non-zero, the value selects the relative base address for User mode data space in RAM, the value
must be greater than BMXDKPBA.

Value is always ‘0’, which forces 1 KB increments

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

BMXDUDBA<15:8>

BMXDUDBA<7:0>

27/19/11/3

Bit

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 47

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 4-4: BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits

bit 9-0 BMXDUPBA<9:0>: Read-Only bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

When non-zero, the value selects the relative base address for User mode program space in RAM,
BMXDUPBA must be greater than BMXDUDBA.

Value is always ‘0’, which forces 1 KB increments

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

BMXDUPBA<15:8>

BMXDUPBA<7:0>

27/19/11/3

Bit

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

Bit

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

DS60001290C-page 48 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 4-5: BMXDRMSZ: DATA RAM SIZE REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits

Bit

31/23/15/7

RRRRR R R R

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

BMXDRMSZ<31:24>

RRRRR R R R

BMXDRMSZ<23:16>

RRRRR R R R

BMXDRMSZ<15:8>

RRRRR R R R

BMXDRMSZ<7:0>

Static value that indicates the size of the Data RAM in bytes:
0x00002000 = Device has 8 KB RAM
0x00004000 = Device has 16 KB RAM
0x00008000 = Device has 32 KB RAM
0x00010000 = Device has 64 KB RAM

Bit

24/16/8/0

REGISTER 4-6: BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS

REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-20 Unimplemented: Read as ‘0’
bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits
bit 10-0 BMXPUPBA<10:0>: Read-Only bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

30/22/14/6

— — — — — — — —

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — BMXPUPBA<19:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Value is always ‘0’, which forces 2 KB increments

Bit

29/21/13/5

Bit

Bit

28/20/12/4

27/19/11/3

BMXPUPBA<15:8>

BMXPUPBA<7:0>

Bit

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

Bit

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXPFMSZ.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 49

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 4-7: BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits

Bit

31/23/15/7

RRRRR R R R

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

BMXPFMSZ<31:24>

RRRRR R R R

BMXPFMSZ<23:16>

RRRRR R R R

BMXPFMSZ<15:8>

RRRRR R R R

BMXPFMSZ<7:0>

Static value that indicates the size of the PFM in bytes:
0x00010000 = Device has 64 KB Flash
0x00020000 = Device has 128 KB Flash
0x00040000 = Device has 256 KB Flash
0x00080000 = Device has 512 KB Flash

Bit

24/16/8/0

REGISTER 4-8: BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits

Bit

31/23/15/7

R R R R R R R R

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

BMXBOOTSZ<31:24>

R R R R R R R R

BMXBOOTSZ<23:16>

R R R R R R R R

BMXBOOTSZ<15:8>

R R R R R R R R

BMXBOOTSZ<7:0>

Static value that indicates the size of the Boot PFM in bytes:
0x00000C00 = Device has 3 KB Boot Flash

Bit

24/16/8/0

DS60001290C-page 50 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Interrupt Controller

Interrupt Requests

Vector Number

CPU Core

Priority Level

5.0 INTERRUPT CONTROLLER

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data

sheet, refer to Section 8. “Interrupt

Controller” (DS60001108) in the “PIC32
Family Reference Manual”, which

available from the Microchip web site
(www.microchip.com/PIC32).

PIC32MX1XX/2XX/5XX 64/100-pin devices generate
interrupt requests in response to interrupt events from
peripheral modules. The interrupt control module exists
externally to the CPU logic and prioritizes the interrupt
events before presenting them to the CPU.

is

The PIC32MX1XX/2XX/5XX 64/100-pin interrupt
module includes the following features:

• Up to 76 interrupt sources

• Up to 46 interrupt vectors

• Single and multi-vector mode operations

• Five external interrupts with edge polarity control

• Interrupt proximity timer

• Seven user-selectable priority levels for each
vector

• Four user-selectable subpriority levels within each
priority

• Software can generate any interrupt

• User-configurable interrupt vector table location

• User-configurable interrupt vector spacing

Note: The dedicated shadow register set is not

available on these devices.

FIGURE 5-1: INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 51

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 5-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION

Interrupt Source

CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No

CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No

CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No

INT0 – External Interrupt 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No

T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No

IC1E – Input Capture 1 Error 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> Yes

IC1 – Input Capture 1 6 5 IFS0<6> IEC0<6> IPC1<12:10> IPC1<9:8> Yes

OC1 – Output Compare 1 7 6 IFS0<7> IEC0<7> IPC1<20:18> IPC1<17:16> No

INT1 – External Interrupt 1 8 7 IFS0<8> IEC0<8> IPC1<28:26> IPC1<25:24> No

T2 – Timer2 9 8 IFS0<9> IEC0<9> IPC2<4:2> IPC2<1:0> No

IC2E – Input Capture 2 10 9 IFS0<10> IEC0<10> IPC2<12:10> IPC2<9:8> Yes

IC2 – Input Capture 2 11 9 IFS0<11> IEC0<11> IPC2<12:10> IPC2<9:8> Yes

OC2 – Output Compare 2 12 10 IFS0<12> IEC0<12> IPC2<20:18> IPC2<17:16> No

INT2 – External Interrupt 2 13 11 IFS0<13> IEC0<13> IPC2<28:26> IPC2<25:24> No

T3 – Timer3 14 12 IFS0<14> IEC0<14> IPC3<4:2> IPC3<1:0> No

IC3E – Input Capture 3 15 13 IFS0<15> IEC0<15> IPC3<12:10> IPC3<9:8> Yes

IC3 – Input Capture 3 16 13 IFS0<16> IEC0<16> IPC3<12:10> IPC3<9:8> Yes

OC3 – Output Compare 3 17 14 IFS0<17> IEC0<17> IPC3<20:18> IPC3<17:16> No

INT3 – External Interrupt 3 18 15 IFS0<18> IEC0<18> IPC3<28:26> IPC3<25:24> No

T4 – Timer4 19 16 IFS0<19> IEC0<19> IPC4<4:2> IPC4<1:0> No

IC4E – Input Capture 4 Error 20 17 IFS0<20> IEC0<20> IPC4<12:10> IPC4<9:8> Yes

IC4 – Input Capture 4 21 17 IFS0<21> IEC0<21> IPC4<12:10> IPC4<9:8> Yes

OC4 – Output Compare 4 22 18 IFS0<22> IEC0<22> IPC4<20:18> IPC4<17:16> No

INT4 – External Interrupt 4 23 19 IFS0<23> IEC0<23> IPC4<28:26> IPC4<25:24> No

T5 – Timer5 24 20 IFS0<24> IEC0<24> IPC5<4:2> IPC5<1:0> No

IC5E – Input Capture 5 Error 25 21 IFS0<25> IEC0<25> IPC5<12:10> IPC5<9:8> Yes

IC5 – Input Capture 5 26 21 IFS0<26> IEC0<26> IPC5<12:10> IPC5<9:8> Yes

OC5 – Output Compare 5 27 22 IFS0<27> IEC0<27> IPC5<20:18> IPC5<17:16> No

AD1 – ADC1 Convert done 28 23 IFS0<28> IEC0<28> IPC5<28:26> IPC5<25:24> Yes

FSCM – Fail-Safe Clock Monitor 29 24 IFS0<29> IEC0<29> IPC6<4:2> IPC6<1:0> No

RTCC – Real-Time Clock and Calendar 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> No

FCE – Flash Control Event 31 26 IFS0<31> IEC0<31> IPC6<20:18> IPC6<17:16> No

CMP1 – Comparator Interrupt 32 27 IFS1<0> IEC1<0> IPC6<28:26> IPC6<25:24> No

CMP2 – Comparator Interrupt 33 28 IFS1<1> IEC1<1> IPC7<4:2> IPC7<1:0> No

USB – USB Interrupts 34 29 IFS1<2> IEC1<2> IPC7<12:10> IPC7<9:8> Yes

SPI1E – SPI1 Fault 35 30 IFS1<3> IEC1<3> IPC7<20:18> IPC7<17:16> Yes

SPI1RX – SPI1 Receive Done 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> Yes

SPI1TX – SPI1 Transfer Done 37 30 IFS1<5> IEC1<5> IPC7<20:18> IPC7<17:16> Yes

U1E – UART1 Fault 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> Yes

U1RX – UART1 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> Yes

U1TX – UART1 Transfer Done 40 31 IFS1<8> IEC1<8> IPC7<28:26> IPC7<25:24> Yes

I2C1B – I2C1 Bus Collision Event 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> Yes

I2C1S – I2C1 Slave Event 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0> Yes

I2C1M – I2C1 Master Event 43 32 IFS1<11> IEC1<11> IPC8<4:2> IPC8<1:0> Yes

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX/2XX/5XX 64/100-pin Controller

Family Features” for the list of available peripherals.

2: This interrupt source is not available on 64-pin devices.

(1)

IRQ #

Vector

#

Highest Natural Order Priority

Flag Enable Priority Sub-priority

Interrupt Bit Location

Persistent

Interrupt

DS60001290C-page 52 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 5-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source

CNA – PORTA Input Change Interrupt 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> Yes

CNB – PORTB Input Change Interrupt 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> Yes

CNC – PORTC Input Change Interrupt 46 33 IFS1<14> IEC1<14> IPC8<12:10> IPC8<9:8> Yes

CND – PORTD Input Change Interrupt 47 33 IFS1<15> IEC1<15> IPC8<12:10> IPC8<9:8> Yes

CNE – PORTE Input Change Interrupt 48 33 IFS1<16> IEC1<16> IPC8<12:10> IPC8<9:8> Yes

CNF – PORTF Input Change Interrupt 49 33 IFS1<17> IEC1<17> IPC8<12:10> IPC8<9:8> Yes

CNG – PORTG Input Change Interrupt 50 33 IFS1<18> IEC1<18> IPC8<12:10> IPC8<9:8> Yes

PMP – Parallel Master Port 51 34 IFS1<19> IEC1<19> IPC8<20:18> IPC8<17:16> Yes

PMPE – Parallel Master Port Error 52 34 IFS1<20> IEC1<20> IPC8<20:18> IPC8<17:16> Yes

SPI2E – SPI2 Fault 53 35 IFS1<21> IEC1<21> IPC8<28:26> IPC8<25:24> Yes

SPI2RX – SPI2 Receive Done 54 35 IFS1<22> IEC1<22> IPC8<28:26> IPC8<25:24> Yes

SPI2TX – SPI2 Transfer Done 55 35 IFS1<23> IEC1<23> IPC8<28:26> IPC8<25:24> Yes

U2E – UART2 Error 56 36 IFS1<24> IEC1<24> IPC9<4:2> IPC9<1:0> Yes

U2RX – UART2 Receiver 57 36 IFS1<25> IEC1<25> IPC9<4:2> IPC9<1:0> Yes

U2TX – UART2 Transmitter 58 36 IFS1<26> IEC1<26> IPC9<4:2> IPC9<1:0> Yes

I2C2B – I2C2 Bus Collision Event 59 37 IFS1<27> IEC1<27> IPC9<12:10> IPC9<9:8> Yes

I2C2S – I2C2 Slave Event 60 37 IFS1<28> IEC1<28> IPC9<12:10> IPC9<9:8> Yes

I2C2M – I2C2 Master Event 61 37 IFS1<29> IEC1<29> IPC9<12:10> IPC9<9:8> Yes

U3E – UART3 Error 62 38 IFS1<30> IEC1<30> IPC9<20:18> IPC9<17:16> Yes

U3RX – UART3 Receiver 63 38 IFS1<31> IEC1<31> IPC9<20:18> IPC9<17:16> Yes

U3TX – UART3 Transmitter 64 38 IFS2<0> IEC2<0> IPC9<20:18> IPC9<17:16> Yes

U4E – UART4 Error 65 39 IFS2<1> IEC2<1> IPC9<28:26> IPC9<25:24> Yes

U4RX – UART4 Receiver 66 39 IFS2<2> IEC2<2> IPC9<28:26> IPC9<25:24> Yes

U4TX – UART4 Transmitter 67 39 IFS2<3> IEC2<3> IPC9<28:26> IPC9<25:24> Yes

U5E – UART5 Error

U5RX – UART5 Receiver

U5TX – UART5 Transmitter

CTMU – CTMU Event

DMA0 – DMA Channel 0 72 42 IFS2<8> IEC2<8> IPC10<20:18> IPC10<17:16> No

DMA1 – DMA Channel 1 73 43 IFS2<9> IEC2<9> IPC10<28:26> IPC10<25:24> No

DMA2 – DMA Channel 2 74 44 IFS2<10> IEC2<10> IPC11<4:2> IPC11<1:0> No

DMA3 – DMA Channel 3 75 45 IFS2<11> IEC2<11> IPC11<12:10> IPC11<9:8> No

CMP3 – Comparator 3 Interrupt 76 46 IFS2<12> IEC2<12> IPC11<20:18> IPC11<17:16> No

CAN1 – CAN1 Event 77 47 IFS2<13> IEC2<13> IPC11<28:26> IPC11<25:24> Yes

SPI3E – SPI3 Fault 78 48 IFS2<14> IEC2<14> IPC12<4:2> IPC12<1:0> Yes

SPI3RX – SPI3 Receive Done 79 48 IFS2<15> IEC2<15> IPC12<4:2> IPC12<1:0> Yes

SPI3TX – SPI3 Transfer Done 80 48 IFS2<16> IEC2<16> IPC12<4:2> IPC12<1:0> Yes

SPI4E – SPI4 Fault

SPI4RX – SPI4 Receive Done

SPI4TX – SPI4 Transfer Done

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX/2XX/5XX 64/100-pin Controller

Family Features” for the list of available peripherals.

2: This interrupt source is not available on 64-pin devices.

(1)

(2)

(2)

(2)

(2)

(2)

(2)
(2)

Vector

IRQ #

68 40 IFS2<4> IEC2<4> IPC10<4:2> IPC10<1:0> Yes

69 40 IFS2<5> IEC2<5> IPC10<4:2> IPC10<1:0> Yes

70 40 IFS2<6> IEC2<6> IPC10<4:2> IPC10<1:0> Yes

71 41 IFS2<7> IEC2<7> IPC10<12:10> IPC10<9:8> Yes

81 49 IFS2<17> IEC2<17> IPC12<12:10> IPC12<9:8> Yes

82 49 IFS2<18> IEC2<18> IPC12<12:10> IPC12<9:8> Yes

83 49 IFS2<19> IEC2<19> IPC12<12:10> IPC12<9:8> Yes

#

Lowest Natural Order Priority

Flag Enable Priority Sub-priority

Interrupt Bit Location

Persistent

Interrupt

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 53

DS60001290C-page 54 Preliminary  2014 Microchip Technology Inc.

5.1 Interrupts Control Registers

TABLE 5-2: INTERRUPT REGISTER MAP

Bits

(3)

Name

Register

(BF88_#)

Virtual Address

1000 INTCON

1010 INTSTAT

1020 IPTMR

1030 IFS0

1040 IFS1

1050 IFS2

1060 IEC0

1070 IEC1

1080 IEC2

1090 IPC0

10A0 IPC1

10B0 IPC2

10C0 IPC3

10D0 IPC4

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is only available on 100-pin devices.

(4)

2: This bit is only implemented on devices with a USB module.
3: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,

SET, and INV Registers” for more information.

4: This register does not have associated CLR, SET, and INV registers.
5: This bit is only implemented on devices with a CAN module.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — — — — — — — — — — — — — — SS0 0000

15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000

31:16

15:0 0000

31:16 FCEIF RTCCIF FSCMIF AD1IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000

15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000

31:16 U3RXIF U3EIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF CNGIF CNFIF CNEIF 0000

15:0 CNDIF CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF USBIF

31:16 — — — — — — — — — — — — SPI4TXIF

15:0 SPI3RXIF SPI3EIF CANIF CMP3IF DMA3IF DMA2IF DMA1IF DMA0IF CTMUIF U5TXIF

31:16 FCEIE RTCCIE FSCMIE AD1IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000

15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000

31:16 U3RXIE U3EIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE CNGIE CNFIE CNEIE 0000

15:0 CNDIE CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE USBIE

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — DMA3IE DMA2IE DMA1IE DMA0IE CTMUIE U5TXIE

31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000

15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000

31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000

15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000

31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000

31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000

15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000

31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000

IPTMR<31:0>

(1)

(1)

U5RXIF

U5RXIE

(2)

(1)

(1)

(1)

U5EIF

U5EIE

(1)

U4TXIF U4RXIF U4EIF U3TXIF 0000

(1)

U4TXIE U4RXIE U4EIE U3TXIE 0000

SPI4RXIF

CMP2IF CMP1IF 0000

(1)

SPI4EIF

(2)

CMP2IE CMP1IE 0000

(1)

SPI3TXIF 0000

All

0000

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Resets

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 55

TABLE 5-2: INTERRUPT REGISTER MAP (CONTINUED)

Bits

(3)

Name

Register

(BF88_#)

Virtual Address

10E0 IPC5

10F0 IPC6

1100 IPC7

1110 IPC8

1120 IPC9

1130 IPC10

1140 IPC11

1150 IPC12

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is only available on 100-pin devices.

2: This bit is only implemented on devices with a USB module.
3: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,

SET, and INV Registers” for more information.

4: This register does not have associated CLR, SET, and INV registers.
5: This bit is only implemented on devices with a CAN module.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000

15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000

31:16 — — — CMP1IP<2:0> CMP1IS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000

15:0 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000

31:16 — — — U1IP<2:0> U1IS<1:0> — — — SPI1IP<2:0> SPI1IS<1:0> 0000

15:0 — — — USBIP<2:0>

31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000

15:0 — — — CNIP<2:0> CNIS<1:0> — — — I2C1IP<2:0> I2C1IS<1:0> 0000

31:16 — — — U4IP<2:0> U4IS<1:0> — — — U3IP<2:0> U3IS<1:0> 0000

15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000

31:16 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000

15:0 — — — CTMUIP<2:0> CTMUIS<1:0> — — — U5IP<2:0> U5IS<1:0> 0000

31:16 — — — CANIP<2:0>

15:0 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — SPI4P<2:0>

(2)

(5)

(1)

USBIS<1:0>

CANIS<1:0>

SPI4S<1:0>

(2)

(5)

(1)

— — — CMP2IP<2:0> CMP2IS<1:0> 0000

— — — CMP3IP<2:0> CMP3IS<1:0> 0000

— — — SPI3P<2:0> SPI3S<1:0> 0000

All

Resets

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 5-1: INTCON: INTERRUPT CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-17 Unimplemented: Read as ‘0’
bit 16 SS0: Single Vector Shadow Register Set bit

bit 15-13 Unimplemented: Read as ‘0’
bit 12 MVEC: Multi Vector Configuration bit

bit 11 Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits

bit 7-5 Unimplemented: Read as ‘0’
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit

bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit

bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit

bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit

bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —SS0

U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

— — — MVEC —TPC<2:0>

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set

1 = Interrupt controller configured for multi vectored mode
0 = Interrupt controller configured for single vectored mode

111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer

1 = Rising edge
0 = Falling edge

1 = Rising edge
0 = Falling edge

1 = Rising edge
0 = Falling edge

1 = Rising edge
0 = Falling edge

1 = Rising edge
0 = Falling edge

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

DS60001290C-page 56 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 5-2: INTSTAT: INTERRUPT STATUS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — —SRIPL<2:0>

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — VEC<5:0>

(1)

(1)

Bit

24/16/8/0

bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 SRIPL<2:0>: Requested Priority Level bits

(1)

111-000 = The priority level of the latest interrupt presented to the CPU

bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 VEC<5:0>: Interrupt Vector bits

(1)

11111-00000 = The interrupt vector that is presented to the CPU

Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.

REGISTER 5-3: IPTMR: INTERRUPT PROXIMITY TIMER REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

IPTMR<31:24>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IPTMR<23:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IPTMR<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IPTMR<7:0>

Bit

24/16/8/0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits

Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 57

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 5-4: IFSx: INTERRUPT FLAG STATUS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IFS31-IFS0: Interrupt Flag Status bits

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS9 IFS8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 IFS1 IFS0

1 = Interrupt request has occurred
0 = No interrupt request has occurred

Bit

24/16/8/0

Note: This register represents a generic definition of the IFSx register. Refer to Table 5-1 for the exact bit

definitions.

REGISTER 5-5: IECx: INTERRUPT ENABLE CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IEC31-IEC0: Interrupt Enable bits

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC9 IEC8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC7 IEC6 IEC5 IEC4 IEC3 IEC2 IEC1 IEC0

1 = Interrupt is enabled
0 = Interrupt is disabled

Bit

Note: This register represents a generic definition of the IECx register. Refer to Tab le 5-1 for the exact bit

definitions.

DS60001290C-page 58 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 5-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP3<2:0>: Interrupt Priority bits

bit 25-24 IS3<1:0>: Interrupt Subpriority bits

bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP2<2:0>: Interrupt Priority bits

bit 17-16 IS2<1:0>: Interrupt Subpriority bits

bit 15-13 Unimplemented: Read as ‘0’
bit 12-10 IP1<2:0>: Interrupt Priority bits

Bit

31/23/15/7

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — —IP3<2:0> IS3<1:0>

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —IP2<2:0> IS2<1:0>

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —IP1<2:0> IS1<1:0>

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —IP0<2:0> IS0<1:0>

111 = Interrupt priority is 7

•

•

•

010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled

11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0

111 = Interrupt priority is 7

•

•

•

010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled

11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0

111 = Interrupt priority is 7

•

•

•

010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled

Bit

24/16/8/0

Note: This register represents a generic definition of the IPCx register. Refer to Table 5-1 for the exact bit

definitions.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 59

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 5-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)

bit 9-8 IS1<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0

bit 7-5 Unimplemented: Read as ‘0’
bit 4-2 IP0<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

•

•

010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled

bit 1-0 IS0<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0

Note: This register represents a generic definition of the IPCx register. Refer to Table 5-1 for the exact bit

definitions.

DS60001290C-page 60 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

6.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data

sheet, refer to Section 5. “Flash
Program Memory” (DS60001121) in the
“PIC32 Family Reference Manual”, which

is available from the Microchip web site
(www.microchip.com/PIC32).

PIC32MX1XX/2XX/5XX 64/100-pin devices contain an
internal Flash program memory for executing user
code. There are three methods by which the user can
program this memory:

• Run-Time Self-Programming (RTSP)

• EJTAG Programming

• In-Circuit Serial Programming™ (ICSP™)

RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP

techniques is available in Section 5. “Flash Program

Memory” (DS60001121) in the “PIC32 Family
Reference Manual”.

EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.

ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.

The EJTAG and ICSP methods are described in the

“PIC32 Flash Programming Specification”

(DS60001145), which can be downloaded from the
Microchip web site.

Note: On PIC32MX1XX/2XX/5XX 64/100-pin

devices, the Flash page size is 1 KB and
the row size is 128 bytes (256 IW and

IW, respectively).

32

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 61

DS60001290C-page 62 Preliminary  2014 Microchip Technology Inc.

6.1 Control Registers

TABLE 6-1: FLASH CONTROLLER REGISTER MAP

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bits

Name

Register

(BF80_#)

Virtual Address

NVMSRC

ADDR

information.

(1)

(1)

F400 NVMCON

F410 NVMKEY

F420

NVMADDR

F430 NVMDATA

F440

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET , and INV Registers” for more

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — — — — — — — — — — — — — — — 0000

15:0 WR WREN WRERR LVDERR LVD STAT — — — — — — — NVMOP<3:0> 0000

31:16

15:0 0000

31:16

15:0 0000

31:16

15:0 0000

31:16

15:0 0000

NVMKEY<31:0>

NVMADDR<31:0>

NVMDATA<31:0>

NVMSRCADDR<31:0>

All Resets

0000

0000

0000

0000

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 6-1: NVMCON: PROGRAMMING CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15 WR: Write Control bit

bit 14 WREN: Write Enable bit

bit 13 WRERR: Write Error bit

bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)

bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)

bit 10-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R-0 R-0 R-0 U-0 U-0 U-0

WR WREN

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

WRERR

(2)

LVDERR

(2)

LVDSTAT

(2)

— — —

— — — — NVMOP<3:0>

This bit is writable when WREN = 1 and the unlock sequence is followed.

1 = Initiate a Flash operation. Hardware clears this bit when the operation completes
0 = Flash operation complete or inactive

(1)

1 = Enable writes to WR bit and enables LVD circuit
0 = Disable writes to WR bit and disables LVD circuit

This is the only bit in this register reset by a device Reset.

(2)

This bit is read-only and is automatically set by hardware.

1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally

(2)

This bit is read-only and is automatically set by hardware.

1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming

(2)

This bit is read-only and is automatically set, and cleared, by hardware.

1 = Low-voltage event active
0 = Low-voltage event NOT active

These bits are writable when WREN = 0.
1111 =Reserved

•

•

•

0111 = Reserved
0110 =No operation
0101 =Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected
0100 =Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 =Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 =No operation
0001 =Word program operation: programs word selected by NVMADDR, if it is not write-protected
0000 = No operation

Bit

Note 1: This bit is cleared by any reset (i.e., POR, BOR, WDT, MCLR

, SWR).

2: This bit is only cleared by setting NVMOP = 0000, and initiating a Flash WR operation or a POR. Any

other kind of reset (i.e., BOR, WDT, MCLR

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 63

) does not clear this bit.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 6-2: NVMKEY: PROGRAMMING UNLOCK REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMKEY<31:0>: Unlock Register bits

Bit

31/23/15/7

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

NVMKEY<31:24>

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<23:16>

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<15:8>

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>

These bits are write-only, and read as ‘0’ on any read.

Bit

24/16/8/0

Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.

Bit

Bit

26/18/10/2

Bit

25/17/9/1

REGISTER 6-3: NVMADDR: FLASH ADDRESS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

27/19/11/3

NVMADDR<31:24>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<23:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMADDR<31:0>: Flash Address bits

Bulk/Chip/PFM Erase: Address is ignored
Page Erase: Address identifies the page to erase
Row Program: Address identifies the row to program
Word Program: Address identifies the word to program

Bit

24/16/8/0

DS60001290C-page 64 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 6-4: NVMDATA: FLASH PROGRAM DATA REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMDATA<31:0>: Flash Programming Data bits

Note: The bits in this register are only reset by a Power-on Reset (POR).

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

NVMDATA<31:24>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<23:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<7:0>

Bit

24/16/8/0

REGISTER 6-5: NVMSRCADDR: SOURCE DATA ADDRESS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

NVMSRCADDR<31:24>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<23:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<7:0>

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.

Bit

24/16/8/0

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 65

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

NOTES:

DS60001290C-page 66 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

MCLR

VDD

VDD Rise

Detect

POR

Sleep or Idle

Brown-out

Reset

WDT

Time-out

Glitch Filter

BOR

Configuration

SYSRST

Software Reset

Power-up

Timer

Voltage

Enabled

Reset

WDTR

SWR

CMR

MCLR

Mismatch

Regulator

Brown-out

Reset

HVDR

VCAP

HVD Detect

and Reset

7.0 RESETS

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data

sheet, refer to Section 7. “Resets”
(DS60001118) in the “PIC32 Family
Reference Manual”, which

from the Microchip web site
(www.microchip.com/PIC32).

FIGURE 7-1: SYSTEM RESET BLOCK DIAGRAM

is available

The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:

• POR: Power-on Reset

• MCLR: Master Clear Reset pin

• SWR: Software Reset

• WDTR: Watchdog Timer Reset

• BOR: Brown-out Reset

• CMR: Configuration Mismatch Reset

• HVDR: High Voltage Detect Reset

A simplified block diagram of the Reset module is
illustrated in Figure 7-1.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 67

DS60001290C-page 68 Preliminary  2014 Microchip Technology Inc.

7.1 Control Registers

TABLE 7-1: RESET SFR SUMMARY

(1)

Name

Register

(BF80_#)

Virtual Address

F600 RCON

F610 RSWRST

Legend: — = unimplemented, read as ‘0’. Address offset values are shown in hexadecimal.
Note 1: The Reset value is dependent on the DEVCFGx Configuration bits and the type of reset.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — HVDR — — — — — — — — — — — — — 0000

15:0 — — — — — — CMR VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR xxxx

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — — — — SWRST 0000

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bits

All Resets

(1)

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 7-1: RCON: RESET CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend: HS = Set by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’
bit 29 HVDR: High Voltage Detect Reset Flag bit

bit 28-10 Unimplemented: Read as ‘0’
bit 9 CMR: Configuration Mismatch Reset Flag bit

bit 8 VREGS: Voltage Regulator Standby Enable bit

bit 7 EXTR: External Reset (MCLR

bit 6 SWR: Software Reset Flag bit

bit 5 Unimplemented: Read as ‘0’
bit 4 WDTO: Watchdog Timer Time-out Flag bit

bit 3 SLEEP: Wake From Sleep Flag bit

bit 2 IDLE: Wake From Idle Flag bit

bit 1 BOR: Brown-out Reset Flag bit

bit 0 POR: Power-on Reset Flag bit

Bit

31/23/15/7

U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— —HVDR— — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0

— — — — — — CMR VREGS

R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS

EXTR SWR — WDTO SLEEP IDLE BOR

1 = High Voltage Detect (HVD) Reset has occurred, voltage on V

CAP > 2.5V

(1)

0 = HVD Reset has not occurred

1 = Configuration mismatch Reset has occurred
0 = Configuration mismatch Reset has not occurred

1 = Regulator is enabled and is on during Sleep mode
0 = Regulator is disabled and is off during Sleep mode

) Pin Flag bit

1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred

1 = Software Reset was executed
0 = Software Reset as not executed

1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred

1 = Device was in Sleep mode
0 = Device was not in Sleep mode

1 = Device was in Idle mode
0 = Device was not in Idle mode

(1)

1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred

(1)

1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred

Bit

24/16/8/0

(1)

POR

Note 1: User software must clear this bit to view next detection.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 69

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 7-2: RSWRST: SOFTWARE RESET REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend: HC = Cleared by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-1 Unimplemented: Read as ‘0’
bit 0 SWRST: Software Reset Trigger bit

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC

— — — — — — —SWRST

(1)

1 = Enable software Reset event
0 = No effect

Bit

24/16/8/0

(1)

Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section

6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.

DS60001290C-page 70 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

8.0 OSCILLATOR CONFIGURATION

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data

sheet, refer to Section 6. “Oscillator
Configuration” (DS60001112) in the
“PIC32 Family Reference Manual”, which

is available from the Microchip web site
(www.microchip.com/PIC32).

The PIC32MX1XX/2XX/5XX 64/100-pin oscillator
system has the following modules and features:

• A Total of four external and internal oscillator
options as clock sources

• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external
oscillator sources

• On-Chip user-selectable divisor postscaler on
select oscillator sources

• Software-controllable switching between
various clock sources

• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown

• Dedicated On-Chip PLL for USB peripheral

A block diagram of the oscillator system is provided in

Figure 8-1.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 71

Notes: 1. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain, add a

parallel resistor, R

P, with a value of 1 MΩ.

2. The internal feedback resistor, R

F, is typically in the range of 2 MΩ to 10 MΩ.

3. Refer to Section 6. “Oscillator Configuration” (DS60001112) in the “PIC32 Family Reference Manual” for help in determining the

best oscillator components.

4. PBCLK out is available on the OSC2 pin in certain clock modes.

5. USB PLL is available on PIC32MX2XX/5XX devices only.

Timer1, RTC C

Clock Control Logic

Fail-Safe

Clock

Monitor

FSCM INT

FSCM Event

COSC<2:0>

NOSC<2:0>

OSWEN

FSCMEN<1:0>

PLL

Secondary Oscillator (SOSC)

SOSCEN and FSOSCEN

SOSCO

SOSCI

Primary Oscillator

P

OSC (XT, HS, EC)

CPU and Select Peripherals

Peripherals

FRCDIV<2:0>

WDT, PWRT

8 MHz typical

FRC

31.25 kHz typical

FRC

Oscillator

LPRC

Oscillator

SOSC

LPRC

FRCDIV

TUN<5:0>

div 16

Postscaler

FPLLIDIV<2:0>

PBDIV<1:0>

FRC/16

Postscaler

COSC<2:0>

FIN

div x

div y

PLLODIV<2:0>

div x

32.768 kHz

PLLMULT<2:0>

PBCLK (T

PB)

UF

IN = 4 MHz

PLL x24

USB Clock (48 MHz)

div 2

UPLLEN

UFRCEN

div x

UPLLIDIV<2:0>

UFIN

4 MHz ≤ FIN ≤ 5 MHz

C1

(3)

C2

(3)

XTAL

R

S

(1)

Enable

OSC2

(4)

OSC1

R

F

(2)

To Internal
Logic

USB PLL

(5)

(POSC)

div 2

To A D C

SYSCLK

REFCLKI

REFCLKO

OE

To S P I

ROSEL<3:0>

POSC

FRC

LPRC

S

OSC

PBCLK

SYSCLK

XTPLL, HSPLL,

ECPLL, FRCPLL

System PLL

2N

M

512

----------+





×

RODIV<14:0>

(N)

ROTRIM<8:0>

(M)

R

P

(1)

÷

96 MHz

FV

CO

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 8-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY CLOCK DIAGRAM

DS60001290C-page 72 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FPLLIDIV X VCO FPLLODIV

SYSCLK

FPLLMULT

FIN:

(1)

3.92 MHz ≤ FIN ≤ 5 ΜΗz

FSYS:

(1)

60 MHz ≤ FSYS ≤ 120 ΜΗz

SYSCLK:

(1)

234,375 Hz ≤ SYSCLK

≤

50 MHz

Divide By:

1,2,3,4,5,6,10,12

Multiply By:

15,16,17,18,19,

20,21,22,23,24

Divide By:

1,2,4,8,16,32,64,256

(Crystal, External Clock

Or Internal RC)

Note 1: This frequency range must be satisfied at all times if the PLL is enabled and software is updating the

corresponding bits in the OSCON register.

FIGURE 8-2: PIC32MX1XX/2XX/5XX PLL BLOCK DIAGRAM

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 73

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 74

8.1 Control Registers

TABLE 8-1: OSCILLATOR CONFIGURATION REGISTER MAP

Bits

(1)

Name

Register

(BF80_#)

Virtual Address

OSCCON

F000

F010 OSCTUN

REFOCON

F020

REFOTRIM

F030

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2

“CLR, SET, and INV Registers” for more information.

2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
3: This bit is only available on devices with a USB module.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — PLLODIV<2:0> FRCDIV<2:0> — SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0> x1xx

15:0 — COSC<2:0> — NOSC<2:0> CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — TUN<5:0> 0000

31:16 — RODIV<14:0> 0000

15:0 ON — SIDL OE RSLP — DIVSWEN ACTIVE — — — —

31:16 ROTRIM<8:0>

15:0

— — — — — — — —

—

— — — — — — —

— — — — — — —

(3)

SOSCEN OSWEN xxxx

ROSEL<3:0>

0000

0000

0000

All Resets

(2)
(2)

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’
bit 29-27 PLLODIV<2:0>: Output Divider for PLL

bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits

bit 23 Unimplemented: Read as ‘0’
bit 22 SOSCRDY: Secondary Oscillator (S

bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit

bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits

Bit

31/23/15/7

U-0 U-0 R/W-y R/W-y R/W-y R/W-0 R/W-0 R/W-1

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — PLLODIV<2:0> FRCDIV<2:0>

U-0 R-0 R-1 R/W-y R/W-y R/W-y R/W-y R/W-y

— SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0>

U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y

— COSC<2:0> — NOSC<2:0>

R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0

CLKLOCK ULOCK

(1)

SLOCK SLPEN CF UFRCEN

(1)

SOSCEN OSWEN

111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1

111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2 (default setting)
000 = FRC divided by 1

OSC) Ready Indicator bit

1 = Indicates that the Secondary Oscillator is running and is stable
0 = Secondary Oscillator is still warming up or is turned off

1 = PBDIV<1:0> bits can be written
0 = PBDIV<1:0> bits cannot be written

11 = PBCLK is SYSCLK divided by 8 (default)
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1

Bit

24/16/8/0

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

Note: Writes to this register require an unlock sequence. Refer to Sectio n 6. “Oscilla tor” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 75

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits

111 = Clock is multiplied by 24
110 = Clock is multiplied by 21
101 = Clock is multiplied by 20
100 = Clock is multiplied by 19
011 = Clock is multiplied by 18
010 = Clock is multiplied by 17
001 = Clock is multiplied by 16
000 = Clock is multiplied by 15

bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits

111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits
110 = Internal Fast RC (FRC) Oscillator divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (S
011 = Primary Oscillator (P
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast RC (FRC) Oscillator

bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits

111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits
110 = Internal Fast RC Oscillator (FRC) divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (S
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast Internal RC Oscillator (FRC)

On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).

bit 7 CLKLOCK: Clock Selection Lock Enable bit

If clock switching and monitoring is

1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified

OSC)

OSC) with PLL module (XTPLL, HSPLL or ECPLL)

OSC)

disabled (FCKSM<1:0> = 1x):

If clock switching and monitoring is enabled (FCKSM<1:0> =
Clock and PLL selections are never locked and may be modified.

bit 6 ULOCK: USB PLL Lock Status bit

1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or

USB PLL is disabled

bit 5 SLOCK: PLL Lock Status bit

1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4 SLPEN: Sleep Mode Enable bit

1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed

bit 3 CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure
0 = No clock failure has been detected

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

Note: Writes to this register require an unlock sequence. Refer to Sectio n 6. “Oscillator” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

DS60001290C-page 76 Preliminary  2014 Microchip Technology Inc.

(1)

0x):

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 2 UFRCEN: USB FRC Clock Enable bit

1 = Enable FRC as the clock source for the USB clock source
0 = Use the Primary Oscillator or USB PLL as the USB clock source

bit 1 SOSCEN: Secondary Oscillator (S

1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

Note: Writes to this register require an unlock sequence. Refer to Sectio n 6. “Oscilla tor” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

(1)

OSC) Enable bit

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 77

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 8-2: OSCTUN: FRC TUNING REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN<5:0>

(1)

(1)

100000 = Center frequency -12.5%
100001 =

•

•

•

111111 =
000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz)
000001 =

•

•

•

011110 =
011111 = Center frequency +12.5%

24/16/8/0

Bit

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the

FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized, nor tested.

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

DS60001290C-page 78 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend: HC = Hardware Clearable HS = Hardware Settable

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Bit

31/23/15/7

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC

ON —SIDLOE

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — —

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

RODIV<7:0>

Bit

27/19/11/3

RODIV<14:8>

(3)

(2)

RSLP

Bit

26/18/10/2

(1)

Bit

25/17/9/1

— DIVSWEN ACTIVE

ROSEL<3:0>

(1)

Bit

24/16/8/0

bit 31 Unimplemented: Read as ‘0’
bit 30-16 RODIV<14:0>: Reference Clock Divider bits

(1)

This value selects the Reference Clock Divider bits. See Figure 8-1 for more information.

bit 15 ON: Output Enable bit

1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled

bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Peripheral Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode

bit 12 OE: Reference Clock Output Enable bit

1 = Reference clock is driven out on REFCLKO pin
0 = Reference clock is not driven out on REFCLKO pin

bit 11 RSLP: Reference Oscillator Module Run in Sleep bit

1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep

bit 10 Unimplemented: Read as ‘0’
bit 9 DIVSWEN: Divider Switch Enable bit

1 = Divider switch is in progress
0 = Divider switch is complete

bit 8 ACTIVE: Reference Clock Request Status bit

1 = Reference clock request is active
0 = Reference clock request is not active

bit 7-4 Unimplemented: Read as ‘0’

(2)

Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may

result.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ‘1’.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 79

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits

1111 = Reserved; do not use

•

•

•

1001 = Reserved; do not use
1000 = REFCLKI
0111 = System PLL output
0110 = USB PLL output
0101 =S
0100 =LPRC
0011 =FRC
0010 =P
0001 = PBCLK
0000 = SYSCLK

Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may

result.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ‘1’.

OSC

OSC

(1)

DS60001290C-page 80 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 8-4: REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits

bit 22-0 Unimplemented: Read as ‘0’

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

ROTRIM<0> — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

111111111 = 511/512 divisor added to RODIV value
111111110 = 510/512 divisor added to RODIV value

•

•

•
100000000 = 256/512 divisor added to RODIV value

•

•

•

000000010 = 2/512 divisor added to RODIV value
000000001 = 1/512 divisor added to RODIV value
000000000 = 0/512 divisor added to RODIV value

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

ROTRIM<8:1>

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

Bit

Note: While the ON bit (REFOCON<15>) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is

also set to ‘1’.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 81

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

NOTES:

DS60001290C-page 82 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Address Decoder

Channel 0 Control

Channel 1 Control

Channel n Control

Global Control

(DMACON)

Bus Interface

Channel Priority

Arbitration

S

E

L

S

E

L

Y

I

0

I

1

I

2

I

n

System IRQINT Controller

Device Bus + Bus Arbitration

Peripheral Bus

9.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data

sheet, refer to Section 31. “Direct

Memory Access (DMA) Controller”

(DS60001117) in the “PIC32 Family
Reference Manual”

from the Microchip web site
(www.microchip.com/PIC32).

The PIC32 Direct Memory Access (DMA) controller is a
bus master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC32 (such
as Peripheral Bus (PBUS) devices: SPI, UART, PMP,
etc.) or memory itself.

Following are some of the key features of the DMA
controller module:

• Four identical channels, each featuring:

- Auto-increment source and destination
address registers

- Source and destination pointers

- Memory to memory and memory to
peripheral transfers

• Automatic word-size detection:

- Transfer granularity, down to byte level

- Bytes need not be word-aligned at source
and destination

, which is available

• Fixed priority channel arbitration

• Flexible DMA channel operating modes:

- Manual (software) or automatic (interrupt)
DMA requests

- One-Shot or Auto-Repeat Block Transfer
modes

- Channel-to-channel chaining

• Flexible DMA requests:

- A DMA request can be selected from any of
the peripheral interrupt sources

- Each channel can select any (appropriate)
observable interrupt as its DMA request
source

- A DMA transfer abort can be selected from
any of the peripheral interrupt sources

- Pattern (data) match transfer termination

• Multiple DMA channel status interrupts:

- DMA channel block transfer complete

- Source empty or half empty

- Destination full or half full

- DMA transfer aborted due to an external
event

- Invalid DMA address generated

• DMA debug support features:

- Most recent address accessed by a DMA
channel

- Most recent DMA channel to transfer data

• CRC Generation module:

- CRC module can be assigned to any of the
available channels

- CRC module is highly configurable

FIGURE 9-1: DMA BLOCK DIAGRAM

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 83

DS60001290C-page 84 Preliminary  2014 Microchip Technology Inc.

9.1 Control Registers

TABLE 9-1: DMA GLOBAL REGISTER MAP

Bits

(1)

Name

Register

(BF88_#)

Virtual Address

3000 DMACON

3010 DMASTAT

3020 DMAADDR

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

TABLE 9-2: DMA CRC REGISTER MAP

(1)

Name

Register

(BF88_#)

Virtual Address

3030 DCRCCON

3040 DCRCDATA

3050 DCRCXOR

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON — — SUSPEND DMABUSY — — — — — — — — — — — 0000

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RDWR DMACH<2:0> 0000

31:16

15:0 0000

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — BYTO<1:0> WBO — — BITO — — — — — — — — 0000

15:0 — — — PLEN<4:0> CRCEN CRCAPP CRCTYP — — CRCCH<2:0> 0000

31:16

15:0 0000

31:16

15:0 0000

DMAADDR<31:0>

Bits

DCRCDATA<31:0>

DCRCXOR<31:0>

0000

0000

0000

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

All Resets

All Resets

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 85

TABLE 9-3: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP

Bits

(1)

Name

Register

(BF88_#)

Virtual Address

3060 DCH0CON

3070 DCH0ECON

3080 DCH0INT

3090 DCH0SSA

30A0 DCH0DSA

30B0 DCH0SSIZ

30C0 DCH0DSIZ

30D0 DCH0SPTR

30E0 DCH0DPTR

30F0 DCH0CSIZ

3100 DCH0CPTR

3110 DCH0DAT

3120 DCH1CON

3130 DCH1ECON

3140 DCH1INT

3150 DCH1SSA

3160 DCH1DSA

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16

15:0 CHBUSY

31:16

15:0

31:16

15:0

31:16

15:0 0000

31:16

15:0 0000

31:16

15:0 CHSSIZ<15:0> 0000

31:16

15:0 CHDSIZ<15:0> 0000

31:16

15:0 CHSPTR<15:0> 0000

31:16

15:0 CHDPTR<15:0> 0000

31:16

15:0 CHCSIZ<15:0> 0000

31:16

15:0 CHCPTR<15:0> 0000

31:16

15:0

31:16

15:0 CHBUSY

31:16

15:0

31:16

15:0

31:16

15:0 0000

31:16

15:0 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

— — — — — — — — CHAIRQ<7:0> 00FF

CHSIRQ<7:0> CFORCE CABORT PAT EN SIRQEN AIRQEN — — — FFF8

— — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

— — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

CHSSA<31:0>

CHDSA<31:0>

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — CHPDAT<7:0> 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

— — — — — — — — CHAIRQ<7:0> 00FF

CHSIRQ<7:0> CFORCE CABORT PAT EN SIRQEN AIRQEN — — — FFF8

— — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

— — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

CHSSA<31:0>

CHDSA<31:0>

0000

0000

0000

0000

All Resets

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290C-page 86 Preliminary  2014 Microchip Technology Inc.

TABLE 9-3: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED)

Bits

(1)

Name

Register

(BF88_#)

Virtual Address

3170 DCH1SSIZ

3180 DCH1DSIZ

3190 DCH1SPTR

31A0 DCH1DPTR

31B0 DCH1CSIZ

31C0 DCH1CPTR

31D0 DCH1DAT

31E0 DCH2CON

31F0 DCH2ECON

3200 DCH2INT

3210 DCH2SSA

3220 DCH2DSA

3230 DCH2SSIZ

3240 DCH2DSIZ

3250 DCH2SPTR

3260 DCH2DPTR

3270 DCH2CSIZ

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16

15:0 CHSSIZ<15:0> 0000

31:16

15:0 CHDSIZ<15:0> 0000

31:16

15:0 CHSPTR<15:0> 0000

31:16

15:0 CHDPTR<15:0> 0000

31:16

15:0 CHCSIZ<15:0> 0000

31:16

15:0 CHCPTR<15:0> 0000

31:16

15:0

31:16

15:0 CHBUSY

31:16

15:0

31:16

15:0

31:16

15:0 0000

31:16

15:0 0000

31:16

15:0 CHSSIZ<15:0> 0000

31:16

15:0 CHDSIZ<15:0> 0000

31:16

15:0 CHSPTR<15:0> 0000

31:16

15:0 CHDPTR<15:0> 0000

31:16

15:0 CHCSIZ<15:0> 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — CHPDAT<7:0> 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

— — — — — — — — CHAIRQ<7:0> 00FF

CHSIRQ<7:0> CFORCE CABORT PAT EN SIRQEN AIRQEN — — — FFF8

— — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

— — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

CHSSA<31:0>

CHDSA<31:0>

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

0000

0000

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

All Resets

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 87

TABLE 9-3: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED)

Bits

(1)

Name

Register

(BF88_#)

Virtual Address

3280 DCH2CPTR

3290 DCH2DAT

32A0 DCH3CON

32B0 DCH3ECON

32C0 DCH3INT

32D0 DCH3SSA

32E0 DCH3DSA

32F0 DCH3SSIZ

3300 DCH3DSIZ

3310 DCH3SPTR

3320 DCH3DPTR

3330 DCH3CSIZ

3340 DCH3CPTR

3350 DCH3DAT

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16

15:0 CHCPTR<15:0> 0000

31:16

15:0

31:16

15:0 CHBUSY

31:16

15:0

31:16

15:0

31:16

15:0 0000

31:16

15:0 0000

31:16

15:0 CHSSIZ<15:0> 0000

31:16

15:0 CHDSIZ<15:0> 0000

31:16

15:0 CHSPTR<15:0> 0000

31:16

15:0 CHDPTR<15:0> 0000

31:16

15:0 CHCSIZ<15:0> 0000

31:16

15:0 CHCPTR<15:0> 0000

31:16

15:0

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — CHPDAT<7:0> 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

— — — — — — — — CHAIRQ<7:0> 00FF

CHSIRQ<7:0> CFORCE CABORT PAT EN SIRQEN AIRQEN — — — FFF8

— — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

— — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

CHSSA<31:0>

CHDSA<31:0>

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — CHPDAT<7:0> 0000

0000

0000

All Resets

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-1: DMACON: DMA CONTROLLER CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: DMA On bit

bit 14-13 Unimplemented: Read as ‘0’
bit 12 SUSPEND: DMA Suspend bit

bit 11 DMABUSY: DMA Module Busy bit

bit 10-0 Unimplemented: Read as ‘0’

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0

(1)

ON

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — SUSPEND DMABUSY

(1)

— — —

— — — — — — — —

(1)

1 = DMA module is enabled
0 = DMA module is disabled

1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally

(1)

1 = DMA module is active
0 = DMA module is disabled and not actively transferring data

24/16/8/0

Bit

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

DS60001290C-page 88 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-2: DMASTAT: DMA STATUS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’
bit 3 RDWR: Read/Write Status bit

bit 2-0 DMACH<2:0>: DMA Channel bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — RDWR DMACH<2:0>

1 = Last DMA bus access was a read
0 = Last DMA bus access was a write

These bits contain the value of the most recent active DMA channel.

24/16/8/0

Bit

REGISTER 9-3: DMAADDR: DMA ADDRESS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DMAADDR<31:0>: DMA Module Address bits

Bit

31/23/15/7

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

DMAADDR<31:24>

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<23:16>

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<15:8>

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<7:0>

These bits contain the address of the most recent DMA access.

24/16/8/0

Bit

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 89

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-4: DCRCCON: DMA CRC CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits

bit 27 WBO: CRC Write Byte Order Selection bit

bit 26-25 Unimplemented: Read as ‘0’
bit 24 BITO: CRC Bit Order Selection bit

Bit

31/23/15/7

U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0

— —BYTO<1:0>WBO

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

(1)

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

— —BITO

— — — — — — — —

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — PLEN<4:0>

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

CRCEN CRCAPP

(1)

CRCTYP — — CRCCH<2:0>

11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order

per half-word)

10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per

half-word)

01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)

(1)

1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered

(1

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)

0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)

Bit

When CRCTYP (DCRCCON<15>) =

0 (CRC module is in LFSR mode):

1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)

bit 23-13 Unimplemented: Read as ‘0’
bit 12-8 PLEN<4:0>: Polynomial Length bits

(1)

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused.

When CRCTYP (DCRCCON<15>) =

0 (CRC module is in LFSR mode):

Denotes the length of the polynomial – 1.

bit 7 CRCEN: CRC Enable bit

1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

DS60001290C-page 90 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)

bit 6 CRCAPP: CRC Append Mode bit

1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer

completes the DMA writes the calculated CRC value to the location given by CHxDSA

0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the

destination

bit 5 CRCTYP: CRC Type Selection bit

1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC

bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 CRCCH<2:0>: CRC Channel Select bits

111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

(1)

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 91

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-5: DCRCDATA: DMA CRC DATA REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DCRCDATA<31:0>: CRC Data Register bits

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

DCRCDATA<31:24>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<23:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<7:0>

Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.

Bit

When CRCTYP (DCRCCON<15>) =

1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.

REGISTER 9-6: DCRCXOR: DMA CRCXOR ENABLE REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

DCRCXOR<31:24>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<23:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<7:0>

24/16/8/0

Bit

bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
This register is unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in

the register

DS60001290C-page 92 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-7: DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15 CHBUSY: Channel Busy bit

bit 14-9 Unimplemented: Read as ‘0’
bit 8 CHCHNS: Chain Channel Selection bit

bit 7 CHEN: Channel Enable bit

bit 6 CHAED: Channel Allow Events If Disabled bit

bit CHCHN: Channel Chain Enable bit

bit 4 CHAEN: Channel Automatic Enable bit

bit 3 Unimplemented: Read as ‘0’
bit 2 CHEDET: Channel Event Detected bit

bit 1-0 CHPRI<1:0>: Channel Priority bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

CHBUSY — — — — — — CHCHNS

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0

(2)

CHEN

CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>

1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled

(1)

1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)

(2)

1 = Channel is enabled
0 = Channel is disabled

1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled

1 = Allow channel to be chained
0 = Do not allow channel to be chained

1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete

1 = An event has been detected
0 = No events have been detected

11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0

Bit

(1)

Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).

2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if

available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 93

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-8: DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

— — — — — — — —

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CHAIRQ<7:0>

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CHSIRQ<7:0>

S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

(1)

(1)

CFORCE CABORT PATEN SIRQEN AIRQEN — — —

Bit

bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits

11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag

•

•

•

00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag

bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits

11111111 = Interrupt 255 will initiate a DMA transfer

•

•

•

00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer

bit 7 CFORCE: DMA Forced Transfer bit

1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’

bit 6 CABORT: DMA Abort Transfer bit

1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’

bit 5 PATEN: Channel Pattern Match Abort Enable bit

1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled

bit 4 SIRQEN: Channel Start IRQ Enable bit

1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer

bit 3 AIRQEN: Channel Abort IRQ Enable bit

1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer

bit 2-0 Unimplemented: Read as ‘0’

(1)

(1)

Note 1: See Table 5-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.

DS60001290C-page 94 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’
bit 23 CHSDIE: Channel Source Done Interrupt Enable bit

bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit

bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit

bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit

bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit

bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit

bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit

bit 16 CHERIE: Channel Address Error Interrupt Enable bit

bit 15-8 Unimplemented: Read as ‘0’
bit 7 CHSDIF: Channel Source Done Interrupt Flag bit

bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit

bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Interrupt is enabled
0 = Interrupt is disabled

1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending

1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending

1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

Bit

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 95

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED)

bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit

1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending

bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit

1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a

pattern match event occurs

0 = No interrupt is pending

bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit

1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending

bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit

1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending

bit 0 CHERIF: Channel Address Error Interrupt Flag bit

1 = A channel address error has been detected

Either the source or the destination address is invalid.

0 = No interrupt is pending

DS60001290C-page 96 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER

Bit Range

31:24

23:16

15:8

7:0

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHSSA<31:0> Channel Source Start Address bits

Channel source start address.

Note: This must be the physical address of the source.

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

CHSSA<31:24>

CHSSA<23:16>

CHSSA<15:8>

CHSSA<7:0>

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

24/16/8/0

Bit

REGISTER 9-11: DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits

Bit

31/23/15/7

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

CHDSA<31:24>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<23:16>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<7:0>

Channel destination start address.

Note: This must be the physical address of the destination.

24/16/8/0

Bit

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 97

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSSIZ<15:0>: Channel Source Size bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSIZ<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSIZ<7:0>

1111111111111111 = 65,535 byte source size

•

•

•

0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size

24/16/8/0

Bit

REGISTER 9-13: DCHxDSIZ: DMA CHANNEL ‘x’ DESTINATION SIZE REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSIZ<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSIZ<7:0>

1111111111111111 = 65,535 byte destination size

•

•

•

0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size

24/16/8/0

Bit

DS60001290C-page 98 Preliminary  2014 Microchip Technology Inc.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHSPTR<15:8>

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHSPTR<7:0>

1111111111111111 = Points to byte 65,535 of the source

•

•

•

0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source

24/16/8/0

Bit

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

REGISTER 9-15: DCHxDPTR: DMA CHANNEL ‘x’ DESTINATION POINTER REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHDPTR<15:8>

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHDPTR<7:0>

1111111111111111 = Points to byte 65,535 of the destination

•

•

•

0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination

24/16/8/0

Bit

 2014 Microchip Technology Inc. Preliminary DS60001290C-page 99

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 9-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHCSIZ<15:8>

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHCSIZ<7:0>

1111111111111111 = 65,535 bytes transferred on an event

•

•

•

0000000000000010 = 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event

24/16/8/0

Bit

REGISTER 9-17: DCHxCPTR: DMA CHANNEL ‘x’ CELL POINTER REGISTER

Bit

Range

31:24

23:16

15:8

7:0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits

Bit

31/23/15/7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

— — — — — — — —

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHCPTR<15:8>

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHCPTR<7:0>

1111111111111111 = 65,535 bytes have been transferred since the last event

•

•

•

0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event

24/16/8/0

Bit

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

DS60001290C-page 100 Preliminary  2014 Microchip Technology Inc.