Datasheet PIC24HJ64GP206A, PIC24HJ64GP210A, PIC24HJ64GP506A, PIC24HJ64GP510A, PIC24HJ128GP206A Datasheet

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PIC24HJXXXGPX06A/X08A/X10A

Data Sheet

High-Performance,

16-bit Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC

logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-015-8

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

PIC24HJXXXGPX06A/X08A/X10A

High-Performance, 16-bit Microcontrollers

Operating Range:

• Up to 40 MIPS operation (@ 3.0-3.6V):

- Industrial temperature range (-40°C to +85°C)

- Extended temperature range (-40°C to +125°C)

• Up to 20 MIPS operation (@ 3.0-3.6V):

- High temperature range (-40°C to +150°C)

High-Performance CPU:

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M instruction words

• Linear data memory addressing up to 64 Kbytes

• 71 base instructions: mostly 1 word/1 cycle

• Sixteen 16-bit General Purpose Registers

• Flexible and powerful Indirect Addressing modes

• Software stack

• 16 x 16 multiply operations

• 32/16 and 16/16 divide operations

• Up to ±16-bit data shifts

Direct Memory Access (DMA):

• 8-channel hardware DMA

• 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA:

- Allows data transfer between RAM and a

peripheral while CPU is executing code (no cycle stealing)

• Most peripherals support DMA

Interrupt Controller:

• 5-cycle latency

• Up to 61 available interrupt sources

• Up to five external interrupts

• Seven programmable priority levels

• FIve processor exceptions

On-Chip Flash and SRAM:

• Flash program memory, up to 256 Kbytes

• Data SRAM, up to 16 Kbytes (includes 2 Kbytes of DMA RAM)

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated PLL

- Extremely low jitter PLL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monitor

• Reset by multiple sources

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Timers/Capture/Compare/PWM:

• Timer/Counters, up to nine 16-bit timers:

- Can pair up to make four 32-bit timers

- One timer runs as Real-Time Clock with

external 32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to eight channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to eight channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM mode

Digital I/O:

• Up to 85 programmable digital I/O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• Up to 5.5V output with open drain configuration on 5V tolerant pins with an external pull-up

• 4 mA sink on all I/O pins

PIC24HJXXXGPX06A/X08A/X10A

Communication Modules:

• 3-wire SPI (up to two modules):

- Framing supports I/O interface to simple codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

C™ (up to two modules):

•I

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

• UART (up to two modules):

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™ module) 2.0B active (up to two modules):

- Up to eight transmit and up to 32 receive buffers

- 16 receive filters and 3 masks

- Loopback, Listen Only and Listen All

- Wake-up on CAN message

- Automatic processing of Remote

- FIFO mode using DMA

- DeviceNet™ addressing support

encoding and decoding in hardware

Messages modes for diagnostics and bus monitoring

Transmission Requests

Analog-to-Digital Converters:

• Up to two Analog-to-Digital Converter (ADC) modules in a device

• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:

- Two, four, or eight simultaneous samples

- Up to 32 input channels with auto-scanning

- Conversion start can be manual or

synchronized with one of four trigger sources

- Conversion possible in Sleep mode

- ±1 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

CMOS Flash Technology:

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial and extended temperature

• Low-power consumption

Packaging:

• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)

• 64-pin TQFP (10x10x1 mm)

• 64-pin QFN (9x9x0.9 mm)

Note: See the device variant tables for exact

peripheral features per device.

PIC24HJXXXGPX06A/X08A/X10A

PIC24H PRODUCT FAMILIES

The PIC24H Family of devices is ideal for a wide variety of 16-bit MCU embedded applications. The device names, pin counts, memory sizes and peripheral availability of each device are listed below, followed by their pinout diagrams.

PIC24H Family Controllers

Device Pins

PIC24HJ64GP206A 64 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP210A 100 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP506A 64 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP510A 100 64 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP206A 64 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP210A 100 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP506A 64 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP510A 100 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP306A 64 128 16 8 9 8 8 0 1 ADC,

PIC24HJ128GP310A 100 128 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP206A 64 256 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP210A 100 256 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP610A 100 256 16 8 9 8 8 0 2 ADC,

Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

Program

Flash

Memory (KB)

(KB)

(1)

RAM

Codec

Interface

Timer 16-bit

DMA Channels

Std. PWM

Input Capture

Output Compare

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

(2)

C™

SPI

CAN

ADC

UART

221 053PT, MR

222 085PF, PT

222 153PT, MR

222 185PF, PT

222 053PT, MR

222 085PF, PT

222 153PT, MR

222 185PF, PT

222 053PT, MR

222 085PF, PT

222 053PT, MR

222 085PF, PT

222 285PF, PT

I/O Pins (Max)

Packages

PIC24HJXXXGPX06A/X08A/X10A

64-Pin QFN

(1)

PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11

IC2/U1CTS

/INT2/RD9 IC1/INT1/RD8 V

OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V

SCL1/RG2

U1RTS

/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3

RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS VDD

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

PGEC3/AN1/V

REF-/CN3/RB1

PGED3/AN0/V

REF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

CAP

(3)

RG1

RF1

RG0

OC2/RD1

OC3/RD2

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

AVDD

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS

/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

SDA1/RG3

SS2

/CN11/RG9

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ64GP206A

(2)

PIC24HJ128GP206A PIC24HJ256GP206A

Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.

2: The PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins.

3: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

= Pins are up to 5V tolerant

64 63 62 61 60 59 58 57 5655

22 23 24 25 26 27 2829 3031

40 39 38 37 36 35 34 33

4 5

7 8

9 10 11

42 41

14 15 16

12 13

18 1920 21

45 44

47 46

52 51 50 49

Pin Diagrams

PIC24HJXXXGPX06A/X08A/X10A

64-Pin QFN

(1)

PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11

IC2/U1CTS

/INT2/RD9 IC1/INT1/RD8 V

OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V

SCL1/RG2

U1RTS

/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3

RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS VDD

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

PGEC3/AN1/V

REF-/CN3/RB1

PGED3/AN0/V

REF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

CAP

(2)

RG1

RF1

RG0

OC2/RD1

OC3/RD2

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS

/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

SDA1/RG3

SS2

/CN11/RG9

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ128GP306A

= Pins are up to 5V tolerant

Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.

2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

64 63 62 61 60 59 58 57 5655

22 23 24 25 26 27 2829 3031

40 39 38 37 36 35 34 33

4 5

7 8

9 10 11

42 41

14 15 16

12 13

18 1920 21

45 44

47 46

52 51 50 49

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

64-Pin QFN

(1)

PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11

IC2/U1CTS

/INT2/RD9 IC1/INT1/RD8 V

OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V

SCL1/RG2

U1RTS

/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3

RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS VDD

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

PGEC3/AN1/V

REF-/CN3/RB1

PGED3/AN0/V

REF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

CAP

(2)

RG1

C1TX/RF1

RG0

OC2/RD1

OC3/RD2

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

AVDD

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS

/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

SDA1/RG3

SS2

/CN11/RG9

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

C1RX/RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ64GP506A

PIC24HJ128GP506A

= Pins are up to 5V tolerant

Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.

2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

64 63 62 61 60 59 58 57 5655

22 23 24 25 26 27 28 29 3031

40 39 38 37 36 35 34 33

4 5

7 8

9 10 11

42 41

14 15 16

12 13

18 19 20 21

45 44

47 46

52 5150 49

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

64-Pin TQFP

1 2 3 4 5 6 7 8 9 10 11 12 13

36 35 34 33

646362616059585756

14 15 16

171819202122232425

PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11

IC2/U1CTS

/INT2/RD9 IC1/INT1/RD8 V

OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V

SCL1/RG2

U1RTS

/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3

RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

PGEC3/AN1/V

REF-/CN3/RB1

PGED3/AN0/V

REF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

CAP

(2)

RG1

RF1

RG0

OC2/RD1

OC3/RD2

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

AVDD

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS

/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2

(1)

/CN18/RF5

U2RX/SDA2

(1)

/CN17/RF4

SDA1/RG3

43 42 41 40 39 38 37

48 47 46

504951

545352

SS2

/CN11/RG9

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ64GP206A PIC24HJ128GP206A PIC24HJ256GP206A

Note 1: This pin is not present on the PIC24HJ64GP206A device.

2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

64-Pin TQFP

1 2 3 4 5 6 7 8 9 10 11 12 13

36 35 34 33

646362616059585756

14 15 16

171819202122232425

PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11

IC2/U1CTS

/INT2/RD9 IC1/INT1/RD8 V

OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V

SCL1/RG2

U1RTS

/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3

RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

PGEC3/AN1/V

REF-/CN3/RB1

PGED3/AN0/V

REF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

CAP

(1)

RG1

RF1

RG0

OC2/RD1

OC3/RD2

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS

/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

SDA1/RG3

43 42 41 40 39 38 37

48 47 46

504951

545352

SS2

/CN11/RG9

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ128GP306A

= Pins are up to 5V tolerant

Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

64-Pin TQFP

1 2 3 4 5 6 7 8 9 10 11 12 13

36 35 34 33

646362616059585756

14 15 16

171819202122232425

PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11

IC2/U1CTS

/INT2/RD9 IC1/INT1/RD8 V

OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V

SCL1/RG2

U1RTS

/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3

RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

PGEC3/AN1/V

REF-/CN3/RB1

PGED3/AN0/V

REF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

CAP

(1)

RG1

C1TX/RF1

RG0

OC2/RD1

OC3/RD2

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

AVDD

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS

/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

SDA1/RG3

43 42 41 40 39 38 37

48 47 46

504951

545352

SS2

/CN11/RG9

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

C1RX/RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ64GP506A

PIC24HJ128GP506A

= Pins are up to 5V tolerant

Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

9294939190898887868584838281807978

2829303132333435363738

969897

4647484950

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

AN23/CN23/RA7

AN22/CN22/RA6

AN26/RE2

RG13

RG12

RG14

AN25/RE1

AN24/RE0

RG0

AN28/RE4

AN27/RE3

RF0

CAP

(1)

PGED2/SOSCI/CN1/RC13

OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

PGEC2/SOSCO/T1CK/CN0/RC14

REF

+/RA10

REF

-/RA9

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

U2CTS/RF12

U2RTS

/RF13

IC7/U1CTS

/CN20/RD14

IC8/U1RTS

/CN21/RD15

PGEC1/AN6/OCFA/RB6

PGED1PGED1/AN7/RB7

U2TX/CN18/RF5

U2RX/CN17/RF4

AN29/RE5

AN30/RE6

AN31/RE7 AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

TMS/RA0

AN20/INT1/RA12

AN21/INT2/RA13

AN5/CN7/RB5 AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

SDI2/CN9/RG7

SDO2/CN10/RG8

PGEC3/AN1/CN3/RB1

PGED3/AN0/CN2/RB0

RG15

SS2/CN11/RG9

MCLR

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

RG1

RF1

OC8/CN16/RD7

OC7/CN15/RD6

TDO/RA5

INT4/RA15

INT3/RA14

TDI/RA4

TCK/RA1

100-Pin TQFP

PIC24HJ64GP210A

PIC24HJ128GP210A

100

PIC24HJ128GP310A PIC24HJ256GP210A

= Pins are up to 5V tolerant

Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

929493

91908988878685848382818079

8 9

2829303132333435363738

969897

4647484950

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

AN23/CN23/RA7

AN22/CN22/RA6

AN26/RE2

RG13

RG12

RG14

AN25/RE1

AN24/RE0

RG0

AN28/RE4

AN27/RE3

C1RX/RF0

CAP

(1)

PGED2/SOSCI/CN1/RC13

OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

PGEC2/SOSCO/T1CK/CN0/RC14

REF

+/RA10

REF

-/RA9

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

U2CTS/RF12

U2RTS

/RF13

IC7/U1CTS

/CN20/RD14

IC8/U1RTS

/CN21/RD15

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

U2TX/CN18/RF5

U2RX/CN17/RF4

AN29/RE5

AN30/RE6

AN31/RE7 AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

TMS/RA0

AN20/INT1/RA12

AN21/INT2/RA13

AN5/CN7/RB5 AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

SDI2/CN9/RG7

SDO2/CN10/RG8

PGEC3/AN1/CN3/RB1

PGED3/AN0/CN2/RB0

RG15

SS2/CN11/RG9

MCLR

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

RG1

C1TX/RF1

OC8/CN16/RD7

OC7/CN15/RD6

TDO/RA5

INT4/RA15

INT3/RA14

TDI/RA4

TCK/RA1

100-Pin TQFP

PIC24HJ64GP510A

100

PIC24HJ128GP510A

= Pins are up to 5V tolerant

Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

9294939190898887868584838281807978

2829303132333435363738

969897

4647484950

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

AN23/CN23/RA7

AN22/CN22/RA6

AN26/RE2

RG13

RG12

RG14

AN25/RE1

AN24/RE0

C2RX/RG0

AN28/RE4

AN27/RE3

C1RX/RF0

CAP

(1)

PGED2/SOSCI/CN1/RC13

OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

PGEC2/SOSCO/T1CK/CN0/RC14

REF

+/RA10

REF

-/RA9

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

U2CTS/RF12

U2RTS

/RF13

IC7/U1CTS

/CN20/RD14

IC8/U1RTS

/CN21/RD15

PGEC1/AN6/OCFA/RB6

PGED1/AN7/RB7

U2TX/CN18/RF5

U2RX/CN17/RF4

AN29/RE5 AN30/RE6

AN31/RE7 AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

TMS/RA0

AN20/INT1/RA12 AN21/INT2/RA13

AN5/CN7/RB5 AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

SDI2/CN9/RG7

SDO2/CN10/RG8

PGEC3/AN1/CN3/RB1

PGED3/AN0/CN2/RB0

RG15

SS2/CN11/RG9

MCLR

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

C2TX/RG1

C1TX/RF1

OC8/CN16/RD7

OC7/CN15/RD6

TDO/RA5

INT4/RA15

INT3/RA14

TDI/RA4

TCK/RA1

100-Pin TQFP

100

PIC24HJ256GP610A

= Pins are up to 5V tolerant

Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

Pin Diagrams (Continued)

PIC24HJXXXGPX06A/X08A/X10A

PIC24H Product Families....................................................................................................................................................................... 5

1.0 Device Overview ........................................................................................................................................................................ 17

2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 23

3.0 CPU............................................................................................................................................................................................ 27

4.0 Memory Organization................................................................................................................................................................. 33

5.0 Flash Program Memory.............................................................................................................................................................. 63

6.0 Reset ......................................................................................................................................................................................... 69

7.0 Interrupt Controller ..................................................................................................................................................................... 73

8.0 Direct Memory Access (DMA).................................................................................................................................................. 117

9.0 Oscillator Configuration............................................................................................................................................................ 127

10.0 Power-Saving Features............................................................................................................................................................ 137

11.0 I/O Ports ................................................................................................................................................................................... 145

12.0 Timer1 ...................................................................................................................................................................................... 147

13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 149

14.0 Input Capture............................................................................................................................................................................ 155

15.0 Output Compare....................................................................................................................................................................... 157

16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 161

17.0 Inter-Integrated Circuit™ (I

18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 175

19.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 181

20.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 209

21.0 Special Features ...................................................................................................................................................................... 221

22.0 Instruction Set Summary .......................................................................................................................................................... 229

23.0 Development Support............................................................................................................................................................... 237

24.0 Electrical Characteristics .......................................................................................................................................................... 241

25.0 High Temperature Electrical Characteristics ............................................................................................................................ 285

26.0 Packaging Information.............................................................................................................................................................. 293

Appendix A: Migrating from PIC24HJXXXGPX06/X08/X10 Devices to PIC24HJXXXGPX06A/X08A/X10A Devices ....................... 303

Appendix B: Revision History............................................................................................................................................................. 304

Index ................................................................................................................................................................................................. 307

The Microchip Web Site ..................................................................................................................................................................... 311

Customer Change Notification Service .............................................................................................................................................. 311

Customer Support.............................................................................................................................................................................. 311

Reader Response .............................................................................................................................................................................. 312

Product Identification System ............................................................................................................................................................ 313

C™).............................................................................................................................................. 167

PIC24HJXXXGPX06A/X08A/X10A

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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Customer Notification System

PIC24HJXXXGPX06A/X08A/X10A

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of the PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest family reference sections of the

“dsPIC33F/PIC24H Family Reference Manual”, which is available from the

Microchip web site (www.microchip.com).

This document contains device specific information for the following devices:

• PIC24HJ64GP206A

• PIC24HJ64GP210A

• PIC24HJ64GP506A

• PIC24HJ64GP510A

• PIC24HJ128GP206A

• PIC24HJ128GP210A

• PIC24HJ128GP506A

• PIC24HJ128GP510A

• PIC24HJ128GP306A

• PIC24HJ128GP310A

• PIC24HJ256GP206A

• PIC24HJ256GP210A

• PIC24HJ256GP610A

The PIC24HJXXXGPX06A/X08A/X10A device family includes devices with different pin counts (64 and 100 pins), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes and 16 Kbytes).

This makes these families suitable for a wide variety of high-performance digital signal control applications. The devices are pin compatible with the dsPIC33F family of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration between device families as may be necessitated by the specific functionality, computational resource and system cost requirements of the application.

The PIC24HJXXXGPX06A/X08A/X10A device family employs a powerful 16-bit architecture, ideal for applications that rely on high-speed, repetitive computations, as well as control.

The 17 x 17 multiplier, hardware support for division operations, multi-bit data shifter, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the PIC24HJXXXGPX06A/X08A/X10A Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the PIC24HJXXXGPX06A/X08A/X10A devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use PIC24HJXXXGPX06A/X08A/X10A devices.

Figure 1-1 shows a general block diagram of the

various core and peripheral modules in the PIC24HJXXXGPX06A/X08A/X10A family of devices, while Ta b le 1 -1 lists the functions of the various pins shown in the pinout diagrams.

OSC1/CLKI

OSC2/CLKO

DD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC Oscillators

Regulator

Voltage

VCAP

UART1,2

ECAN1,2

IC1-8

OC/

SPI1,2

I2C1,2

PORTA

Note: Not all pins or features are implemented on all device pinout configurations. See Pin Diagrams for the specific pins and

features present on each device.

PWM1-8

CN1-23

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

PSV and Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Address Latch

Program Memory

Data Latch

Literal Data

Data Latch

Address

Latch

X RAM

Data Bus

17 x 17 Multiplier

Divide Support

DMA

RAM

DMA

Controller

Control Signals to Various Blocks

ADC1,2

Timers

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

Address Generator Units

1-9

PIC24HJXXXGPX06A/X08A/X10A

FIGURE 1-1: PIC24HJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM

PIC24HJXXXGPX06A/X08A/X10A

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN31 I Analog Analog input channels.

DD P P Positive supply for analog modules. This pin must be connected at all times.

AVSS P P Ground reference for analog modules.

CLKI CLKO

CN0-CN23 I ST Input change notification inputs.

C1RX C1TX C2RX C2TX

PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3

IC1-IC8 I ST Capture inputs 1 through 8.

INT0 INT1 INT2 INT3 INT4

MCLR

OCFA OCFB OC1-OC8

OSC1

OSC2

RA0-RA7 RA9-RA10 RA12-RA15

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC1-RC4 RC12-RC15

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RE0-RE7 I/O ST PORTE is a bidirectional I/O port.

RF0-RF8 RF12-RF13

RG0-RG3 RG6-RG9 RG12-RG15

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

Type

I/O

I I I I I

I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

I I

I/O

I/O I/O I/O

I/O I/O

I/O ST PORTF is a bidirectional I/O port.

I/O I/O I/O

Buffer

Typ e

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

—

ST ST ST ST ST ST

ST ST ST ST ST

ST ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS

ST ST ST

ST ST

ST ST ST

ECAN1 bus receive pin. ECAN1 bus transmit pin. ECAN2 bus receive pin. ECAN2 bus transmit pin.

Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3.

External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4.

Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare Fault B input (for Compare Channels 5, 6, 7 and 8). Compare outputs 1 through 8.

otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

Description

PIC24HJXXXGPX06A/X08A/X10A

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL1 SDA1 SCL2 SDA2

SOSCI SOSCO

TMS TCK TDI TDO

T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK

U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX

DD P — Positive supply for peripheral logic and I/O pins.

CAP P — CPU logic filter capacitor connection.

VSS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog voltage reference (high) input.

REF- I Analog Analog voltage reference (low) input.

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

Type

I/O

O I/O I/O

O I/O

I/O I/O I/O I/O

I I I

I I I I I I I I I

Buffer

Typ e

ST ST

— ST ST ST

— ST

ST ST ST ST

ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.

ST ST ST

—

ST ST ST ST ST ST ST ST ST

— ST

—

Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2.

32.768 kHz low-power oscillator crystal output.

JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin.

Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. Timer6 external clock input. Timer7 external clock input. Timer8 external clock input. Timer9 external clock input.

UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit.

Description

PIC24HJXXXGPX06A/X08A/X10A

1.1 Referenced Source

This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature.

Note: To access the documents listed below,

browse to the documentation section of the PIC24HJ256GP610A product page on the Microchip web site (www.microchip.com) or by selecting a family reference manual section from the following list.

In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections.

• Section 1. “Introduction” (DS70242)

• Section 2. “CPU” (DS70245)

• Section 3. “Data Memory” (DS70237)

• Section 4. “Program Memory” (DS70238)

• Section 5. “Flash Programming” (DS70228)

• Section 6. “Interrupts” (DS70224)

• Section 7. “Oscillator” (DS70227)

• Section 8. “Reset” (DS70229)

• Section 9. “Watchdog Timer and Power-Saving Modes” (DS70236)

• Section 10. “I/O Ports” (DS70230)

• Section 11. “Timers” (DS70244)

• Section 12. “Input Capture” (DS70248)

• Section 13. “Output Compare” (DS70247)

• Section 16. “Analog-to-Digital Converter (ADC)” (DS70225)

• Section 17. “UART” (DS70232)

• Section 18. “Serial Peripheral Interface (SPI)” (DS70243)

• Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70235)

• Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70226)

• Section 22. “Direct Memory Access (DMA)” (DS70223)

• Section 23. “CodeGuard™ Security” (DS70239)

• Section 24. “Programming and Diagnostics” (DS70246)

• Section 25. “Device Configuration” (DS70231)

• Section 26. “Development Tool Support” (DS70240)

PIC24HJXXXGPX06A/X08A/X10A

NOTES:

PIC24HJXXXGPX06A/X08A/X10A

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS

Note 1: This data sheet summarizes the features

of the PIC24HJXXXGPX06A/X08A/X10A family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections.

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

2.1 Basic Connection Requirements

Getting started with the PIC24HJXXXGPX06A/X08A/X10A family of 16-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected:

DD and VSS pins

• All V

(see Section 2.2 “Decoupling Capacitors”)

• All AV

•V

•MCLR

• PGECx/PGEDx pins used for In-Circuit Serial

• OSC1 and OSC2 pins when external oscillator

Additionally, the following pins may be required:

•V

DD and AVSS pins (regardless if ADC module

is not used) (see Section 2.2 “Decoupling Capacitors”)

CAP

(see Section 2.3 “CPU Logic Filter Capacitor

Connection (Vcap)”)

(see Section 2.4 “Master Clear (MCLR) Pin”)

Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”)

source is used (see Section 2.6 “External Oscillator Pins”)

REF+/VREF- pins used when external voltage

reference for ADC module is implemented

Note: The AV

connected independent of the ADC voltage reference source.

DD and AVSS pins must be

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of power supply pins, such as V AVSS is required.

Consider the following criteria when using decoupling capacitors:

• Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

• Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

DD, VSS, AVDD and

PIC24HJXXXGPX06A/X08A/X10A

PIC24H

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

MCLR

0.1 µF

Ceramic

VCAP

10 Ω

Note 1: R ≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the MCLR

pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR

from the external capacitor C, in the

event of MCLR

pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR

IH and VIL specifications are met.

MCLR

PIC24H

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

2.2.1 TANK CAPACITORS

On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including MCUs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device functions:

• Device Reset

• Device programming and debugging

During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.

For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR

pin during programming and debugging

operations.

Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

pin. Consequently,

pin.

2.3 CPU Logic Filter Capacitor

CAP)

Connection (V

A low-ESR (< 5 Ohms) capacitor is required on the

CAP pin, which is used to stabilize the voltage

V regulator output voltage. The V connected to V

4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 24.0

“Electrical Characteristics” for additional

information.

The placement of this capacitor should be close to the

CAP. It is recommended that the trace length not

V exceed one-quarter inch (6 mm). Refer to Section 21.2

“On-Chip Voltage Regulator” for details.

DD, and must have a capacitor between

CAP pin must not be

PIC24HJXXXGPX06A/X08A/X10A

Main Oscillator

Guard Ring

Guard Trace

Secondary Oscillator

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high

IH) and input low (VIL) requirements.

Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB

For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website.

• “MPLAB

• “Using MPLAB

• “MPLAB

• “Using MPLAB® ICD 3 In-Circuit Debugger”

• “MPLAB

• “Using MPLAB

ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.

ICD 2 In-Circuit Debugger User’s

Guide” DS51331

ICD 2” (poster) DS51265

ICD 2 Design Advisory” DS51566

(poster) DS51765

ICD 3 Design Advisory” DS51764

REAL ICE™ In-Circuit Emulator User’s

Guide” DS51616

REAL ICE™” (poster) DS51749

2.6 External Oscillator Pins

Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator

Configuration” for details).

The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR CIRCUIT

PIC24HJXXXGPX06A/X08A/X10A

2.7 Oscillator Value Conditions on Device Start-up

If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤8 MHz for start-up with PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed.

Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word.

2.8 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register.

The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device.

If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module.

When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality.

2.9 Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic-low state.

Alternatively, connect a 1k to 10k resistor between V and the unused pins.

PIC24HJXXXGPX06A/X08A/X10A

3.0 CPU

Note 1: This data sheet summarizes the features

“dsPIC33F/PIC24H Family Reference Manual”, which is available from the

Microchip website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

The PIC24HJXXXGPX06A/X08A/X10A CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point.

The PIC24HJXXXGPX06A/X08A/X10A devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

The PIC24HJXXXGPX06A/X08A/X10A instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJXXXGPX06A/X08A/X10A is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the PIC24HJXXXGPX06A/X08A/X10A is shown in

Figure 3-2.

3.1 Data Addressing Overview

The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM.

3.2 Special MCU Features

The PIC24HJXXXGPX06A/X08A/X10A features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible.

The PIC24HJXXXGPX06A/X08A/X10A supports 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle.

PIC24HJXXXGPX06A/X08A/X10A

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stac k

Control

Logic

Loop

Control

Logic

Control Signals

to Various Blocks

Literal Data

To Peripheral Modules

Data Latch

Address

Latch

X RAM

Address Generator Units

X Data Bus

DMA

Controller

DMA

RAM

17 x 17

Divide Support

PSV and Table

Data Access

Control Block

Program Memory

Data Latch

Address Latch

Multiplier

FIGURE 3-1: PIC24HJXXXGPX06A/X08A/X10A CPU CORE BLOCK DIAGRAM

PIC24HJXXXGPX06A/X08A/X10A

PC22

PC0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

Program Space Visibility Page Address

— — ——

RCOUNT

REPEAT Loop Counter

IPL2 IPL1

SPLIM

Stack Pointer Limit Register

SRL

PUSH.S Shadow

DO Shadow

——

Core Configuration Register

Legend

CORCON

— DC

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

FIGURE 3-2: PIC24HJXXXGPX06A/X08A/X10A PROGRAMMER’S MODEL

PIC24HJXXXGPX06A/X08A/X10A

3.3 CPU Control Registers

REGISTER 3-1: SR: CPU STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

(1)

R/W-0

IPL<2:0>

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: MCU ALU Half Carry/Borrow

1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)

0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress 0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow

1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

(2)

R/W-0

(2)

of the result occurred

data) of the result occurred

R/W-0

(2)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit

(2)

bit

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

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Datasheet PIC24HJ64GP206A, PIC24HJ64GP210A, PIC24HJ64GP506A, PIC24HJ64GP510A, PIC24HJ128GP206A Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Operating Range:

High-Performance CPU:

Direct Memory Access (DMA):

Interrupt Controller:

On-Chip Flash and SRAM:

System Management:

Power Management:

Timers/Capture/Compare/PWM:

Digital I/O:

Communication Modules:

Analog-to-Digital Converters:

CMOS Flash Technology:

Packaging:

PIC24H PRODUCT FAMILIES

PIC24H Family Controllers

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC24HJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM

1.1 Referenced Source

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS

2.1 Basic Connection Requirements

2.2 Decoupling Capacitors

2.2.1 TANK CAPACITORS

2.4 Master Clear (MCLR) Pin

2.5 ICSP Pins

2.6 External Oscillator Pins

2.7 Oscillator Value Conditions on Device Start-up

2.8 Configuration of Analog and Digital Pins During ICSP Operations

2.9 Unused I/Os

3.0 CPU

3.1 Data Addressing Overview

3.2 Special MCU Features

FIGURE 3-1: PIC24HJXXXGPX06A/X08A/X10A CPU CORE BLOCK DIAGRAM

FIGURE 3-2: PIC24HJXXXGPX06A/X08A/X10A PROGRAMMER’S MODEL

3.3 CPU Control Registers

REGISTER 3-1: SR: CPU STATUS REGISTER