Datasheet PIC24FV32KA304 Datasheet

PIC24FV32KA304 FAMILY

20/28/44/48-Pin, General Purpose, 16-Bit Flash

Microcontrollers with XLP Technology

Power Management Modes:

• Run – CPU, Flash, SRAM and Peripherals On

• Doze – CPU Clock Runs Slower than Peripherals

• Idle – CPU Off, Flash, SRAM and Peripherals On

• Sleep – CPU, Flash and Peripherals Off and SRAM on

• Deep Sleep – CPU, Flash, SRAM and Most Peripherals
Off; Multiple Autonomous Wake-up Sources

• Low-Power Consumption:

- Run mode currents down to 8 μA, typical

- Idle mode currents down to 2.2 μA, typical

- Deep Sleep mode currents down to 20 nA, typical

- Real-Time Clock/Calendar currents down to

700 nA, 32 kHz, 1.8V

-

Watchdog Timer 500 nA, 1.8V typical

High-Performance CPU:

• Modified Harvard Architecture

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options

• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier

• 32-Bit by 16-Bit Hardware Divider, 16-Bit x 16-Bit
Working Register Array

• C Compiler Optimized Instruction Set Architecture

Peripheral Features:

• Hardware Real-Time Clock and Calendar (RTCC):

- Provides clock, calendar and alarm functions

- Can run in Deep Sleep mode

- Can use 50/60 Hz power line input as clock source

• Programmable 32-bit Cyclic Redundancy Check
(CRC)

• Multiple Serial Communication modules:

- Two 3-/4-wire SPI modules

2

-Two I

- Two UART modules supporting RS-485, RS-232,

• Five 16-Bit Timers/Counters with Programmable
Prescaler:

- Can be paired as 32-bit timers/counters

• Three 16-Bit Capture Inputs with Dedicated Timers

• Three 16-Bit Compare/PWM Output with Dedicated
Timers

• Configurable Open-Drain Outputs on Digital I/O Pins

• Up to Three External Interrupt Sources

C™ modules with multi-master/slave support

LIN/J2602, IrDA

®

Analog Features:

• 12-Bit, Up to 16-Channel Analog-to-Digital Converter:

- 100 ksps conversion rate

- Conversion available during Sleep and Idle

- Auto-sampling timer-based option for Sleep and
Idle modes

- Wake on auto-compare option

• Dual Rail-to-Rail Analog Comparators with
Programmable Input/Output Configuration

• On-Chip Voltage Reference

• Internal Temperature Sensor

• Charge Time Measurement Unit (CTMU):

- Used for capacitance sensing, 16 channels

- Time measurement, down to 200 ps resolution

-

Delay/pulse generation, down to 1 ns resolution

Special Microcontroller Features:

• Wide Operating Voltage Range:

- 1.8V to 3.6V (PIC24F devices)

- 2.0V to 5.5V (PIC24FV devices)

• Low Power Wake-up Sources and Supervisors:

- Ultra-Low Power Wake-up (ULPWU) for

Sleep/Deep Sleep

- Low-Power Watchdog Timer (DSWDT) for

Deep Sleep

- Extreme Low-Power Brown-out Reset (DSBOR)

for Deep Sleep, LPBOR for all other modes

• System Frequency Range Declaration bits:

- Declaring the frequency range optimizes the

current consumption.

• Standard Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation

• Programmable High/Low-Voltage Detect (HLVD)

• Standard Brown-out Reset (BOR) with 3 Programmable
Trip Points that can be Disabled in Sleep

•

High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

• Flash Program Memory:

- Erase/write cycles: 10,000 minimum

- 40 years’ data retention minimum

• Data EEPROM:

- Erase/write cycles: 100,000 minimum

- 40 years’ data retention minimum

• Fail-Safe Clock Monitor (FSCM)

• Programmable Reference Clock Output

• Self-Programmable under Software Control

• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins

 2011-2012 Microchip Technology Inc. DS39995C-page 1

PIC24FV32KA304 FAMILY

Memory

PIC24F
Device

PIC24FV16KA301/
PIC24F16KA301

PIC24FV32KA301/
PIC24F32KA301

PIC24FV16KA302/
PIC24F16KA302

PIC24FV32KA302/
PIC24F32KA302

PIC24FV16KA304/
PIC24F16KA304

PIC24FV32KA304/
PIC24F32KA304

Pins

Flash

2016K2K51253322212312Y

2032K2K51253322212312Y

2816K2K51253322213313Y

2832K2K51253322213313Y

4416K2K51253322216316Y

4432K2K51253322216316Y

SRAM

(bytes)

Program

(bytes)

Timers

(bytes)

EE Data

Input

16-Bit

Capture

Compare/PWM

Output

®

IrDA

UART w/

SPI

2

C™
I

RTCC

CTMU (ch)

Comparators

12-Bit A/D (ch)

DS39995C-page 2  2011-2012 Microchip Technology Inc.

Pin Diagrams

Legend: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices.
Note 1: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant.

20-Pin SPDIP/SSOP/SOIC

(1)

24FVXXKA301

MCLR/RA5

RA3

RA0
RA1

V

DD

VSS

RB0

RB7

RA4

RB4

RB8

RA2

RB2

RB1

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16

15
14

13
12

11

RB15
RB14
RB13
RB12

RB9

RA6 or V

CAP

Pin

Pin Features

PIC24FVXXKA301 PIC24FXXKA301

1MCLR

/VPP/RA5 MCLR/VPP/RA5

2 PGEC2/V

REF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0 PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0

3 PGED2/CV

REF-/VREF-/AN1/SDO2/CN3/RA1 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1

4 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/SDI2/

OC2/CN4/RB0

PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/SDI2/
OC2/CN4/RB0

5 PGEC1/AN3/C1INC/C2INA/U2RX/OC3/CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/OC3/CTED12/CN5/RB1

6 AN4/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 AN4/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2

7 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2

8 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3

9 PGED3/SOSCI/AN15/U2RTS

/CN1/RB4 PGED3/SOSCI/AN15/U2RTS/CN1/RB4

10 PGEC3/SOSCO/SCLKI/U2CTS

/CN0/RA4 PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4

11 U1TX/C2OUT/OC1/IC1/CTED1/INT0/CN23/RB7 U1TX/INT0/CN23/RB7

12 SCL1/U1CTS

/C3OUT/CTED10/CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8

13 SDA1/T1CK/U1RTS

/IC2/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9

14 V

CAP C2OUT/OC1/IC1/CTED1/INT2/CN8/RA6

15 AN12/HLVDIN/SCK1/SS2

/IC3/CTED2/INT2/CN14/RB12 AN12/HLVDIN/SCK1/SS2/IC3/CTED2/CN14/RB12

16 AN11/SDO1/OCFB/CTPLS/CN13/RB13 AN11/SDO1/OCFB/CTPLS/CN13/RB13

17 CV

REF/AN10/C3INB/RTCC/SDI1/C1OUT/OCFA/CTED5/INT1/

CN12/RB14

CVREF/AN10/C3INB/RTCC/SDI1/C1OUT/OCFA/CTED5/INT1/
CN12/RB14

18 AN9/C3INA/SCL2/T3CK/T2CK/REFO/SS1

/CTED6/CN11/RB15 AN9/C3INA/SCL2/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15

19 V

SS/AVSS VSS/AVSS

20 VDD/AVDD VDD/AVDD

24FXXKA301

PIC24FV32KA304 FAMILY

 2011-2012 Microchip Technology Inc. DS39995C-page 3

PIC24FV32KA304 FAMILY

28-Pin SPDIP/SSOP/SOIC

(1,2)

PIC24FVXXKA302

MCLR/RA5

V

SS

VDD

RA0
RA1

V

DD

VSS

RB0

RB6

RA4

RB4

RA7

RA3

RA2

RA6 or V

CAP

RB7

RB9
RB8

RB3

RB2

RB1

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24

23

22
21

20

19
18
17

16

15

RB15
RB14
RB13
RB12

RB10

RB11

RB5

Pin

Pin Features

PIC24FVXXKA302 PIC24FXXKA302

1MCLR

/VPP/RA5 MCLR/VPP/RA5

2V

REF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0

3CV

REF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1

4 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0

PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0

5 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1

6 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2

7 AN5/C1INA/C2INC/SCL2/CN7/RB3 AN5/C1INA/C2INC/SCL2/CN7/RB3

8V

SS VSS

9 OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2

10 OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3

11 SOSCI/AN15/U2RTS

/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4

12 SOSCO/SCLKI/U2CTS

/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4

13 V

DD VDD

14 PGED3/ASDA

(1)

/SCK2/CN27/RB5 PGED3/ASDA

(1)

/SCK2/CN27/RB5

15 PGEC3/ASCL

(1)

/SDO2/CN24/RB6 PGEC3/ASCL

(1)

/SDO2/CN24/RB6

16 U1TX/C2OUT/OC1/INT0/CN23/RB7 U1TX/INT0/CN23/RB7

17 SCL1/U1CTS

/C3OUT/CTED10/CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8

18 SDA1/T1CK/U1RTS

/IC2/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9

19 SDI2/IC1/CTED3/CN9/RA7 SDI2/IC1/CTED3/CN9/RA7

20 V

CAP C2OUT/OC1/CTED1/INT2/CN8/RA6

21 PGED2/SDI1/OC3/CTED11/CN16/RB10 PGED2/SDI1/OC3/CTED11/CN16/RB10

22 PGEC2/SCK1/OC2/CTED9/CN15/RB11 PGEC2/SCK1/OC2/CTED9/CN15/RB11

23 AN12/HLVDIN/SS2

/IC3/CTED2/INT2/CN14/RB12 AN12/HLVDIN/SS2/IC3/CTED2/CN14/RB12

24 AN11/SDO1/OCFB/CTPLS/CN13/RB13 AN11/SDO1/OCFB/CTPLS/CN13/RB13

25 CV

REF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/RB14 CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/

RB14

26 AN9/C3INA/T3CK/T2CK/REFO/SS1

/CTED6/CN11/RB15 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15

27 V

SS/AVSS VSS/AVSS

28 VDD/AVDD VDD/AVDD

PIC24FXXKA302

Legend: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices.
Note 1: Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set.

2: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V toleran.t

Pin Diagrams

DS39995C-page 4  2011-2012 Microchip Technology Inc.

Pin Diagrams

Legend: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices.
Note 1: Exposed pad on underside of device is connected to V

SS.

2: Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set.
3: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant.

28-Pin QFN

(1,2,3)

10 11

2
3

6

1

18

19

20

21

22

12 1314

15

8

7

16

17

232425262728

9

PIC24FVXXKA302

5

4

MCLR/RA5

VSS

VDD

RA0

RA1

VDDVSS

RB0

RB6

RA4

RB4

RA7

RA3

RA2

RA6 or V

CAP

RB7

RB9

RB8

RB3

RB2

RB1

RB15

RB14

RB13
RB12

RB10

RB11

RB5

Pin

Pin Features

PIC24FVXXKA302 PIC24FXXKA302

1

PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0

PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0

2 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1

3 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2

4 AN5/C1INA/C2INC/SCL2/CN7/RB3 AN5/C1INA/C2INC/SCL2/CN7/RB3

5V

SS VSS

6 OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2

7 OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3

8 SOSCI/AN15/U2RTS

/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4

9 SOSCO/SCLKI/U2CTS

/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4

10 V

DD VDD

11 PGED3/ASDA1

(2)

/SCK2/CN27/RB5 PGED3/ASDA1

(2)

/SCK2/CN27/RB5

12 PGEC3/ASCL1

(2)

/SDO2/CN24/RB6 PGEC3/ASCL1

(2)

/SDO2/CN24/RB6

13 U1TX/C2OUT/OC1/INT0/CN23/RB7 U1TX/INT0/CN23/RB7

14 SCL1/U1CTS

/C3OUT/CTED10/CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8

15 SDA1/T1CK/U1RTS

/IC2/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9

16 SDI2/IC1/CTED3/CN9/RA7 SDI2/IC1/CTED3/CN9/RA7

17 V

CAP C2OUT/OC1/CTED1/INT2/CN8/RA6

18 PGED2/SDI1/OC3/CTED11/CN16/RB10 PGED2/SDI1/OC3/CTED11/CN16/RB10

19 PGEC2/SCK1/OC2/CTED9/CN15/RB11 PGEC2/SCK1/OC2/CTED9/CN15/RB11

20 AN12/HLVDIN/SS2

/IC3/CTED2/INT2/CN14/RB12 AN12/HLVDIN/SS2/IC3/CTED2/CN14/RB12

21 AN11/SDO1/OCFB/CTPLS/CN13/RB13 AN11/SDO1/OCFB/CTPLS/CN13/RB13

22 CV

REF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/

RB14

CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/
RB14

23 AN9/C3INA/T3CK/T2CK/REFO/SS1

/CTED6/CN11/RB15 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15

24 V

SS/AVSS VSS/AVSS

25 VDD/AVDD VDD/AVDD

26 MCLR/VPP/RA5 MCLR/VPP/RA5

27 V

REF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 VREF+/CVREF+/AN0/C3INC/CN2/RA0

28 CV

REF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1

PIC24FXXKA302

PIC24FV32KA304 FAMILY

 2011-2012 Microchip Technology Inc. DS39995C-page 5

PIC24FV32KA304 FAMILY

Legend: Pin numbers in bold indicate pin

function differences between
PIC24FV and PIC24F devices.

Note 1: Exposed pad on underside of device

is connected to V

SS.

2: Alternative multiplexing for SDA1

(ASDA1) and SCL1 (ASCL1) when
the I2CSEL Configuration bit is set.

3: PIC24F32KA304 device pins have a

maximum voltage of 3.6V and are not
5V tolerant.

Pin

Pin Features

PIC24FVXXKA304 PIC24FXXKA304

1 SDA1/T1CK/U1RTS

/CTED4/CN21/

RB9

SDA1/T1CK/U1RTS/CTED4/CN21/
RB9

2 U1RX/CN18/RC6 U1RX/CN18/RC6

3 U1TX/CN17/RC7 U1TX/CN17/RC7

4 OC2/CN20/RC8 OC2/CN20/RC8

5 IC2/CTED7/CN19/RC9 IC2/CTED7/CN19/RC9

6 IC1/CTED3/CN9/RA7 IC1/CTED3/CN9/RA7

7V

CAP C2OUT/OC1/CTED1/INT2/CN8/RA6

8 PGED2/SDI1/CTED11/CN16/RB10 PGED2/SDI1/CTED11/CN16/RB10

9 PGEC2/SCK1/CTED9/CN15/RB11 PGEC2/SCK1/CTED9/CN15/RB11

10 AN12/HLVDIN/CTED2 /INT2/CN14/

RB12

AN12/HLVDIN/CTED2/CN14/RB12

11 AN11/SDO1/CTPLS/CN13/RB13 AN11/SDO1/CTPLS/CN13/RB13

12 OC3/CN35/RA10 OC3/CN35/RA10

13 IC3/CTED8/CN36/RA11 IC3/CTED8/CN36/RA11

14 CV

REF/AN10/C3INB/RTCC/

C1OUT/OCFA/CTED5/INT1/CN12/
RB14

CV

REF/AN10/C3INB/RTCC/

C1OUT/OCFA/CTED5/INT1/CN12/
RB14

15 AN9/C3INA/T3CK/T2CK/REFO/

SS1

/CTED6/CN11/RB15

AN9/C3INA/T3CK/T2CK/REFO/
SS1/CTED6/CN11/RB15

16 V

SS/AVSS VSS/AVSS

17 VDD/AVDD VDD/AVDD

18 MCLR/VPP/RA5 MCLR/VPP/RA5

19 V

REF+/CVREF+/AN0/C3INC/

CTED1/CN2/RA0

VREF+/CVREF+/AN0/C3INC/CN2/
RA0

20 CV

REF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1

21

PGED1/AN2/ULPWU/CTCMP/
C1IND/C2INB/C3IND/U2TX/CN4/RB0

PGED1/AN2/ULPWU/CTCMP/C1IND/
C2INB/C3IND/U2TX/CN4/RB0

22 PGEC1/AN3/C1INC/C2INA/U2RX/

CTED12/CN5/RB1

PGEC1/AN3/C1INC/C2INA/U2RX/
CTED12/CN5/RB1

23 AN4/C1INB/C2IND/SDA2/T5CK/

T4CK/CTED13/CN6/RB2

AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2

24 AN5/C1INA/C2INC/SCL2/CN7/

RB3

AN5/C1INA/C2INC/SCL2/CN7/RB3

25 AN6/CN32/RC0 AN6/CN32/RC0

26 AN7/CN31/RC1 AN7/CN31/RC1

27 AN8/CN10/RC2 AN8/CN10/RC2

28 V

DD VDD

29 VSS VSS

30 OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2

31 OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3

32 OCFB/CN33/RA8 OCFB/CN33/RA8

33 SOSCI/AN15/U2RTS

/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4

34 SOSCO/SCLKI/U2CTS

/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4

35 SS2

/CN34/RA9 SS2/CN34/RA9

36 SDI2/CN28/RC3 SDI2/CN28/RC3

37 SDO2/CN25/RC4 SDO2/CN25/RC4

38 SCK2/CN26/RC5 SCK2/CN26/RC5

39 V

SS VSS

40 VDD VDD

41 PGED3/ASDA1

(2)

/CN27/RB5 PGED3/ASDA1

(2)

/CN27/RB5

42 PGEC3/ASCL1

(2)

/CN24/RB6 PGEC3/ASCL1

(2)

/CN24/RB6

43 C2OUT/OC1/INT0/CN23/RB7 INT0/CN23/RB7

44 SCL1/U1CTS

/C3OUT/CTED10/

CN22/RB8

SCL1/U1CTS/C3OUT/CTED10/
CN22/RB8

10

11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

PIC24FVXXKA304

37

RB8

RB7

RB6

RB5

V

DD

VSS

RC5

RC4

RC3

RA9

RA4

RB4
RA8
RA3
RA2
V

SS

VDD
RC2
RC1
RC0
RB3
RB2

RB9
RC6
RC7
RC8
RC9
RA7

RA6 or V

CAP

RB10
RB11
RB12
RB13

RB1

RB0

RA1

RA0

MCLR

/RA5

V

DD

VSS

RB15

RB14

RA11

RA10

44-Pin TQFP/QFN

(1,2,3)

PIC24FXXKA304

Pin Diagrams

DS39995C-page 6  2011-2012 Microchip Technology Inc.

Pin Diagrams

Pin

Pin Features

PIC24FVXXKA304 PIC24FXXKA304

1

SDA1/T1CK/U1RTS/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/CTED4/CN21/

RB9

2

U1RX/CN18/RC6 U1RX/CN18/RC6

3

U1TX/CN17/RC7 U1TX/CN17/RC7

4

OC2/CN20/RC8 OC2/CN20/RC8

5

IC2/CTED7/CN19/RC9 IC2/CTED7/CN19/RC9

6

IC1/CTED3/CN9/RA7 IC1/CTED3/CN9/RA7

7VCAP C20UT/OC1/CTED1/INT2CN8/RA6

8N/C N/C

9

PGED2/SDI1/CTED11/CN16/RB10 PGED2/SDI1/CTED11/CN16/RB10

10

PGEC2/SCK1/CTED9/CN15/RB11 PGEC2/SCK1/CTED9/CN15/RB11

11

AN12/HLVDIN/CTED2/

INT2/

CN14/RB12 AN12/HLVDIN/CTED2/CN14/RB12

12

AN11/SDO1/CTPLS/CN13/RB13 AN11/SDO1/CTPLS/CN13/RB13

13

OC3/CN35/RA10 OC3/CN35/RA10

14

IC3/CTED8/CN36/RA11 IC3/CTED8/CN36/RA11

15

CV

REF

/AN10/C3INB/RTCC/

C1OUT/OCFA/CTED5/

INT1/

CN12/RB14

CV

REF

/AN10/C3INB/RTCC/C1OUT/

OCFA/CTED5/

INT1/

CN12/RB14

16

AN9/C3INA/T3CK/T2CK/REFO/
SS1

/CTED6/CN11/RB15

AN9/C3INA/T3CK/T2CK/REFO/
SS1/CTED6/CN11/RB15

17 VSS/AVSS VSS/AVSS

18 VDD/AVDD VDD/AVDD

19 MCLR/RA5 MCLR/RA5

20 N/C N/C

21

V

REF

+/CV

REF

+/AN0/C3INC/

CTED1/CN2/RA0

V

REF

+/CV

REF

+/AN0/C3INC/CN2/

RA0

22

CV

REF

-/V

REF

-/AN1/CN3/RA1 CV

REF

-/V

REF

-/AN1/CN3/RA1

23

PGED1/AN2/ULPWU/CTCMP/C1IND/
C2INB/C3IND/U2TX/CN4/RB0

PGED1/AN2/ULPWU/CTCMP/C1IND/
C2INB/C3IND/U2TX/CN4/RB0

24

PGEC1/AN3/C1INC/C2INA/U2RX/
CTED12/CN5/RB1

PGEC1/AN3/C1INC/C2INA/U2RX/
CTED12/CN5/RB1

25

AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2

AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2

26

AN5/C1INA/C2INC/SCL2/CN7/RB3 AN5/C1INA/C2INC/SCL2/CN7/RB3

27

AN6/CN32/RC0 AN6/CN32/RC0

28

AN7/CN31/RC1 AN7/CN31/RC1

29

AN8/CN10/RC2 AN8/CN10/RC2

30 VDD VDD

31 VSS VSS

32 N/C N/C

33

OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2

34

OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3

35

OCFB/CN33/RA8 OCFB/CN33/RA8

36

SOSCI/AN15/U2RTS/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4

37

SOSCO/SCLKI/U2CTS/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4

38

SS2/CN34/RA9 SS2/CN34/RA9

39

SDI2/CN28/RC3 SDI2/CN28/RC3

40

SDO2/CN25/RC4 SDO2/CN25/RC4

41

SCK2/CN26/RC5 SCK2/CN26/RC5

42 VSS VSS

43 VDD VDD

44 N/C N/C

45

PGED3/ASDA1

(2)

/CN27/RB5 PGED3/ASDA1

(2)

/CN27/RB5

46

PGEC3/ASCL1

(2)

/CN24/RB6 PGEC3/ASCL1

(2)

/CN24/RB6

47

C2OUT/OC1/

INT0/

CN23/RB7

INT0/

CN23/RB7

48

SCL1/U1CTS/C3OUT/CTED10/
CN22/RB8

SCL1/U1CTS/C3OUT/CTED10/
CN22/RB8

R

B

8

R

B

7

R

B

6

R

B

5

N

/

C

V

D

D

V

S

S

R

C

5

R

C

4

R

C

3

R

A

9

R

A

4

RB9

RB4

RC6

RA8

RC7

RA3

RC8

RA2

RC9

N/C

RA7

V

SS

RA6 or V

CAP

V

DD

N/C

RC2

RB10

RC1

RB11

RC0

RB12

RB3

RB13

RB2

R

A

1

0

R

A

1

1

R

B

1

4

R

B

1

5

V

S

S

/

A

V

S

S

V

D

D

/

A

V

D

D

N

/

C

R

A

0

R

A

1

R

B

0

R

B

1

Legend: Pin numbers in bold indicate pin func-

tion differences between PIC24FV and
PIC24F devices.

Note 1: Exposed pad on underside of device is

connected to V

SS.

2: Alternative multiplexing for SDA1

(ASDA1) and SCL1 (ASCL1) when the
I2CSEL Configuration bit is set.

3: PIC24F32KA3XX device pins have a

maximum voltage of 3.6V and are not
5V tolerant.

48-Pin UQFN

(1,2,3)

M

C

L

R

/

R

A

5

4

8

4

7

4

6

4

5

4

4

4

3

4

2

4

1

4

0

3

9

3

8

3

7

36
35
34
33
32
31
30
29
28
27
26
25

1

3

1

4

1

5

1

6

1

7

1

8

1

9

2

0

2

1

2

2

2

3

2

4

PIC24FVXXKA304

PIC24FXXKA304

1

2
3
4
5
6

7

8
9
10
11

12

PIC24FV32KA304 FAMILY

 2011-2012 Microchip Technology Inc. DS39995C-page 7

PIC24FV32KA304 FAMILY

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 23

3.0 CPU ........................................................................................................................................................................................... 29

4.0 Memory Organization ................................................................................................................................................................. 35

5.0 Flash Program Memory.............................................................................................................................................................. 57

6.0 Data EEPROM Memory ............................................................................................................................................................. 63

7.0 Resets ........................................................................................................................................................................................ 69

8.0 Interrupt Controller ..................................................................................................................................................................... 75

9.0 Oscillator Configuration ............................................................................................................................................................ 113

10.0 Power-Saving Features............................................................................................................................................................ 123

11.0 I/O Ports ................................................................................................................................................................................... 135

12.0 Timer1 ..................................................................................................................................................................................... 139

13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................. 141

14.0 Input Capture with Dedicated Timers ....................................................................................................................................... 147

15.0 Output Compare with Dedicated Timers .................................................................................................................................. 151

16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 161

17.0 Inter-Integrated Circuit™ (I

18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 177

19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 185

20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 199

21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 205

22.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 207

23.0 Comparator Module.................................................................................................................................................................. 225

24.0 Comparator Voltage Reference................................................................................................................................................ 229

25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 231

26.0 Special Features ...................................................................................................................................................................... 239

27.0 Development Support............................................................................................................................................................... 251

28.0 Instruction Set Summary.......................................................................................................................................................... 255

29.0 Electrical Characteristics.......................................................................................................................................................... 263

30.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 295

31.0 Packaging Information.............................................................................................................................................................. 315

Appendix A: Revision History............................................................................................................................................................. 339

Index .................................................................................................................................................................................................. 341

The Microchip Web Site..................................................................................................................................................................... 347

Customer Change Notification Service .............................................................................................................................................. 347

Customer Support .............................................................................................................................................................................. 347

Reader Response .............................................................................................................................................................................. 348

Product Identification System............................................................................................................................................................. 349

2

C™).............................................................................................................................................. 169

DS39995C-page 8  2011-2012 Microchip Technology Inc.

PIC24FV32KA304 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2011-2012 Microchip Technology Inc. DS39995C-page 9

PIC24FV32KA304 FAMILY

NOTES:

DS39995C-page 10  2011-2012 Microchip Technology Inc.

PIC24FV32KA304 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC24FV16KA301, PIC24F16KA301

• PIC24FV16KA302, PIC24F16KA302

• PIC24FV16KA304, PIC24F16KA304

• PIC24FV32KA301, PIC24F32KA301

• PIC24FV32KA302, PIC24F32KA302

• PIC24FV32KA304, PIC24F32KA304

The PIC24FV32KA304 family introduces a new line of
extreme low-power Microchip devices. This is a 16-bit
microcontroller family with a broad peripheral feature set
and enhanced computational performance. This family
also offers a new migration option for those
high-performance applications which may be
outgrowing their 8-bit platforms, but do not require the
numerical processing power of a digital signal processor.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s

®

digital signal controllers. The PIC24F CPU core

dsPIC
offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces

• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)

• A 16-element working register array with built-in
software stack support

• A 17 x 17 hardware multiplier with support for
integer math

• Hardware support for 32-bit by 16-bit division

• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as C

• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

All of the devices in the PIC24FV32KA304 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
features include:

• On-the-Fly Clock Switching: The device clock

can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing users to
incorporate power-saving ideas into their software
designs.

• Doze Mode Operation: When timing-sensitive

applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.

• Instruction-Based Power-Savi ng Modes: There

are three instruction-based power-saving modes:

- Idle Mode: The core is shut down while leaving
the peripherals active.

- Sleep Mode: The core and peripherals that
require the system clock are shut down, leaving
the peripherals that use their own clock, or the
clock from other devices, active.

- Deep Sleep Mode: The core, peripherals
(except RTCC and DSWDT), Flash and SRAM
are shut down.

1.1.3 OSCILLATOR OPTIONS AND FEATURES

The PIC24FV32KA304 family offers five different
oscillator options, allowing users a range of choices in
developing application hardware. These include:

• Two Crystal modes using crystals or ceramic

resonators.

• Two External Clock modes offering the option of a

divide-by-2 clock output.

• Two Fast Internal oscillators (FRCs): One with a

nominal 8 MHz output and the other with a
nominal 500 kHz output. These outputs can also
be divided under software control to provide clock
speed as low as 31 kHz or 2 kHz.

• A Phase Locked Loop (PLL) frequency multiplier,

available to the external Oscillator modes and the
8 MHz FRC oscillator, which allows clock speeds
of up to 32 MHz.

• A separate internal RC oscillator (LPRC) with a

fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.

 2011-2012 Microchip Technology Inc. DS39995C-page 11

PIC24FV32KA304 FAMILY

The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the
internal oscillator and enables the controller to switch to
the internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.

1.1.4 EASY MIGRATION

Regardless of the memory size, all the devices share
the same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.

The consistent pinout scheme used throughout the
entire family also helps in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 20-pin or
28-pin devices to 44-pin/48-pin devices.

The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex.

1.2 Other Special Features

• Communications: The PIC24FV32KA304 family

incorporates a range of serial communication
peripherals to handle a range of application
requirements. There is an I
supports both the Master and Slave modes of
operation. It also comprises UARTs with built-in

®

encoders/decoders and an SPI module.

IrDA

• Real-Time Clock/Calendar: This module

implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.

• 12-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
faster sampling speed. The 16-deep result buffer
can be used either in Sleep to reduce power, or in
Active mode to improve throughput.

• Charge Time Measurement Unit (CTMU)
Interface: The PIC24FV32KA304 family includes

the new CTMU interface module, which can be
used for capacitive touch sensing, proximity
sensing, and also for precision time measurement
and pulse generation.

2

C™ module that

1.3 Details on Individual Family Members

Devices in the PIC24FV32KA304 family are available
in 20-pin, 28-pin, 44-pin and 48-pin packages. The
general block diagram for all devices is shown in

Figure 1-1.

The devices are different from each other in four ways:

1. Flash program memory (16 Kbytes for

PIC24FV16KA devices, 32 Kbytes for
PIC24FV32KA devices).

2. Available I/O pins and ports (18 pins on two

ports for 20-pin devices, 22 pins on two ports for
28-pin devices and 38 pins on three ports for
44/48-pin devices).

3. Alternate SCLx and SDAx pins are available

only in 28-pin, 44-pin and 48-pin devices and not
in 20-pin devices.

4. Members of the PIC24FV32KA301 family are

available as both standard and high-voltage
devices. High-voltage devices, designated with
an “FV” in the part number (such as
PIC24FV32KA304), accommodate an operating

DD range of 2.0V to 5.5V, and have an

V
on-board voltage regulator that powers the core.
Peripherals operate at VDD. Standard devices,
designated by “F” (such as PIC24F32KA304),
function over a lower VDD range of 1.8V to 3.6V.
These parts do not have an internal regulator,
and both the core and peripherals operate
directly from V

All other features for devices in this family are identical;
these are summarized in Ta bl e 1 -1 .

A list of the pin features available on the
PIC24FV32KA304 family devices, sorted by function,
is provided in Table 1-3.

Note: Table 1-1 provides the pin location of

DD.

individual peripheral features and not how
they are multiplexed on the same pin. This
information is provided in the pinout
diagrams on pages 3, 4, 5, 6 and 7 of the
data sheet. Multiplexed features are
sorted by the priority given to a feature,
with the highest priority peripheral being
listed first.

DS39995C-page 12  2011-2012 Microchip Technology Inc.

PIC24FV32KA304 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FV32KA304 FAMILY

Features

PIC24FV16KA301

Operating Frequency DC – 32 MHz

Program Memory (bytes) 16K 32K 16K 32K 16K 32K

Program Memory (instructions) 5632 11264 5632 11264 5632 11264

Data Memory (bytes) 2048

Data EEPROM Memory (bytes) 512

Interrupt Sources (soft vectors/
NMI traps)

I/O Ports PORTA<5:0>

PORTB<15:12,9:7,4,2:0>

Total I/O Pins 17 23 38

Timers: Total Number (16-bit) 5

32-Bit (from paired 16-bit timers) 2

Input Capture Channels 3

Output Compare/PWM Channels 3

Input Change Notification Interrupt 16 22 37

Serial Communications: UART
SPI (3-wire/4-wire)

2

C™ 2

I

12-Bit Analog-to-Digital Module
(input channels)

Analog Comparators 3
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 20-Pin

PDIP/SSOP/SOIC

12 13 16

REPEAT Instruction, Hardware Traps, Configuration Word Mismatch

PIC24FV32KA301

( P WR T, OS T, P L L L oc k )

PIC24FV16KA302

30 (26/4)

PORTA<7,5:0>

PORTB<15:0>

2

28-Pin

SPDIP/SSOP/SOIC/QFN

PIC24FV32KA302

PIC24FV16KA304

PORTA<11:7,5:0>

PORTB<15:0>

PORTC<9:0>

44-Pin QFN/TQFP

48-Pin UQFN

PIC24FV32KA304

 2011-2012 Microchip Technology Inc. DS39995C-page 13

PIC24FV32KA304 FAMILY

TABLE 1-2: DEVICE FEATURES FOR THE PIC24F32KA304 FAMILY

Features

PIC24F16KA301

Operating Frequency DC – 32 MHz

Program Memory (bytes) 16K 32K 16K 32K 16K 32K

Program Memory (instructions) 5632 11264 5632 11264 5632 11264

Data Memory (bytes) 2048

Data EEPROM Memory (bytes) 512

Interrupt Sources (soft vectors/
NMI traps)

I/O Ports PORTA<6:0>,

PORTB<15:12, 9:7, 4, 2:0>

Total I/O Pins 18 24 39

Timers: Total Number (16-bit) 5

32-Bit (from paired 16-bit timers) 2

Input Capture Channels 3

Output Compare/PWM Channels 3

Input Change Notification Interrupt 17 23 38

Serial Communications: UART
SPI (3-wire/4-wire)

2

C™ 2

I

12-Bit Analog-to-Digital Module
(input channels)

Analog Comparators 3
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 20-Pin

PDIP/SSOP/SOIC

12 13 16

REPEAT Instruction, Hardware Traps, Configuration Word Mismatch

PIC24F32KA301

( P WR T, OS T, P L L L oc k )

PIC24F16KA302

30 (26/4)

PORTA<7:0>,

PORTB<15:0>

2

28-Pin

SPDIP/SSOP/SOIC/QFN

PIC24F32KA302

PIC16F16KA304

PORTA<11:0>,

PORTB<15:0>,

PORTC<9:0>

44-Pin QFN/TQFP

48-Pin UQFN

PIC24F32KA304

DS39995C-page 14  2011-2012 Microchip Technology Inc.

PIC24FV32KA304 FAMILY

Instruction

Decode and

Control

16

PCH PCL

16

Program Counter

16-Bit ALU

23

24

Data Bus

Inst Register

16

Divide

Support

Inst Latch

16

EA MUX

Read AGU
Write AGU

16

16

8

Interrupt

Controller

PSV and Table

Data Access
Control Block

Stac k

Control

Logic

Repeat
Control

Logic

Data Latch

Data RAM

Address

Latch

Address Latch

Program Memory

Data Latch

16

Address Bus

Literal Data

23

Control Signals

16

16

16 x 16

W Reg Array

Multiplier

17x17

PORTA

(1)

RA<0:7>

PORTB

(1)

RB<0:15>

Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-3 for I/O port pin

descriptions.

Comparators

Timer4/5

Timer2/3

CTMU

IC1-3

A/D

12-Bit

PWM/

SPI1

I2C1

CN1-22

(1)

UART1/2

Data EEPROM

OSCI/CLKI

OSCO/CLKO

V

DD, VSS

Timi ng

Generation

MCLR

Power-up

Time r

Oscillator

Star t -u p Ti mer

Power-on

Reset

Watchdog

Time r

BOR

FRC/LPRC
Oscillators

DSWDT

Timer1RTCC

REFO

OC1-3

HLVD

PORTC

(1)

RC<9:0>

Precision

Reference

Band Gap

Voltag e

V

CAP

Regulator

FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM

 2011-2012 Microchip Technology Inc. DS39995C-page 15

DS39995C-page 16  2011-2012 Microchip Technology Inc.

PIC24FV32KA304 FAMILY

TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS

FFV

Pin Number Pin Number

Function

AN0 2 2 27 19 21 2 2 27 19 21 I ANA A/D Analog Inputs

AN1 3 32820223 3282022IANA

AN2 4 4 1 21 23 4 4 1 21 23 I ANA

AN3 5 5 2 22 24 5 5 2 22 24 I ANA

AN4 6 6 3 23 25 6 6 3 23 25 I ANA

AN5 — 7 4 24 26 — 7 4 24 26 I ANA

AN6 — — — 25 27 — — — 25 27 I ANA

AN7 — — — 26 28 — — — 26 28 I ANA

AN8 — — — 27 29 — — — 27 29 I ANA

AN9 18 26 23 15 16 18 26 23 15 16 I ANA

AN10 17 25 22 14 15 17 25 22 14 15 I ANA

AN11 16 24 21 11 12 16 24 21 11 12 I ANA

AN12 15 23 20 10 11 15 23 20 10 11 I ANA

AN13 7 9 6 30 33 7 9 6 30 33 I ANA

AN14 8107313481073134IANA

AN15 9 11 8 33 36 9 11 8 33 36 I ANA

ASCL1 — 15 12 42 46 — 15 12 42 46 I/O I

ASDA1 — 14 11 41 45 — 14 11 41 45 I/O I

AV

DD 20 28 25 17 18 20 28 25 17 18 I ANA A/D Supply Pins

AV

SS 19 27 24 16 17 19 27 24 16 17 I ANA

C1INA 8 7 4 24 26 8 7 4 24 26 I ANA Comparator 1 Input A (+)

C1INB 7 6 3 23 25 7 6 3 23 25 I ANA Comparator 1 Input B (-)

C1INC 5 5 2 22 24 5 5 2 22 24 I ANA Comparator 1 Input C (+)

C1IND 4 4 1 21 23 4 4 1 21 23 I ANA Comparator 1 Input D (-)

C1OUT 17 25 22 14 15 17 25 22 14 15 O — Comparator 1 Output

C2INA 5 5 2 22 24 5 5 2 22 24 I ANA Comparator 2 Input A (+)

C2INB 4 4 1 21 23 4 4 1 21 23 I ANA Comparator 2 Input B (-)

C2INC 8 7 4 24 26 8 7 4 24 26 I ANA Comparator 2 Input C (+)

C2IND 7 6 3 23 25 7 6 3 23 25 I ANA Comparator 2 Input D (-)

C2OUT 14 20 17 7 7 11 16 13 43 47 O — Comparator 2 Output

20-Pin

PDIP/

SSOP/

SOIC

28-Pin
SPDIP/
SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

SPDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

2

C™ Alternate I2C1 Clock Input/Output

2

C Alternate I2C1 Data Input/Output

 2011-2012 Microchip Technology Inc. DS39995C-page 17

TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

FFV

Pin Number Pin Number

Function

C3INA 18 26 23 15 16 18 26 23 15 16 I ANA Comparator 3 Input A (+)

C3INB 17 25 22 14 15 17 25 22 14 15 I ANA Comparator 3 Input B (-)

C3INC 2 2 27 19 21 2 2 27 19 21 I ANA Comparator 3 Input C (+)

C3IND 4 4 1 21 23 4 4 1 21 23 I ANA Comparator 3 Input D (-)

C3OUT 12171444481217144448O—Comparator 3 Output

CLK I 7 9 6 30 33 7 9 6 30 33 I ANA Main Clock Input

CLKO 8107313481073134O—System Clock Output

CN0 10 12 9 34 37 10 12 9 34 37 I ST Interrupt-on-Change Inputs

CN1 9118333691183336IST

CN2 2 2 27 19 21 2 2 27 19 21 I ST

CN3 3 3 28 20 22 3 3 28 20 22 I ST

CN4 4 4 1 21 23 4 4 1 21 23 I ST

CN5 5 5 2 22 24 5 5 2 22 24 I ST

CN6 6 6 3 23 25 6 6 3 23 25 I ST

CN7 — 7 4 24 26 –- 7 4 24 26 I ST

CN8 14 20 17 7 7 –- –- –- — –- I ST

CN9 –- 19 16 6 6 –- 19 16 6 6 I ST

CN10 –- — — 27 29 –- –- –- 27 29 I ST

CN11 18 26 23 15 16 18 26 23 15 16 I ST

CN12 17 25 22 14 15 17 25 22 14 15 I ST

CN13 16 24 21 11 12 16 24 21 11 12 I ST

CN14 15 23 20 10 11 15 23 20 10 11 I ST

CN15 –- 22 19 9 10 –- 22 19 9 10 I ST

CN16 –- 21 18 8 9 –- 21 18 8 9 I ST

CN17 –- — — 3 3 –- — — 3 3 I ST

CN18 — — — 2 2 — — — 2 2 I ST

CN19 –- — — 5 5 — — –- 5 5 I ST

CN20 –- — — 4 4 — –- –- 4 4 I ST

CN21 13 18 15 1 1 13 18 15 1 1 I ST

CN22 12 17 14 44 48 12 17 14 44 48 I ST

20-Pin

PDIP/

SSOP/

SOIC

28-Pin
SPDIP/
SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

SPDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV32KA304 FAMILY

DS39995C-page 18  2011-2012 Microchip Technology Inc.

TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

FFV

Pin Number Pin Number

Function

CN23 11 16 13 43 47 11 16 13 43 47 I ST Interrupt-on-Change Inputs

CN24 –- 15 12 42 46 –- 15 12 42 46 I ST

CN25 –- — — 37 40 –- –- –- 37 40 I ST

CN26 –- — — 38 41 –- –- –- 38 41 I ST

CN27 –- 14 11 41 45 –- 14 11 41 45 I ST

CN28 –- — — 36 39 –- –- –- 36 39 I ST

CN29 8107313481073134IST

CN30 7 9 6 30 33 7 9 6 30 33 I ST

CN31 –- — — 26 28 — — — 26 28 I ST

CN32 –- — — 25 27 — — — 25 27 I ST

CN33 –- — — 32 35 — — — 32 35 I ST

CN34 –- — — 35 38 — — — 35 38 I ST

CN35 –- — — 12 13 — — — 12 13 I ST

CN36 –- — — 13 14 — — — 13 14 I ST

CV

REF 17 25 22 14 15 17 25 22 14 15 I ANA Comparator Voltage Reference Output

CV

REF+ 2 2 27 19 21 2 2 27 19 21 I ANA Comparator Reference Positive Input Voltage

CV

REF- 3 3 28 20 22 3 3 28 20 22 I ANA Comparator Reference Negative Input Voltage

CTCMP 4 4 1 21 23 4 4 1 21 23 I ANA CTMU Comparator Input

CTED1 14 20 17 7 7 11 2 27 19 21 I ST

CTED2 15 23 20 10 11 15 23 20 10 11 I ST

CTED3 — 19 16 6 6 — 19 16 6 6 I ST

CTED4 13 18 15 1 1 13 18 15 1 1 I ST

CTED5 17 25 22 14 15 17 25 22 14 15 I ST

CTED6 18 26 23 15 16 18 26 23 15 16 I ST

CTED7 — — — 5 5 — — — 5 5 I ST

CTED8 — — — 13 14 — — — 13 14 I ST

CTED9 —2219 9 10—2219 9 10IST

CTED10 12 17 14 44 48 12 17 14 44 48 I ST

CTED11 — 21 18 8 9 — 21 18 8 9 I ST

CTED12 5 5 2 22 24 5 5 2 22 24 I ST

CTED13 6 6 3 23 25 6 6 3 23 25 I ST

20-Pin

PDIP/

SSOP/

SOIC

28-Pin
SPDIP/
SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

SPDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

CTMU Trigger Edge Inputs

PIC24FV32KA304 FAMILY

 2011-2012 Microchip Technology Inc. DS39995C-page 19

TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

FFV

Pin Number Pin Number

Function

CTPLS 16 24 21 11 12 16 24 21 11 12 O — CTMU Pulse Output

HLVDIN 15 23 20 10 11 15 23 20 10 11 I ST High/Low-Voltage Detect Input

IC1 14 19 16 6 6 11 19 16 6 6 I ST Input Capture 1 Input

IC2 13 18 15 5 5 13 18 15 5 5 I ST Input Capture 2 Input

IC3 15 23 20 13 14 15 23 20 13 14 I ST Input Capture 3 Input

INT0 11 16 13 43 47 11 16 13 43 47 I ST Interrupt 0 Input

INT1 17 25 22 14 15 17 25 22 14 15 I ST Interrupt 1 Input

INT2 14 20 17 7 7 15 23 20 10 11 I ST Interrupt 2 Input

MCLR

1 1 26 18 19 1 1 26 18 19 I ST Master Clear (Device Reset) Input (active-low)

OC1 14 20 17 7 7 11 16 13 43 47 O — Output Compare/PWM1 Output

OC2 4 22 19 4 4 4 22 19 4 4 O — Output Compare/PWM2 Output

OC3 5 21 18 12 13 5 21 18 12 13 O — Output Compare/PWM3 Output

OCFA 17 25 22 14 15 17 25 22 14 15 O — Output Compare Fault A

OFCB 16 24 21 32 35 16 24 21 32 35 O — Output Compare Fault B

OSCI 7 9 6 30 33 7 9 6 30 33 I ANA Main Oscillator Input

OSCO 8 10 7 31 34 8 10 7 31 34 O ANA Main Oscillator Output

PGEC1 5 5 2 22 24 5 5 2 22 24 I/O ST ICSP™ Clock 1

PCED1 4 4 1 21 23 4 4 1 21 23 I/O ST ICSP Data 1

PGEC2 2 22191910 2 22191910I/OSTICSP Clock 2

PGED2 3 21 18 8 9 3 21 18 8 9 I/O ST ICSP Data 2

PGEC3 10 15 12 42 46 10 15 12 42 46 I/O ST ICSP Clock 3

PGED3 9 14 11 41 45 9 14 11 41 45 I/O ST ICSP Data 3

20-Pin

PDIP/

SSOP/

SOIC

28-Pin
SPDIP/
SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

SPDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV32KA304 FAMILY

DS39995C-page 20  2011-2012 Microchip Technology Inc.

TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

FFV

Pin Number Pin Number

Function

RA0 2 2 27 19 21 2 2 27 19 21 I/O ST PORTA Pins

RA1 3 3 28 20 22 3 3 28 20 22 I/O ST

RA2 7 9 6 30 33 7 9 6 30 33 I/O ST

RA3 8107313481073134I/OST

RA4 1012 9 34371012 9 3437I/OST

RA5 1 1 26 18 19 1 1 26 18 19 I/O ST

RA6 14 20 17 7 7 — — — — — I/O ST

RA7 — 19 16 6 6 — 19 16 6 6 I/O ST

RA8 — — — 32 35 — — — 32 35 I/O ST

RA9 — — — 35 38 — — — 35 38 I/O ST

RA10 — — — 12 13 — — — 12 13 I/O ST

RA11 ———1314———1314I/OST

RB0 4 4 1 21 23 4 4 1 21 23 I/O ST PORTB Pins

RB1 5 5 2 22 24 5 5 2 22 24 I/O ST

RB2 6 6 3 23 25 6 6 3 23 25 I/O ST

RB3 — 7 4 24 26 — 7 4 24 26 I/O ST

RB4 9118333691183336I/OST

RB5 —14114145—14114145I/OST

RB6 — 15 12 42 46 — 15 12 42 46 I/O ST

RB7 11 16 13 43 47 11 16 13 43 47 I/O ST

RB8 12 17 14 44 48 12 17 14 44 48 I/O ST

RB9 13 18 15 1 1 13 18 15 1 1 I/O ST

RB10 — 21 18 8 9 — 21 18 8 9 I/O ST

RB11 —2219 9 10—2219 9 10I/OST

RB12 15 23 20 10 11 15 23 20 10 11 I/O ST

RB13 16 24 21 11 12 16 24 21 11 12 I/O ST

RB14 17 25 22 14 15 17 25 22 14 15 I/O ST

RB15 18 26 23 15 16 18 26 23 15 16 I/O ST

20-Pin

PDIP/

SSOP/

SOIC

28-Pin
SPDIP/
SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

SPDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV32KA304 FAMILY

 2011-2012 Microchip Technology Inc. DS39995C-page 21

TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

FFV

Pin Number Pin Number

Function

RC0 — — — 25 27 — — — 25 27 I/O ST PORTC Pins

RC1 — — — 26 28 — — — 26 28 I/O ST

RC2 — — — 27 29 — — — 27 29 I/O ST

RC3 — — — 36 39 — — — 36 39 I/O ST

RC4 — — — 37 40 — — — 37 40 I/O ST

RC5 — — — 38 41 — — — 38 41 I/O ST

RC6 — — — 2 2 — — — 2 2 I/O ST

RC7 — — — 3 3 — — — 3 3 I/O ST

RC8 — — — 4 4 — — — 4 4 I/O ST

RC9 — — — 5 5 — — — 5 5 I/O ST

REFO 18 26 23 15 16 18 26 23 15 16 O — Reference Clock Output

RTCC 17 25 22 14 15 17 25 22 14 15 O — Real-Time Clock/Calendar Output

SCK1 15 22 19 9 10 15 22 19 9 10 I/O ST SPI1 Serial Input/Output Clock

SCK2 2 14 11 38 41 2 14 11 38 41 I/O ST SPI2 Serial Input/Output Clock

SCL1 12 17 14 44 48 12 17 14 44 48 I/O I

SCL2 18 7 4 24 26 18 7 4 24 26 I/O I

SCLKI 10 12 9 34 37 10 12 9 34 37 I ST Digital Secondary Clock Input

SDA1 13 18 15 1 1 13 18 15 1 1 I/O I

SDA2 6 6 3 23 25 6 6 3 23 25 I/O I

SDI1 17 21 18 8 9 17 21 18 8 9 I ST SPI1 Serial Data Input

SDI2 4 19 16 36 39 4 19 16 36 39 I ST SPI2 Serial Data Input

SDO1 16 24 21 11 12 16 24 21 11 12 O — SPI1 Serial Data Output

SDO2 3 15123740 3 15123740O—SPI2 Serial Data Output

SOSCI 9 11 8 33 36 9 11 8 33 36 I ANA Secondary Oscillator Input

SOSCO 10 12 9 34 37 10 12 9 34 37 O ANA Secondary Oscillator Output

SS1

SS2

20-Pin

PDIP/

SSOP/

SOIC

18 26 23 15 16 18 26 23 15 16 O — SPI1 Slave Select

15 23 20 35 38 15 23 20 35 38 O — SPI2 Slave Select

28-Pin
SPDIP/
SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

SPDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

2

C I2C1 Clock Input/Output

2

C I2C2 Clock Input/Output

2

C I2C1 Data Input/Output

2

C I2C2 Data Input/Output

PIC24FV32KA304 FAMILY

DS39995C-page 22  2011-2012 Microchip Technology Inc.

TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

FFV

Pin Number Pin Number

Function

T1CK 13 18 15 1 1 13 18 15 1 1 I ST Timer1 Clock

T2CK 18 26 23 15 16 18 26 23 15 16 I ST Timer2 Clock

T3CK 18 26 23 15 16 18 26 23 15 16 I ST Timer3 Clock

T4CK 6 6 3 23 25 6 6 3 23 25 I ST Timer4 Clock

T5CK 6 6 3 23 25 6 6 3 23 25 I ST Timer5 Clock

U1CTS 12 17 14 44 48 12 17 14 44 48 I ST UART1 Clear-to-Send Input

U1RTS 13 18 15 1 1 13 18 15 1 1 O — UART1 Request-to-Send Output

U1RX 6632266322ISTUART1 Receive

U1TX 11 16 13 3 3 11 16 13 3 3 O — UART1 Transmit

U2CTS 10 12 9 34 37 10 12 9 34 37 I ST UART2 Clear-to-Send Input

U2RTS 9 11 8 33 36 9 11 8 33 36 O — UART2 Request-to-Send Output

U2RX 5 5 2 22 24 5 5 2 22 24 I ST UART2 Receive

U2TX 4 4 1 21 23 4 4 1 21 23 O — UART2 Transmit

ULPWU 4 4 1 21 23 4 4 1 21 23 I ANA Ultra Low-Power Wake-up Input

V

CAP —————142017 7 7P—Core Power

V

DD 20 28,13 25,10 17,28,40 18,30,43 20 28,13 25,10 17,28,40 18,30,43 P — Device Digital Supply Voltage

V

REF+ 2 2 27 19 21 2 2 27 19 21 I ANA A/D Reference Voltage Input (+)

V

REF- 3 3 28 20 22 3 3 28 20 22 I ANA A/D Reference Voltage Input (-)

V

SS 19 27,8 24,5 16,29,39 17,31,42 19 27,8 24,5 16,29,39 17,31,42 P — Device Digital Ground Return

20-Pin

PDIP/

SSOP/

SOIC

28-Pin
SPDIP/
SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

SPDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV32KA304 FAMILY

PIC24FV32KA304 FAMILY

PIC24FXXKXX

VDD

VSS

VDD

VSS

VSS

VDD

AVDD

AVSS

VDD

VSS

C1

R1

V

DD

MCLR

VCAP

R2

C7

C2

(2)

C3

(2)

C4

(2)

C5

(2)

C6

(2)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 16V tantalum or ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pin

(V

CAP)” for explanation of VCAP pin

connections.

2: The example shown is for a PIC24F device

with five V

DD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.

3: Some PIC24F K parts do not have a

regulator.

(1)

(3)

2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTIONS

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC24FV32KA304 family
family of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development.

The following pins must always be connected:

DD and VSS pins

•All V

(see Section 2.2 “Power Supply Pins”)

•All AV

•MCLR

•V

These pins must also be connected if they are being
used in the end application:

• PGECx/PGEDx pins used for In-Circuit Serial

• OSCI and OSCO pins when an external oscillator

Additionally, the following pins may be required:

•V

The minimum mandatory connections are shown in

Figure 2-1.

DD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

CAP pins

(see Section 2.4 “Voltage Regulator Pin (V

CAP)”)

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

source is used

(see Section 2.6 “External Oscillator Pins”)

REF+/VREF- pins are used when external voltage

reference for analog modules is implemented

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of
the analog modules are being used.

 2011-2012 Microchip Technology Inc. DS39995C-page 23

PIC24FV32KA304 FAMILY

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the
MCLR

pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR

from the external capacitor, C, in the

event of MCLR

pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR

pin

V

IH and VIL specifications are met.

C1

R2

R1

V

DD

MCLR

PIC24FXXKXX

JP

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of
power supply pins, such as V

SS, is required.

AV

Consider the following criteria when using decoupling
capacitors:

• Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci­tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).

• Maximizing performance: On the board layout

from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.

DD, VSS, AVDD and

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to V
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.

During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR
levels (V
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.

Any components associated with the MCLR
should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

DD may be all that is required. The

pin. Consequently, specific voltage

IH and VIL) and fast signal transitions must

pin during programming and

pin

CONNECTIONS

2.2.2 TANK CAPACITORS

On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac­itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.

DS39995C-page 24  2011-2012 Microchip Technology Inc.

PIC24FV32KA304 FAMILY

10

1

0.1

0.01

0.001

0.01 0.1 1 10 100 1000 10,000

Frequency (MHz)

ESR ()

Note: Typical data measurement at 25°C, 0V DC bias.

2.4 Voltage Regulat or Pin (VCAP)

Refer to Se ction 29.0 “Electri cal Characteristics” for

information on V

DD and VDDCORE.

Note: This section applies only to PIC24F K

devices with an on-chip voltage regulator.

Some of the PIC24F K devices have an internal voltage
regulator. These devices have the voltage regulator

FIGURE 2-3: FREQUENCY vs. ESR

PERFORMANCE FOR
SUGGESTED V

CAP

output brought out on the VCAP pin. On the PIC24F K
devices with regulators, a low-ESR (< 5Ω) capacitor is
required on the V
regulator output. The V

DD and must use a capacitor of 10 µF connected to

V

CAP pin to stabilize the voltage

CAP pin must not be connected to

ground. The type can be ceramic or tantalum. Suitable
examples of capacitors are shown in Table 2-1.
Capacitors with equivalent specifications can be used.

Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.

The placement of this capacitor should be close to V

CAP.

It is recommended that the trace length not exceed

0.25 inch (6 mm). Refer to Section 29.0 “Electrical

Characteristics” for additional information.

TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS

Make Part #

TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC

TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC

Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC

Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC

Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC

Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC

Nominal

Capacitance

Base Tolerance Rated Voltage Temp. Range

 2011-2012 Microchip Technology Inc. DS39995C-page 25

PIC24FV32KA304 FAMILY

-80

-70

-60

-50

-40

-30

-20

-10

0

10

5 1011121314151617

DC Bias Voltage (VDC)

Capacitance Change (%)

01234 67 89

16V Capacitor

10V Capacitor

6.3V Capacitor

2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS

In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.

Ceramic capacitors are suitable for use with the inter­nal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.

Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial toler­ance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or

-20%/+80% (Y5V). However, the effective capacitance

that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.

The X5R and X7R capacitors typically exhibit satisfac­tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capaci­tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.

In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi­cant, but is often overlooked or is not always
documented.

A typical DC bias voltage vs. capacitance graph for
X7R type capacitors is shown in Figure 2-4.

FIGURE 2-4: DC BIAS VOLTAGE vs.

CAPACITANCE
CHARACTERISTICS

When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor volt­age. For example, choose a ceramic capacitor rated at
16V for the 3.3V or 2.5V core voltage. Suggested
capacitors are shown in Table 2-1.

2.5 ICSP Pins

The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom­mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica­tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter­natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high

IH) and input low (VIL) requirements.

(V

For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins), programmed
into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.

For more information on available Microchip
development tools connection requirements, refer to

Section 27.0 “Development Support”.

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PIC24FV32KA304 FAMILY

GND

`

`

`

OSC1

OSC2

T1OSO

T1OS I

Copper Pour

Primary Oscillator

Crystal

Timer1 Oscillator

Crystal

DEVICE PINS

Primary

Oscillator

C1

C2

T1 Oscillator: C1

T1 Oscillator: C2

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

GND

OSCO

OSCI

Bottom Layer

Copper Pour

Oscillator

Crystal

Top Layer Copper Pour

C2

C1

DEVICE PINS

(tied to ground)

(tied to ground)

2.6 External Oscillator Pins

Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to for

Section 9.0 “Oscillator Configuration”details).

The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.

Use a grounded copper pour around the oscillator cir­cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.

Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com­pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.

In planning the application’s routing and I/O assign­ments, ensure that adjacent port pins and other
signals, in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).

For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):

• AN826, “Crystal Os cillator Basics and Crystal

Selection for rfPIC™ and PICmicro

• AN849, “Basic PICmicro

• AN943, “Practical PICmicro
and Design”

• AN949, “Making Your Oscill ator Work ”

2.7 Unused I/Os

Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.

®

®

Oscillator Design”

®

Devices”

Oscillator Analysis

FIGURE 2-5: SUGGESTED PLACEMENT

OF THE OSCILLATOR
CIRCUIT

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NOTES:

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PIC24FV32KA304 FAMILY

3.0 CPU

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not
intended to be a comprehensive refer­ence source. For more information on the

CPU, refer to the “PIC24F Family
Reference Manual”, Section 2. “CPU”

(DS39703).

The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.

PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16
Software Stack Pointer (SSP) for interrupts and calls.

The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary of either program memory or data
EEPROM memory, defined by the 8-bit Program Space
Visibility Page Address (PSVPAG) register. The
program to data space mapping feature lets any
instruction access program space as if it were data
space.

The Instruction Set Architecture (ISA) has been signifi­cantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibil­ity. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.

The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.

th

working register (W15) operates as a

For most instructions, the core is capable of executing
a data (or program data) memory read, a working
register (data) read, a data memory write and a pro­gram (instruction) memory read per instruction cycle.
As a result, three parameter instructions can be
supported, allowing trinary operations (i.e., A + B = C)
to be executed in a single cycle.

A high-speed, 17-bit by 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
8-bit by 8-bit integer multiplication. All multiply
instructions execute in a single cycle.

The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by 16-bit integer signed and unsigned
division. All divide operations require 19 cycles to
complete but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.

A block diagram of the CPU is illustrated in Figure 3-1.

3.1 Programmer’s Model

Figure 3-2 displays the programmer’s model for the

PIC24F. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions.

Table 3-1 provides a description of each register. All

registers associated with the programmer’s model are
memory mapped.

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Instruction

Decode and

Control

PCH PCL

16

Program Counter

16-Bit ALU

23

23

24

23

Data Bus

Instruction Reg

16

16 x 16

W Register Array

Divide

Support

ROM Latch

16

EA MUX

RAGU
WAGU

16

16

8

Interrupt

Controller

PSV and Table

Data Access

Control Block

Stac k

Control

Logic

Loop

Control

Logic

Data Latch

Data RAM

Address

Latch

Control Signals

to Various Blocks

Program Memory

Data Latch

Address Bus

16

Literal Data

16

16

Hardware

Multiplier

16

To Peripheral Modules

Address Latch

Data EEPROM

FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM

TABLE 3-1: CPU CORE REGISTERS

Register(s) Name Description

W0 through W15 Working Register Array

PC 23-Bit Program Counter

SR ALU STATUS Register

SPLIM Stack Pointer Limit Value Register

TBLPAG Table Memory Page Address Register

PSVPAG Program Space Visibility Page Address Register

RCOUNT Repeat Loop Counter Register

CORCON CPU Control Register

DS39995C-page 30  2011-2012 Microchip Technology Inc.