PIC24FJ256DA210 Family
Data Sheet
64/100-Pin,
16-Bit Flash Microcontrollers
with Graphics Controller and
USB On-The-Go (OTG)
2010 Microchip Technology Inc. DS39969B
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC
logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-235-9
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS39969B-page 2 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
64/100-Pin, 16-Bit Flash Microcontrollers
with Graphics Controller and USB On-The-Go (OTG)
Graphics Controller Features:
• Three Graphics Hardware Accelerators to Facilitate
Rendering of Block Copying, Text and Unpacking of
Compressed Data
• Color Look-up Table (CLUT) with Maximum of 256 Entries
• 1/2/4/8/16 bits-per-pixel (bpp) Color Depth Set at
Run Time
• Display Resolution Programmable According to
Frame Buffer:
- Supports direct access to external memory on
devices with EPM
P
- Resolution supported is up to 480x272 @ 60 Hz,
16 bpp; 640x480 @ 30 Hz, 16 bpp or
640x480 @ 60 Hz, 8 bpp
• Supports Various Display Interfaces:
- 4/8/16-bit Monochrome STN
- 4/8/16-bit Color STN
- 9/12/18/24-bit Color TFT (18 and 24-bit displays
are connected as 16-bit, 5-6-5 RGB color format)
Universal Serial Bus Features:
• USB v2.0 On-The-Go (OTG) Compliant
• Dual Role Capable – Can act as either Host or Peripheral
• Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps)
USB Operation in Host mode
• Full-Speed USB Operation in Device mode
• High-Precision PLL for USB
• Supports up to 32 Endpoints (16 bidirectional):
- USB module can use the internal RAM location
from 0x800 to 0xFFFF as USB endpoint buffers
• On-Chip USB Transceiver with Interface for Off-Chip
Transceiver
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• On-Chip Pull-up and Pull-Down Resistors
Remappable Peripherals
Peripheral Features:
• Enhanced Parallel Master Port/Parallel Slave Port
(EPMP/PSP), 100-pin devices only:
- Direct access from CPU with an Extended Data
Space (EDS) interface
- 4, 8 and 16-bit wide data bus
- Up to 23 programmable address lines
- Up to 2 chip select lines
- Up to 2 Acknowledgement lines (one per chip
select)
- Programmable address/data multiplexing
- Programmable address and data Wait states
- Programmable polarity on control signals
• Peripheral Pin Select:
- Up to 44 available pins (100-pin devices)
• Three 3-Wire/4-Wire SPI modules (supports 4 Frame
modes)
•Three I2C™ modules Supporting Multi-Master/Slave
modes and 7-Bit/10-Bit Addressing
•Four UART modules:
- Supports RS-485, RS-232, LIN/J2602 protocols
and IrDA
• Five 16-Bit Timers/Counters with Programmable
Prescaler
• Nine 16-Bit Capture Inputs, each with a Dedicated Time
Base
• Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base
• Hardware Real-Time Clock and Calendar (RTCC)
• Enhanced Programmable Cyclic Redundancy Check
(CRC) Generator
• Up to 5 External Interrupt Sources
®
®
PIC24FJ Device
PIC24FJ128DA106 64 128K 24K 29 5 9/9 4 3 3 16 3 Y N Y Y Y
PIC24FJ256DA106 64 256K 24K 29 5 9/9 4 3 3 16 3 Y N Y Y Y
PIC24FJ128DA110 100/121 128K 24K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y
PIC24FJ256DA110 100/121 256K 24K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y
PIC24FJ128DA206 64 128K 96K 29 5 9/9 4 3 3 16 3 Y N Y Y Y
PIC24FJ256DA206 64 256K 96K 29 5 9/9 4 3 3 16 3 Y N Y Y Y
PIC24FJ128DA210 100/121 128K 96K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y
PIC24FJ256DA210 100/121 256K 96K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y
2010 Microchip Technology Inc. DS39969B-page 3
Pins
(bytes)
Program Memory
Pins
SRAM (bytes)
Remappable
IC/OC PWM
16-Bit Timers
UART w/IrDA
C™
2
I
SPI
10-Bit A/D (ch)
CTMU
Comparators
EPMP/PSP
RTCC
USB OTG
Graphics Controller
PIC24FJ256DA210 FAMILY
High-Performance CPU
• Modified Harvard Architecture
• Up to 16 MIPS Operation at 32 MHz
• 8 MHz Internal Oscillator
• 17-Bit x 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
with Flexible Addressing modes
• Linear Program Memory Addressing, up to
12 Mbytes
• Data Memory Addressing, up to 16 Mbytes:
- 2K SFR space
- 30K linear data memory
- 66K extended data memory
- Remaining (from 16 Mbytes) memory (external)
can be accessed using extended data Memory
(
EDS) and EPMP (EDS is divided into 32-Kbyte
pages)
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
Power Management:
• On-Chip Voltage Regulator of 1.8V
• Switch between Clock Sources in Real Time
• Idle, Sleep and Doze modes with Fast Wake-up and
Two-Speed Start-up
• Run Mode: 800 A/MIPS, 3.3V Typical
• Sleep mode Current Down to 20 A, 3.3V Typical
• Standby Current with 32 kHz Oscillator: 22 A,
3.3V Typical
Analog Features:
• 10-Bit, up to 24-Channel Analog-to-Digital (A/D)
Converter at 500 ksps:
- Operation is possible in Sleep mode
- Band gap reference input feature
• Three Analog Comparators with Programmable
Input/Output Configuration
• Charge Time Measurement Unit (CTMU):
- Supports capacitive touch sensing for touch
screens and capacitive switches
- Minimum time measurement setting at 100 ps
• Available LVD Interrupt VLVD Level
Special Microcontroller Features:
• Operating Voltage Range of 2.2V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• Configurable Open-Drain Outputs on Digital I/O
Ports
• High-Current Sink/Source (18 mA/18 mA) on all
I/O Ports
• Selectable Power Management modes:
- Sleep, Idle and Doze modes with fast wake-up
• Fail-Safe Clock Monitor (FSCM) Operation:
- Detects clock failure and switches to on-chip,
FRC oscillator
• On-Chip LDO Regulator
• Power-on Reset (POR) and
Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR)
• Flexible Watchdog Timer (WDT) with On-Chip
Low-Power RC Oscillator for Reliable Operation
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins
• JTAG Boundary Scan Support
• Flash Program Memory:
- 10,000 erase/write cycle endurance (minimum)
- 20-year data retention minimum
- Selectable write protection boundary
- Self-reprogrammable under software control
- Write protection option for Configuration Words
DS39969B-page 4 2010 Microchip Technology Inc.
Pin Diagram (64-Pin TQFP/QFN)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
22
44
242526272829303132
1
46
45
23
43
42
41
40
39
C3INB/CN15/RD6
RP20
/GPWR/CN14/RD5
RP25
/GCLK/CN13/RD4
RP22
/GEN/CN52/RD3
DPH/
RP23
/CN51/RD2
V
CPCON
/
RP24
/GD9/V
BUSCHG
/CN50/RD1
HSYNC/CN62/RE4
GD3/CN61/RE3
GD2/CN60/RE2
GD1/CN59/RE1
GD10/V
BUSST
/V
CMPST
1/V
BUSVLD
/CN68/RF0
V
CAP
SOSCI/C3IND/CN1/RC13
DMH/
RP11
/INT0/CN49/RD0
SCL1/
RP3
/GD6/CN55/RD10
DPLN/SDA1/
RP4
/GD8/CN54/RD9
RTCC/DMLN/
RP2
/CN53/RD8
RP12
/GD7/CN56/RD11
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
VDD
D+/CN83/RG2
VUSB
V
BUS
/RF7
RP16
/USBID/CN71/RF3
D-/CN84/RG3
AV
DD
AN8/
RP8
/CN26/RB8
AN9/
RP9
/CN27/RB9
TMS/CV
REF
/AN10/CN28/RB10
TDO/AN11/CN29/RB11
V
DD
PGEC2/AN6/
RP6
/CN24/RB6
PGED2/AN7/
RP7
/RCV/CN25/RB7
SCL2/
RP17
/GD5/CN18/RF5
SDA2/
RP10
/GD4/CN17/ GD4/RF4
V
SYNC
/CN63/RE5
GD12/SCL3/CN64/RE6
GD13/SDA3/CN65/RE7
C1IND/
RP21
/CN8/RG6
VDD
PGEC3/AN5/C1INA/V
BUSON
/
RP18
/CN7/RB5
PGED3/AN4/C1INB/USBOEN/
RP28
/CN6/RB4
AN3/C2INA/VPIO/CN5/RB3
AN2/C2INB/VMIO/
RP13
/CN4/RB2
C1INC/
RP26
/CN9/RG7
C2IND/
RP19
/GD14/CN10/RG8
PGEC1/AN1/V
REF
-/
RP1
/CN3/RB1
PGED1/AN0/V
REF
+/
RP0
/CN2/RB0
C2INC/
RP27
/GD15/CN11/RG9
MCLR
TCK/AN12/CTEDG2/CN30/RB12
TDI/AN13CTEDG1/CN31/RB13
AN14/CTPLS/
RP14
/CN32/RB14
AN15/
RP29
/REFO/CN12/RB15
GD0/CN58/RE0
GD11/V
CMPST
2/SESSVLD/CN69/RF1
C3INA/SESSEND/CN16/RD7
VSS
(1)
V
SS
(1)
VSS
(1)
ENVREG
6362615960
5857565455
5352514950
38
37
34
36
35
33
17
192021
18
AV
SS
64
SOSCO/SCLKI/ T1CK/C3INC/
RPI37
/CN0/
Note 1: The back pad on QFN devices should be connected to VSS.
Legend: RPn and RPIn represents remappable peripheral pins.
Shaded pins indicate pins that are tolerant to up to +5.5V.
PIC24FJXXXDAX06
RC14
PIC24FJ256DA210 FAMILY
2010 Microchip Technology Inc. DS39969B-page 5
PIC24FJ256DA210 FAMILY
TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES
Pin Function Pin Function
SYNC/CN63/RE5 33 RP16/USBID/CN71/RF3
1V
2 GD12/SCL3/CN64/RE6 34 V
3 GD13/SDA3/CN65/RE7 35 V
4C1IND/RP21/CN8/RG6 36 D-/CN84/RG3
5C1INC/RP26/CN9/RG7 37 D+/CN83/RG2
6C2IND/RP19/GD14/CN10/RG8 38 V
7MCLR 39 OSCI/CLKI/CN23/RC12
8C2INC/RP27/GD15/CN11/RG9 40 OSCO/CLKO/CN22/RC15
9VSS 41 VSS
10 VDD 42 RTCC/DMLN/RP2/CN53/RD8
11 PGEC3/AN5/C1INA/V
BUSON/RP18/CN7/RB5 43 DPLN/SDA1/RP4/GD8/CN54/RD9
12 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 44 SCL1/RP3/GD6/CN55/RD10
13 AN3/C2INA/VPIO/CN5/RB3 45 RP12/GD7/CN56/RD11
14 AN2/C2INB/VMIO/RP13/CN4/RB2 46 DMH/RP11/INT0/CN49/RD0
15 PGEC1/AN1/V
16 PGED1/AN0/V
REF-/RP1/CN3/RB1 47 SOSCI/C3IND/CN1/RC13
REF+/RP0/CN2/RB0 48 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14
17 PGEC2/AN6/RP6/CN24/RB6 49 V
18 PGED2/AN7/RP7/RCV/CN25/RB7 50 DPH/RP23/CN51/RD2
19 AV
20 AV
DD 51 RP22/GEN/CN52/RD3
SS 52 RP25/GCLK/CN13/RD4
21 AN8/RP8/CN26/RB8 53 RP20/GPWR/CN14/RD5
22 AN9/RP9/CN27/RB9 54 C3INB/CN15/RD6
23 TMS/CV
REF/AN10/CN28/RB10 55 C3INA/SESSEND/CN16/RD7
24 TDO/AN11/CN29/RB11 56 V
25 VSS 57 ENVREG
DD 58 GD10/VBUSST/VCMPST1/VBUSVLD/CN68/RF0
26 V
27 TCK/AN12/CTEDG2/CN30/RB12 59 GD11/V
28 TDI/AN13/CTEDG1/CN31/RB13 60 GD0/CN58/RE0
29 AN14/CTPLS/RP14/CN32/RB14 61 GD1/CN59/RE1
30 AN15/RP29/REFO/CN12/RB15 62 GD2/CN60/RE2
31 SDA2/RP10/GD4/CN17/RF4 63 GD3/CN61/RE3
32 SCL2/RP17/GD5/CN18/RF5 64 HSYNC/CN62/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
BUS/RF7
USB
DD
CPCON/RP24/GD9/VBUSCHG/CN50/RD1
CAP
CMPST2/SESSVLD/CN69/RF1
DS39969B-page 6 2010 Microchip Technology Inc.
Pin Diagram (100-Pin TQFP)
9294939190898887868584838281807978
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
2829303132333435363738
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
969897
99
27
464748
49
50
55
54
53
52
51
100
RP20
/PMRD/CN14/RD5
RP25
/PMWR/CN13/RD4
PMD13/CN19/RD13
RPI42
/PMD12/CN57/RD12
RP22
/PMBE0/CN52/RD3
DPH/
RP23
/GD11/PMACK1/CN51/RD2
V
CPCON
/
RP24
/GD7/V
BUSCHG
/CN50/RD1
AN22/PMA17/CN40/RA7
AN23/GEN/CN39/RA6
PMD2/CN60/RE2
HSYNC/CN80/RG13
V
SYNC
/CN79/RG12
PMA16/CN81/RG14
PMD1/CN59/RE1
PMD0/CN58/RE0
PMD8/CN77/RG0
PMD4/CN62/RE4
PMD3/CN61/RE3
V
BUSST
/V
CMPST
1/V
BUSVLD
/PMD11/CN68/RF0
V
CAP
SOSCI/C3IND/CN1/RC13
DMH/
RP11
/INT0/CN49/RD0
RP3
/PMA15/PMCS2/CN55/
DPLN/
RP4
/GD10/PMACK2/CN54/
DMLN/RTCC/
RP2
/CN53/RD8
RP12/
PMA14/PMCS1/CN56/RD11
SDA1/
RPI35
/PMBE1/CN44/
SCL1/
RPI36
/
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
V
DD
D+/CN83/RG2
V
USB
V
BUS
/CN73/RF7
RP15
/GD9/CN74/RF8
D-/CN84/RG3
RP30
/GD3/CN70/RF2
RP16
/USBID/CN71/RF3
V
SS
V
REF
+/PMA6/CN42/RA10
V
REF
-/PMA7/CN41/RA9
AV
DD
AV
SS
AN8/
RP8
/GD12/CN26/RB8
GD13/AN9/
RP9
/GD13/CN27/RB9
AN10/CV
REF
/PMA13/CN28/RB10
AN11/PMA12/CN29/RB11
V
DD
RPI32
/PMA18/PMA5
/
CN75/RF12
RP31
/GD2/CN76/RF13
V
SS
V
DD
RP5
/GD15/CN21/RD15
RPI43
/GD14/CN20/RD14
PGEC2/AN6/
RP6
/CN24/RB6
PGED2/AN7/
RP7
/RCV/GPWR/CN25/RB7
RP17
/PMA8/CN18/RF5
RP10
/PMA9/CN17/RF4
PMD5/CN63/RE5
SCL3/PMD6/CN64/RE6
SDA3/PMD7/CN65/RE7
RPI38
/GD0/CN45/RC1
RPI39
/GD8/CN46/RC2
RPI40
/GD1/CN47/RC3
AN16/
RPI41
/PMCS2/PMA22/CN48/RC4
AN17/C1IND/
RP21
/PMA5/PMA18/CN8/
V
DD
TMS/CN33/RA0
RPI33
/PMCS1/CN66/RE8
AN21/
RPI34
/PMA19/CN67/RE9
PGEC3/AN5/C1INA/V
BUSON
/
RP18
/CN7/RB5
AN3/C2INA/GD5/VPIO/CN5/RB3
AN2/C2INB/VMIO/
RP13
/GD6/CN4/RB2
RG6
AN19/C2IND/
RP19
/PMA3/PMA21/CN10/RG8
PGEC1/A N1/V
REF
-/
RP1
/CN3/RB1
PGED1/AN0/V
REF
+
/RP0
/CN2/RB0
GCLK/CN82/RG15
V
DD
AN20/C2INC/
RP27
/PMA2/CN11/RG9
MCLR
AN12/PMA11/CTEDG2/CN30/RB12
AN13/PMA10/CTEDG1/CN31/RB13
AN14/CTPLS/
RP14
/PMA1/CN32/RB14
AN15/REFO/
RP29
/PMA0/CN12/RB15
PMD9/CN78/RG1
V
CMPST
2/SESSVLD/PMD10/CN69/RF1
C3INA/SESSEND/PMD15/CN16/RD7
C3INB/PMD14/CN15/RD6
TDO/CN38/RA5
SDA2/PMA20/PMA4/CN36/RA3
SCL2/CN35/RA2
V
SS
V
SS
V
SS
ENVREG
TDI/PMA21/PMA3/CN37/RA4
TCK/CN34/RA1
SOSCO/SCLKI/TICK/C3INC/
PGED3/AN4/C1INB/USBOEN /
RP28
/GD4/CN6/RB4
Legend: RPn and RPIn represent remappable peripheral pins.
Shaded pins indicate pins that are tolerant to up to +5.5V.
AN18/C1INC/
RP26
/PMA4/PMA20/CN9/RG7
CN43/RA14
PMA22/PMCS2
/
RA15
RD9
RPI37
/CN0/RC14
PIC24FJXXXDAX10
RD10
PIC24FJ256DA210 FAMILY
2010 Microchip Technology Inc. DS39969B-page 7
PIC24FJ256DA210 FAMILY
TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES
PinFunctionPinFunction
1 GCLK/CN82/RG15 41 AN12/PMA11/CTEDG2/CN30/RB12
2V
DD 42 AN13/PMA10/CTEDG1/CN31/RB13
3 PMD5/CN63/RE5 43 AN14/CTPLS/RP14/PMA1/CN32/RB14
4 SCL3/PMD6/CN64/RE6 44 AN15/REFO/RP29/PMA0/CN12/RB15
5 SDA3/PMD7/CN65/RE7 45 V
6 RPI38/GD0/CN45/RC1 46 VDD
7 RPI39/GD8/CN46/RC2 47 RPI43/GD14/CN20/RD14
8 RPI40/GD1/CN47/RC3 48 RP5/GD15/CN21/RD15
9 AN16/RPI41/PMCS2/PMA22
10 AN17/C1IND/RP21/PMA5/PMA18
11 AN18/C1INC/RP26/PMA4/PMA20
12 AN19/C2IND/RP19/PMA3/PMA21
(2)
/CN48/RC4 49 RP10/PMA9/CN17/RF4
(2)
/CN8/RG6 50 RP17/PMA8/CN18/RF5
(2)
/CN9/RG7
(2)
/CN10/RG8 52 RP30/GD3/CN70/RF2
13 MCLR
14 AN20/C2INC/RP27/PMA2/CN11/RG9 54 V
15 V
SS 55 VUSB
16 VDD 56 D-/CN84/RG3
17 TMS/CN33/RA0 57 D+/CN83/RG2
18 RPI33/PMCS1/CN66/RE8 58 SCL2/CN35/RA2
19 AN21/RPI34/PMA19/CN67/RE9 59 SDA2/PMA20/PMA4
20 PGEC3/AN5/C1INA/V
BUSON/RP18/CN7/RB5 60 TDI/PMA21/PMA3
21 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 61 TDO/CN38/RA5
22 AN3/C2INA/GD5/VPIO/CN5/RB3 62 V
23 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2
24 PGEC1/AN1/V
25 PGED1/AN0/V
(1)
REF-
/RP1/CN3/RB1 64 OSCO/CLKO/CN22/RC15
(1)
REF+
/RP0/CN2/RB0 65 VSS
26 PGEC2/AN6/RP6/CN24/RB6 66 SCL1/RPI36/PMA22/PMCS2
27 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 67 SDA1/RPI35/PMBE1/CN44/RA15
28 V
REF-/PMA7/CN41/RA9 68 DMLN/RTCC/RP2/CN53/RD8
29 V
REF+/PMA6/CN42/RA10 69 DPLN/RP4/GD10/PMACK2/CN54/RD9
30 AV
31 AV
DD 70 RP3/PMA15/PMCS2
SS 71 RP12/PMA14/PMCS1
32 AN8/RP8/GD12/CN26/RB8 72 DMH/RP11/INT0/CN49/RD0
33 AN9/RP9/GD13/CN27/RB9 73 SOSCI/C3IND/CN1/RC13
34 AN10/CV
REF/PMA13/CN28/RB10 74 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14
35 AN11/PMA12/CN29/RB11 75 V
36 VSS 76 VCPCON/RP24/GD7/VBU SCHG/CN50/RD1
37 V
DD 77 DPH/RP23/GD11/PMACK1/CN51/RD2
38 TCK/CN34/RA1 78 RP22/PMBE0/CN52/RD3
39 RP31/GD2/CN76/RF13 79 RPI42/PMD12/CN57/RD12
40 RPI32/PMA18/PMA5
(2)
/CN75/RF12 80 PMD13/CN19/RD13
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for V
2: Alternate pin assignments for EPMP when the ALTPMP
REF+ and VREF- when the ALTVREF Configuration bit is programmed.
Configuration bit is programmed.
3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.
SS
RP16/USBID/CN71/RF3
51
53 RP15/GD9/CN74/RF8
BUS/CN73/RF7
(2)
DD
OSCI/CLKI/CN23/RC12
63
SS
(2)
/CN36/RA3
/CN37/RA4
(2)
(3)
/CN55/RD10
(3)
/CN56/RD11
/CN43/RA14
DS39969B-page 8 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES
PinFunctionPinFunction
81 RP25/PMWR/CN13/RD4 91 AN23/GEN/CN39/RA6
82 RP20/PMRD/CN14/RD5 92 AN22/PMA17/CN40/RA7
83 C3INB/PMD14/CN15/RD6 93 PMD0/CN58/RE0
84 C3INA/SESSEND/PMD15/CN16/RD7 94 PMD1/CN59/RE1
85 V
CAP 95 PMA16/CN81/RG14
86 ENVREG 96 V
87 V
BUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 97 HSYNC/CN80/RG13
88 V
CMPST2/SESSVLD/PMD10/CN69/RF1 98 PMD2/CN60/RE2
89 PMD9/CN78/RG1 99 PMD3/CN61/RE3
90 PMD8/CN77/RG0 100 PMD4/CN62/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for V
2: Alternate pin assignments for EPMP when the ALTPMP
3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.
REF+ and VREF- when the ALTVREF Configuration bit is programmed.
Configuration bit is programmed.
SYNC/CN79/RG12
2010 Microchip Technology Inc. DS39969B-page 9
PIC24FJ256DA210 FAMILY
135
10 11
A
RE4 RE3
HSYNC/
RE0 RG0 R F1
ENVREG
N/C RD12 GD11/
GD7/
RD1
B
N/C GCLK/ RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14
C
RE6
VDD
VSYNC/
RG14
GEN/
N/C
RD7
RD4
VDD
RC13 RD11
D
GD0/
RE7
RE5
VSS VSS
N/C
RD6
RD13
RD0 n/c
RD10
E
RC4
GD1/
RG6
GD8/
VDD RG1
N/C
RA15 RD8
GD10/
RA14
F
MCLR
RG8 RG9 RG7
VSS
n/c N/C
VDD
OSCI/
VSS
OSCO/
G
RE8 RE9 RA0
N/C
VDD VSS VSS N/C RA5
RA3
RA4
H
PGEC3/ PGED3/
VSS VDD
N/C VDD n/c
VBUS/
VUSB
D+/RG2 RA2
J
GD5/ GD6/
PGED2/
AVDD
RB11 RA1 RB12
N/C
N/C
GD9/RF8 D-/RG3
K
PGEC1/ PGED1/
RA10
GD12/
N/C
RF12 RB14
VDD
GD15/ USBID/ GD3/
L
PGEC2/ RA9
AVSS
GD13/ RB10 GD2/ RB13
RB15
GD14/ RF4 RF5
24 6
Note 1: See Table 3 for complete functional pinout descriptions.
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
Shaded pins indicate pins tolerant to up to +5.5V.
RF7
RG13
RD2
RG15
RG12 RA6
RC1
RC3
RC2
RD9
RC12 RC15
RB3 RB2
RB8
RD15
RF3 RF2
RB9
RF13 RD14
RB5
GD4/RB4
RB1 RB0
RB6
RB7
GPWR
9
8
7
Pin Diagram – Top View (121-Pin BGA)
(1)
DS39969B-page 10 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES
PinFunctionPinFunction
A1 PMD4/CN62/RE4 E5 V
A2 PMD3/CN61/RE3 E6 PMD9/CN78/RG1
A3 HSYNC/CN80/RG13 E7 N/C
A4 PMD0/CN58/RE0 E8 SDA1/RPI35/PMBE1/CN44/RA15
A5 PMD8/CN77/RG0 E9 DMLN/RTCC/RP2/CN53/RD8
A6 V
CMPST2/SESSVLD/PMD10/CN69/RF1 E10 DPLN/RP4/GD10/PMACK2/CN54/RD9
A7 ENVREG E11 SCL1/RPI36/PMA22/PMCS2
A8 N/C F1 MCLR
A9 RPI42/PMD12/CN57/RD12 F2 AN19/C2IND/RP19/PMA3/PMA21
A10 DPH/RP23/GD11/PMACK1/CN51/RD2 F3 AN20/C2INC/RP27/PMA2/CN11/RG9
A11 V
CPCON/RP24/GD7/VBUSCHG/CN50/RD1 F4 AN18/C1INC/RP26/PMA4/PMA20
B1 N/C F5 V
B2 GCLK/CN82/RG15 F6 N/C
B3 PMD2/CN60/RE2 F7 N/C
B4 PMD1/CN59/RE1 F8 V
B5 AN22/PMA17/CN40/RA7 F9 OSCI/CLKI/CN23/RC12
B6 V
BUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 F10 VSS
B7 VCAP F11 OSCO/CLKO/CN22/RC15
B8 RP20/PMRD/CN14/RD5 G1 RPI33/PMCS1/CN66/RE8
B9 RP22/PMBE0/CN52/RD3 G2 AN21/RPI34/PMA19/CN67/RE9
B10 V
SS G3 TMS/CN33/RA0
B11 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 G4 N/C
C1 SCL3/PMD6/CN64/RE6 G5 V
C2 VDD G6 VSS
C3 VSYNC/CN79/RG12 G7 VSS
C4 PMA16/CN81/RG14 G8 N/C
C5 AN23/GEN/CN39/RA6 G9 TDO/CN38/RA5
C6 N/C G10 SDA2/PMA20/PMA4
C7 C3INA/SESSEND/PMD15/CN16/RD7 G11 TDI/PMA21/PMA3
C8 RP25/PMWR/CN13/RD4 H1 PGEC3/AN5/C1INA/V
C9 V
DD H2 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4
C10 SOSCI/C3IND/CN1/RC13 H3 V
C11 RP12/PMA14/PMCS1
(3)
/CN56/RD11 H4 VDD
D1 RPI38/GD0/CN45/RC1 H5 N/C
D2 SDA3/PMD7/CN65/RE7 H6 V
D3 PMD5/CN63/RE5 H7 N/C
D4 V
SS H8 VBUS/CN73/RF7
D5 V
SS H9 VUSB
D6 N/C H10 D+/CN83/RG2
D7 C3INB/PMD14/CN15/RD6 H11 SCL2/CN35/RA2
D8 PMD13/CN19/RD13 J1 AN3/C2INA/GD5/VPIO/CN5/RB3
D9 DMH/RP11/INT0/CN49/RD0 J2 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2
D10 N/C J3 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7
D11 RP3/PMA15/PMCS2
E1 AN16/RPI41/PMCS2/PMA22
(3)
/CN55/RD10 J4 AVDD
(2)
/CN48/RC4 J5 AN11/PMA12/CN29/RB11
E2 RPI40/GD1/CN47/RC3 J6 TCK/CN34/RA1
E3 AN17/C1IND/RP21/PMA5/PMA18
(2)
/CN8/RG6 J7 AN12/PMA11/CTEDG2/CN30/RB12
E4 RPI39/GD8/CN46/RC2 J8 N/C
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
Note 1: Alternate pin assignments for V
2: Alternate pin assignments for EPMP when the ALTPMP
REF+ and VREF- when the ALTVREF Configuration bit is programmed.
Configuration bit is programmed.
3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.
DD
(2)
/CN43/RA14
(2)
/CN10/RG8
(2)
/CN9/RG7
SS
DD
DD
(2)
/CN36/RA3
(2)
/CN37/RA4
BUSON/RP18/CN7/RB5
SS
DD
2010 Microchip Technology Inc. DS39969B-page 11
PIC24FJ256DA210 FAMILY
TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES
PinFunctionPinFunction
J9 N/C L1 PGEC2/AN6/RP6/CN24/RB6
J10 RP15/GD9/CN74/RF8 L2 V
J11 D-/CN84/RG3 L3 AVSS
K1 PGEC1/AN1/V
K2 PGED1/AN0/V
K3 V
K4 AN8/RP8/GD12/CN26/RB8 L7 AN13/PMA10/CTEDG1/CN31/RB13
K5 N/C L8 AN15/REFO/RP29/PMA0/CN12/RB15
K6 RPI32/PMA18/PMA5
K7 AN14/CTPLS/RP14/PMA1/CN32/RB14 L10 RP10/PMA9/CN17/RF4
K8 V
K9 RP5/GD15/CN21/RD15 — —
K10 RP16/USBID/CN71/RF3 — —
K11 RP30/GD3/CN70/RF2 — —
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
Note 1: Alternate pin assignments for V
(1)
REF+
/PMA6/CN42/RA10 L6 RP31/GD2/CN76/RF13
DD L11 RP17/GD5/PMA8/SCL2/CN18/RF5
2: Alternate pin assignments for EPMP when the ALTPMP
3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.
(1)
REF-
/RP1/CN3/RB1 L4 AN9/RP9/GD13/CN27/RB9
(1)
REF+
/RP0/CN2/RB0 L5 AN10/CVREF/PMA13/CN28/RB10
(2)
/CN75/RF12 L9 RPI43/GD14/CN20/RD14
REF+ and VREF- when the ALTVREF Configuration bit is programmed.
Configuration bit is programmed.
(1)
REF-
/PMA7/CN41/RA9
DS39969B-page 12 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 33
3.0 CPU ........................................................................................................................................................................................... 39
4.0 Memory Organization ................................................................................................................................................................. 45
5.0 Flash Program Memory.............................................................................................................................................................. 81
6.0 Resets ........................................................................................................................................................................................ 87
7.0 Interrupt Controller ..................................................................................................................................................................... 93
8.0 Oscillator Configuration............................................................................................................................................................ 141
9.0 Power-Saving Features............................................................................................................................................................ 155
10.0 I/O Ports ................................................................................................................................................................................... 157
11.0 Timer1 ...................................................................................................................................................................................... 189
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 191
13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 197
14.0 Output Compare with Dedicated Timers.................................................................................................................................. 201
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 211
16.0 Inter-Integrated Circuit™ (I
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 231
18.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 239
19.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 273
20.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 285
21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 297
22.0 Graphics Controller Module (GFX) ........................................................................................................................................... 305
23.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 325
24.0 Triple Comparator Module........................................................................................................................................................ 335
25.0 Comparator Voltage Reference................................................................................................................................................ 341
26.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 343
27.0 Special Features ...................................................................................................................................................................... 347
28.0 Development Support............................................................................................................................................................... 359
29.0 Instruction Set Summary.......................................................................................................................................................... 363
30.0 Electrical Characteristics.......................................................................................................................................................... 371
31.0 Packaging Information.............................................................................................................................................................. 387
Appendix A: Revision History............................................................................................................................................................. 397
Index ................................................................................................................................................................................................. 399
The Microchip Web Site..................................................................................................................................................................... 405
Customer Change Notification Service .............................................................................................................................................. 405
Customer Support .............................................................................................................................................................................. 405
Reader Response .............................................................................................................................................................................. 406
Product Identification System ............................................................................................................................................................ 407
2
C™).............................................................................................................................................. 223
2010 Microchip Technology Inc. DS39969B-page 13
PIC24FJ256DA210 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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DS39969B-page 14 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ128DA106 • PIC24FJ128DA206
• PIC24FJ256DA106 • PIC24FJ256DA206
• PIC24FJ128DA110 • PIC24FJ128DA210
• PIC24FJ256DA110 • PIC24FJ256DA210
The PIC24FJ256DA210 family enhances on the existing line of Microchip‘s 16-bit microcontrollers, adding a
new Graphics Controller (GFX) module to interface
with a graphical LCD display and also adds large data
RAM, up to 96 Kbytes. The PIC24FJ256DA210 family
allows the CPU to fetch data directly from an external
memory device using the EPMP module.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such
as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
All of the devices in the PIC24FJ256DA210 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing the user to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
• Instruction-Based Power-Saving Modes: The
microcontroller can suspend all operations, or
selectively shut down its core while leaving its
peripherals active with a single instruction in
software.
1.1.3 OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC24FJ256DA210 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• A Fast Internal Oscillator (FRC) with a nominal
8 MHz output, which can also be divided under
software control to provide clock speeds as low as
31 kHz.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes and the
FRC oscillator, which allows clock speeds of up to
32 MHz.
• A separate Low-Power Internal RC Oscillator
(LPRC) with a fixed 31 kHz output, which provides
a low-power option for timing-insensitive
applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the internal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger, or even in jumping from 64-pin to 100-pin
devices.
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
2010 Microchip Technology Inc. DS39969B-page 15
PIC24FJ256DA210 FAMILY
1.2 Graphics Controller
With the PIC24FJ256DA210 family of devices,
Microchip introduces the Graphics Controller module,
which acts as an interface between the CPU (mainly
through SFRs) and a display. On-board RAM is provided for display buffer, scratch areas, images and
fonts. In some cases, the RAM requirements for the
display used exceeds the on-board RAM; external
memory connected through EPMP can be used.
This module provides acceleration for drawing points,
vertical and horizontal lines, rectangles, copying rectangles between different locations on screen, drawing
text and decompressing compressed data.
1.3 USB On-The-Go
The USB On-The-Go (USB OTG) module provides
on-chip functionality as a target device compatible with
the USB 2.0 standard, as well as limited stand-alone
functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module
can also dynamically switch between device and host
operation, allowing for a much wider range of versatile
USB enabled applications on a microcontroller
platform.
In addition to USB host functionality,
PIC24FJ256DA210 family devices provide a true
single chip USB solution, including an on-chip
transceiver and voltage regulator, and a voltage boost
generator for sourcing bus power during host
operations.
1.4 Other Special Features
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Communications: The PIC24FJ256DA210 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are three independent I
modules that support both Master and Slave
modes of operation. Devices also have, through
the PPS feature, four independent UARTs with
built-in IrDA
modules.
• Analog Features: All members of the
PIC24FJ256DA210 family include a 10-bit A/D
Converter (ADC) module and a triple comparator
module. The ADC module incorporates programmable acquisition time, allowing for a channel to
be selected and a conversion to be initiated
without waiting for a sampling period, and faster
sampling speeds. The comparator module
includes three analog comparators that are
configurable for a wide range of operations.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ256DA210
family include the CTMU interface module. This
provides a convenient method for precision time
measurement and pulse generation, and can
serve as an interface for capacitive sensors.
• Enhanced Parallel Master/Parallel Slave Port:
There are general purpose I/O ports, which can
be configured for parallel data communications. In
this mode, the device can be master or slave on
the communication bus. 4-bit, 8-bit and 16-bit data
transfers, with up to 23 external address lines are
supported in Master modes.
• Real-Time Clock and Calendar: (RTCC) This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
®
encoders/decoders and three SPI
2
C™
DS39969B-page 16 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
1.5 Details on Individual Family Members
Devices in the PIC24FJ256DA210 family are available
in 64-pin and 100-pin packages. The general block
diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in seven
ways:
1. Flash program memory (128 Kbytes for
PIC24FJ128DAXXX devices and 256 Kbytes
for PIC24FJ256DAXXX devices).
2. Data memory (24 Kbytes for PIC24FJXXXDA1XX
devices, and 96 Kbytes for PIC24FJXXXDA2XX
devices).
3. Available I/O pins and ports (52 pins on 6 ports
for PIC24FJXXXDAX06 devices and 84 pins on
7 ports for PIC24FJXXXDAX10 devices).
4. Available Interrupt-on-Change Notification (ICN)
inputs (52 on PIC24FJXXXDAx06 devices and
84 on PIC24FJXXXDAX10 devices).
5. Available remappable pins (29 pins on
PIC24FJXXXDAX06 devices and 44 pins on
PIC24FJXXXDAX10 devices).
6. Analog channels for ADC (16 channels for
PIC24FJXXXDAX06 devices and 24 channels
for PIC24FJxxxDAx10 devices).
7. EPMP module (available in PIC24FJXXXDAX10
devices and not in PIC24FJXXXDAX06 devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
A list of the pin features available on the
PIC24FJ256DA210 family devices, sorted by function,
is shown in Table 1-1. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
2010 Microchip Technology Inc. DS39969B-page 17
PIC24FJ256DA210 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 64-PIN
Features PIC24FJ128DA106 PIC24FJ256DA106 PIC24FJ128DA206 PIC24FJ256DA206
Operating Frequency DC – 32 MHz
Program Memory (bytes) 128K 256K 128K 256K
Program Memory (instructions) 44,032 87,552 44,032 87,552
Data Memory (bytes) 24K 96K
Interrupt Sources (soft vectors/
NMI traps)
I/O Ports Ports B, C, D, E, F, G
Total I/O Pins 52
Remappable Pins 29 (28 I/O, 1 Input only)
Timers:
Total Number (16-bit) 5
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 9
Output Compare/PWM Channels 9
Input Change Notification Interrupt 52
Serial Communications:
UART 4
SPI (3-wire/4-wire) 3
I2C™ 3
Parallel Communications
(EPMP/PSP)
JTAG Boundary Scan Yes
10-Bit Analog-to-Digital Converter
(ADC) Module (input channels)
Analog Comparators 3
CTMU Interface Yes
USB OTG Yes
Graphics Controller Yes
Resets (and Delays) POR, BOR, RESET Instruction, MCLR
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 64-Pin TQFP and QFN
Note 1: Peripherals are accessible through remappable pins.
65 (61/4)
(1)
(1)
(1)
(1)
(1)
No
16
, WDT; Illegal Opcode,
(OST, PLL Lock)
DS39969B-page 18 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 100-PIN DEVICES
Features PIC24FJ128DA110 PIC24FJ256DA110 PIC24FJ128DA210 PIC24FJ256DA210
Operating Frequency DC – 32 MHz
Program Memory (bytes) 128K 256K 128K 256K
Program Memory (instructions) 44,032 87,552 44,032 87,552
Data Memory (bytes) 24K 96K
Interrupt Sources (soft vectors/NMI
traps)
I/O Ports Ports A, B, C, D, E, F, G
To t a l I / O Pi n s 84
Remappable Pins 44 (32 I/O, 12 input only)
Timers:
Total Number (16-bit) 5
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 9
Output Compare/PWM Channels 9
Input Change Notification Interrupt 84
Serial Communications:
UART 4
SPI (3-wire/4-wire) 3
I2C™ 3
Parallel Communications (EPMP/PSP) Yes
JTAG Boundary Scan Yes
10-Bit Analog-to-Digital Converter
(ADC) Module (input channels)
Analog Comparators 3
CTMU Interface Yes
USB OTG Yes
Graphics Controller Yes
Resets (and delays)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 100-Pin TQFP and 121-Pin BGA
Note 1: Peripherals are accessible through remappable pins.
POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
66 (62/4)
(1)
(1)
(1)
(1)
(1)
24
(OST, PLL Lock)
2010 Microchip Technology Inc. DS39969B-page 19
PIC24FJ256DA210 FAMILY
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
EDS and Table
Data Access
Control Block
Stac k
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
LVD & BOR
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Volt ag e
VCAP
ENVREG
PORTA
(1)
PORTC
(1)
(12 I/O)
(8 I/O)
PORTB
(16 I/O)
Note 1:
Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count
.
2:
These peripheral I/Os are only accessible through remappable pins.
3: Not available on 64-pin devices (PIC24FJxxxDAx06).
PORTD
(1)
(16 I/O)
Comparators
(2)
Time r2/3
(2)
Timer1
RTCC
IC
ADC
10-Bit
OC/PWM SPI
I2C
Timer4/5
(2)
™
EPMP/PSP
(3)
1-9
(2)
ICNs
(1)
UART
REFO
PORTE
(1)
PORTG
(1)
(10 I/O)
(12 I/O)
PORTF
(1)
(10 I/O)
1/2/3
(2)
1/2/3
1/2/3/4
(2)
1-9
(2)
CTMU
(2)
USB OTG
Graphics
Controller
Up to 0x7FFF
Space
Program Memory/
FIGURE 1-1: PIC24FJ256DA210 FAMILY GENERAL BLOCK DIAGRAM
DS39969B-page 20 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS
Pin Number
Function
AN0 16 25 K2 I ANA
AN1 15 24 K1 I ANA
AN2 14 23 J2 I ANA
AN3 13 22 J1 I ANA
AN4 12 21 H2 I ANA
AN5 11 20 H1 I ANA
AN6 17 26 L1 I ANA
AN7 18 27 J3 I ANA
AN8 21 32 K4 I ANA
AN9 22 33 L4 I ANA
AN10 23 34 L5 I ANA
AN11 24 35 J5 I ANA
AN12 27 41 J7 I ANA
AN13 28 42 L7 I ANA
AN14 29 43 K7 I ANA
AN15 30 44 L8 I ANA
AN16 — 9 E1 I ANA
AN17 — 10 E3 I ANA
AN18 — 11 F4 I ANA
AN19 — 12 F2 I ANA
AN20 — 14 F3 I ANA
AN21 — 19 G2 I ANA
AN22 — 92 B5 I ANA
AN23 — 91 C5 I ANA
DD 19 30 J4 P — Positive Supply for Analog modules.
AV
SS 20 31 L3 P — Ground Reference for Analog modules.
AV
C1INA 11 20 H1 I ANA Comparator 1 Input A.
C1INB 12 21 H2 I ANA Comparator 1 Input B.
C1INC 5 11 F4 I ANA Comparator 1 Input C.
C1IND 4 10 E3 I ANA Comparator 1 Input D.
C2INA 13 22 J1 I ANA Comparator 2 Input A.
C2INB 14 23 J2 I ANA Comparator 2 Input B.
C2INC 8 14 F3 I ANA Comparator 2 Input C.
C2IND 6 12 F2 I ANA Comparator 2 Input D.
C3INA 55 84 C7 I ANA Comparator 3 Input A.
C3INB 54 83 D7 I ANA Comparator 3 Input B.
C3INC 48 74 B11 I ANA Comparator 3 Input C.
C3IND 47 73 C10 I ANA Comparator 3 Input D.
CLKI 39 63 F9 I ST Main Clock Input Connection.
CLKO 40 64 F11 O — System Clock Output.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
A/D Analog Inputs.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
2010 Microchip Technology Inc. DS39969B-page 21
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
CN0 48 74 B11 I ST
CN1 47 73 C10 I ST
CN2 16 25 K2 I ST
CN3 15 24 K1 I ST
CN4 14 23 J2 I ST
CN5 13 22 J1 I ST
CN6 12 21 H2 I ST
CN7 11 20 H1 I ST
CN8 4 10 E3 I ST
CN9 5 11 F4 I ST
CN10 6 12 F2 I ST
CN11 8 14 F3 I ST
CN12 30 44 L8 I ST
CN13 52 81 C8 I ST
CN14 53 82 B8 I ST
CN15 54 83 D7 I ST
CN16 55 84 C7 I ST
CN17 31 49 L10 I ST
CN18 32 50 L11 I ST
CN19 — 80 D8 I ST
CN20 — 47 L9 I ST
CN21 — 48 K9 I ST
CN22 40 64 F11 I ST
CN23 39 63 F9 I ST
CN24 17 26 L1 I ST
CN25 18 27 J3 I ST
CN26 21 32 K4 I ST
CN27 22 33 L4 I ST
CN28 23 34 L5 I ST
CN29 24 35 J5 I ST
CN30 27 41 J7 I ST
CN31 28 42 L7 I ST
CN32 29 43 K7 I ST
CN33 — 17 G3 I ST
CN34 — 38 J6 I ST
CN35 — 58 H11 I ST
CN36 — 59 G10 I ST
CN37 — 60 G11 I ST
CN38 — 61 G9 I ST
CN39 — 91 C5 I ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
Interrupt-on-Change Inputs.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
DS39969B-page 22 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
CN40 — 92 B5 I ST
CN41 — 28 L2 I ST
CN42 — 29 K3 I ST
CN43 — 66 E11 I ST
CN44 — 67 E8 I ST
CN45 — 6 D1 I ST
CN46 — 7 E4 I ST
CN47 — 8 E2 I ST
CN48 — 9 E1 I ST
CN49 46 72 D9 I ST
CN50 49 76 A11 I ST
CN51 50 77 A10 I ST
CN52 51 78 B9 I ST
CN53 42 68 E9 I ST
CN54 43 69 E10 I ST
CN55 44 70 D11 I ST
CN56 45 71 C11 I ST
CN57 — 79 A9 I ST
CN58 60 93 A4 I ST
CN59 61 94 B4 I ST
CN60 62 98 B3 I ST
CN61 63 99 A2 I ST
CN62 64 100 A1 I ST
CN63 1 3 D3 I ST
CN64 2 4 C1 I ST
CN65 3 5 D2 I ST
CN66 — 18 G1 I ST
CN67 — 19 G2 I ST
CN68 58 87 B6 I ST
CN69 59 88 A6 I ST
CN70 — 52 K11 I ST
CN71 33 51 K10 I ST
CN73 — 54 H8 I ST
CN74 — 53 J10 I ST
CN75 — 40 K6 I ST
CN76 — 39 L6 I ST
CN77 — 90 A5 I ST
CN78 — 89 E6 I ST
CN79 — 96 C3 I ST
CN80 — 97 A3 I ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
Interrupt-on-Change Inputs.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
2010 Microchip Technology Inc. DS39969B-page 23
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
CN81 — 95 C4 I ST
CN82 — 1 B2 I ST
CN83 37 57 H10 I ST
CN84 36 56 J11 I ST
CTEDG1 28 42 L7 I ANA CTMU External Edge Input 1.
CTEDG2 27 41 J7 I ANA CTMU External Edge Input 2.
CTPLS 29 43 K7 O — CTMU Pulse Output.
REF 23 34 L5 O — Comparator Voltage Reference Output.
CV
D+ 37 57 H10 I/O — USB Differential Plus Line (internal transceiver).
D- 36 56 J11 I/O — USB Differential Minus Line (internal transceiver).
DMH 46 72 D9 O — D- External Pull-up Control Output.
DMLN 42 68 E9 O — D- External Pull-down Control Output.
DPH 50 77 A10 O — D+ External Pull-up Control Output.
DPLN 43 69 E10 O — D+ External Pull-down Control Output.
ENVREG 57 86 J7 I ST Voltage Regulator Enable.
GCLK 52 1 B2 O — Graphics Display Pixel Clock.
GD0 60 6 D1 O —
GD1 61 8 E2 O —
GD2 62 39 L6 O —
GD3 63 52 K11 O —
GD4 31 21 H2 O —
GD5 32 22 J1 O —
GD6 44 23 J2 O —
GD7 45 76 A11 O —
GD8 43 7 E4 O —
GD9 49 53 J10 O —
GD10 58 69 E10 O —
GD11 59 77 A10 O —
GD12 2 32 K4 O —
GD13 3 33 L4 O —
GD14 6 47 L9 O —
GD15 8 48 K9 O —
GEN 51 91 C5 O — Graphics Display Enable Output.
GPWR 53 27 J3 O — Graphics Display Power System Enable.
HSYNC 64 97 A3 O — Graphics Display Horizontal Sync Pulse.
INT0 46 72 D9 I ST External Interrupt Input.
MCLR
OSCI 39 63 F9 I ANA Main Oscillator Input Connection.
OSCO 40 64 F11 O ANA Main Oscillator Output Connection.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
7 13 F1 I ST Master Clear (device Reset) Input. This line is brought low
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
Interrupt-on-Change Inputs.
Graphics Controller Data Output.
to cause a Reset.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
DS39969B-page 24 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
64-Pin
TQFP/QFN
100-Pin
TQFP
121-Pin
BGA
PGEC1 15 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1.
PGED1 16 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 1.
PGEC2 17 26 L1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 2.
PGED2 18 27 J3 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 2.
PGEC3 11 20 H1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 3.
PGED3 12 21 H2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 3.
PMA0 — 44 L8 I/O ST Parallel Master Port Address bit 0 Input (Buffered Slave
PMA1 — 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave
PMA2 — 14 F3 O —
PMA3 — 12, 60
PMA4 — 11,59
PMA5 — 10,40
(1)
(1)
(1)
F2, G11
F4,G10
E3,K6
(1)
(1)
(1)
PMA6 — 29 K3 O —
PMA7 — 28 L2 O —
PMA8 — 50 L11 O —
PMA9 — 49 L10 O —
PMA10 — 42 L7 O —
PMA11 — 41 J7 O —
PMA12 — 35 J5 O —
PMA13 — 34 L5 O —
PMA14 — 71 C11 O —
PMA15 — 70 D11 O —
PMA16 — 95 C4 O —
PMA17 — 92 B5 O —
PMA18 — 40,10
(1)
K6,E3
(1)
PMA19 — 19 G2 O —
PMA20 — 59, 11
PMA21 — 60,12
PMA22 — 66,9
(1)
(1)
(1)
G10, F4
G11,F2
E11,E1
(1)
(1)
(1)
PMACK1 — 77 A10 I ST/TTL Parallel Master Port Acknowledge Input 1.
PMACK2 — 69 E10 I ST/TTL Parallel Master Port Acknowledge Input 2.
PMALL — 44 L8 O — Parallel Master Port Lower Address Latch Strobe.
PMALH — 43 K7 O — Parallel Master Port Higher Address Latch Strobe.
PMALU — 14 F3 O — Parallel Master Port Upper Address Latch Strobe.
PMBE0 — 78 B9 O — Parallel Master Port Byte Enable Strobe 0.
PMBE1 — 67 E8 O — Parallel Master Port Byte Enable Strobe 1.
PMCS1 — 71
PMCS2 — 70
(3)
,18 C11
(2)
,9,
(1)
66
(3)
,G1 I/O ST/TTL Parallel Master Port Chip Select Strobe 1.
(2)
D11
,E1,
(1)
E11
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
Input
I/O
Buffer
O—
O—
O—
O—
O—
O—
O—
O—
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
modes) and Output (Master modes).
modes) and Output (Master modes).
Parallel Master Port Address bits<22:2>.
Parallel Master Port Chip Select Strobe 2.
2010 Microchip Technology Inc. DS39969B-page 25
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
PMD0 — 93 A4 I/O ST/TTL
PMD1 — 94 B4 I/O ST/TTL
PMD2 — 98 B3 I/O ST/TTL
PMD3 — 99 A2 I/O ST/TTL
PMD4 — 100 A1 I/O ST/TTL
PMD5 — 3 D3 I/O ST/TTL
PMD6 — 4 C1 I/O ST/TTL
PMD7 — 5 D2 I/O ST/TTL
PMD8 — 90 A5 I/O ST/TTL
PMD9 — 89 E6 I/O ST/TTL
PMD10 — 88 A6 I/O ST/TTL
PMD11 — 87 B6 I/O ST/TTL
PMD12 — 79 A9 I/O ST/TTL
PMD13 — 80 D8 I/O ST/TTL
PMD14 — 83 D7 I/O ST/TTL
PMD15 — 84 C7 I/O ST/TTL
PMRD — 82 B8 I/O ST/TTL Parallel Master Port Read Strobe.
PMWR — 81 C8 I/O ST/TTL Parallel Master Port Write Strobe.
RA0 — 17 G3 I/O ST
RA1 — 38 J6 I/O ST
RA2 — 58 H11 I/O ST
RA3 — 59 G10 I/O ST
RA4 — 60 G11 I/O ST
RA5 — 61 G9 I/O ST
RA6 — 91 C5 I/O ST
RA7 — 92 B5 I/O ST
RA9 — 28 L2 I/O ST
RA10 — 29 K3 I/O ST
RA14 — 66 E11 I/O ST
RA15 — 67 E8 I/O ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
Parallel Master Port Data bits<15:0>.
PORTA Digital I/O.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
DS39969B-page 26 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
RB0 16 25 K2 I/O ST
RB1 15 24 K1 I/O ST
RB2 14 23 J2 I/O ST
RB3 13 22 J1 I/O ST
RB4 12 21 H2 I/O ST
RB5 11 20 H1 I/O ST
RB6 17 26 L1 I/O ST
RB7 18 27 J3 I/O ST
RB8 21 32 K4 I/O ST
RB9 22 33 L4 I/O ST
RB10 23 34 L5 I/O ST
RB11 24 35 J5 I/O ST
RB12 27 41 J7 I/O ST
RB13 28 42 L7 I/O ST
RB14 29 43 K7 I/O ST
RB15 30 44 L8 I/O ST
RC1 — 6 D1 I/O ST
RC2 — 7 E4 I/O ST
RC3 — 8 E2 I/O ST
RC4 — 9 E1 I/O ST
RC12 39 63 F9 I/O ST
RC13 47 73 C10 I/O ST
RC14 48 74 B11 I/O ST
RC15 40 64 F11 I/O ST
RCV 18 27 J3 I ST USB Receive Input (from external transceiver).
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
PORTB Digital I/O.
PORTC Digital I/O.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
2010 Microchip Technology Inc. DS39969B-page 27
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
RD0 46 72 D9 I/O ST
RD1 49 76 A11 I/O ST
RD2 50 77 A10 I/O ST
RD3 51 78 B9 I/O ST
RD4 52 81 C8 I/O ST
RD5 53 82 B8 I/O ST
RD6 54 83 D7 I/O ST
RD7 55 84 C7 I/O ST
RD8 42 68 E9 I/O ST
RD9 43 69 E10 I/O ST
RD10 44 70 D11 I/O ST
RD11 45 71 C11 I/O ST
RD12 — 79 A9 I/O ST
RD13 — 80 D8 I/O ST
RD14 — 47 L9 I/O ST
RD15 — 48 K9 I/O ST
RE0 60 93 A4 I/O ST
RE1 61 94 B4 I/O ST
RE2 62 98 B3 I/O ST
RE3 63 99 A2 I/O ST
RE4 64 100 A1 I/O ST
RE5 1 3 D3 I/O ST
RE6 2 4 C1 I/O ST
RE7 3 5 D2 I/O ST
RE8 — 18 G1 I/O ST
RE9 — 19 G2 I/O ST
REFO 30 44 L8 O — Reference Clock Output.
RF0 58 87 B6 I/O ST
RF1 59 88 A6 I/O ST
RF2 — 52 K11 I/O ST
RF3 33 51 K10 I/O ST
RF4 31 49 L10 I/O ST
RF5 32 50 L11 I/O ST
RF7 34 54 H8 I/O ST
RF8 — 53 J10 I/O ST
RF12 — 40 K6 I/O ST
RF13 — 39 L6 I/O ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
PORTD Digital I/O.
PORTE Digital I/O.
PORTF Digital I/O.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
DS39969B-page 28 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
RG0 — 90 A5 I/O ST
RG1 — 89 E6 I/O ST
RG2 37 57 H10 I/O ST
RG3 36 56 J11 I/O ST
RG6 4 10 E3 I/O ST
RG7 5 11 F4 I/O ST
RG8 6 12 F2 I/O ST
RG9 8 14 F3 I/O ST
RG12 — 96 C3 I/O ST
RG13 — 97 A3 I/O ST
RG14 — 95 C4 I/O ST
RG15 — 1 B2 I/O ST
RP0 16 25 K2 I/O ST
RP1 15 24 K1 I/O ST
RP2 42 68 E9 I/O ST
RP3 44 70 D11 I/O ST
RP4 43 69 E10 I/O ST
RP5 — 48 K9 I/O ST
RP6 17 26 L1 I/O ST
RP7 18 27 J3 I/O ST
RP8 21 32 K4 I/O ST
RP9 22 33 L4 I/O ST
RP10 31 49 L10 I/O ST
RP11 46 72 D9 I/O ST
RP12 45 71 C11 I/O ST
RP13 14 23 J2 I/O ST
RP14 29 43 K7 I/O ST
RP15 — 53 J10 I/O ST
RP16 33 51 K10 I/O ST
RP17 32 50 L11 I/O ST
RP18 11 20 H1 I/O ST
RP19 6 12 F2 I/O ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
I/O
Input
Buffer
PORTG Digital I/O.
Remappable Peripheral (input or output).
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
2010 Microchip Technology Inc. DS39969B-page 29
PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
RP20 53 82 B8 I/O ST
RP21 4 10 E3 I/O ST
RP22 51 78 B9 I/O ST
RP23 50 77 A10 I/O ST
RP24 49 76 A11 I/O ST
RP25 52 81 C8 I/O ST
RP26 5 11 F4 I/O ST
RP27 8 14 F3 I/O ST
RP28 12 21 H2 I/O ST
RP29 30 44 L8 I/O ST
RP30 — 52 K11 I/O ST
RP31 — 39 L6 I/O ST
RPI32 — 40 K6 I ST
RPI33 — 18 G1 I ST
RPI34 — 19 G2 I ST
RPI35 — 67 E8 I ST
RPI36 — 66 E11 I ST
RPI37 48 74 B11 I ST
RPI38 — 6 D1 I ST
RPI39 — 7 E4 I ST
RPI40 — 8 E2 I ST
RPI41 — 9 E1 I ST
RPI42 — 79 A9 I ST
RPI43 — 47 L9 I ST
RTCC 42 68 E9 O — Real-Time Clock Alarm/Seconds Pulse Output.
SCL1 44 66 E11 I/O I
SCL2 32 58 H11 I/O I
SCL3 2 4 C1 I/O I
SCLKI 48 74 B11 O ANA Secondary Clock Input.
SDA1 43 67 E8 I/O I
SDA2 31 59 G10 I/O I
SDA3 3 5 D2 I/O I
SESSEND 55 84 C7 I ST USB V
SESSVLD 59 88 A6 I ST USB V
SOSCI 47 73 C10 I ANA Secondary Oscillator/Timer1 Clock Input.
SOSCO 48 74 B11 O ANA Secondary Oscillator/Timer1 Clock Output.
T1CK 48 74 B11 I ST Timer1 Clock.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
64-Pin
TQFP/QFN
ANA = Analog level input/output I
100-Pin
TQFP
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
121-Pin
BGA
Input
I/O
Buffer
Remappable Peripheral (input or output).
Remappable Peripheral (input only).
2
C™ I2C1 Synchronous Serial Clock Input/Output.
2
C I2C2 Synchronous Serial Clock Input/Output.
2
C I2C3 Synchronous Serial Clock Input/Output.
2
C I2C1 Data Input/Output.
2
C I2C2 Data Input/Output.
2
C I2C3 Data Input/Output.
BUS Boost Generator, Comparator Input 3.
BUS Boost Generator, Comparator Input 2.
2
C™ = I2C/SMBus input buffer
(CW3<12>) bit is programmed to ‘0’.
Description
DS39969B-page 30 2010 Microchip Technology Inc.
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