PIC24FJ128GA310 FAMILY
64/80/100-Pin, General Purpose, 16-Bit Flash Mi crocontr ollers
with LCD Controller and nanoWatt XLP Technology
Extreme Low-Power Features:
• Multiple Power Management Options for Extreme
Power Reduction:
-VBAT allows the device to transition to a back-up
battery for the lowest power consumption with
RTCC
- Deep Sleep allows near total power-down, with
the ability to wake-up on external triggers
- Sleep and Idle modes selectively shut down
peripherals and/or core for substantial power
reduction and fast wake-up
- Doze mode allows CPU to run at a lower clock
speed than peripherals
• Alternate Clock modes Allow On-the-Fly Switching to
a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for
Deep Sleep:
- WDT: 270 nA @ 3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current, 40 na, 3.3V typical
Peripheral Features:
• LCD Display Controller:
- Up to 60 segments by 8 commons
- Internal charge pump and low-power, internal
resistor biasing
- Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS): Allows Independent I/O
Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
- Can be paired as 32-bit timers/counters
• Six-Channel DMA supports All Peripheral modules
- Minimizes CPU overhead and increases data
throughput
Memory Remappable Peripherals
Peripheral Features (continued):
• Seven Input Capture modules, each with a
Dedicated 16-Bit Timer
• Seven Output Compare/PWM modules, each with a
Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
- Runs in Deep Sleep and V
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
2
•Two I
•Four UART modules:
• Programmable 32-bit Cyclic Redundancy Check
• Digital Signal Modulator Providers On-Chip FSK and
• Configurable Open-Drain Outputs on Digital I/O Pins
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
C™ modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
- Support RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA
- Auto-wake-up on Auto-Baud Detect
- 4-level deep FIFO buffer
(CRC) Generator
PSK Modulation for a Digital Signal Stream
BAT modes
®
Analog Features:
• 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:
- Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
- Conversion available during Sleep and Idle
• Three Rail-to-Rail Enhanced Analog Comparators
with Programmable Input/Output Configuration
• On-Chip Programmable Voltage Reference
• Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 24 channels
- Time measurement down to 1 ns resolution
- CTMU temperature sensing
®
BAT
C™
Device
PIC24FJ128GA310 100 128K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y
PIC24FJ128GA308 80 128K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y
PIC24FJ128GA306 64 128K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y
PIC24FJ64GA310 100 64K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y
PIC24FJ64GA308 80 64K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y
PIC24FJ64GA306 64 64K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y
2010-2011 Microchip Technology Inc. DS39996F-page 1
Pins
Flash
(bytes)
Program
(bytes)
Data SRAM
16-Bit Timers
Capture Inp ut
Output
UART w/IrDA
Compare/PWM
2
I
SPI
(ch)
CTMU (ch)
10/12-Bit A/D
Comparators
EPMP/EPSP
JTAG
LCD (pixels)
Deep Sleep w/V
PIC24FJ128GA310 FAMILY
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator:
- 4x PLL option
- Multiple clock divide options
- Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
Special Microcontroller Features:
• Operating Voltage Range of 2.0V to 3.6V
• Two On-Chip Voltage Regulators (1.8V and 1.2V) for
Regular and Extreme Low-Power Operation
• 20,000 Erase/Write Cycle Endurance Flash Program
Memory, typical
• Flash Data Retention: 20 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Operation below V
• Low-Voltage Detect (LVD)
• Flexible Watchdog Timer (WDT) with its own
RC Oscillator for Reliable Operation
• Standard and Ultra Low-Power Watchdog Timers
(WDT) for Reliable Operation in Standard and Deep
Sleep modes
BOR
DS39996F-page 2 2010-2011 Microchip Technology Inc.
Pin Diagrams
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
2244242526272829303132
PIC24FJXXXGA306
1
46
45
23
43
42
41
40
39
C3INB/SEG25/CN15/RD6
RP20
/SEG24/PMRD/CN14/RD5
RP25
/SEG23/PMWR/CN13/RD4
RP22
/SEG22/PMBE0/CN52/RD3
RP23
/SEG21/PMACK1/CN51/RD2
RP24
/SEG20/CN50/RD1
LVDIN/CTED8/PMD4/CN62/RE4
COM0/CTED9/PMD3/CN61/RE3
COM1/PMD2/CN60/RE2
COM2/PMD1/CN59/RE1
SEG27/CN68/RF0
V
CAP
/V
DDCORE
SOSCI/RC13
RP11
/SEG17/CN49/RD0
RP3
/SEG15/PMA15/C3IND/CS2/CN55/RD10
RP4
/SEG14/PMACK2/CN54/RD9
RP2
/SEG13/RTCC/CN53/RD8
RP12
/C3INC/SEG16/PMA14/CS1/CN56/RD11
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
V
DD
SEG28/CN72/SCL1/RG2
INT0/CN84/RF6
RP30
/CN70/RF2
RP16
/SEG12/CN71/RF3
SEG47/CN73/SDA1/RG3
SOSCO/
RPI37
/SCKLI/RC14
AV
DD
AN8/
RP8
/SEG31/COM7/CN26/RB8
AN9/
RP9
/SEG30/COM6/T1CK/PMA7/CN27/RB9
TMS/CV
REF
/AN10/SEG29/COM5/PMA13/CN28/RB10
TDO/AN11/PMA12/CN29/RB11
V
DD
PGEC2/AN6/
RP6
/LCDBIAS3/CN24/RB6
PGED2/AN7/
RP7
/CN25/RB7
PMA8/
RP17
/SCL2/SEG11/CN18/RF5
RP10
/SDA2/SEG10/PMA9/CN17/RF4
PMD5/CTED4/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
C1IND/
RP21
/SEG0/PMA5/CN8/RG6
V
DD
PGEC3/AN5/C1INA/
RP18
/SEG2/CN7/RB5
PGED3/AN4/C1INB/
RP28
/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
AN2/C2INB/CTCMP/CTED13/
RP13
/SEG5/CN4/RB2
V
LCAP
1/C1INC/
RP26
/PMA4/CN9/RG7
V
LCAP
2/C2IND/
RP19
/PMA3/CN10/RG8
PGEC1/CV
REF
-/AN1/
RP1
/SEG6/CTED12/CN3/RB1
PGED1/CV
REF
+/AN0/
RP0
/SEG7/PMA6/CN2/RB0
C2INC/
RP27
/SEG1/PMA2/CN11/RG9
MCLR
TCK/AN12/CTED2/PMA11/SEG18/CN30/RB12
TDI/AN13/SEG19/CTED1/PMA10/CN31/RB13
AN14/
RP14
/SEG8/CTED5/CTPLS/PMA1/CN32/RB14
AN15/
RP29
/SEG9/CTED6/REFO/PMA0/CN12/RB15
COM3/PMD0/CN58/RE0
COM4/SEG48/CN69/RF1
C3INA/SEG26/CN16/RD7
V
SS
V
SS
V
SS
V
BAT
636261596058575654555352514950
38
37
34
36
35
33
171920
21
18
AV
SS
64
64-Pin TQFP, QFN
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Note: Pinouts are subject to change.
PIC24FJ128GA310 FAMILY
2010-2011 Microchip Technology Inc. DS39996F-page 3
807978
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
60
59
26
56
40
39
2829303132333435363738
PIC24FJXXXGA308
17
18
19
1
76
77
58
57
27
55
54
53
52
51
RP20
/SEG24/PMRD/CN14/RD5
RP25
/SEG23/PMWR/CN13/RD4
SEG45/PMD13/CN19/RD13
RPI42
/SEG44/PMD12/CN57/RD12
RP22
/SEG22/PMBE0/CN52/ RD3
RP23
/SEG21/PMACK1/CN51/ RD2
RP24
/SEG20/CN50/RD1
COM1/PMD2/CN60/RE2
COM2/PMD1/CN59/RE1
COM3/PMD0/CN58/RE0
SEG50/PMD8/CN77/RG0
LVDIN/CTED8/PMD4/CN62/RE4
CTED9/COM0/PMD3/CN61/ RE3
SEG27/PMD11/CN68/RF0
V
CAP
/V
DDCORE
SOSCI/RC13
RP11
/SEG17/CN49/RD0
RP3
/SEG15/C3IND/PMA15/CS2/CN55/RD10
RP4
/SEG14/PMACK2/CN54/RD9
RP2
/SEG13/RTCC/CN53/RD8
RP12
/C3INC/SEG16/PMA14/CS1/CN56/RD11
RPI35
/SEG43/PMBE1/CN44/RA15
RPI36
/SEG42/PMA22/CN43/RA14
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
V
DD
SEG28/SCL1/CN72/RG2
INT0/CN84/RF6
CN83/RF7
RP15
/SEG41/CN74/RF8
SEG47/SDA1/CN73/RG3
RP30
/SEG40/CN70/RF2
RP16
/SEG12/CN71/RF3
RPI37
/SOSCO/SCKLI/RC14
V
REF
+/SEG37/PMA6/CN42/RA10
V
REF
-/SEG36/PMA7/CN41/RA9
AV
DD
AN8/
RP8
/SEG31/COM7/CN26/RB8
AN9/
RP9/
SEG30/COM6/T1CK/CN27/RB9
CV
REF
/AN10/SEG29/COM5/PMA13/CN28/RB10
AN11/PMA12/CN29/RB11
V
DD
RPI43
/SEG38/CN20/RD14
RP5
/SEG39/CN21/RD15
PGEC2/AN6/
RP6
/LCDBIAS3/CN24/RB6
PGED2/AN7/
RP7
/CN25/RB7
RP17
/SEG11/SCL2/PMA8/CN18/RF5
RP10
/SEG10/SDA2/PMA9/CN17/RF4
PMD5/CTED4/LCDBIAS2/CN6 3/RE5
PMD6/LCDBIAS1/CN64/ RE6
PMD7/LCDBIAS0/CN65/ RE7
RPI38
/SEG32/CN45/RC1
RPI40
/SEG33/CN47/RC3
C1IND/
RP21
/SEG0/PMA5/CN8/RG6
V
DD
TMS/
RPI33
/SEG34/PMCS1/CN66/ RE8
TDO/
RPI34
/SEG35/PMA19/CN67/ RE9
AN3/C2INA/SEG4/CN5/RB3
AN2/C2INB/
RP13
/CTCMP/SEG5/CTED13/CN4/RB2
V
LCAP
1/C1INC/
RP26
/PMA4/CN9/RG7
V
LCAP
2/C2IND/
RP19
/PMA3/CN10/RG8
PGEC1/CV
REF
-/AN1/
RP1
/SEG6/CTED12/CN3/RB1
PGED1/CV
REF
+/AN0/
RP0
/SEG7/CN2/RB0
C2INC/
RP27/
SEG1/PMA2/CN11/RG9
MCLR
TCK/AN12/CTED2/SEG18/ PMA11/CN30/RB12
TDI/AN13/CTED1/SEG19/PMA10/CN31/RB13
AN14/
RP14
/SEG8/CTPLS/CTED5/PMA1/CN32/RB14
AN15/
RP29
/SEG9/CTED6/REFO/PMA 0/CN12/RB15
SEG46/PMD9/CN78/RG1
COM4/SEG48/PMD10/CN69/RF1
C3INA/SEG26/PMD15/CN16/RD7
C3INB/SEG25/PMD14/CN15/RD6
V
SS
Vss
V
SS
V
BAT
757473717270696866676564636162
50
49
46
48
47
45
44
43
42
41
212324
25
22
AV
SS
PGEC3/AN5/C1INA/
RP18
/SEG2/CN7/RB5
PGED3/AN4/C1INB/
RP28
/SEG3/CN6/RB4
80-Pin TQFP
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Note: Pinouts are subject to change.
PIC24FJ128GA310 FAMILY
Pin Diagrams (continued)
DS39996F-page 4 2010-2011 Microchip Technology Inc.
9294939190898887868584838281807978
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
2829303132333435363738
PIC24FJXXXGA310
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
969897
99
27
4647484950
55
54
53
52
51
100
RP20
/SEG24/PMRD/CN14/RD5
RP25
/SEG23/PMWR/CN13/RD4
SEG45/PMD13 /CN19/RD13
RPI42
/SEG44/PMD12/CN57/RD12
RP22
/SEG22/PMBE0/CN52/RD3
RP23
/SEG21/PMACK1/CN51/RD2
RP24
/SEG20/CN50/RD1
AN22/SEG59/PMA17/CN40/RA7
AN23/SEG58/CN39/RA6
COM1/PMD2/CN60/RE2
SEG62/CTED10/CN80/RG13
SEG61/CN79/RG12
SEG60/PMA16/CTED11/CN81/RG14
COM2/PMD1/CN59/RE1
COM3/PMD0/CN58/RE0
SEG50/PMD8/CN77/RG0
SEG63/PMD4/LVDIN/CTED8/CN62/RE4
COM0/PMD3/CTED9/CN61/RE3
SEG27/PMD11/CN68/RF0
V
CAP
/V
DDCORE
SOSCI/RC13
RP11
/SEG17/CN49/RD0
RP3
/SEG15/C3IND/PMA15/CS2/ CN55/RD10
RP4
/SEG14/PMACK2/CN54/RD9
RP2
/SEG13/RTCC/CN53/RD8
RP12
/SEG16/C3INC/PMA14/CS1/CN5 6/RD11
RPI35
/SEG43/PMBE1/CN44/RA15
RPI36
/SEG42/PMA22/CN43/RA14
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
V
DD
SCL1/SEG28/CN72/RG2
INT0/CN84/RF6
CN83/RF7
RP15
/SEG41/CN74/RF8
SDA1/SEG47/CN73/RG3
RP30
/SEG40/CN70/RF2
RP16
/SEG12/CN71/RF3
V
SS
RPI37
/SOSCO/SCLKI/RC14
V
REF
+/SEG37/PMA6/CN42/RA10
V
REF
-/SEG36/PMA7/CN41/RA9
AV
DD
AV
SS
AN8/
RP8
/SEG31/COM7/CN26/RB8
AN9/
RP9
/SEG30/T1CK/COM6/CN27/RB9
CV
REF
/AN10/SEG29/COM5/PMA13/CN28/RB10
AN11/PMA12/CN29/RB11
V
DD
RPI32
/SEG55/CTED7/PMA18/CN75/RF12
RP31
/SEG54/CN76/RF13
V
SS
V
DD
RP5
/SEG39/CN21/RD15
RPI43
/SEG38/CN20/RD14
PGEC2/AN6/
RP6
/LCDBIAS3/CN24/RB6
PGED2/AN7/
RP7
/CN25/RB7
RP17
/SEG11/PMA8/CN18/RF5
RP10
/SEG10/PMA9/CN17/RF4
CTED4/PMD5/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
RPI38
/SEG32/CN45/RC1
RPI39
/SEG52/CN46/RC2
RPI40
/SEG33/CN47/RC3
AN16/
RPI41
/SEG53/PMCS2/CN48/RC4
AN17/C1IND/
RP21
/SEG0/PMA5/CN8/RG6
V
DD
TMS/CTED0/SEG49/CN33/RA0
RPI33
/SEG34/PMCS1/CN66/RE8
AN21/
RPI34
/SEG35/PMA19/CN67/RE9
PGEC3/AN5/C1INA/
RP18
/SEG2/CN7/RB5
AN3/C2INA/SEG4/CN5/RB3
AN2/C2INB/
RP13
/SEG5/CTED13/CTCMP/CN4/RB2
V
LCAP
1/AN18/C1INC/
RP26
/PMA4/CN9/RG7
V
LCAP
2/AN19/C2IND/
RP19
/PMA3/CN10/RG8
PGEC1/CV
REF
-/AN1/
RP1
/SEG6/CTED12/CN3/RB1
PGED1/CV
REF
+/AN0/
RP0
/SEG7/CN2/RB0
SEG51/CTED3/CN82/RG15
V
DD
AN20/C2INC/
RP27
/SEG1/PMA2/CN11/RG9
MCLR
AN12/CTED2/SEG18/PMA11/CN30/RB12
AN13/CTED1/PMA10/SEG19/CN31/RB13
AN14/
RP14
/SEG8/CTPLS/CTED5/PMA1/CN32/RB14
AN15/
RP29
/SEG9/REFO/CTED6/PMA0/CN12/RB15
SEG46/PMD9/CN78/RG1
COM4/SEG48/PMD10/CN69/RF1
C3INA/SEG26/PMD15/CN16/RD7
C3INB/SEG25/PMD14/CN15/RD6
TDO/CN38/RA5
SDA2/SEG57/PMA20/CN36/RA3
SCL2/SEG56/CN35/RA2
V
SS
V
SS
V
SS
V
BAT
TDI/PMA21/CN37/RA4
TCK/CN34/RA1
PGED3/AN4/C1INB/
RP28
/SEG3/CN6/RB4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Note: Pinouts are subject to change.
100-Pin TQFP
PIC24FJ128GA310 FAMILY
Pin Diagrams (continued)
2010-2011 Microchip Technology Inc. DS39996F-page 5
PIC24FJ128GA310 FAMILY
1 3 5 7 8 9 10 11
A
RE4 RE3 RE0 RG0 RF1 VBAT N/C RD12 RD1
B
N/C RE2 R E1 RA 7 RF0 VCAP/ RD5 RD3 VSS RC14
C
RE6 VDD RG14 N/C RD7 RD4 N/C RC13 RD11
D
RE7 RE5 N/C N/C N/C RD6 RD13 RD0 N/C RD10
E
RC4 RG6 N/C RG1 N/C RA15 RD8 RA14
F
MCLR RG8 RG9 RG7 VSS N/C N/C VDD OSCI/ VSS OSCO/
G
RE8 RE9 RA0 N/C VDD VSS VSS N/C RA5 RA3 RA4
H
N/C N/C N/C VDD N/C RF6 RG2 RA2
J
AVDD RB11 RA1 RB12 N/C N/C RF8 RG3
K
RA10 N/C RF12 RB 14 VDD
L
RA9 AVSS RB10 RB13 RB15 RF4 RF5
24 6
RF7
RG13 RD2
RG15
RG12 RA6
RC1
RC3 RC2 RD9
RC12
RC15
RB4
RB3 RB2
RB8 RD15 RF3 RF2
RB9 RF13 RD14
RB5
RB1 RB0
RB6
RB7
VDDCORE
121-Pin BGA (Top View)
Legend: Shaded pins indicate pins that are tolerant up to +5.5V.
Note: See Ta b le 1 for complete pinout descriptions. Pinouts are subject to change.
Pin Diagrams (continued)
DS39996F-page 6 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES
PinFunctionPinFunction
A1 SEG63/PMD4/LVDIN/CTED8/CN62/RE4 E1 AN16/RPI41/SEG53/PMCS2/CN48/RC4
A2 COM0/PMD3/CTED9/CN61/RE3 E2 RPI40/SEG33/CN47/RC3
A3 SEG62/CTED10/CN80/RG13 E3 AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6
A4 COM3/PMD0/CN58/RE0 E4 RPI39/SEG52/CN46/RC2
A5 SEG50/ PMD8/CN77/RG0 E5 N/C
A6 SEG48/COM4/PMD10/CN69/RF1 E6 SEG46/PMD9/CN78/RG1
A7 V
BAT E7 N/C
A8 N/C E8 RPI35/SEG43/PMBE1/CN44/RA15
A9 RPI42/SEG44/PMD12/CN57/RD12 E9 RP2/SEG13/RTCC/CN53/RD8
A10 RP23/SEG21/PMACK1/CN51/RD2 E10 RP4/SEG14/PMACK2/CN54/RD9
A11 RP24/SEG20/CN50/RD1 E11 RPI36/SEG42/PMA22/CN43/RA14
B1 N/C F1 MCLR
B2 SEG51/CTED3/CN82/RG15 F2 VLCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8
B3 COM1/PMD2/CN60/RE2 F3 AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9
B4 COM2/PMD1/CN59/RE1 F4 V
B5 AN22/SEG59/PMA17/CN40/RA7 F5 V
B6 SEG27/PMD11/CN68/RF0 F6 N/C
B7 V
CAP F7 N/C
B8 RP20/SEG24/PMRD/CN14/RD5 F8 V
B9 RP22/SEG22/PMBE0/CN52/RD3 F9 OSCI/CLKI/CN23/RC12
B10 V
B11 RPI37/SOSCO/SCLKI/RC14 F11 OSCO/CLKO/CN22/RC15
C10 SOSCI/RC13 G10 SDA2/SEG57/PMA20/CN36/RA3
C11 RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11 G11 TDI/PMA21/CN37/RA4
D10 N/C H10 SCL1/SEG28/CN72/RG2
D11 RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10 H11 SCL2/SEG56/CN35/RA2
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
SS F10 VSS
C1 PMD6/LCDBIAS1/CN64/RE6 G1 RPI33/SEG34/PMCS1/CN66/RE8
C2 V
DD G2 AN21/RPI34/SEG35/PMPA19/CN67/RE9
C3 SEG61/CN79/RG12 G3 TMS/SEG49/CTED0/CN33/RA0
C4 SEG60/PMA16/CTED11/CN81/RG14 G4 N/C
C5 AN23/SEG58/CN39/RA6 G5 V
C6 N/C G6 VSS
C7 C3INA/SEG26/PMD15/CN16/RD7 G7 VSS
C8 RP25/SEG23/PMWR/CN13/RD4 G8 N/C
C9 N/C G9 TDO/CN38/RA5
D1 RPI38/SEG32/CN45/RC1 H1 PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
D2 PMD7/LCDBIAS0/CN65/RE7 H2 PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
D3 PMD5/CTED4/LCDBIAS2/CN63/RE5 H3 N/C
D4 N/C H4 N/C
D5 N/C H5 N/C
D6 N/C H6 V
D7 C3INB/SEG25/PMD14/CN15/RD6 H7 N/C
D8 SEG45/PMD13/CN19/RD13 H8 CN83/RF7
D9 RP11/SEG17/CN49/RD0 H9 INT0/CN84/RF6
Note: Pinouts are subject to change.
LCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7
SS
DD
DD
DD
2010-2011 Microchip Technology Inc. DS39996F-page 7
PIC24FJ128GA310 FAMILY
TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES (CONTINUED)
PinFunctionPinFunction
J1 AN3/C2INA/SEG4/CN5/RB3 K7 AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14
J2 AN2/C2INB/RP13/SEG5/CTCMP/CTED13/CN4/RB2 K8 V
J3 PGED2/AN7/RP7/CN25/RB7 K9 RP5/SEG39/CN21/RD15
J4 AV
J5 AN11/PMA12/CN29/RB11 K11 RP30/SEG40/CN70/RF2
J6 TCK/CN34/RA1 L1 PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6
J7 AN12/SEG18/CTED2/PMA11/CN30/RB12 L2 V
J8 N/C L3 AV
J9 N/C L4 AN9/RP9/COM6/SEG30/T1CK/CN27/RB9
J10 RP15/SEG41/CN74/RF8 L5 CV
J11 SDA1/SEG47/CN73/RG3 L6 RP31/SEG54/CN76/RF13
K1 PGEC1/CV
K2 PGD1/CV
K3 V
K4 AN8/RP8/COM7/SEG31/CN26/RB8 L10 RP10/SEG10/PMA9/CN17/RF4
K5 N/C L11 RP17 /SEG11/PMA8/CN18/RF5
K6 RPI32/SEG55/CTED7/PMA18/CN75/RF12
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
Note: Pinouts are subject to change.
DD K10 RP16/SEG12/CN71/RF3
REF-/AN1/RP1/SEG6/CTED12/CN3/RB1 L7 AN13/SEG19/CTED1/PMA10/CN31/RB13
REF+/AN0/RP0/SEG7/CN2/RB0 L8 AN15/RP29/SEG9/CTED6/REFO/PMA0/CN12/RB15
REF+/SEG37/PMA6/CN42/RA10 L9 RPI43/SEG38/CN20/RD14
DD
REF-/SEG36/PMA7/CN41/RA9
SS
REF/AN10/COM5/SEG29/PMA13/CN28/RB10
DS39996F-page 8 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 29
3.0 CPU ........................................................................................................................................................................................... 35
4.0 Memory Organization ................................................................................................................................................................. 41
5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 75
6.0 Flash Program Memory.............................................................................................................................................................. 83
7.0 Resets ........................................................................................................................................................................................ 89
8.0 Interrupt Controller ..................................................................................................................................................................... 95
9.0 Oscillator Configuration............................................................................................................................................................ 145
10.0 Power-Saving Features............................................................................................................................................................ 155
11.0 I/O Ports ................................................................................................................................................................................... 167
12.0 Timer1 ...................................................................................................................................................................................... 197
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 199
14.0 Input Capture with Dedicated Timers ....................................................................................................................................... 205
15.0 Output Compare with Dedicated Timers .................................................................................................................................. 211
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 221
17.0 Inter-Integrated Circuit™ (I
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 241
19.0 Data Signal Modulator.............................................................................................................................................................. 249
20.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 253
21.0 Liquid Crystal Display (LCD) Controller.................................................................................................................................... 265
22.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 275
23.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 289
24.0 12-Bit A/D Converter with Threshold Scan............................................................................................................................... 295
25.0 Triple Comparator Module........................................................................................................................................................ 315
26.0 Comparator Voltage Reference................................................................................................................................................ 321
27.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 323
28.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 331
29.0 Section Special Features ........................................................................................................................................................ 333
30.0 Development Support............................................................................................................................................................... 347
31.0 Instruction Set Summary.......................................................................................................................................................... 351
32.0 Electrical Characteristics.......................................................................................................................................................... 359
33.0 Packaging Information.............................................................................................................................................................. 377
Appendix A: Revision History............................................................................................................................................................. 393
Index .................................................................................................................................................................................................. 395
The Microchip Web Site..................................................................................................................................................................... 401
Customer Change Notification Service .............................................................................................................................................. 401
Customer Support .............................................................................................................................................................................. 401
Reader Response .............................................................................................................................................................................. 402
Product Identification System ............................................................................................................................................................ 403
2
C™).............................................................................................................................................. 233
2010-2011 Microchip Technology Inc. DS39996F-page 9
PIC24FJ128GA310 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS39996F-page 10 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ64GA306 • PIC24FJ128GA306
• PIC24FJ64GA308 • PIC24FJ128GA308
• PIC24FJ64GA310 • PIC24FJ128GA310
The PIC24FJ128GA310 family adds many new features to Microchip‘s 16-bit microcontrollers, including
new ultra low-power features, Direct Memory Access
(DMA) for peripherals, and a built-in LCD Controller
and Driver. Together, these provide a wide range of
powerful features in one economical and power-saving
package.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such
as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2 nanoWatt XLP POWER-SAVING
TECHNOLOGY
The PIC24FJ128GA310 family of devices introduces a
greatly-expanded range of power-saving operating
modes for the ultimate in power conservation. The new
modes include:
• Retention Sleep, with essential circuits being
powered from a separate low-voltage regulator
• Deep Sleep without RTCC, for the lowest possible
power consumption under software control
BAT mode (with or without RTCC), to continue
•V
operation limited operation from a back-up battery
DD is removed
when V
Many of these new low-power modes also support the
continuous operation of the low-power, on-chip
Real-Time Clock/Calendar (RTCC), making it possible
for an application to keep time while the device is
otherwise asleep.
Aside from these new features, PIC24FJ128GA310 family devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower-power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of Idle and the many Sleep modes.
1.1.3 OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ128GA310 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes
• Two External Clock modes
• A Phase Lock Loop (PLL) frequency multiplier,
which allows clock speeds of up to 32 MHz
• A Fast Internal Oscillator (FRC) (nominal 8 MHz
output) with multiple frequency divider options
• A separate Low-Power Internal RC Oscillator
(LPRC) (31 kHz nominal) for low-power,
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the internal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger, or even in jumping from 64-pin to 100-pin
devices.
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
2010-2011 Microchip Technology Inc. DS39996F-page 11
PIC24FJ128GA310 FAMILY
1.2 DMA Controller
PIC24FJ128GA310 family devices also introduce a
new Direct Memory Access Controller (DMA) to the
PIC24F architecture. This module acts in concert with
the CPU, allowing data to move between data memory
and peripherals without the intervention of the CPU,
increasing data throughput and decreasing execution
time overhead. Six independently programmable channels make it possible to service multiple peripherals at
virtually the same time, with each channel peripheral
performing a different operation.
Many types of data
transfer operations are supported.
1.3 LCD Controller
With the PIC24FJ128GA310 family of devices,
Microchip introduces its versatile Liquid Crystal Display
(LCD) controller and driver to the PIC24F family. The
on-chip LCD driver includes many features that make
the integration of displays in low-power applications
easier. These include an integrated voltage regulator
with charge pump and an integrated internal resistor
ladder that allows contrast control in software and
display operation above device V
DD.
1.4 Other Special Features
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Communications: The PIC24FJ128GA310 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I
modules that support both Master and Slave
modes of operation. Devices also have, through
the PPS feature, four independent UARTs with
built-in IrDA
modules.
• Analog Features: All members of the
PIC24FJ128GA310 family include the new 12-bit
A/D Converter (A/D) module and a triple comparator module. The A/D module incorporates a range
of new features that allow the converter to assess
and make decisions on incoming data, reducing
CPU overhead for routine A/D conversions. The
comparator module includes three analog comparators that are configurable for a wide range of
operations.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ128GA310
family include the CTMU interface module. This
provides a convenient method for precision time
measurement and pulse generation, and can
serve as an interface for capacitive sensors.
®
encoders/decoders and two SPI
2
C™
• Enhanced Parallel Master/Parallel Slave Port:
This module allows rapid and transparent access
to the microcontroller data bus, and enables the
CPU to directly address external data memory. The
parallel port can function in Master or Slave mode,
accommodating data widths of 4, 8 or 16 bits, and
address widths up to 23 bits in Master modes.
• Real-Time Clock and Calendar (RTCC): This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
• Data Signal Modulator (DSM): The Data Signal
Modulator (DSM) allows the user to mix a digital
data stream (the “modulator signal”) with a carrier
signal to produce a modulated output.
1.5 Details on Individual Family Members
Devices in the PIC24FJ128GA310 family are available
in 64-pin, 80-pin and 100-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in
six ways:
1. Flash program memory (64 Kbytes for
PIC24FJ64GA3XX devices and 128 Kbytes for
PIC24FJ128GA3XX devices).
2. Available I/O pins and ports (53 pins on 6 ports
for 64-pin devices, 69 pins on 7 ports for 80-pin
devices and 85 pins on 7 ports for 100-pin
devices).
3. Available Interrupt-on-Change Notification (ICN)
inputs (52 on 64-pin devices, 66 on 80-pin
devices and 82 on 100-pin devices).
4. Available remappable pins (29 pins on 64-pin
devices, 40 on 80-pin devices and 44 pins on
100-pin devices).
5. Maximum available drivable LCD pixels (272 on
64-pin devices, 368 on 80-pin devices and
480 on 100-pin devices.)
6. Analog input channels (16 channels for 64-pin
and 80-pin devices, and 24 channels for 100-pin
devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1, Tab le 1 -2 and
Table 1-3.
A list of the pin features available on the
PIC24FJ128GA310 family devices, sorted by function,
is shown in Ta bl e 1 -4. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
PIC24FJDS39996F-page 12 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 64-PIN
Features PIC24FJ64GA306 PIC24FJ128GA306
Operating Frequency DC – 32 MHz
Program Memory (bytes) 64K 128K
Program Memory (instructions) 22,016 44,032
Data Memory (bytes) 8K
Interrupt Sources (soft vectors/
NMI traps)
I/O Ports Ports B, C, D, E, F, G
Total I/O Pins 53
Remappable Pins 30 (29 I/O, 1 Input only)
Timers:
Total Number (16-bit) 5
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 7
Output Compare/PWM Channels 7
Input Change Notification Interrupt 52
Serial Communications:
UART 4
SPI (3-wire/4-wire) 2
I2C™ 2
Digital Signal Modulator Yes
Parallel Communications (EPMP/PSP) Yes
JTAG Boundary Scan Yes
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators 3
CTMU Interface Yes
LCD Controller (available pixels) 240 (30 SEG x 8 COM)
Resets (and Delays) Core POR, V
MCLR
Hardware Traps, Configuration Word Mismatch
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 64-Pin TQFP and QFN
Note 1: Peripherals are accessible through remappable pins.
DD POR, VBAT POR,BOR, RESET Instruction,
, WDT; Illegal Opcode, REPEAT Instruction,
65 (61/4)
(1)
(1)
(1)
(1)
(1)
16
(OST, PLL Lock)
2010-2011 Microchip Technology Inc. DS39996F-page 13
PIC24FJ128GA310 FAMILY
TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 80-PIN
Features PIC24FJ64GA308 PIC24FJ128GA308
Operating Frequency DC – 32 MHz
Program Memory (bytes) 64K 128K
Program Memory (instructions) 22,016 44,032
Data Memory (bytes) 8K
Interrupt Sources (soft vectors/
NMI traps)
I/O Ports Ports A, B, C, D, E, F, G
Total I/O Pins 69
Remappable Pins 40 (31 I/O, 9 Input only)
Timers:
Total Number (16-bit) 5
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 7
Output Compare/PWM Channels 7
Input Change Notification Interrupt 66
Serial Communications:
UART 4
SPI (3-wire/4-wire) 2
I2C™ 2
Digital Signal Modulator Yes
Parallel Communications (EPMP/PSP) Yes
JTAG Boundary Scan Yes
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators 3
CTMU Interface Yes
LCD Controller (available pixels) 368 (46 SEG x 8 COM)
Resets (and Delays) Core POR, V
MCLR
Hardware Traps, Configuration Word Mismatch
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 80-Pin TQFP and QFN
Note 1: Peripherals are accessible through remappable pins.
DD POR, VBAT POR,BOR, RESET Instruction,
, WDT; Illegal Opcode, REPEAT Instruction,
65 (61/4)
(1)
(1)
(1)
(1)
(1)
16
(OST, PLL Lock)
PIC24FJDS39996F-page 14 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 100-PIN DEVICES
Features PIC24FJ64GA310 PIC24FJ128GA310
Operating Frequency DC – 32 MHz
Program Memory (bytes) 64K 128K
Program Memory (instructions) 22,016 44,032
Data Memory (bytes) 8K
Interrupt Sources (soft vectors/NMI
traps)
I/O Ports Ports A, B, C, D, E, F, G
To t al I / O P i n s 85
Remappable Pins 44 (32 I/O, 12 input only)
Timers:
Total Number (16-bit) 5
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 7
Output Compare/PWM Channels 7
Input Change Notification Interrupt 82
Serial Communications:
UART 4
SPI (3-wire/4-wire) 2
I2C™ 2
Digital Signal Modulator Yes
Parallel Communications
(EPMP/PSP)
JTAG Boundary Scan Yes
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators 3
CTMU Interface Yes
LCD Controller (available pixels) 480 (60 SEG x 8 COM)
Resets (and delays) Core POR, V
MCLR
Hardware Traps, Configuration Word Mismatch
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 100-Pin TQFP and 121-Pin BGA
Note 1: Peripherals are accessible through remappable pins.
DD POR, VBAT POR,BOR, RESET Instruction,
, WDT; Illegal Opcode, REPEAT Instruction,
66 (62/4)
(1)
(1)
(1)
(1)
(1)
Yes
24
(OST, PLL Lock)
2010-2011 Microchip Technology Inc. DS39996F-page 15
PIC24FJ128GA310 FAMILY
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
EDS and
Stac k
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
LVD & BOR
(2)
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulators
Vol tage
VCAP
PORTA
(1)
PORTC
(1)
(12 I/O)
(8 I/O)
PORTB
(16 I/O)
Note 1:
Not all I/O pins or features are i mplemented on all device pinout configurations. See Ta b l e 1- 4 for specific implementations by pin count
.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
3:
These peripheral I/Os are only accessible through remappable pins.
PORTD
(1)
(16 I/O)
Comparators
(3)
Timer2/3
(3)
Timer1
RTCC
IC
A/D
12-Bit
OC/PWM
SPI
I2C
Timer4/5
(3)
™
EPMP/PSP
1-7
(3)
ICNs
(1)
UART
REFO
PORTE
(1)
PORTG
(1)
(10 I/O)
(12 I/O)
PORTF
(1)
(10 I/O)
1/2
(3)
1/2
1/2/3/4
(3)
1-7
(3)
CTMU
Digital
LCD
Driver
Space
Program Memory/
Modulator
DMA
Controller
Data
DMA
Data Bus
16
Tab l e D a ta
Access Control
VBAT
FIGURE 1-1: PIC24FJ128GA310 FAMILY GENERAL BLOCK DIAGRAM
PIC24FJDS39996F-page 16 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
T ABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS
Pin
Function
AN0 16 20 25 K2 I ANA A/D Analog Inputs.
AN1 151924K1 IANA
AN1- 15 19 24 K1 I ANA
AN2 14 18 23 J2 I ANA A/D Analog Inputs.
AN3 131722J1 IANA
AN4 121621H2 IANA
AN5 11 15 20 H1 I ANA
AN6 172126L1 IANA
AN7 182227J3 IANA
AN8 212732K4 IANA
AN9 222833L4 IANA
AN10 23 29 34 L5 I ANA
AN11 24 30 35 J5 I ANA
AN12 27 33 41 J7 I ANA
AN13 28 34 42 L7 I ANA
AN14 29 35 43 K7 I ANA
AN15 30 36 44 L8 I ANA
AN16 — — 9 E1 I ANA
AN17 — — 10 E3 I ANA
AN18 — — 11 F4 I ANA
AN19 — — 12 F2 I ANA
AN20 — — 14 F3 I ANA
AN21 — — 19 G2 I ANA
AN22 — — 92 B5 I ANA
AN23 — — 91 C5 I ANA
DD 19 25 30 J4 P — Positive Supply for Analog modules.
AV
SS 20 26 31 L3 P — Ground Reference for Analog modules.
AV
C1INA 11 15 20 H1 I ANA Comparator 1 Input A.
C1INB 12 16 21 H2 I ANA Comparator 1 Input B.
C1INC 5 7 11 F4 I ANA Comparator 1 Input C.
C1IND 4 6 10 E3 I ANA Comparator 1 Input D.
C2INA 13 17 22 J1 I ANA Comparator 2 Input A.
C2INB 14 18 23 J2 I ANA Comparator 2 Input B.
C2INC 8 10 14 F3 I ANA Comparator 2 Input C.
C2IND 6 8 12 F2 I ANA Comparator 2 Input D.
C3INA 55 69 84 C7 I ANA Comparator 3 Input A.
C3INB 54 68 83 D7 I ANA Comparator 3 Input B.
C3INC 45 57 71 C11 I ANA Comparator 3 Input C.
C3IND 44 56 70 D11 I ANA Comparator 3 Input D.
CLKI 39 49 63 F9 I ANA Main Clock Input Connection.
CLKO 40 50 64 F11 O — System Clock Output.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
2010-2011 Microchip Technology Inc. DS39996F-page 17
PIC24FJ128GA310 FAMILY
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
CN2 16 20 25 K2 I ST Interrupt-on-Change Inputs.
CN3 15 19 24 K1 I ST
CN4 14 18 23 J2 I ST
CN5 13 17 22 J1 I ST
CN6 12 16 21 H2 I ST
CN7 11 15 20 H1 I ST
CN8 4 6 10 E3 I ST
CN9 5 7 11 F4 I ST
CN10 6 8 12 F2 I ST
CN11 8 10 14 F3 I ST
CN12 303644L8 IST
CN13 526681C8 I ST
CN14 536782B8 IST
CN15 546883D7 I ST
CN16 556984C7 I ST
CN17 313949L10IST
CN18 324050L11I ST
CN19 — 65 80 D8 I ST
CN20 — 37 47 L9 I ST
CN21 — 38 48 K9 I ST
CN22 405064F11I ST
CN23 394963F9 I ST
CN24 172126L1 IST
CN25 182227J3 IST
CN26 212732K4 IST
CN27 222833L4 IST
CN28 232934L5 IST
CN29 243035J5 IST
CN30 273341J7 IST
CN31 283442L7 IST
CN32 293543K7 IST
CN33 — — 17 G3 I ST
CN34 — — 38 J6 I ST
CN35 — — 58 H11 I ST
CN36 — — 59 G10 I ST
CN37 — — 60 G11 I ST
CN38 — — 61 G9 I ST
CN39 — — 91 C5 I ST
CN40 — — 92 B5 I ST
CN41 — 23 28 L2 I ST
CN42 — 24 29 K3 I ST
CN43 — 52 66 E11 I ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
PIC24FJDS39996F-page 18 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
CN44 — 53 67 E8 I ST Interrupt-on-Change Inputs.
CN45 — 4 6 D1 I ST
CN46 — — 7 E4 I ST
CN47 — 5 8 E2 I ST
CN48 — — 9 E1 I ST
CN49 465872D9 I ST
CN50 496176A11IST
CN51 506277A10IST
CN52 516378B9 IST
CN53 425468E9 IST
CN54 435569E10IST
CN55 445670D11IST
CN56 455771C11IST
CN57 — 64 79 A9 I ST
CN58 607693A4 IST
CN59 617794B4 IST
CN60 627898119I ST
CN61 637999A2 IST
CN62 64 80 100 A1 I ST
CN63 1 1 3 D3 I ST
CN64 2 2 4 C1 I ST
CN65 3 3 5 D2 I ST
CN66 — 13 18 G1 I ST
CN67 — 14 19 G2 I ST
CN68 587287B6 IST
CN69 597388A6 IST
CN70 344252K11IST
CN71 334151K10IST
CN72 374757H10IST
CN73 364656J11IST
CN74 — 43 53 J10 I ST
CN75 — — 40 K6 I ST
CN76 — — 39 L6 I ST
CN77 — 75 90 A5 I ST
CN78 — 74 89 E6 I ST
CN79 — — 96 C3 I ST
CN80 — — 97 A3 I ST
CN81 — — 95 C4 I ST
CN82 — — 1 B2 I ST
CN83 — 44 54 H8 I ST
CN84 354555H9 I ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
2010-2011 Microchip Technology Inc. DS39996F-page 19
PIC24FJ128GA310 FAMILY
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
COM0 63 79 99 A2 O — LCD Driver Common Outputs.
COM1 62 78 98 B3 O —
COM2 61 77 94 B4 O —
COM3 60 76 93 A4 O —
COM4 59 73 88 A6 O —
COM5 23 29 34 L5 O —
COM6 22 28 33 L4 O —
COM7 21 27 32 K4 O —
CS1 45 57 71 C11 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe (shared
CS2 44 56 70 D11 O — Parallel Master Port Chip Select 2 Strobe (shared
CTCMP 14 18 23 J2 I ANA CTMU Comparator 2 Input (Pulse mode).
CTED0 — — 17 G3 I ANA CTMU External Edge Inputs.
CTED1 283442L7 IANA
CTED2 273341J7 IANA
CTED3 — — 1 B2 I ANA
CTED4 1 1 3 D3 I ANA
CTED5 293543K7 IANA
CTED6 303644L8 IANA
CTED7 — — 40 47 I ANA
CTED8 64 80 100 A1 I ANA
CTED9 637999A2 IANA
CTED10 — — 97 A3 I ANA
CTED11 — — 95 C4 I ANA
CTED12 15 19 24 K1 I ANA
CTED13 14 18 23 J2 I ANA
CTPLS 29 35 43 K7 O — CTMU Pulse Output.
REF 23 29 34 L5 O — Comparator Voltage Reference Output.
CV
CV
REF+ 16 20 25 K2 I ANA Comparator/A/D Reference Voltage (low) Input.
REF- 15 19 24 K1 I ANA Comparator/A/D Reference Voltage (high) Input.
CV
INT0 35 45 55 H9 I ST External Interrupt Input 0.
LCDBIAS0 3 3 5 D2 I ANA Bias Inputs for LCD Driver Charge Pump.
LCDBIAS1 2 2 4 C1 I ANA
LCDBIAS2 1 1 3 D3 I ANA
LCDBIAS3 17 21 26 L1 I ANA
LVDIN 64 80 100 A1 I ANA Low-Voltage Detect Input.
MCLR
OSCI 39 49 63 F9 I ANA Main Oscillator Input Connection.
OSCO 40 50 64 F11 O — Main Oscillator Output Connection.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
7 9 13 F1 I ST Master Clear (device Reset) Input. This line is
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
with PMA14)
with PMA15)
brought low to cause a Reset.
PIC24FJDS39996F-page 20 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
T ABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
PGEC1 15 19 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming
PGED1 16 20 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
PGEC2 17 21 26 L1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
PGED2 18 22 27 J3 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
PGEC3 11 15 20 H1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
PGED3 12 16 21 H2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
PMA0 30 36 44 L8 I/O ST Parallel Master Port Address Bit 0 Input (Buffered
PMA1 29 35 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered
PMA2 8 10 14 F3 O — Parallel Master Port Address (bits<22:2>).
PMA3 6 8 12 F2 O —
PMA4 5 7 11 F4 O —
PMA5 4 6 10 E3 O —
PMA6 16 24 29 K3 O —
PMA7 22 23 28 L2 O —
PMA8 32 40 50 L11 O —
PMA9 31 39 49 L10 O —
PMA10 283442L7O—
PMA11 27 33 41 J7 O —
PMA12 24 30 35 J5 O —
PMA13 232934L5O—
PMA14 45 57 71 C11 O —
PMA15 44 56 70 D11 O —
PMA16 — — 95 C4 O —
PMA17 — — 92 B5 O —
PMA18 — — 40 K6 O —
PMA19 — 14 19 G2 O —
PMA20 — — 59 G10 O —
PMA21 — — 60 G11 O —
PMA22 — 52 66 E11 O —
PMACK1 50 62 77 A10 I ST/TTL Parallel Master Port Acknowledge Input 1.
PMACK2 43 55 69 E10 I ST/TTL Parallel Master Port Acknowledge Input 2.
PMBE0 51 63 78 B9 O — Parallel Master Port Byte Enable 0 Strobe.
PMBE1 — 53 67 E8 O — Parallel Master Port Byte Enable 1 Strobe.
PMCS1 — 13 18 G1 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe.
PMCS2 — — 9 E1 O — Parallel Master Port Chip Select 2 Strobe.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
Clock.
Data.
Clock.
Data.
Clock.
Data.
Slave modes) and Output (Master modes).
Slave modes) and Output (Master modes).
2010-2011 Microchip Technology Inc. DS39996F-page 21
PIC24FJ128GA310 FAMILY
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
PMD0 60 76 93 A4 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master
PMD1 61 77 94 B4 I/O ST/TTL
PMD2 62 78 98 B3 I/O ST/TTL
PMD3 63 79 99 A2 I/O ST/TTL
PMD4 64 80 100 A1 I/O ST/TTL
PMD5 1 1 3 D3 I/O ST/TTL
PMD6 2 2 4 C1 I/O ST/TTL
PMD7 3 3 5 D2 I/O ST/TTL
PMD8 — 75 90 A5 I/O ST/TTL
PMD9 — 74 89 E6 I/O ST/TTL
PMD10 — 73 88 A6 I/O ST/TTL
PMD11 — 72 87 B6 I/O ST/TTL
PMD12 — 64 79 A9 I/O ST/TTL
PMD13 — 65 80 D8 I/O ST/TTL
PMD14 — 68 83 D7 I/O ST/TTL
PMD15 — 69 84 C7 I/O ST/TTL
PMRD 53 67 82 B8 O — Parallel Master Port Read Strobe.
PMWR 52 66 81 C8 O — Parallel Master Port Write Strobe.
RA0 — — 17 G3 I/O ST PORTA Digital I/O.
RA1 — — 38 J6 I/O ST
RA2 — — 58 H11 I/O ST
RA3 — — 59 G10 I/O ST
RA4 — — 60 G11 I/O ST
RA5 — — 61 G9 I/O ST
RA6 — — 91 C5 I/O ST
RA7 — — 92 B5 I/O ST
RA9 — 23 28 L2 I/O ST
RA10 — 24 29 K3 I/O ST
RA14 — 52 66 E11 I/O ST
RA15 — 53 67 E8 I/O ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
mode) or Address/Data (Multiplexed Master modes).
PIC24FJDS39996F-page 22 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
T ABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
RB0 16 20 25 K2 I/O ST PORTB Digital I/O.
RB1 151924K1I/OST
RB2 141823J2I/OST
RB3 131722J1I/OST
RB4 121621H2I/OST
RB5 11 15 20 H1 I/O ST
RB6 172126L1I/OST
RB7 182227J3I/OST
RB8 212732K4I/OST
RB9 222833L4I/OST
RB10 23 29 34 L5 I/O ST
RB11 24 30 35 J5 I/O ST
RB12 27 33 41 J7 I/O ST
RB13 28 34 42 L7 I/O ST
RB14 29 35 43 K7 I/O ST
RB15 30 36 44 L8 I/O ST
RC1 — 4 6 D1 I/O ST PORTC Digital I/O.
RC2 — — 7 E4 I/O ST
RC3 — 5 8 E2 I/O ST
RC4 — — 9 E1 I/O ST
RC12 394963F9I/OST
RC13 475973C10IST
RC14 486074B11IST
RC15 405064F11I/OST
RD0 46 58 72 D9 I/O ST PORTD Digital I/O.
RD1 49 61 76 A11 I/O ST
RD2 50 62 77 A10 I/O ST
RD3 51 63 78 B9 I/O ST
RD4 52 66 81 C8 I/O ST
RD5 53 67 82 B8 I/O ST
RD6 54 68 83 D7 I/O ST
RD7 55 69 84 C7 I/O ST
RD8 42 54 68 E9 I/O ST
RD9 43 55 69 E10 I/O ST
RD10 445670D11I/OST
RD11 455771C11I/OST
RD12 — 64 79 A9 I/O ST
RD13 — 65 80 D8 I/O ST
RD14 — 37 47 L9 I/O ST
RD15 — 38 48 K9 I/O ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
2010-2011 Microchip Technology Inc. DS39996F-page 23
PIC24FJ128GA310 FAMILY
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
RE0 60 76 93 A4 I/O ST PORTE Digital I/O.
RE1 617794B4I/OST
RE2 627898B3I/OST
RE3 637999A2I/OST
RE4 64 80 100 A1 I/O ST
RE5 1 1 3 D3 I/O ST
RE6 2 2 4 C1 I/O ST
RE7 3 3 5 D2 I/O ST
RE8 — 13 18 G1 I/O ST
RE9 — 14 19 G2 I/O ST
REFO 30 36 44 L8 O — Reference Clock Output.
RF0 587287B6I/OST
RF1 597388A6I/OST
RF2 344252K11I/OST
RF3 334151K10I/OST
RF4 313949L10I/OST
RF5 324050L11I/OST
RF6 354555H9I/OST
RF7 — 44 54 H8 I/O ST
RF8 — 43 53 J10 I/O ST
RF12 — — 40 K6 I/O ST PORTG Digital I/O.
RF13 — — 39 L6 I/O ST
RG0 — 75 90 A5 I/O ST
RG1 — 74 89 E6 I/O ST
RG2 374757H10I/OST
RG3 364656J11I/OST
RG6 4 6 10 E3 I/O ST
RG7 5 7 11 F4 I/O ST
RG8 6 8 12 F2 I/O ST
RG9 8 10 14 F3 I/O ST
RG12 — — 96 C3 I/O ST
RG13 — — 97 A3 I/O ST
RG14 — — 95 C4 I/O ST
RG15 — — 1 B2 I/O ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
PORTF Digital I/O.
PIC24FJDS39996F-page 24 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
T ABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
RP0 16 20 25 K2 I/O ST Remappable Peripheral (input or output).
RP1 151924K1I/OST
RP2 425468E9I/OST
RP3 445670D11I/OST
RP4 435569E10I/OST
RP5 — 38 48 K9 I/O ST
RP6 172126L1I/OST
RP7 182227J3I/OST
RP8 212732K4I/OST
RP9 222833L4I/OST
RP10 31 39 49 L10 I/O ST
RP11 46 58 72 D9 I/O ST
RP12 45 57 71 C11 I/O ST
RP13 14 18 23 J2 I/O ST
RP14 29 35 43 K7 I/O ST
RP15 — 43 53 J10 I/O ST
RP16 33 41 51 K10 I/O ST
RP17 32 40 50 L11 I/O ST
RP18 11 15 20 H1 I/O ST
RP19 6 8 12 F2 I/O ST
RP20 53 67 82 B8 I/O ST
RP21 4 6 10 E3 I/O ST
RP22 51 63 78 B9 I/O ST
RP23 50 62 77 A10 I/O ST
RP24 49 61 76 A11 I/O ST
RP25 52 66 81 C8 I/O ST
RP26 5 7 11 F4 I/O ST
RP27 8 10 14 F3 I/O ST
RP28 12 16 21 H2 I/O ST
RP29 30 36 44 L8 I/O ST
RP30 34 42 52 K11 I/O ST
RP31 — — 39 L6 I/O ST
RPI32 — — 40 K6 I ST Remappable Peripheral (input only).
RPI33 — 13 18 G1 I ST
RPI34 — 14 19 G2 I ST
RPI35 — 53 67 E8 I ST
RPI36 — 52 66 E11 I ST
RPI37 486074B11IST
RPI38 — 4 6 D1 I ST
RPI39 — — 7 E4 I ST
RPI40 — 5 8 E2 I ST
RPI41 — — 9 E1 I ST
RPI42 — 64 79 A9 I ST
RPI43 — 37 47 L9 I ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
2010-2011 Microchip Technology Inc. DS39996F-page 25
PIC24FJ128GA310 FAMILY
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
RTCC 42 54 68 E9 O — Real-Time Clock Alarm/Seconds Pulse Output.
SCL1 37 47 57 H10 I/O I
SCL2 32 40 58 H11 I/O I
SCLKI 486074B11
SDA1 36 46 56 J11 I/O I
SDA2 31 39 59 G10 I/O I
SEG0 4 6 10 E3 O — LCD Driver Segment Outputs.
SEG1 8 10 14 F3 O —
SEG2 11 15 20 H1 O —
SEG3 12 16 21 H2 O —
SEG4 13 17 22 J1 O —
SEG5 14 18 23 J2 O —
SEG6 15 19 24 K1 O —
SEG7 16 20 25 K2 O —
SEG8 29 35 43 K7 O —
SEG9 30 36 44 L8 O —
SEG10 313949L10O—
SEG11 324050L11O—
SEG12 334151K10O—
SEG13 425468E9O—
SEG14 435569E10O—
SEG15 445670D11O—
SEG16 455771C11O—
SEG17 465872D9O—
SEG18 273341J7O—
SEG19 283442L7O—
SEG20 496176A11O—
SEG21 506277A10O—
SEG22 516378B9O—
SEG23 526681C8O—
SEG24 536782B8O—
SEG25 546883D7O—
SEG26 556984C7O—
SEG27 587287B6O—
SEG28 374757H10O—
SEG29 232934L5O—
SEG30 222833L4O—
SEG31 212732K4O—
SEG32 — 4 6 D1 O —
SEG33 — 5 8 E2 O —
SEG34 — 13 18 G1 O —
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
2
C I2C1 Synchronous Serial Clock Input/Output.
2
C I2C2 Synchronous Serial Clock Input/Output.
2
C I2C1 Data Input/Output.
2
C I2C2 Data Input/Output.
Description
PIC24FJDS39996F-page 26 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
T ABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
SEG35 — 14 19 G2 O — LCD Driver Segment Outputs.
SEG36 — 23 28 L2 O —
SEG37 — 24 29 K3 O —
SEG38 — 37 47 L9 O —
SEG39 — 38 48 K9 O —
SEG40 — 42 52 K11 O —
SEG41 — 43 53 J10 O —
SEG42 — 52 66 E11 O —
SEG43 — 53 67 E8 O —
SEG44 — 64 79 A9 O —
SEG45 — 65 80 D8 O —
SEG46 — 74 89 E6 O —
SEG47 364656J11O—
SEG48 597388A6O—
SEG49 — — 17G3O —
SEG50 — 75 90 A5 O —
SEG51 — — 1 B2 O —
SEG52 — — 7 E4 O —
SEG53 — — 9 E1 O —
SEG54 — — 39 L6 O —
SEG55 — — 40 K6 O —
SEG56 — — 58 H11 O —
SEG57 — — 59 G10 O —
SEG58 — — 91C5O—
SEG59 — — 92 B5 O —
SEG60 — — 95C4O—
SEG61 — — 96C3O—
SEG62 — — 97 A3 O —
SEG63 — — 100 A1 O —
SOSCI 47 59 73 C10 I ANA Secondary Oscillator/Timer1 Clock Input.
SOSCO 48 60 74 B11 O ANA Secondary Oscillator/Timer1 Clock Output.
T1CK 22 28 33 L4 I ST Timer1 Clock.
TCK 27 33 38 J6 I ST JTAG Test Clock/Programming Clock Input.
TDI 28 34 60 G11 I ST JTAG Test Data/Programming Data Input.
TDO 24 14 61 G9 O — JTAG Test Data Output.
TMS 23 13 17 G3 I ST JTAG Test Mode Select Input.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
Description
2010-2011 Microchip Technology Inc. DS39996F-page 27
PIC24FJ128GA310 FAMILY
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
VBAT 57 71 86 A7 P — Back-up Battery.
CAP 56 70 85 B7 P — External Filter Capacitor Connection (regulator
V
DD 10, 26,
V
LCAP1 5 7 11 F4 I ANA LCD Drive Charge Pump Capacitor Inputs.
V
LCAP26812F2IANA
V
REF+ — 24 29 K3 I ANA Comparator/A/D Reference Voltage (low) Input
V
REF- — 23 28 L2 I ANA Comparator/A/D Reference Voltage (high) Input
V
Vss 9, 25, 41 11, 31, 5115, 36,
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
Pin Number/Grid Locator
64-Pin
TQFP
38
80-Pin
TQFP
12, 32, 482, 16,
100-Pin
TQFP
37, 46,
62
45, 65,
75
121-Pin
BGA
C2, F8,
G5, H6,
K8
B10, F5,
F10, G6,
G7
2
C™ = I2C/SMBus input buffer
I/O
Input
Buffer
P — Positive Supply for Peripheral Digital Logic and I/O
P — Ground Reference for Logic and I/O Pins.
Description
enabled).
Pins.
(default).
(default).
PIC24FJDS39996F-page 28 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
PIC24FJXXXX
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
C1
R1
V
DD
MCLR
VCAP
R2
C7
C2
(2)
C3
(2)
C4
(2)
C5
(2)
C6
(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1: See Section 2.4 “Voltage Regulator Pin
(V
CAP)” for details on selecting the proper
capacitor for Vcap.
2: The example shown is for a PIC24F device
with five V
DD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
(1)
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC24FJ128GA310 family
family of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development.
The following pins must always be connected:
DD and VSS pins
•All V
(see Section 2.2 “Power Supply Pins”)
•All AV
•MCLR
•V
These pins must also be connected if they are being
used in the end application:
• PGECx/PGEDx pins used for In-Circuit Serial
• OSCI and OSCO pins when an external oscillator
Additionally, the following pins may be required:
•V
The minimum mandatory connections are shown in
Figure 2-1.
DD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
CAP pin
(see Section 2.4 “Voltage Regulator Pin (V
CAP)”)
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
source is used
(see Section 2.6 “External Oscillator Pins”)
REF+/VREF- pins used when external voltage
reference for analog modules is implemented
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
2010-2011 Microchip Technology Inc. DS39996F-page 29
PIC24FJ128GA310 FAMILY
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR
pin VIH and VIL specifications are met.
2: R2 470 will limit any current flowing into
MCLR
from the external capacitor, C, in the
event of MCLR
pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin
V
IH and VIL specifications are met.
C1
R2
R1
V
DD
MCLR
PIC24FXXXX
JP
2.2 Power Supply Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as V
SS is required.
AV
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
DD, VSS, AVDD and
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: device Reset, and device programming
and debugging. If programming and debugging are
not required in the end application, a direct
connection to V
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR
levels (V
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
DD may be all that is required. The
pin. Consequently, specific voltage
IH and VIL) and fast signal transitions must
pin during programming and
pin
CONNECTIONS
2.2.2 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS39996F-page 30 2010-2011 Microchip Technology Inc.
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