Datasheet PIC18F87K90 Datasheet

PIC18F87K90 Family

Data Sheet

64/80-Pin, High-Performance

Microcontrollers with LCD Driver and

nanoWatt XLP Technology

 2011 Microchip Technology Inc. DS39957C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-018-9

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS39957C-page 2  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

64/80-Pin, High-Performance Microcontrollers with

LCD Driver and nanoWatt XLP Technology

Low-Power Features:

• Power-Managed modes:

- Run: CPU on, peripherals on

- Idle: CPU off, peripherals on

- Sleep: CPU off, peripherals off

• Two-Speed Oscillator Start-up

• Fail-Safe Clock Monitor

• Power-Saving Peripheral Module Disable (PMD)

• Ultra Low-Power Wake-up

• Fast Wake-up, 2 s Typical

• Low-Power WDT, 300 nA Typical

• Ultra Low 50 nA Input Leakage

• Run mode Currents Down to Very Low 5.5 A, Typical

• Idle mode Currents Down to Very Low 2.2 A, Typical

• Sleep mode Current Down to Very Low 20 nA, Typical

• RTCC Current Down to Very Low 700 nA, Typical

• LCD Current Down to Very Low 300 nA, Typical

LCD Driver and Keypad Features:

• Direct LCD Panel Drive Capability:

- Can drive LCD panel while in Sleep mode

• Up to 48 Segments and 192 Pixels, Software-Selectable

• Programmable LCD Timing module:

- Multiple LCD timing sources available

- Up to four commons: static, 1/2, 1/3 or

1/4 multiplex

- Bias configuration: Static, 1/2 or 1/3

• Low-Power Resistor Bias Network for LCD

Peripheral Highlight s:

• Ten or Eight CCP/ECCP modules:

- Seven Capture/Compare/PWM (CCP) modules

- Three Enhanced Capture/Compare/PWM (ECCP) modules

• Eleven 8/16-Bit Timer/Counter modules:

- Timer0 – 8/16-bit timer/counter with 8-bit programmable prescaler

- Timer1,3,5,7 – 16-bit timer/counter

- Timer2,4,6,8,10,12 – 8-bit timer/counter

• Three Analog Comparators

• Configurable Reference Clock Output

• Hardware Real-Time Clock and Calendar (RTCC) module with Clock, Calendar and Alarm Functions

- Time-out from 0.5s to 1 year

• Charge Time Measurement Unit (CTMU):

- Capacitance measurement for mTouch™

Sensing

- Time measurement with 1 ns typical resolution

• High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC)

• Up to Four External Interrupts

• Two Master Synchronous Serial Port (MSSP) modules:

- 3/4-wire SPI (supports all four SPI modes)

2

C™ Master and Slave mode

-I

Flash

Device

PIC18F65K90 32K 2K 1K 53 132 4/4 5/3 Yes Yes 2 16 3 Y Y

PIC18F66K90 64K 4K 1K 53 132 6/5 7/3 Yes Yes 2 16 3 Y Y

PIC18F67K90 128K 4K 1K 53 132 6/5 7/3 Yes Yes 2 16 3 Y Y

PIC18F85K90 32K 2K 1K 69 192 4/4 5/3 Yes Yes 2 24 3 Y Y

PIC18F86K90 64K 4K 1K 69 192 6/5 7/3 Yes Yes 2 24 3 Y Y

PIC18F87K90 128K 4K 1K 69 192 6/5 7/3 Yes Yes 2 24 3 Y Y

 2011 Microchip Technology Inc. DS39957C-page 3

Program

Memory

(Bytes)

SRAM

Data

Memory

(Bytes)

EEPROM

(Bytes)

I/O

LCD

Pixels

Timers

8/16-Bit

CCP/

ECCP

SPI I

2

C™

EUSART

12-Bit A/D

(Channels)

RTCC

CTMU

Comparators

PIC18F87K90 FAMILY

Special Microcontroller Features:

• Operating Voltage Range: 1.8V to 5.5V

• On-Chip 3.3V Regulator

• Operating Speed up to 64 MHz

• Up to 128 Kbytes On-Chip Flash Program Memory

• Data EEPROM of 1,024 Bytes

• 4K x 8 General Purpose Registers (SRAM)

• 10,000 Erase/Write Cycle Flash Program Memory, Typical

• 1,000,000 Erase/write Cycle Data EEPROM Memory, Typical

• Flash Retention 40 Years, Minimum

• Three Internal Oscillators: LF-INTRC (31 kHz), MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz)

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 4,194s (about 70 minutes)

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug via Two Pins

• Programmable:

-BOR

-LVD

• Two Enhanced Addressable USART modules:

- LIN/J2602 support

- Auto-Baud Detect (ABD)

• 12-Bit A/D Converter with up to 24 Channels:

- Auto-acquisition and Sleep operation

- Differential Input mode of operation

DS39957C-page 4  2011 Microchip Technology Inc.

Pin Diagrams – PIC18F6XK90

64-Pin QFN, TQFP

50 49

RE2/LCDBIAS3/P2B/CCP10

(2)

RE3/COM0/P3C/CCP9

(2)

/REFO

RE4/COM1/P3B/CCP8

RE5/COM2/P1C/CCP7

RE6/COM3/P1B/CCP6

RE7/ECCP2

(1)

/SEG31/P2A

RD0/SEG0/CTPLS

V

DD

VSS

RD1/SEG1/T5CKI/T7G

RD2/SEG2

RD3/SEG3

RD4/SEG4/SDO2

RD5/SEG5/SDI2/SDA2

RD6/SEG6/SCK2/SCL2

RD7/SEG7/SS2

RE1/LCDBIAS2/P2C

RE0/LCDBIAS1/P2D

RG0/ECCP3/P3A

RG1/TX2/CK2/AN19/C3OUT

RG2/RX2/DT2/AN18/C3INA

RG3/CCP4/AN17/P3D/C3INB

MCLR

/RG5

V

SS

VDDCORE/VCAP

RF7/AN5/SS1/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CV

REF/SEG23/C1INB

RF4/AN9/SEG22/C2INA

RF3/AN8/SEG21/C2INB/CTMUI

RF2/AN7/C1OUT/SEG20

RB0/INT0/SEG30/FLTO

RB1/INT1/SEG8

RB2/INT2/SEG9/CTED1

RB3/INT3/SEG10/CTED2/P2A

RB4/KBI0/SEG11

RB5/KBI1/SEG29/T3CKI/T1G

RB6/KBI2/PGC

V

SS

OSC2/CLKO/RA6

OSC1/CLKI/RA7

V

DD

RB7/KBI3/PGD

RC4/SDI1/SDA1/SEG16

RC3/SCK1/SCL1/SEG17

RC2/ECCP1/P1A/SEG13

ENVREG

RF1/AN6/C2OUT/SEG19/CTDIN

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1/SEG18

RA0/AN0/ULPWU

V

SS

VDD

RA4/T0CKI/SEG14

RA5/AN4/T1CKI/SEG15/T3G/HLVDIN

RC1/SOSCI/ECCP2

(1)

/P2A/SEG32

RC0/SOSCO/SCLKI

RC7/RX1/DT1/SEG28

RC6/TX1/CK1/SEG27

RC5/SDO1/SEG12

5453 52 5158 57 56 5560 59

64

63 62 61

Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting.

2: Not available on the PIC18F65K90 and PIC18F85K90.

PIC18F65K90 PIC18F66K90 PIC18F67K90

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 17 18 19 20 21 22 23 24 25263127 28

29 30 32

38

37

36

35

34

33

40

39

48

47

46

45

44

43

42

41

RG0/ECCP3/P3A

RG4/SEG26/RTCC/T7CKI

(2)

/T5G/CCP5/AN16/P1D/C3INC

PIC18F87K90 FAMILY

 2011 Microchip Technology Inc. DS39957C-page 5

PIC18F87K90 FAMILY

80-Pin TQFP

3 4 5 6 7 8

9 10 11 12 13

14 15 16

48 47 46 45 44 43 42 41

40

39

64 63 62 61

21 22 23 24 25 2627 28 29 30 31 32

RE2/LCDBIAS3/P2B/CCP10

(2)

RE3/COM0/P3C/CCP9

(2)(3)

/REFO

RE4/COM1/P3B/CCP8

(3)

RE5/COM2/P1C/CCP7

(3)

RE6/COM3/P1B/CCP6

(3)

RE7/ECCP2

(1)

/P2A/SEG31

RD0/SEG0/CTPLS

V

DD

VSS

RD1/SEG1/T5CKI/T7G

RD2/SEG2

RD3/SEG3

RD4/SEG4/SDO2

RD5/SEG5/SDI2/SDA2

RD6/SEG6/SCK2/SCL2

RD7/SEG7/SS2

RE1/LCDBIAS2/P2C RE0/LCDBIAS1/P2D

RG0/ECCP3/P3A

RG1/TX2/CK2/AN19/C3OUT

RG2/RX2/DT2/AN18/C3INA

RG3/CCP4/AN17/P3D/C3INB

MCLR

/RG5

V

SS

VDDCORE/VCAP

VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 V

DD

ENVREG

RF1/AN6/C2OUT/SEG19/CTDIN

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1/SEG18

RA0/AN0/ULPWU

V

SS

VDD

RJ0

RJ1/SEG33

RH1/SEG46/AN22

RH0/SEG47/AN23

1

2

RH2/SEG45/AN21 RH3/SEG44/AN20

17 18

RH7/SEG43/CCP6

(3)

/P1B/AN15

RH6/SEG42/CCP7

(3)

/P1C/AN14/C1INC

RH5/SEG41/CCP8

(3)

/P3B/AN13/C2IND

RH4/SEG40/CCP9

(2)(3)

/P3C/AN12/C2INC

RJ5/SEG38

RJ4/SEG39

37

RJ7/SEG36 RJ6/SEG37

50 49

RJ2/SEG34 RJ3/SEG35

19 20

3334

35 36 38

58

57 56 55 54 53 52 51

60 59

68 6766 6572 71 70 6974 73

78

77 76 75

79

80

RB0/INT0/SEG30/FLT0 RB1/INT1/SEG8 RB2/INT2/SEG9/CTED1

RB3/INT3/SEG10/CTED2/P2A

RB4/KBI0/SEG11 RB5/KBI1/SEG29/T3CKI/T1G RB6/KBI2/PGC

RB7/KBI3/PGD

RC2/ECCP1/P1A/SEG13

RC5/SDO1/SEG12

RA4/T0CKI/SEG14

RA5/AN4/T1CKI/SEG15/T3G/HLVDIN

RC1/SOSCI/ECCP2

(1)

I/SEG32/P2A

RC0/SOSCO/SCKLI

RC7/RX1/DT1/SEG28

RF7/AN5/SS1/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CV

REF/SEG23/C1INB

RF4/AN9/SEG22/C2INA

RF3/AN8/SEG21/C2INB/CTMUI

RF2/AN7/C1OUT/SEG20

RC4/SDI1/SDA1/SEG16 RC3/SCK1/SCL1/SEG17

PIC18F85K90 PIC18F86K90 PIC18F87K90

RG4/SEG26/RTCC/T7CKI

(2)

/T5G/CCP5/AN16/P1D/C3INC

RC6/TX1/CK1/SEG27

VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 V

DD

RJ7/SEG36 RJ6/SEG37

RJ2/SEG34 RJ3/SEG35 RB0/INT0/SEG30/FLT0 RB1/INT1/SEG8 RB2/INT2/SEG9/CTED1

RB4/KBI0/SEG11

RB6/KBI2/PGC

RB7/KBI3/PGD

RC2/ECCP1/P1A/SEG13

RC5/SDO1/SEG12 RC4/SDI1/SDA1/SEG16 RC3/SCK1/SCL1/SEG17

Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting.

2: Not available on the PIC18F65K90 and PIC18F85K90. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting

Pin Diagrams – PIC18F8XK90

DS39957C-page 6  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for the following devices:

• PIC18F65K90 • PIC18F85K90

• PIC18F66K90 • PIC18F86K90

• PIC18F67K90 • PIC18F87K90

This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with a versatile on-chip LCD driver, while maintaining an extremely competitive price point. These features make the PIC18F87K90 family a logical choice for many high-performance applications where price is a primary consideration.

1.1 Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F87K90 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal RC oscillator, power consumption during code execution can be reduced.

• Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further.

• On-the-Fly Mode Swit ching: The power-managed

modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• nanoWatt XL P: An extra low-power BOR, RTCC

and low-power Watchdog Timer. Also, an ultra low-power regulator for Sleep mode is provided in regulator-enabled modes.

1.1.2 OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F87K90 family offer different oscillator options, allowing users a range of choices in developing application hardware. These include:

• External Resistor/Capacitor (RC); RA6 available

• External Resistor/Capacitor with Clock Out (RCIO)

• Three External Clock modes:

- External Clock (EC); RA6 available

- External Clock with Clock Out (ECIO)

- External Crystal (XT, HS, LP)

• A Phase Lock Loop (PLL) frequency multiplier,

available to the External Oscillator modes which allows clock speeds of up to 64 MHz. PLL can also be used with the internal oscillator.

• An internal oscillator block that provides a 16 MHz clock (±2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature

DD)

and V

- Operates as HF-INTOSC or MF-INTOSC

when block selected for 16 MHz or 500 kHz

- Frees the two oscillator pins for use as

additional general purpose I/O

The internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.

• T wo-S pe ed Start-up: This option allows the

internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

1.1.3 MEMORY OPTIONS

The PIC18F87K90 family provides ample room for application code, from 32 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last up to 10,000 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 40 years.

The Flash program memory is readable and writable. During normal operation, the PIC18F87K90 family also provides plenty of room for dynamic application data with up to 3,828 bytes of data RAM.

1.1.4 EXTENDED INSTRUCTION SET

The PIC18F87K90 family implements the optional extension to the PIC18 instruction set, adding 8 new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as ‘C’.

1.1.5 EASY MIGRATION

Regardless of the memory size, all devices share the same rich set of peripherals (except the 32-Kbyte parts, which have two less CCPs and three less Timers), allowing for a smooth migration path as applications grow and evolve.

The consistent pinout scheme, used throughout the entire family, also aids in migrating to the next larger device. This is true when moving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices.

 2011 Microchip Technology Inc. DS39957C-page 9

PIC18F87K90 FAMILY

The PIC18F87K90 family is also largely pin-compatible with other PIC18 families, such as the PIC18F8720, PIC18F8722, PIC18F85J11, PIC18F8490, PIC18F85J90, PIC18F87J90 and PIC18F87J93 families of microcontrollers with LCD drivers. This allows a new dimension to the evolution of applications, allowing developers to select different price points within Microchip’s PIC18 portfolio, while maintaining a similar feature set.

1.2 LCD Driver

The on-chip LCD driver includes many features that ease the integration of displays in low-power applications. These include an integrated internal resistor ladder, so bias voltages can be generated internally. This enables software-controlled contrast control and eliminates the need for external bias voltage resistors.

1.3 Other Special Features

• Communications: The PIC18F87K90 family

incorporates a range of serial communication peripherals including two Enhanced USART, that support LIN/J2602, and two Master SSP modules capable of both SPI and I modes of operation.

• CCP Modules: PIC18F87K90 family devices

incorporate up to seven or five Capture/ Compare/PWM (CCP) modules. Up to six different time bases can be used to perform several different operations at once.

• ECCP Modules: The PIC18F87K90 family has

three Enhanced CCP (ECCP) modules to maximize flexibility in control applications:

- Up to eight different time bases for performing several different operations at once

- Up to four PWM outputs for each module, for a total of 12 PWMs

- Other beneficial features, such as polarity selection, programmable dead time, auto-shutdown and restart, and Half-Bridge and Full-Bridge Output modes

• 12-Bit A/D Converter: The PIC18F87K90 family

has differential ADC. It incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and thus, reducing code overhead.

• Charge Time Me as ure ment Unit (CTMU): The

CTMU is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation.

Together with other on-chip analog modules, the CTMU can precisely measure time, measure capacitance or relative changes in capacitance, or generate output pulses that are independent of the system clock.

2

C™ (Master and Slave)

• LP Watchdog Timer (WDT): This enhanced

version incorporates a 22-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See

Section 31.0 “Electrical Characteristics” for

time-out periods.

• Real-Time Clock and Calendar Module (RTCC):

The RTCC module is intended for applications requiring that accurate time be maintained for extended periods of time with minimum to no intervention from the CPU.

The module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099.

1.4 Details on Individual Family Members

Devices in the PIC18F87K90 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in these ways:

• Flash Program Memory:

- PIC18FX5K90 (PIC18F65K90 and PIC18F85K90) – 32 Kbytes

- PIC18FX6K90 (PIC18F66K90 and PIC18F86K90) – 64 Kbytes

- PIC18FX7K90 (PIC18F67K90 and PIC18F87K90) – 128 Kbytes

• Data RAM:

- All devices except PIC18FX5K90 – 4 Kbytes

- PIC18FX5K90 – 2 Kbytes

• I/O Ports:

- PIC18F6XK90 (64-pin devices) – Seven bidirectional ports

- PIC18F8XK90 (80-pin devices) – Nine bidirectional ports

• LCD Pixels:

- PIC18F6XK90 – 132 pixels (33 SEGs x 4 COMs)

- PIC18F8XK90 – 192 pixels (48 SEGs x 4 COMs)

• CCP Module:

- All devices except PIC18FX5K90 have seven CCP modules, PIC18FX5K90 has only five CCP modules

•Timers:

- All devices except 18FX5K90 have six 8-bit timers and five 16-bit timers, PIC18FX5K90 has only four 8-bit timers and four 16-bit timers.

• A/D Channels:

- All PIC18F8XK90 devices have 24 A/D channels, all PIC18F6XK90 devices have 16 A/D channels

All other features for devices in this family are identical. These are summarized in Ta bl e 1 -1 and Tab le 1- 2.

The pinouts for all devices are listed in Tab l e 1 -3 and

Table 1-4.

DS39957C-page 10  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XK90 (64-PIN DEVICES)

Features PIC18F65K90 PIC18F66K90 PIC18F67K90

Operating Frequency DC – 64 MHz

Program Memory (Bytes) 32K 64K 128K

Program Memory (Instructions) 16,384 32,768 65,536

Data Memory (Bytes) 2K 4K 4K

Interrupt Sources 42 48

I/O Ports Ports A, B, C, D, E, F, G

LCD Driver (available pixels to drive) 132 (33 SEGs x 4 COMs)

Timers 8 11

Comparators 3

CTMU Yes

RTCC Yes

Capture/Compare/PWM (CCP) Modules 5 7 7

Enhanced CCP (ECCP) Modules 3

Serial Communications Two MSSP and two Enhanced USART (EUSART)

12-Bit Analog-to-Digital Module 16 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR

(PWRT, OST)

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 64-Pin QFN, 64-Pin TQFP

, WDT

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F8XK90 (80-PIN DEVICES)

Features PIC18F85K90 PIC18F86K90 PIC18F87K90

Operating Frequency DC – 64 MHz

Program Memory (Bytes) 32K 64K 128K

Program Memory (Instructions) 16,384 32,768 65,536

Data Memory (Bytes) 2K 4K 4K

Interrupt Sources 42 48

I/O Ports Ports A, B, C, D, E, F, G, H, J

LCD Driver (available pixels to drive) 192 (48 SEGs x 4 COMs)

Timers 8 11

Comparators 3

CTMU Yes

RTCC Yes

Capture/Compare/PWM (CCP) Modules 5 7 7

Enhanced CCP (ECCP) Modules 3

Serial Communications Two MSSP and two Enhanced USART (EUSART)

12-Bit Analog-to-Digital Module 24 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR

(PWRT, OST)

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 80-Pin TQFP

, WDT

 2011 Microchip Technology Inc. DS39957C-page 11

PIC18F87K90 FAMILY

Instruction

Decode and

Control

PORTA

Data Latch

Data Memory

(2/4 Kbytes)

Address Latch

Data Address<12>

12

Access

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

ALU<8>

Address Latch

Program Memory

Data Latch

20

8

Table Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

Note 1: See Table 1-3 for I/O port pin descriptions.

2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator

Configurations”.

3: Unimplemented in the PIC18F65K90.

EUSART1

Comparator

MSSP1/2

3/5/7

(3)

2/4/6/8/10

(3)

/12

(3)

CTMUTimer1

ADC

12-Bit

W

Instruction Bus <16>

STKPTR

Bank

8

State Machine Control Signals

Decode

8

EUSART2

ROM Latch

LCD

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1,2)

RC0:RC7

(1)

RD0:RD7

(1)

RF1:RF7

(1)

RG0:RG5

(1)

PORTB

RB0:RB7

(1)

OSC1/CLKI

OSC2/CLKO

V

DD,

Timing

Generation

V

SS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

BOR and

LVD

Precision

Reference

Band Gap

INTRC

Oscillator

Regulator

Voltage

VDDCORE/VCAP

ENVREG

Driver

16 MHz

Oscillator

RE0:RE7

(1)

Timer0

4/5/6/7/8/9

(3)

/10

(3)

RTCC

Timer

1/2/3

CCP

ECCP

1/2/3

FIGURE 1-1: PIC18F6XK90 (64-PIN) BLOCK DIAGRAM

DS39957C-page 12  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

Instruction

Decode and

Control

Data Latch

Address Latch

Data Address<12>

12

Access

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

ALU<8>

Address Latch

Program Memory

Data Latch

20

8

Table Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

W

Instruction Bus <16>

STKPTR

Bank

8

State Machine Control Signals

Decode

8

ROM Latch

OSC1/CLKI

OSC2/CLKO

V

DD,VSS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Precision

Reference

Band Gap

Regulator

Voltage

VDDCORE/VCAP

ENVREG

PORTA

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1,2)

RC0:RC7

(1)

RD0:RD7

(1)

RF1:RF7

(1)

RG0:RG5

(1)

PORTB

RB0:RB7

(1)

PORTH

RH0:RH7

(1)

PORTJ

RJ0:RJ7

(1)

Note 1: See Table 1-3 for I/O port pin descriptions.

2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for

more information.

3: Unimplemented in the PIC18F85K90.

Timing

Generation

INTRC

Oscillator

16 MHz

Oscillator

RE0:RE7

BOR and

LVD

Data Memory

(2/4 Kbytes)

EUSART1

Comparator

MSSP1/2

3/5/7

(3)

2/4/6/8/10

(3)

/12

(3)

CTMUTimer1

ADC

12-Bit

EUSART2

LCD

Driver

Timer0

4/5/6/7/8/9

(3)

/10

(3)

RTCC

Timer

1/2/3

CCP

ECCP

1/2/3

FIGURE 1-2: PIC18F8XK90 (80-PIN) BLOCK DIAGRAM

 2011 Microchip Technology Inc. DS39957C-page 13

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

QFN/TQFP

Type

Buffer

Type

Description

/RG5

MCLR

RG5

OSC1/CLKI/RA7

OSC1 CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

7

39

40

I/O

O

I/O

I

STSTMaster Clear (input) or programming voltage (input).

This pin is an active-low Reset to the device.

I

CMOS

I

CMOS

TTL

—

TTL

General purpose, input only pin.

Oscillator crystal or external clock input.

Oscillator crystal input. External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

DD)

DS39957C-page 14  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0/ULPWU

RA0 AN0 ULPWU

RA1/AN1/SEG18

RA1 AN1 SEG18

RA2/AN2/V

RA2 AN2 V

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI/SEG14

RA4 T0CKI SEG14

RA5/AN4/SEG15/T1CKI/ T3G/HLVDIN

RA5 AN4 SEG15 T1CKI T3G HLVDIN

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

REF-

REF+

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

I

C™ = I2C/SMBus

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

Pin Number

QFN/TQFP

24

23

22

21

28

27

Type

I/O

I I

I/O

I

O

I/O

I I

I/O

I I

I/O

I

O

I/O

I

O

I I I

Buffer

Type

TTL Analog Analog

ST ST

Analog

TTL Analog Analog

ST ST

Analog

Description

PORTA is a bidirectional I/O port.

Digital I/O. Analog Input 0. Ultra low-power wake-up input.

Digital I/O. Analog Input 1. SEG18 output for LCD.

Digital I/O. Analog Input 2. A/D reference voltage (low) input.

Digital I/O. Analog Input 3. A/D reference voltage (high) input.

Digital I/O. Timer0 external clock input. SEG14 output for LCD.

Digital I/O. Analog Input 4. SEG15 output for LCD. Timer1 clock input. Timer3 external clock gate input. High/Low-Voltage Detect (HLVD) input.

DD)

 2011 Microchip Technology Inc. DS39957C-page 15

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/SEG30/FLTO

RB0 INT0 SEG30 FLTO

RB1/INT1/SEG8

RB1 INT1 SEG8

RB2/INT2/SEG9/CTED1

RB2 INT2 CTED1 SEG9

RB3/INT3/SEG10/CTED2/ ECCP2/P2A

RB3 INT3 SEG10 CTED2 ECCP2 P2A

RB4/KBI0/SEG11

RB4 KBI0 SEG11

RB5/KBI1/SEG29/T3CKI/ T1G

RB5 KBI1 SEG29 T3CKI T1G

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

Pin Number

QFN/TQFP

48

47

46

45

44

43

42

37

Type

I/O

I

O

I

I/O

I

O

I/O

I I

O

I/O

I

O

I

I/O

O

I/O

I

O

I/O

I

O

I I

I/O

I

I/O

I

I/O

Buffer

Type

TTL

ST

Analog

ST

TTL

ST

Analog

TTL

ST ST

Analog

TTL

ST

Analog

ST ST

—

TTL TTL

Analog

TTL TTL

Analog

ST ST

TTL TTL

ST

TTL TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External Interrupt 0. SEG30 output for LCD. Enhanced PWM Fault input for ECCP1/2/3.

Digital I/O. External Interrupt 1. SEG8 output for LCD.

Digital I/O. External Interrupt 2. CTMU Edge 1 input. SEG9 output for LCD.

Digital I/O. External Interrupt 3. SEG10 output for LCD. CTMU Edge 2 input. Capture 2 input/Compare 2 output/PWM2. Enhanced PWM2 Output A.

Digital I/O. Interrupt-on-change pin. SEG11 output for LCD.

Digital I/O. Interrupt-on-change pin. SEG29 output for LCD. Timer3 clock input. Timer1 external clock gate input.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

DD)

DS39957C-page 16  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/SOSCO/SCLKI

RC0 SOSCO SCLKI

RC1/SOSCI/ECCP2/P2A/ SEG32

RC1 SOSCI ECCP2 P2A SEG32

RC2/ECCP1/P1A/SEG13

RC2 ECCP1 P1A SEG13

RC3/SCK1/SCL1/SEG17

RC3 SCK1 SCL1 SEG17

RC4/SDI1/SDA1/SEG16

RC4 SDI1 SDA1 SEG16

RC5/SDO1/SEG12

RC5 SDO1 SEG12

RC6/TX1/CK1/SEG27

RC6 TX1 CK1 SEG27

RC7/RX1/DT1/SEG28

RC7 RX1 DT1 SEG28

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

(1)

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

Pin Number

QFN/TQFP

30

29

33

34

35

36

31

32

Type

I/O

O

I

I/O

I

I/O

O O

I/O I/O

O O

I/O I/O I/O

O

I/O

I

I/O

O

I/O

O O

I/O

O

I/O

O

I/O

I

I/O

O

Buffer

Type

ST

—

ST

CMOS

ST

—

Analog

ST ST

—

Analog

ST ST

2

C

I

Analog

ST ST

2

C

I

Analog

ST

—

Analog

ST

—

ST

Analog

ST ST ST

Analog

Description

PORTC is a bidirectional I/O port.

Digital I/O. SOSC oscillator output. Digital SOSC input.

Digital I/O. SOSC oscillator input. Capture 2 input/Compare 2 output/PWM2 output. Enhanced PWM2 Output A. SEG32 output for LCD.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Enhanced PWM1 Output A. SEG13 output for LCD.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C™ mode. SEG17 output for LCD.

Digital I/O. SPI data in. I2C data I/O. SEG16 output for LCD.

Digital I/O. SPI data out. SEG12 output for LCD.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX1/DT1). SEG27 output for LCD.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX1/CK1). SEG28 output for LCD.

DD)

 2011 Microchip Technology Inc. DS39957C-page 17

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/SEG0/CTPLS

RD0 SEG0 CTPLS

RD1/SEG1/T5CKI/T7G

RD1 SEG1 T5CKI T7G

RD2/SEG2

RD2 SEG2

RD3/SEG3

RD3 SEG3

RD4/SEG4/SDO2

RD4 SEG4 SDO2

RD5/SEG5/SDI2/SDA2

RD5 SEG5 SDI2 SDA2

RD6/SEG6/SCK2/SCL2

RD6 SEG6 SCK2 SCL2

RD7/SEG7/SS2

RD7 SEG7 SS2

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

I

C™ = I2C/SMBus

Pin Number

QFN/TQFP

58

55

54

53

52

51

50

49

Buffer

Type

I/O

O

Analog

O

I/O

O

Analog I I

I/OOST

Analog

I/OOST

Analog

I/O

O

Analog

O

I/O

O

Analog I

I/O

O

Analog

I/O I/O

I/O

O

Analog I

PORTD is a bidirectional I/O port.

ST

—

ST

ST ST

ST

—

ST

2

I

ST

2

I

C

ST

TTL

C

Digital I/O. SEG0 output for LCD. CTMU pulse generator output.

Digital I/O. SEG1 output for LCD. Timer5 clock input. Timer7 external clock gate input.

Digital I/O. SEG2 output for LCD.

Digital I/O. SEG3 output for LCD.

Digital I/O. SEG4 output for LCD. SPI data out.

Digital I/O. SEG5 output for LCD. SPI data in.

2

C™ data I/O.

I

Digital I/O. SEG6 output for LCD. Synchronous serial clock. Synchronous serial clock for I2C mode.

Digital I/O. SEG7 output for LCD. SPI slave select input.

Description

DD)

DS39957C-page 18  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/LCDBIAS1/P2D

RE0 LCDBIAS1 P2D

RE1/LCDBIAS2/P2C

RE1 LCDBIAS2 P2C

RE2/LCDBIAS3/P2B/ CCP10

RE2 LCDBIAS3 P2B

(3)

CCP10

RE3/COM0/P3C/CCP9/ REFO

RE3 COM0 P3C CCP9 REFO

RE4/COM1/P3B/CCP8

RE4 COM1 P3B CCP8

RE5/COM2/P1C/CCP7

RE5 COM2 P1C CCP7

RE6/COM3/P1B/CCP6

RE6 COM3 P1B CCP6

RE7/ECCP2/SEG31/P2A

RE7 ECCP2 SEG31 P2A

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

(3)

(2)

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

Pin Number

QFN/TQFP

2

1

64

63

62

61

60

59

Type

I/O

I

O

I/O

I

O

I/O

I

O

I/O

O O

I/O

O

I/O

O O

I/O

O O

I/O

O O

I/O

I/O I/O

O O

Buffer

Type

ST

Analog

—

ST

Analog

—

ST

Analog

—

S/T

ST

Analog

—

S/T

—

ST

Analog

—

S/T

ST

Analog

—

S/T

ST

Analog

—

S/T

ST ST

Analog

—

Description

PORTE is a bidirectional I/O port.

Digital I/O. BIAS1 input for LCD. EECP2 PWM Output D.

Digital I/O. BIAS2 input for LCD. ECCP2 PWM Output C.

Digital I/O. BIAS3 input for LCD. ECCP2 PWM Output B. Capture 10 input/Compare 10 output/PWM10 output.

Digital I/O. COM0 output for LCD. ECCP3 PWM Output C. Capture 9 input/Compare 9 output/PWM9 output. Reference clock out.

Digital I/O. COM1 output for LCD. ECCP3 PWM Output B. Capture 8 input/Compare 8 output/PWM8 output.

Digital I/O. COM2 output for LCD. ECCP1 PWM Output C. Capture 7 input/Compare 7 output/PWM7 output.

Digital I/O. COM3 output for LCD. ECCP1 PWM Output B. Capture 6 input/Compare 6 output/PWM6 output.

Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. SEG31 Output for LCD. ECCP2 PWM output A.

DD)

 2011 Microchip Technology Inc. DS39957C-page 19

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RF1/AN6/C2OUT/SEG19/ CTDIN

RF1 AN6 C2OUT SEG19 CTDIN

RF2/AN7/C1OUT/SEG20

RF2 AN7 C1OUT SEG20

RF3/AN8/SEG21/C2INB/ CTMUI

RF3 AN8 SEG21 C2INB CTMUI

RF4/AN9/SEG22/C2INA

RF4 AN9 SEG22 C2INA

RF5/AN10/CV SEG23/C1INB

RF5 AN10

REF

CV SEG23 C1INB

RF6/AN11/SEG24/C1INA

RF6 AN11 SEG24 C1INA

RF7/AN5/SS1

RF7 AN5 SS1 SEG25

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

REF/

/SEG25

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Pin Number

QFN/TQFP

17

16

15

14

13

12

11

Type

I/O

I

O O

I

I/O

I

O O

I/O

I

O

I

O

I/O

I

O

I

I/O

I

O O

I

I/O

I

O

I

I/O

O

I

O

Buffer

Type

ST

Analog

—

Analog

ST

Analog

—

Analog

ST Analog Analog Analog

—

ST Analog Analog Analog

ST Analog Analog Analog Analog

ST Analog Analog Analog

ST

AnalogT

TL

Analog

Description

PORTF is a bidirectional I/O port.

Digital I/O. Analog Input 6. Comparator 2 output. SEG19 output for LCD. CTMU pulse delay input.

Digital I/O. Analog Input 7. Comparator 1 output. SEG20 output for LCD.

Digital I/O. Analog Input 8. SEG21 output for LCD. Comparator 2 Input B. CTMU pulse generator charger for the C2INB comparator input.

Digital I/O. Analog Input 9. SEG22 output for LCD Comparator 2 Input A.

Digital I/O. Analog Input 10. Comparator reference voltage output. SEG23 output for LCD. Comparator 1 Input B.

Digital I/O. Analog Input 11. SEG24 output for LCD Comparator 1 Input A.

Digital I/O. Analog Input 5. SPI1 slave select input. SEG25 output for LCD.

DD)

DS39957C-page 20  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RG0/ECCP3/P3A

RG0 ECCP3 P3A

RG1/TX2/CK2/AN19/ C3OUT

RG1 TX2 CK2 AN19 C3OUT

RG2/RX2/DT2/AN18/ C3INA

RG2 RX2 DT2 AN18 C3INA

RG3/CCP4/AN17/P3D/ C3INB

RG3 CCP4 AN17 P3D C3INB

RG4/SEG26/RTCC/ T7CKI/T5G/CCP5/AN16/ P1D/C3INC

RG4 SEG26 RTCC

(3)

T7CKI T5G CCP5 AN16 P1D C3INC

RG5 7 See the MCLR

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

Pin Number

QFN/TQFP

3

4

5

6

8

Type

I/O I/O

O

I/O

O

I/O

I

O

I/O

I

I/O

I I

I/O I/O

I

O

I

I/O

O O

I I

I/O

I

O

I

Buffer

Type

ST ST

—

ST

—

ST

Analog

—

ST ST

ST Analog Analog

ST

S/T

Analog

—

Analog

ST Analog

— ST ST ST

Analog

—

Analog

Description

PORTG is a bidirectional I/O port.

Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A.

Digital I/O. USART asynchronous transmit. USART synchronous clock (see related RX2/DT2). Analog Input 19. Comparator 3 output.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). Analog Input 18. Comparator 3 Input A.

Digital I/O. Capture 4 input/Compare 4 output/PWM4 output. Analog Input 18. ECCP3 PWM Output D. Comparator 3 Input B.

Digital I/O. SEG26 output for LCD. RTCC output Timer7 clock input. Timer5 external clock gate input. Capture 5 input/Compare 5 output/PWM5 output. Analog Input 16. ECCP1 PWM Output D. Comparator 3 Input C.

/RG5 pin.

DD)

 2011 Microchip Technology Inc. DS39957C-page 21

PIC18F87K90 FAMILY

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.

V

DD 26, 38, 57 P — Positive supply for logic and I/O pins.

AVSS 20 P — Ground reference for analog modules.

AVDD 19 P — Positive supply for analog modules.

ENVREG 18 I ST Enable for on-chip voltage regulator.

VDDCORE/VCAP

VDDCORE VCAP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices.

Pin Number

QFN/TQFP

10

Buffer

Type

P—

Description

Core logic power or external filter capacitor connection.

External filter capacitor connection (regulator enabled/disabled).

DD)

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS

Pin Name

/RG5

MCLR

RG5

OSC1/CLKI/RA7

OSC1 CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

Pin Number

TQFP

9

49

50

Type

I

I I

I/O

O

I/O

Buffer

Type

STSTMaster Clear (input) or programming voltage (input).

This pin is an active-low Reset to the device. General purpose, input only pin.

Oscillator crystal or external clock input. CMOS CMOS

TTL

—

TTL

Oscillator crystal input. External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

Description

DD)

DS39957C-page 22  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0/ULPWU

RA0 AN0 ULPWU

RA1/AN1/SEG18

RA1 AN1 SEG18

RA2/AN2/V

RA2 AN2 V

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI/SEG14

RA4 T0CKI SEG14

RA5/AN4/SEG15/T1CKI/ T3G/HLVDIN

RA5 AN4 SEG15 T1CKI T3G HLVDIN

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

REF-

REF+

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

I

C™ = I2C/SMBus

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

Pin Number

TQFP

30

29

28

27

34

33

Type

I/O

I I

I/O

I

O

I/O

I I

I/O

I I

I/O

I

O

I/O

I

O

I I I

Buffer

Type

TTL Analog Analog

ST ST

Analog

TTL Analog Analog

ST ST

Analog

Description

PORTA is a bidirectional I/O port.

Digital I/O. Analog Input 0. Ultra low-power wake-up input.

Digital I/O. Analog Input 1. SEG18 output for LCD.

Digital I/O. Analog Input 2. A/D reference voltage (low) input.

Digital I/O. Analog Input 3. A/D reference voltage (high) input.

Digital I/O. Timer0 external clock input. SEG14 output for LCD.

Digital I/O. Analog Input 4. SEG15 output for LCD. Timer1 clock input. Timer3 external clock gate input. High/Low-Voltage Detect (HLVD) input.

DD)

 2011 Microchip Technology Inc. DS39957C-page 23

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/SEG30/FLT0

RB0 INT0 SEG30 FLT0

RB1/INT1/SEG8

RB1 INT1 SEG8

RB2/INT2/SEG9/CTED1

RB2 INT2 SEG9 CTED1

RB3/INT3/SEG10/ CTED2/ECCP2/P2A

RB3 INT3 SEG10 CTED2 ECCP2 P2A

RB4/KBI0/SEG11

RB4 KBI0 SEG11

RB5/KBI1/SEG29/T3CKI/ T1G

RB5 KBI1 SEG29 T3CKI T1G

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

Pin Number

TQFP

58

57

56

55

54

53

Type

I/O

I

O

I

I/O

I

O

I/O

I

O

I

I/O

I

O

I

I/O

O

I/O

I

O

I/O

I

O

I I

Buffer

Type

TTL

ST

Analog

ST

TTL

ST

Analog

TTL

ST

Analog

ST

TTL

ST

Analog

ST ST ST

TTL TTL

Analog

TTL TTL

Analog

ST ST

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External Interrupt 0. SEG30 output for LCD. Enhanced PWM Fault input for ECCP1/2/3.

Digital I/O. External Interrupt 1. SEG8 output for LCD.

Digital I/O. External Interrupt 2. SEG9 output for LCD. CTMU Edge 1 input.

Digital I/O. External Interrupt 3. SEG10 output for LCD. CTMU Edge 2 input. Capture 2 input/Compare 2 output/PWM2 output. Enhanced PWM 2 Output A.

Digital I/O. Interrupt-on-change pin. SEG11 output for LCD.

Digital I/O. Interrupt-on-change pin. SEG29 output for LCD. Timer3 clock input. Timer1 external clock gate input.

DD)

DS39957C-page 24  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

I

C™ = I2C/SMBus

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

Pin Number

TQFP

52

47

Type

I/O

I

I/O

I

I/O

Buffer

Type

TTL

ST

TTL

ST

Description

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

DD)

 2011 Microchip Technology Inc. DS39957C-page 25

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/SOSCO/SCKLI

RC0 SOSCO SCKLI

RC1/SOSCI/ECCP2/ SEG32/P2A

RC1 SOSCI

(1)

ECCP2 SEG32 P2A

RC2/ECCP1/P1A/SEG13

RC2 ECCP1 P1A SEG13

RC3/SCK1/SCL1/SEG17

RC3 SCK1 SCL1 SEG17

RC4/SDI1/SDA1/SEG16

RC4 SDI1 SDA1 SEG16

RC5/SDO1/SEG12

RC5 SDO1 SEG12

RC6/TX1/CK1/SEG27

RC6 TX1 CK1 SEG27

RC7/RX1/DT1/SEG28

RC7 RX1 DT1 SEG28

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

Pin Number

TQFP

36

35

43

44

45

46

37

38

Type

I/O

O

I

I/O

I

I/O

O O

I/O I/O

O O

I/O I/O I/O

O

I/O

I

I/O

O

I/O

O O

I/O

O

I/O

O

I/O

I

I/O

O

Buffer

Type

ST

—

ST

CMOS

ST

Analog

—

ST ST

—

Analog

ST ST ST

Analog

ST ST ST

Analog

ST

—

Analog

ST

—

ST

Analog

ST ST ST

Analog

Description

PORTC is a bidirectional I/O port.

Digital I/O. SOSC oscillator output. Digital SOSC input.

Digital I/O. SOSC oscillator input. Capture 2 input/Compare 2 output/PWM2 output. SEG32 output for LCD. Enhanced PWM 2 Output A.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Enhanced PWM 1 Output A. SEG13 output for LCD.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I SEG17 output for LCD.

Digital I/O. SPI data in.

2

C data I/O.

I SEG16 output for LCD.

Digital I/O. SPI data out. SEG12 output for LCD.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX1/DT1). SEG27 output for LCD.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX1/CK1). SEG28 output for LCD.

2

C™ mode.

DD)

DS39957C-page 26  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/SEG0/CTPLS

RD0 SEG0 CTPLS

RD1/SEG1/T5CKI/T7G

RD1 SEG1 T5CKI T7G

RD2/SEG2

RD2 SEG2

RD3/SEG3

RD3 SEG3

RD4/SEG4/SDO2

RD4 SEG4 SDO2

RD5/SEG5/SDI2/SDA2

RD5 SEG5 SDI2 SDA2

RD6/SEG6/SCK2/SCL2

RD6 SEG6 SCK2 SCL2

RD7/SEG7/SS2

RD7 SEG7 SS2

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

I

C™ = I2C/SMBus

Pin Number

TQFP

72

69

68

67

66

65

64

63

Buffer

Type

I/O

O

Analog

O

I/O

O

Analog

I I

I/OOST

Analog

I/OOST

Analog

I/O

O

Analog

O

I/O

O

Analog

I

I/O

O

Analog

I/O I/O

I/O

O

Analog

I

PORTD is a bidirectional I/O port.

ST

ST ST

ST

—

ST

2

C

I

ST

2

I

C

ST

TTL

Digital I/O. SEG0 output for LCD. CTMU pulse generator output.

Digital I/O. SEG1 output for LCD. Timer5 clock input. Timer7 external clock gate input.

Digital I/O. SEG2 output for LCD.

Digital I/O. SEG3 output for LCD.

Digital I/O. SEG4 output for LCD. SPI data out.

Digital I/O. SEG5 output for LCD. SPI data in.

2

C™ data in.

I

Digital I/O. SEG6 output for LCD. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C™ mode.

Digital I/O. SEG7 output for LCD. SPI slave select input.

Description

DD)

 2011 Microchip Technology Inc. DS39957C-page 27

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

RE0/LCDBIAS1/P2D

4 RE0 LCDBIAS1 P2D

RE1/LCDBIAS2/P2C

3 RE1 LCDBIAS2 P2C

RE2/LCDBIAS3/P2B/

78

CCP10

RE2 LCDBIAS3 P2B

(3)

CCP10

RE3/COM0/P3C/CCP9/

77

REFO

RE3 COM0 P3C

(3)(4)

CCP9 REFO

RE4/COM1/P3B/CCP8

76 RE4 COM1 P3B

(4)

CCP8

RE5/COM2/P1C/CCP7

75 RE5 COM2 P1C

(4)

CCP7

RE6/COM3/P1B/CCP6

74 RE6 COM3 P1B

(4)

CCP6

RE7/ECCP2/P2A/SEG31

RE7

(2)

ECCP2

73

P2A SEG31

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

Type

I/O

I

O

I/O

I

O

I/O

I

O

I/O

O O

I/O

O

I/O

O O

I/O

O O

I/O

O O

I/O

I/O I/O

O O

Buffer

Type

ST

Analog

—

ST

Analog

—

ST

Analog

ST ST

ST

Analog

—

S/T

—

ST

Analog

—

ST

Analog

—

ST

Analog

—

ST

ST ST

—

Analog

Description

PORTE is a bidirectional I/O port.

Digital I/O. BIAS1 input for LCD. ECCP2 PWM Output D.

Digital I/O. BIAS2 input for LCD. ECCP2 PWM Output C.

Digital I/O. BIAS3 input for LCD. ECCP2 PWM Output B. Capture 10 input/Compare 10 output/PWM10 output.

Digital I/O. COM0 output for LCD. ECCP3 PWM Output C. Capture 9 input/Compare 9 output/PWM9 output. Reference clock out.

Digital I/O. COM1 output for LCD. ECCP4 PWM Output B. Capture 8 input/Compare 8 output/PWM8 output.

Digital I/O. COM2 output for LCD. ECCP1 PWM Output C. Capture 7 input/Compare 7 output/PWM7 output.

Digital I/O. COM3 output for LCD. ECCP1 PWM Output B. Capture 6 input/Compare 6 output/PWM6 output.

Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. SEG31 output for LCD.

DD)

DS39957C-page 28  2011 Microchip Technology Inc.

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RF1/AN6/C2OUT/SEG19/ CTDIN

RF1 AN6 C2OUT SEG19 CTDIN

RF2/AN7/C1OUT/ SEG20/CTMUI

RF2 AN7 C1OUT SEG20 CTMUI

RF3/AN8/SEG21/C2INB

RF3 AN8 SEG21 C2INB

RF4/AN9/SEG22/C2INA

RF4 AN9 SEG22 C2INA

RF5/AN10/CV SEG23/C1INB

RF5 AN10 CVREF SEG23 C1INB

RF6/AN11/SEG24/C1INA

RF6 AN11 SEG24 C1INA

RF7/AN5/SS1

RF7 AN5 SS1 SEG25

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

REF/

/SEG25

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

Pin Number

TQFP

23

18

17

16

15

14

13

Type

I/O

I O O

I

I/O

I O O O

I/O

I O

I

I/O

I O

I

I/O

I O O

I

I/O

I O

I

I/O

O

I O

Buffer

Type

ST

Analog

—

Analog

ST

Analog

—

Analog

—

ST Analog Analog Analog

ST Analog Analog Analog Analog

ST Analog Analog Analog

ST Analog

TTL

Analog

Description

PORTF is a bidirectional I/O port.

Digital I/O. Analog Input 6. Comparator 2 output. SEG19 output for LCD. CTMU pulse delay input.

Digital I/O. Analog Input 7. Comparator 1 output. SEG20 output for LCD. CTMU pulse generator charger for the C2INB comparator input.

Digital I/O. Analog Input 8. SEG21 output for LCD. Comparator 2 Input B.

Digital I/O. Analog Input 9. SEG22 output for LCD. Comparator 2 Input A.

Digital I/O. Analog Input 10. Comparator reference voltage output. SEG23 output for LCD. Comparator 1 Input B.

Digital I/O. Analog Input 11. SEG24 output for LCD. Comparator 1 Input A.

Digital I/O. Analog Input 5. SPI slave select input. SEG25 output for LCD.

DD)

 2011 Microchip Technology Inc. DS39957C-page 29

PIC18F87K90 FAMILY

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RG0/ECCP3/P3A

RG0 ECCP3 P3A

RG1/TX2/CK2/AN19/ C3OUT

RG1 TX2 CK2 AN19 C3OUT

RG2/RX2/DT2/AN18/ C3INA

RG2 RX2 DT2 AN18 C3INA

RG3/CCP4/AN17/P3D/ C3INB

RG3 CCP4 AN17 P3D C3INB

RG4/SEG26/RTCC/ T7CKI/T5G/CCP5/AN16/ P1D/C3INC

RG4 SEG26 RTCC

(3)

T7CKI T5G CCP5 AN16 P1D C3INC

RG5 9 See the MCLR

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2

C™ = I2C/SMBus

I

2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.

Pin Number

TQFP

5

6

7

8

10

Type

I/O I/O

O

I/O

O

I/O

I

O

I/O

I

I/O

I I

I/O I/O

I

O

I

I/O

O O

I I

I/O

I

O

I

Buffer

Type

ST ST

—

ST

—

ST

Analog

—

ST ST

ST Analog Analog

ST

ST Analog

—

Analog

ST Analog

— ST ST ST

Analog

—

Analog

Description

PORTG is a bidirectional I/O port.

Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX2/DT2). Analog Input 19. Comparator 3 output.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX2/CK2). Analog Input 18. Comparator 3 Input A.

Digital I/O. Capture 4 input/Compare 4 output/PWM4 output. Analog Input 17. ECCP3 PWM Output D. Comparator 3 Input B.

Digital I/O. SEG26 output for LCD. RTCC output. Timer7 clock input. Timer5 external clock gate input. Capture 5 input/Compare 5 output/PWM5 output. Analog Input 16. ECCP1 PWM Output D. Comparator 3 Input C.

/RG5 pin.

DD)

DS39957C-page 30  2011 Microchip Technology Inc.

Datasheet PIC18F87K90 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Low-Power Features:

LCD Driver and Keypad Features:

Peripheral Highlight s:

Special Microcontroller Features:

Pin Diagrams – PIC18F6XK90

Pin Diagrams – PIC18F8XK90

Table of Contents

1.0 DEVICE OVERVIEW

1.1 Core Features

1.1.1 nanoWatt TECHNOLOGY

1.1.2 OSCILLATOR OPTIONS AND FEATURES

1.1.3 MEMORY OPTIONS

1.1.4 EXTENDED INSTRUCTION SET

1.1.5 EASY MIGRATION

1.2 LCD Driver

1.3 Other Special Features

1.4 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XK90 (64-PIN DEVICES)

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F8XK90 (80-PIN DEVICES)

FIGURE 1-1: PIC18F6XK90 (64-PIN) BLOCK DIAGRAM

FIGURE 1-2: PIC18F8XK90 (80-PIN) BLOCK DIAGRAM

TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS

TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS