Datasheet PIC18F66J93, PIC18F67J93, PIC18F86J93, PIC18F87J93 Datasheet

PIC18F87J93 Family

Data Sheet

64/80-Pin, High-Performance Microcontrollers

with LCD Driver, 12-Bit A/D

and nanoWatt Technology

© 2009 Microchip Technology Inc. Preliminary DS39948A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and t he lik e is provided only for your convenience
and may be su perseded by upda t es . It is y our responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life supp ort and/or safety ap plications is entir ely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless M icrochip from any and all dama ges, claims,
suits, or expenses re sulting from such use. No licens es are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programmin g , IC SP, ICEPIC, Mindi , MiW i , MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
Omniscient Code Generation, PICC, PICC-18, PICkit,
PICDEM, PICDEM.net, PICtail, PIC

32

logo, REAL ICE, rfLAB,
Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS39948A-page ii Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

64/80-Pin, High-Performance Microcontrollers with

LCD Driver, 12-Bit A/D and nanoWatt Technology

LCD Driver and Keypad Interface Features:

• Direct LCD Panel Drive Capability:

- Can drive LCD panel while in Sleep mode

• Up to 48 Segments and 192 Pixels, Software
Selectable

• Programmable LCD Timing module:

- Multiple LCD timing sources available

- Up to four commons: static, 1/2, 1/3 or

1/4 multiplex

- Static, 1/2 or 1/3 bias configuration

• On-Chip LCD Boost Voltage Regulator for
Contrast Control

• Charge Time Measu rem ent Unit (C TMU) for
Capacitive Touch Sensing

• ADC for Resistive Touch Sensing

Low-Power Features:

• Power-Managed modes:

- Run: CPU On, Peripherals On

- Idle: CPU Off, Peripherals On

- Sleep: CPU Off, Peripherals Off

• Two-Speed Oscillator Start-up

Flexible Oscillator Struc ture:

• Two Crystal modes, 4-25 MHz

• Two External Clock modes, up to 48 MHz

• 4x Phase Lock Loop (PLL)

• Internal Oscillator Block with PLL:

- Eight user-selectable frequencies from

31.25 kHz to 8 MHz

• Secondary Oscillator using Timer1 at 32 kHz

• Fail-Safe Clock Monitor (FSCM):

- Allows for safe shutdown if peripheral clock fails

Peripheral Highlight s:

• High-Current Sink/Source 25 m A/25mA
(PORTB and PORTC)

• Up to Four External Interrupts

• Four 8-Bit/16-Bit Timer/Counter modules

• Two Capture/Compare/PWM (CCP) modules

• Master Synchronous Serial Port (MSSP) module
with Two Modes of Operation:

- 3-Wire/4-Wire SPI (supports all four SPI modes)

2

-I

C™ Master and Slave mode

• One Addressable USART module

• One Enhanced Addressable USAR T mod ule :

- LIN/J2602 support

- Auto-wake-up on Start bit and Break character

- Auto-Baud Detect (ABD)

• 12-Bit, up to 12-Channel A/D Converter:

- Auto-acquisition

- Conversion available during Sleep

• Two Analog Comparators

• Programmable Reference Voltage for Comparators

• Hardware Real-Time Clock and Calendar (RTCC)
with Clock, Calendar and Alarm Functions

• Charge Time Measurement Unit (CTMU):

- Capacitance measurement

- Time measuremen t with 1 ns typical resolution

Note: This document is supplemented by the

“PIC18F87J90 Family Data Sheet”

(DS39933). See Section 1.0 “Device
Overview”.

SPI

MSSP

Master

I

2

C™

EUSART

AUSART

12-Bit A/D

RTCC

(Channels)

BOR/LVD

Comparators

CTMU

Flash

Device

PIC18F66J93 64K 3,923 51 132 1/3 2 Y es Yes 1/1 12 2 Yes Yes Yes
PIC18F67J93 128K 3,923 51 132 1/3 2 Yes Yes 1/1 12 2 Yes Yes Yes
PIC18F86J93 64K 3,923 67 192 1/3 2 Y es Yes 1/1 12 2 Y es Yes Y es
PIC18F87J93 128K 3,923 67 192 1/3 2 Yes Yes 1/1 12 2 Yes Yes Yes

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 1

Program

Memory

(Bytes)

SRAM

Data

Memory

(Bytes)

I/O

LCD

(Pixels)

Timers

8/16-Bit

CCP

PIC18F87J93 FAMILY

Special Microcontroller Features:

• 10,000 Erase/Write Cycle Flash Program
Memory, T ypical

• Flash Retention 20 Years, Minimum

• Self-Programmable under Software Control

• Flash Program Memory has Word Write
Capability for Data EEPROM Emulators

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• In-Circuit Serial Programming™ (ICSP™) via
Two Pins

• In-Circuit Debug via Two Pins

• Operating Voltage Range: 2.0V to 3.6V

• 5.5V Tolerant Input (digital pins only)

• Selectable Open- Dr ain Conf igu rati on for Serial
Communication an d CCP Pins for Driving Output s
up to 5V

• On-Chip 2.5V Regulator

DS39948A-page 2 Preliminary © 2009 Microchip Technology Inc.

64-Pin TQFP

50 49

LCDBIAS3

RE3/COM0

RE4/COM1

RE5/COM2

RE6/COM3

RE7/CCP2

(1)

/SEG31

RD0/SEG0/CTPLS

V

DD

VSS

RD1/SEG1

RD2/SEG2

RD3/SEG3

RD4/SEG4

RD5/SEG5

RD6/SEG6

RD7/SEG7

RE1/LCDBIAS2
RE0/LCDBIAS1

RG0/LCDBIAS0

RG1/TX2/CK2

RG2/RX2/DT2/V

LCAP1

RG3/V

LCAP2

MCLR

RG4/SEG26/RTCC

VSS

VDDCORE/VCAP

RF7/AN5/SS/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CV

REF/SEG23/C1INB

RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB

RF2/AN7/C1OUT/SEG20

RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
V

SS

OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

DD

RB7/KBI3/PGD

RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13

ENVREG

RF1/AN6/C2OUT/SEG19

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1/SEG18

RA0/AN0

V

SS

VDD

RA4/T0CKI/SEG14

RA5/AN4/SEG15

RC1/T1OSI/CCP2

(1)

/SEG32

RC0/T1OSO/T13CKI

RC7/RX1/DT1/SEG28

RC6/TX1/CK1/SEG27

RC5/SDO/SEG12

54 53 52 5158 57 56 5560 59

64

63 62 61

Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting.

PIC18F66J93
PIC18F67J93

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 263127 28

29 30 32

38
37
36
35
34
33

40
39

48
47
46
45
44
43
42
41

Pin Diagrams – PIC18F6XJ93

PIC18F87J93 FAMILY

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 3

PIC18F87J93 FAMILY

80-Pin TQFP

3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41

40

39

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

LCDBIAS3

RE3/COM0

RE4/COM1

RE5/COM2

RE6/COM3

RE7/CCP2

(1)

/SEG31

RD0/SEG0/CTPLS

VDD

VSS

RD1/SEG1

RD2/SEG2

RD3/SEG3

RD4/SEG4

RD5/SEG5

RD6/SEG6

RD7/SEG7

RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0

RG1/TX2/CK2

RG2/RX2/DT2/V

LCAP1

RG3/V

LCAP2

MCLR

RG4/SEG26/RTCC

VSS

VDDCORE/VCAP

VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

DD

ENVREG

RF1/AN6/C2OUT/SEG19

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1/SEG18

RA0/AN0

V

SS

VDD

RJ0

RJ1/SEG33

RH1/SEG46

RH0/SEG47

1
2

RH2/SEG45
RH3/SEG44

17

18
RH7/SEG43
RH6/SEG42

RH5/SEG41

RH4/SEG40

RJ5/SEG38

RJ4/SEG39

37

RJ7/SEG36
RJ6/SEG37

50
49

RJ2/SEG34
RJ3/SEG35

19

20

33 34

35 36

38

58
57
56
55
54
53
52
51

60
59

68 67 66 6572 71 70 6974 73

78

77 76 75

79

80

RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC

RB7/KBI3/PGD

RC2/CCP1/SEG13

RC5/SDO/SEG12

RA4/T0CKI/SEG14

RA5/AN4/SEG15

RC1/T1OSI/CCP2

(1)

I/SEG32

RC0/T1OSO/T13CKI

RC7/RX1/DT1/SEG28

RC6/TX1/CK1/SEG27

RF7/AN5/SS/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CV

REF/SEG23/C1INB

RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB

RF2/AN7/C1OUT/SEG20

RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17

Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting.

PIC18F86J93
PIC18F87J93

Pin Diagrams – PIC18F8XJ93

DS39948A-page 4 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 7

2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 27

3.0 Special Features of the CPU........................... .............. .............................. .............. ................................................................. 37

4.0 Electrical Characteristics............................................................................................................................................................39

5.0 Packaging Information... ............... .............. ............... .............................. .............. ..................................................................... 43

Appendix A: Revision History............................................................................................................................................................... 45

Appendix B: Device Differences .......................................................................................................................................................... 45

Appendix C: Conversion Considerations ............................................................................................................................................. 46

Appendix D: Migration From Baseline to Enhanced Devices .............................................................................................................. 46

Index .................................................................................................................................................................................................... 47

The Microchip Web Site.............. ............... ............... .............. ............... ............... .............. ................................................................. 49

Customer Change Notification Service ................................................................................................................................................ 49

Customer Support................................................................................................................................................................................49

Reader Response................................................................................................................................................................................ 50

Product Identification System.............................................................................................................................................................. 51

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 5

PIC18F87J93 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents r egarding t his publication, p lease c ontact the M arket ing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS39948A-page 6 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

1.0 DEVICE OVERVIEW

This document cont a ins dev ice -specific information for
the following devices:

• PIC18F66J93 • PIC18F67J93

• PIC18F86J93 • PIC18F87J93

Note: This data sheet documents only the devices’

features and specific ations that are in addi tion
to the features and specifications of the
PIC18F87J90 family devices. For information
on the features and specifications shared by
the PIC18F87J93 family and PIC18F87J90
family devices, see the “PIC18F87J90 Family
Data Sheet” (DS39933).

The PIC18F87J93 family of devices offers the
advantages of all PIC18 microcontrollers – high compu­tatio n al pe r fo rm a nc e, a rich fea ture set an d econ omica l
price – with the addition of a versatile, on-chip LCD
driver . These feat ures ma ke the PIC18 F87 J93 famil y a
logical choice for many high-performance applications
where price is a primary consideration.

1.1 Special Features

• 12-Bit A/D Converter: The PIC18F87J93 family
implements a 12-bit A/D converter. A/D converters
in both families incorporate programmable acquisi­tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting for
a sampling period and thus, reducing code

overhead.

• Data RAM: The PIC18F87J93 family devices have
3,923 bytes of RAM.

1.2 Details on Individual Family Members

Devices in the PIC18F87J93 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in the
following ways:

• Flash Program Memory (64 Kbytes for

PIC18FX6J93 devices and 128 Kbytes for
PIC18FX7J93).

• LCD Pixels:

- 64-pin devices – 132 pixels
(33 SEGs x 4 COMs)

- 80-pin devices – 192 pixels
(48 SEGs x 4 COMs)

• I/O Ports (seven bidirectional ports on
PIC18F6XJ93 devices and nine bidirection al ports
on PIC18F8XJ93 devices).

All other features for devic es in this fam il y ar e id enti ca l
and are summarized in Table 1-1 and Table 1-2.

The devices’ block diagrams are given in Figure 1-1
and Figure 1-2.

The pinouts for all devices are listed in Table 1-3 and
Table 1-4.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 7

PIC18F87J93 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XJ93 (64-PIN DEVICES)

Features PIC18F66J93 PIC18F67J93

Operating Frequency DC – 48 MHz
Program Memory (Bytes) 64K 128K
Program Memory (Instructions) 32,768 65,536
Data Memory (Bytes) 3,923 3,923
Interrupt Sources 29
I/O Ports Ports A, B, C, D , E, F, G
LCD Driver (available pixels to drive) 132 (33 SEGs x 4 COMs)
Timers 4
Comparators 2
CTMU Yes
RTCC Y es
Capture/Compare/PWM Modules 2
Serial Communications MSSP, Addressable USART, Enhanced USART
12-Bit Analog-to-Digital Module 12 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow , MCLR

(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 64-Pin TQFP

, WDT

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F8XJ93 (80-PIN DEVICES)

Features PIC18F86J93 PIC18F87J93

Operating Frequency DC – 48 MHz
Program Memory (Bytes) 64K 128K
Prog r a m M e m o r y ( I n s t r u c t i on s ) 32,768 65,536
Data Memory (Bytes) 3,923 3,923
Interrupt Sources 29
I/O Ports Ports A, B, C , D, E, F, G, H, J
LCD Driver (available pixels to drive) 192 (48 SEGs x 4 COMs)
Timers 4
Comparators 2
CTMU Yes
RTCC Y es
Capture/Compare/PWM Modules 2
Serial Communications MSSP, Addressable USART, Enhanced USART
12-Bit Analog-to-Digital Module 12 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow , MCLR

(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 80-Pin TQFP

, WDT

DS39948A-page 8 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

Instruction

Decode and

Control

PORTA

Data Latch

Data Memory

(2.0, 3.9

Address Latc h

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

Address Latch

Program Memory

(96 Kbytes)

Data Latch

20

8

8

T able Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

Note 1: See Table 1-3 for I/O port pin descriptions.

2: RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.

AUSART

Comparators

MSSP

Timer3Timer2 CTMUTimer1

CCP2

ADC

12-Bit

W

Instruction Bus <16>

STKPTR

Bank

8

State Machine
Control Signals

Decode

8

8

EUSART

ROM Latch

LCD

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1,2)

RC0:RC7

(1)

RD0:RD7

(1)

RE0:RE1,

RF1:RF7

(1)

RG0:RG4

(1)

PORTB

RB0:RB7

(1)

OSC1/CLKI

OSC2/CLKO

V

DD,

Timing

Generation

V

SS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

BOR and

LVD

(3)

Precision

Reference

Band Gap

INTRC

Oscillator

Regulator

Voltage

VDDCORE/VCAP

ENVREG

Kbytes)

Driver

8 MHz

Oscillator

RE3:RE7

(1)

Timer0

CCP1

RTCC

FIGURE 1-1: PIC18F6XJ93 (64-PIN) BLOCK DIAGRAM

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 9

PIC18F87J93 FAMILY

Instruction

Decode and

Control

Data Latch

Data Memory

(2.0, 3.9

Address Latc h

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

Address Latch

Program Memory

(96 Kbytes)
Data Latch

20

8

8

Table Po in t er <2 1 >

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

W

Instruction Bus <16>

STKPTR

Bank

8

State Machine
Control Signals

Decode

8

8

ROM Latch

OSC1/CLKI

OSC2/CLKO

V

DD,VSS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Precision

Reference

Band Gap

Regulator

Voltage

VDDCORE/VCAP

ENVREG

Kbytes)

PORTA

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1,2)

RC0:RC7

(1)

RD0:RD7

(1)

RF1:RF7

(1)

RG0:RG4

(1)

PORTB

RB0:RB7

(1)

PORTH

RH0:RH7

(1)

PORTJ

RJ0:RJ7

(1)

Note 1: See Table1-3 for I/O port pin descriptions.

2: RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.

Timing

Generation

INTRC

Oscillator

8 MHz

Oscillator

RE0:RE1,

RE3:RE7

(1)

BOR and

LVD

(3)

AUSART

Comparators

MSSP

Timer3Timer2 CTMUTimer1

CCP2

ADC

12-Bit

EUSART

LCD

Driver

Timer0

CCP1

RTCC

FIGURE 1-2: PIC18F8XJ93 (80-PIN) BLOCK DIAGRAM

DS39948A-page 10 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

MCLR

OSC1/CLKI/RA7

OSC1
CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO

RA6

RA0/AN0

RA0
AN0

RA1/AN1/SEG18

RA1
AN1
SEG18

RA2/AN2/V

RA2
AN2
V

REF-

REF-

7 I ST Master Clear (input) or programming voltage (input). This

pin is an active-low Reset to the device.

39

40

24

23

22

I

CMOS

I

CMOS

I/O

O
O

I/O

I/OITTL

Analog

I/O

I

Analog

O

Analog

I/O

I

Analog

I

Analog

Oscillator crystal or external clock input.

Oscillator cryst al inp ut.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)

TTL

—
—

TTL

TTL

TTL

General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Osc ill ato r mode .
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog In put 0.

Digital I/O.
Analog In put 1.
SEG18 output for LCD.

Digital I/O.
Analog In put 2.
A/D reference voltage (l ow) input.

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/SEG14

RA4
T0CKI
SEG14

RA5/AN4/SEG15

RA5
AN4

SEG15
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

REF+

REF+

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

21

28

27

I/O

I/O

O

I/O

O

I
I

I

I

TTL
Analog
Analog

ST
ST

Analog

TTL
Analog
Analog

Digital I/O.
Analog In put 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.

Digital I/O.
Analog In put 4.
SEG15 output for LCD.

DD)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 11

PIC18F87J93 FAMILY

TABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/SEG30

RB0
INT0
SEG30

Pin Number

TQFP

48

Pin

Type

I/O

I

O

Buffer

Type

TTL

ST

Analog

Description

PORTB is a bidirectional I/O port. PORTB can be software
programme d for internal weak pull-ups on all inputs.

Digital I/O.
External Interrupt 0.
SEG30 output for LCD.

RB1/INT1/SEG8

RB1
INT1
SEG8

RB2/INT2/SEG9/CTED1

RB2
INT2
SEG9
CTED1

RB3/INT3/SEG10/CTED2

RB3
INT3
SEG10
CTED2

RB4/KBI0/SEG11

RB4
KBI0
SEG11

RB5/KBI1/SEG29

RB5
KBI1
SEG29

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

47

46

45

44

43

42

37

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O
I/O

I/O
I/O

I

I
I

I
I

I

I

I

I

TTL

ST

Analog

TTL

ST

Analog

ST

TTL

ST

Analog

ST

TTL
TTL

Analog

TTL
TTL

Analog

TTL
TTL

ST

TTL
TTL

ST

Digital I/O.
External Interrupt 1.
SEG8 output for LCD.

Digital I/O.
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.

Digital I/O.
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.

Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.

Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DD)

DS39948A-page 12 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/SEG32

RC1
T1OSI

(1)

CCP2
SEG32

RC2/CCP1/SEG13

RC2
CCP1
SEG13

RC3/SCK/SCL/SEG17

RC3
SCK
SCL
SEG17

RC4/SDI/SDA/SEG16

RC4
SDI
SDA
SEG16

RC5/SDO/SEG12

RC5
SDO
SEG12

30

29

33

34

35

36

I/O

O

I/O
I/O

O

I/O
I/O

O

I/O
I/O
I/O

O

I/O
I/O

O

I/O

O
O

I

I

I

ST

—

ST

ST

CMOS

ST

Analog

ST
ST

Analog

ST
ST
ST

Analog

ST
ST
ST

Analog

ST

—

Analog

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.

Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchron ous serial clock input/ou tput for I
SEG17 output for LCD.

Digital I/O.
SPI data in.

2

C data I/O.

I
SEG16 output for LCD.

Digital I/O.
SPI data out.
SEG12 output for LCD.

2

C™ mode.

RC6/TX1/CK1/SEG27

RC6
TX1
CK1
SEG27

RC7/RX1/DT1/SEG28

RC7
RX1
DT1
SEG28

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 13

31

32

I/O

O

I/O

O

I/O
I/O

O

I

ST

—

ST

Analog

ST
ST
ST

Analog

Digital I/O.
EUSART asynchronous transm it.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.

Digital I/O.
EUSART asynchronous rece iv e.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.

DD)

PIC18F87J93 FAMILY

TABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/SEG0/CTPLS

RD0
SEG0
CTPLS

RD1/SEG1

RD1
SEG1

RD2/SEG2

RD2
SEG2

RD3/SEG3

RD3
SEG3

RD4/SEG4

RD4
SEG4

RD5/SEG5

RD5
SEG5

RD6/SEG6

RD6
SEG6

RD7/SEG7

RD7
SEG7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

58

55

54

53

52

51

50

49

I/O

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

ST

O

Analog

O

—

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.

Digital I/O.
SEG1 output for LCD.

Digital I/O.
SEG2 output for LCD.

Digital I/O.
SEG3 output for LCD.

Digital I/O.
SEG4 output for LCD.

Digital I/O.
SEG5 output for LCD.

Digital I/O.
SEG6 output for LCD.

Digital I/O.
SEG7 output for LCD.

DD)

DS39948A-page 14 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

RE0/LCDBIAS1

RE0
LCDBIAS1

RE1/LCDBIAS2

RE1

LCDBIAS2
LCDBIAS3 64 I Analog BIAS3 input for LCD.
RE3/COM0

RE3

COM0
RE4/COM1

RE4

COM1
RE5/COM2

RE5

COM2
RE6/COM3

RE6

COM3
RE7/CCP2/SEG31

RE7

(2)

CCP2

SEG31
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

63

62

61

60

59

2

I/OIST

Analog

1

I/OIST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/O
I/O

ST
ST

O

Analog

Digital I/O.
BIAS1 input for LCD.

Digital I/O.
BIAS2 input for LCD.

Digital I/O.
COM0 output for LCD.

Digital I/O.
COM1 output for LCD.

Digital I/O.
COM2 output for LCD.

Digital I/O.
COM3 output for LCD.

Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.

DD)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 15

PIC18F87J93 FAMILY

TABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF1/AN6/C2OUT/SEG19

RF1
AN6
C2OUT
SEG19

RF2/AN7/C1OUT/SEG20

RF2
AN7
C1OUT
SEG20

RF3/AN8/SEG21/C2INB

RF3
AN8
SEG21
C2INB

RF4/AN9/SEG22/C2INA

RF4
AN9
SEG22
C2INA

RF5/AN10/CV
SEG23/C1INB

RF5
AN10

REF

CV
SEG23
C1INB

REF/

17

16

15

14

13

I/O

O
O

I/O

O
O

I/O

O

I/O

O

I/O

O
O

I

I

I
I

I
I

I

I

ST

Analog

—

Analog

ST

Analog

—

Analog

ST
Analog
Analog
Analog

ST
Analog
Analog
Analog

ST
Analog
Analog
Analog
Analog

Digital I/O.
Analog In put 6.
Comparator 2 output.
SEG19 output for LCD.

Digital I/O.
Analog In put 7.
Comparator 1 output.
SEG20 output for LCD.

Digital I/O.
Analog In put 8.
SEG21 output for LCD.
Comparator 2 input B.

Digital I/O.
Analog In put 9.
SEG22 output for LCD
Comparator 2 input A.

Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 input B.

RF6/AN11/SEG24/C1INA

RF6
AN11
SEG24
C1INA

RF7/AN5/SS

RF7
AN5
SS
SEG25

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

DS39948A-page 16 Preliminary © 2009 Microchip Technology Inc.

/SEG25

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

12

11

I/O

O

I/O

O
O

I
I

I

ST
Analog
Analog
Analog

ST
Analog

TTL

Analog

Digital I/O.
Analog Input 11.
SEG24 output for LCD
Comparator 1 input A.

Digital I/O.
Analog In put 5.
SPI slave select input.
SEG25 output for LCD.

DD)

PIC18F87J93 FAMILY

T ABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/LCDBIAS0

RG0
LCDBIAS0

RG1/TX2/CK2

RG1
TX2
CK2

RG2/RX2/DT2/V

RG2
RX2
DT2

LCAP1

V

LCAP2

RG3/V

RG3
VLCAP2

RG4/SEG26/RTCC

RG4
SEG26
RTCC

SS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.

V
VDD 26, 38, 57 P — Positive supply for logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.

DD 19 P — Positive supply for analog modules.

AV
ENVREG 18 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP

VDDCORE
VCAP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

LCAP1

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

10

3

I/OIST

Analog

4

I/O
I/O

5

I/O
I/O

6

I/OIST

8

I/O

ST

O

O
O

P
P

I
I

—

ST

ST
ST
ST

Analog

Analog

ST

Analog

—

—
—

Digital I/O.
BIAS0 input for LCD.

Digital I/O.
AUSART asynchronous transm it.
AUSART synchronous clock (see related RX2/DT2).

Digital I/O.
AUSART asynchronous rece iv e.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.

Digital I/O.
LCD charge pump capacitor input.

Digital I/O.
SEG26 output for LCD.
RTCC output

Core logic power or external filter capacitor connection.

Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor co nne cti on (regu la tor enab led ).

DD)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 17

PIC18F87J93 FAMILY

TABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

MCLR

OSC1/CLKI/RA7

OSC1
CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO

RA6

RA0/AN0

RA0
AN0

RA1/AN1/SEG18

RA1
AN1
SEG18

RA2/AN2/V

RA2
AN2
V

REF-

REF-

9 I ST Master Clear (input) or programming voltage (input). This

pin is an active-low Reset to the device.

49

50

30

29

28

I

CMOS

I

CMOS

I/O

O
O

I/O

I/OITTL

Analog

I/O

I

Analog

O

Analog

I/O

I

Analog

I

Analog

Oscillator crystal or external clock input.

Oscillator crystal input.
External clock source input. Alw ay s assoc ia ted
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)

TTL

—
—

TTL

TTL

TTL

General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog Input 0.

Digital I/O.
Analog Input 1.
SEG18 output for LCD.

Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/SEG14

RA4
T0CKI
SEG14

RA5/AN4/SEG15

RA5
AN4

SEG15
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

REF+

REF+

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

27

34

33

I/O

I/O

O

I/O

O

I
I

I

I

TTL
Analog
Analog

ST
ST

Analog

TTL
Analog
Analog

Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.

Digital I/O.
Analog Input 4.
SEG15 output for LCD.

DD)

DS39948A-page 18 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/SEG30

RB0
INT0
SEG30

Pin Number

TQFP

58

Pin

Type

I/O

I

O

Buffer

Type

TTL

ST

Analog

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.
External Interrupt 0.
SEG30 output for LCD.

RB1/INT1/SEG8

RB1
INT1
SEG8

RB2/INT2/SEG9/CTED1

RB2
INT2
SEG9
CTED1

RB3/INT3/SEG10/
CTED2

RB3
INT3
SEG10
CTED2

RB4/KBI0/SEG11

RB4
KBI0
SEG11

RB5/KBI1/SEG29

RB5
KBI1
SEG29

RB6/KBI2/PGC

RB6
KBI2
PGC

57

56

55

54

53

52

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O
I/O

I

I
I

I
I

I

I

I

TTL

ST

Analog

TTL

ST

Analog

ST

TTL

ST

Analog

ST

TTL
TTL

Analog

TTL
TTL

Analog

TTL
TTL

ST

Digital I/O.
External Interrupt 1.
SEG8 output for LCD.

Digital I/O.
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.

Digital I/O.
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.

Digital I/O.
Interrupt-on-change pin.
SEG1 1 output for LCD.

Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 19

47

I/O
I/O

TTL

I

TTL

ST

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DD)

PIC18F87J93 FAMILY

TABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/SEG32

RC1
T1OSI

(1)

CCP2
SEG32

RC2/CCP1/SEG13

RC2
CCP1
SEG13

RC3/SCK/SCL/SEG17

RC3
SCK
SCL
SEG17

RC4/SDI/SDA/SEG16

RC4
SDI
SDA
SEG16

RC5/SDO/SEG12

RC5
SDO
SEG12

36

35

43

44

45

46

I/O

O

I/O
I/O

O

I/O
I/O

O

I/O
I/O
I/O

O

I/O
I/O

O

I/O

O
O

I

I

I

ST

—

ST

ST

CMOS

ST

Analog

ST
ST

Analog

ST
ST
ST

Analog

ST
ST
ST

Analog

ST

—

Analog

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.

Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
SEG17 output for LCD.

Digital I/O.
SPI data in.

2

C data I/O.

I
SEG16 output for LCD.

Digital I/O.
SPI data out.
SEG12 output for LCD.

2

C™ mode.

RC6/TX1/CK1/SEG27

RC6
TX1
CK1
SEG27

RC7/RX1/DT1/SEG28

RC7
RX1
DT1
SEG28

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

DS39948A-page 20 Preliminary © 2009 Microchip Technology Inc.

37

38

I/O

O

I/O

O

I/O
I/O

O

I

ST

—

ST

Analog

ST
ST
ST

Analog

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.

DD)

PIC18F87J93 FAMILY

T ABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/SEG0/CTPLS

RD0
SEG0
CTPLS

RD1/SEG1

RD1
SEG1

RD2/SEG2

RD2
SEG2

RD3/SEG3

RD3
SEG3

RD4/SEG4

RD4
SEG4

RD5/SEG5

RD5
SEG5

RD6/SEG6

RD6
SEG6

RD7/SEG7

RD7
SEG7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

72

69

68

67

66

65

64

63

I/O

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

ST

O

Analog

O

ST

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.

Digital I/O.
SEG1 output for LCD.

Digital I/O.
SEG2 output for LCD.

Digital I/O.
SEG3 output for LCD.

Digital I/O.
SEG4 output for LCD.

Digital I/O.
SEG5 output for LCD.

Digital I/O.
SEG6 output for LCD.

Digital I/O.
SEG7 output for LCD.

DD)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 21

PIC18F87J93 FAMILY

TABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

RE0/LCDBIAS1

RE0
LCDBIAS1

RE1/LCDBIAS2

RE1

LCDBIAS2
LCDBIAS3 78 I Analog BIAS3 input for LCD.
RE3/COM0

RE3

COM0
RE4/COM1

RE4

COM1
RE5/COM2

RE5

COM2
RE6/COM3

RE6

COM3
RE7/CCP2/SEG31

RE7

(2)

CCP2

SEG31
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

77

76

75

74

73

4

I/OIST

Analog

3

I/OIST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/O
I/O

ST
ST

O

Analog

Digital I/O.
BIAS1 input for LCD.

Digital I/O.
BIAS2 input for LCD.

Digital I/O.
COM0 output for LCD.

Digital I/O.
COM1 output for LCD.

Digital I/O.
COM2 output for LCD.

Digital I/O.
COM3 output for LCD.

Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.

DD)

DS39948A-page 22 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF1/AN6/C2OUT/SEG19

RF1
AN6
C2OUT
SEG19

RF2/AN7/C1OUT/SEG20

RF2
AN7
C1OUT
SEG20

RF3/AN8/SEG21/C2INB

RF3
AN8
SEG21
C2INB

RF4/AN9/SEG22/C2INA

RF4
AN9
SEG22
C2INA

RF5/AN10/CV
SEG23/C1INB

RF5
AN10
CV
SEG23
C1INB

REF/

REF

23

18

17

16

15

I/O

O
O

I/O

O
O

I/O

O

I/O

O

I/O

O
O

I

I

I
I

I
I

I

I

ST

Analog

—

Analog

ST

Analog

—

Analog

ST
Analog
Analog
Analog

ST
Analog
Analog
Analog

ST
Analog
Analog
Analog
Analog

Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.

Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.

Digital I/O.
Analog Input 8.
SEG21 output for LCD.
Comparator 2 input B.

Digital I/O.
Analog Input 9.
SEG22 output for LCD.
Comparator 2 input A.

Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 input B.

RF6/AN11/SEG24/C1INA

RF6
AN11
SEG24
C1INA

RF7/AN5/SS

RF7
AN5
SS
SEG25

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 23

/SEG25

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

14

13

I/O

O

I/O

O
O

I
I

I

ST
Analog
Analog
Analog

ST
Analog

TTL

Analog

Digital I/O.
Analog Input 11.
SEG24 output for LCD.
Comparator 1 input A.

Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.

DD)

PIC18F87J93 FAMILY

TABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/LCDBIAS0

RG0
LCDBIAS0

RG1/TX2/CK2

RG1
TX2
CK2

RG2/RX2/DT2/V

RG2
RX2
DT2

LCAP1

V

LCAP2

RG3/V

RG3
VLCAP2

RG4/SEG26/RTCC

RG4
SEG26
RTCC

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

LCAP1

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

10

5

I/OIST

Analog

6

I/O
I/O

7

I/O
I/O

8

I/OIST

I/O

ST

O

—

ST

ST

I

ST
ST

I

Analog

Analog

ST

O

Analog

O

—

Digital I/O.
BIAS0 input for LCD.

Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).

Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.

Digital I/O.
LCD charge pump capacitor input.

Digital I/O.
SEG26 output for LCD.
RTCC output.

DD)

DS39948A-page 24 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTH is a bidirectional I/O port.

RH0/SEG47

RH0
SEG47

RH1/SEG46

RH1
SEG46

RH2/SEG45

RH2
SEG45

RH3/SEG44

RH3
SEG44

RH4/SEG40

RH4
SEG40

RH5/SEG41

RH5
SEG41

RH6/SEG42

RH6
SEG42

RH7/SEG43

RH7
SEG43

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

79

80

1

2

22

21

20

19

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

Digital I/O.
SEG47 output for LCD.

Digital I/O.
SEG46 output for LCD.

Digital I/O.
SEG45 output for LCD.

Digital I/O.
SEG44 output for LCD.

Digital I/O.
SEG40 output for LCD.

Digital I/O.
SEG41 output for LCD.

Digital I/O.
SEG42 output for LCD.

Digital I/O.
SEG43 output for LCD.

DD)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 25

PIC18F87J93 FAMILY

TABLE 1-4: PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RJ0 62 I/O ST Digital I/O.
RJ1/SEG33

RJ1
SEG33

RJ2/SEG34

RJ2
SEG34

RJ3/SEG35

RJ3
SEG35

RJ4/SEG39

RJ4
SEG39

RJ5/SEG38

RJ5
SEG38

RJ6/SEG37

RJ6
SEG37

RJ7/SEG36

RJ7
SEG36

SS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.

V
VDD 32, 48, 71 P — Positive supply for logic and I/O pins.
AVSS 26 P — Ground reference for analog modules.

DD 25 P — Positive supply for analog modules.

AV
ENVREG 24 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP

VDDCORE
VCAP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

Pin Number

TQFP

61

60

59

39

40

41

42

12

Pin

Buffer

Type

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

P
P

Type

—
—

Description

PORTJ is a bidirectional I/O port.

Digital I/O.
SEG33 output for LCD.

Digital I/O.
SEG34 output for LCD.

Digital I/O.
SEG35 output for LCD.

Digital I/O.
SEG39 output for LCD.

Digital I/O
SEG38 output for LCD.

Digital I/O.
SEG37 output for LCD.

Digital I/O.
SEG36 output for LCD.

Core logic power or exte rnal filter capacitor connection.

Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connect ion (regulator enabled).

DD)

DS39948A-page 26 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

2.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has
12 inputs for all PIC18F87J93 family devices. This
module allows conversion of an analog input signal to
a corresponding 12-bit digital number.

The module has these registers:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.

REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCAL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 ADCAL: A/D Calibration bit

1 = Calibration is performed on next A/D conversion
0 = Normal A/D converter operation (no calibration is performed)

bit 6 Unimplemented: Read as ‘0’
bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)
0110 = Channel 06 (AN6)
0111 = Channel 07 (AN7)
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
11xx = Unused

bit 1 GO/DONE

When ADON =

1 = A/D conversion in progress
0 = A/D Idle

bit 0 ADON: A/D On bit

1 = A/D converter module is enabled
0 = A/D converter module is disabled

: A/D Conversion Status bit

1:

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 27

PIC18F87J93 FAMILY

A = Analog input D = Digital I/O

PCFG <3:0> AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

0000 AAAAAAAAAAAA
0001 AAAAAAAAAAAA
0010 AAAAAAAAAAAA
0011 AAAAAAAAAAAA
0100 DAAAAAAAAAAA
0101 DDAAAAAAAAAA
0110 DDDAAAAAAAAA
0111 DDDDAAAAAAAA
1000 DDDDDAAAAAAA
1001 DDDDDDAAAAAA
1010 DDDDDDDAAAAA
1011 DDDDDDDDAAAA
1100 DDDDDDDDDAAA
1101 DDDDDDDDDDAA
1110 DDDDDDDDDDDA
1111 DDDDDDDDDDDD

REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TRIGSEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TRIGSEL: Special Trigger Select bit

bit 6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (V

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source )

bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits:

— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

1 = Selects the special trig ger from the CTMU
0 = Selects the special trigger from th e CCP2

REF- source)

1 =V

REF- (AN2)

0 =AV

SS

REF+ (AN3)

1 =V

DD

0 =AV

DS39948A-page 28 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits

bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits

— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

1 = Right justified
0 = Left justified

111 = 20 T

AD

110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD

111 = FRC (clock derived from A/D RC oscillator)
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F

(1)

OSC/64
OSC/16
OSC/4
RC (clock derived from A/D RC oscillator)
OSC/32
OSC/8
OSC/2

(1)

(1)

Note 1: If the A/D F

RC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D

clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 29

PIC18F87J93 FAMILY

(Input Voltage)

V

AIN

VREF+

Reference

Voltage

AV

DD

VCFG<1:0>

CHS<3:0>

AN7

AN6

AN4

AN3

AN2

AN1

AN0

0111

0110

0100

0011

0010

0001

0000

12-Bit

A/D

VREF-

AVSS

Converter

AN1 1

AN10

AN9

AN8

1011

1010

1001

1000

Note 1: Channels AN15 through AN12 are not available on PIC18F6XJ93 devices.

2: I/O pins have diode protection to V

DD and VSS.

AN5

0101

The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AV

DD and AVSS) or the voltage level on the RA3/AN3/

VREF+ and RA2/AN2/VREF- pins.
The A/D converter has a unique feature of being able

to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.

Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I /O. The
ADRESH and ADRESL registers contain the result of the

FIGURE 2-1: A/D BLOCK DIAGRAM

(1,2)

A/D conversion. W hen the A/D conve rsion is complete,
the result is loaded into the ADRESH:ADRESL register
pair , t he GO/ DONE
A/D Interrupt Flag bi t, A D IF, is set.

A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.

The block diagram of the A/D module is shown in
Figure 2-1.

bit (ADCON0<1>) is cleared and the

DS39948A-page 30 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

VAIN

CPIN

RS

ANx

5 pF

V

DD

VT = 0.6V

V

T = 0.6V

I

LEAKAGE

RIC ≤ 1k

Sampling
Switch

SS

R

SS

CHOLD = 25 pF

V

SS

Sampling Switch

1234

(kΩ)

VDD

±100 nA

Legend: CPIN

VT
ILEAKAGE

RIC
SS
C

HOLD

= Input Capacitance
= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)

various junctions

= Sampling Switch ResistanceRSS

After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi­tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO /DONE

bit and the actual

start of the conversion.
The following steps should be followed to do an A/D

conversion:

1. Configure the A/D module:

• Configure analog pins, volt age refere nce and
digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCO N2)

• Turn on A/D module (ADCON0)

FIGURE 2-2: ANALOG INPUT MODEL

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion:

• Set GO/DONE

bit (ADCON0<1>)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

bit to be cleared

OR

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH:ADRESL);
clear ADIF bit, if required.

7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as T

AD. A minimum wait of 2 TAD is

required before next acquisition starts.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 31

PIC18F87J93 FAMILY

2.1 A/D Acquisition Requirements

For the A/D co nverter to meet its s pecified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is sh own in Figure 2-2. The source
impedance (R

S) and the internal sampling switch (RSS)

impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (V
source impedance affect s the of fset vol tage at the ana­log input (due to pin leakage current). The maximum

recommended impedance for analog sources is

2.5 kΩ. After the analog input channel is selected

(changed), the channel must be sampled for at least
the minimum acquisition time before starting a

HOLD) must be allowed

DD). The

To calculate the minimum acquis ition time, Equation2-1
may be used. This equation assumes that 1/2 LSb error
is used (1,024 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.

Equation 2-3 shows the calculation of the minimum
required acquisition time, T
based on the following application system
assumptions:

CHOLD =25 pF
Rs = 2.5 kΩ
Conversion Error ≤ 1/2 LSb
V

DD =3V→ Rss = 2 kΩ

Temperature = 85°C (system max.)

conversion.

Note: When the conversion is started, the

holding capacitor is disconnected from the
input pin.

EQUATION 2-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

AMP + TC + TCOFF

=T

ACQ. This calculation is

EQUATION 2-2: A/D MINIMUM CHARGING TIME

V

HOLD = (VREF – (VREF/2048)) • (1 – e

or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)

(-TC/CHOLD(RIC + RSS + RS))

)

EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

T

ACQ =TAMP + TC + TCOFF

TAMP =0.2 μs

COFF = (Temp – 25°C)(0.02 μs/°C)

T

(85°C – 25°C)(0.02 μs/°C)

1.2 μs

Temperature coefficient is only required for temperatures > 25°C. Below 25°C, T

C = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs

T

-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs

1.05 μs

ACQ =0.2 μs + 1 μs + 1.2 μs

T

2.4 μs

COFF = 0 ms.

DS39948A-page 32 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

2.2 Selecting and Configuring Automatic A c q u is ition Time

The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.

When the GO/DO NE

bit is set, sampling is stopp ed and
a conversion beg ins. The u ser is res ponsible for ensur­ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE

bit. This occurs when the ACQT<2:0> bits
(ADCON2<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.

If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE

bit is set, the A/D modu le continues
to sample the i nput for the select ed acquis ition tim e, then
automatically begins a conversion. Since the acquisition
time is program med, ther e may be no need to wait fo r an
acquisition time between selecting a channel and setting
the GO/DONE

bit.

In either case, when the conversion is completed, the
GO/DONE

bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.

2.3 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 T
The source of the A/D conversion clock is software
selectable.

There are seven possible options for T

OSC

•2 T

•4 TOSC

•8 TOSC

•16 TOSC

•32 TOSC

•64 T

OSC

• Internal RC Oscill ator
For correct A/D conversions, the A/D conversion clock

AD) must be as short as possible but greater than the

(T
minimum T

AD.

Table 2-1 shows the resultant T
the device operating frequencies and the A/D clock
source selected.

AD per 12-bit conversion.

AD:

AD times derive d from

T ABLE 2-1: TAD vs. DEVICE OPERATING

FREQUENCIES

AD Clock Source (TAD)Maximum

Device

Operation ADCS<2:0>

2 T

OSC 000 2.86 MHz
OSC 100 5.71 MHz

4 T

Frequency

8 TOSC 001 11.43 MHz

16 TOSC 101 22.86 MHz

OSC 010 40.0 MHz

32 T
64 TOSC 110 40.0 MHz

RC

(2)

x11 1.00 MHz

(1)

Note 1: The RC source has a typical TAD time of

4 μs.

2: For device frequencies above 1 MHz, the

device must be in Sleep mod e for the entire
conversion or the A/D accuracy m ay be ou t
of specification.

2.4 Configuring Analog Port Pins

The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pin s
needed as analog inputs must have their correspond­ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (V
converted.

The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.

Note 1: When reading the PORT register, all pins

configured as analog input channels will
read as cleared (a lo w l ev el). Pin s co nfi g­ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.

2: Analog levels on any pin defined as a

digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.

OH or VOL) will be

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 33

PIC18F87J93 FAMILY

TAD1 TAD2

TAD3

TAD4 TAD5

TAD6 TAD7

TAD8

TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analo g input (typically 100 ns )

TAD9 TAD10

TCY - TAD

Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

b0

b9

b6

b5

b4

b3

b2

b1

b8

b7

1

2

3 4 5

6

7

8

11

Set GO/DONE bit

(Holding capacitor is disconnected)

9 10

Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is reconnected to analog input.

Conversio n starts

1

2

3 4

(Holding capacitor continues
acquiring input)

T

ACQT Cycles

TAD Cycles

Automatic
Acquisition
Time

b0b9

b6

b5 b4

b3

b2

b1

b8

b7

2.5 A/D Conversions

Figure 2-3 s hows the operation of the A/D converte r
after the GO/DONE
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.

Figure 2-4 s hows the operation of the A/D converte r
after the GO/DONE
bits are set to ‘010’ and a 4 T
selected before the conversion starts.

Clearing the GO/DONE
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

AD wai t is required be fore the next a cquisition can b e

2T
started. After this wait, acquisition on the selected
channel is automatically started.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

bit has been set and the

bit has been set; the ACQT<2:0>

AD acquisition time is

bit during a conversion will abort

2.6 Use of the CCP2 Trigger

An A/D conversion can be st arted by t he “S pecial Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE
will be set, st arting the A/D acquis ition and conversion,
and the Timer1 (or Timer3) counte r will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate ana log input cha nnel must b e selected
and the minimum acquisition period is either timed by
the user , or an ap propriate T
the Special Eve nt T rigger set s the GO/DONE
a conversion).

If the A/D module is not enabled (A DON is cleared) , the
Specia l Event T rigger will be i gnored by the A/D module
but will still reset the Timer1 (or Timer3) counter.

ACQ time is selecte d before

bit

bit (starts

FIGURE 2-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 2-4: A/D CONVERSION T

AD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

DS39948A-page 34 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

2.7 A/D Converter Calibration

The A/D converter in the PIC18F87J93 family of
devices includes a self-calibration feature which com­pensates for any offset generated within the module.
The calibration proce ss is au tomated and i s initiate d by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE
“dummy” conversion (w hich means it is rea ding none of
the input channels) and store the resulting value
internally to compensate for offset. Thus, subsequent
offsets will be compensated.

The calibration proces s assumes that the dev ice is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.

bit is set, the module will perform a

2.8 Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-mana ged mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. I f desired, the dev ice may be placed into
the corresponding power-managed Idle mode during
the conversion.

If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.

Operation in Sleep mode requires the A/D RC clock to
be selected. If bi ts, ACQ T< 2 :0 > , ar e se t t o ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCSx bits in the OSCCON register must have already
been cleared prior to starting the conversion.

TABLE 2-2: SUMMARY OF A/D REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes

INTCON GIE/GIEH PEIE/GIEL
PIR1
PIE1 —ADIERC1IE TX1IE SSPIE — TMR2IE TMR1IE 2
IPR1 —ADIPRC1IP TX1IP SSPIP — TMR2IP TMR1IP 2
PIR3
PIE3 — LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 2
IPR3 — LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 2
ADRESH A/D Result Register High Byte 2
ADRESL A/D Result Register Low Byte 2

ADCON0 ADCAL
ADCON1 TRIGSEL
ADCON2 ADFM
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 2
PORTA
TRISA
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — 2
TRISF TRISF5 TRISF4 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal

oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.

2: For these Reset values, see Section 4.0 “Reset” of the “PIC18F87J90 Family Data Sheet” (DS39933).

—ADIFRC1IF TX1IF SSPIF — TMR2IF TMR1IF 2

— LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 2

— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 2
— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 2
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 2

(1)

RA7

TRISA7

(1)

RA6

TRISA6

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 2

(1)

RA5 RA4 RA3 RA2 RA1 RA0 2

(1)

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 2

— 2

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 35

PIC18F87J93 FAMILY

NOTES:

DS39948A-page 36 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

3.0 SPECIAL FEATURES OF THE

CPU

Note 1: This section documents only the CPU

features that are di fferent from, or in addi­tion to, the features of the PIC18F87J90
family devices.

2: For additional details on the Configuration

bits, refer to Section 24.1 “Configuration

Bits” in the “PIC18F87J90 Family Data
Sheet” (DS39933).

3.1 Device ID Registers

The Device ID registers are “read-onl y” registers . They
identify the device type and revision for device
programmers and can be read by firmware using table
reads.

TABLE 3-1: DEVICE ID REGISTERS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 10x1

Legend: x = unknown, — = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset

states, the configuration bytes maintain their previously programmed states.

2: See Register 3-1 and Register 3-2 for DEVID values. These registers are read-only and cannot be programmed by

the user.

Default/

Unprogram med

Value

(1)

(2)
(2)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 37

PIC18F87J93 FAMILY

REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J93 FAMILY DEVICES

RRRRRRRR

DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

bit 7 bit 0

Legend:

R = Read-only bit

bit 7-5 DEV<2:0>: Device ID bits

111 = PIC18F87J93
110 = PIC18F86J93
011 = PIC18F67J93
010 = PIC18F66J93

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to indicate the device revision.

REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J93 FAMILY DEVICES

RRRRRRRR

DEV10

(1)

DEV9

(1)

DEV8

(1)

DEV7

(1)

DEV6

(1)

DEV5

(1)

DEV4

(1)

DEV3

(1)

bit 7 bit 0

Legend:

R = Read-only bit

bit 7-0 DEV<10:3>: Device ID bits

(1)

These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
0101 0000 = PIC18F87J93 family devices

Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always

identified by using the entire DEV<10:0> bit sequence.

DS39948A-page 38 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

4.0 ELECTRICAL CHARACTERISTICS

Note: Other than some basic data, this section docume nts only the PIC18F87J93 fam il y de vi ce s’ s pec ifi ca tio ns that

differ from those of the PIC18F87J90 family devices. For detailed information on the electrical specifications
shared by the PIC18F87J93 family and PIC18F87J90 family devices, see the “PIC18F87J90 Family Data
Sheet” (DS39933).

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +100°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any digital only I/O pin or MCLR
Voltage on any combined digital and analog pin with respect to V
Voltage on V
Voltage on V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of V
Maximum current into V

Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA

Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins..........................................................8 mA

Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins ............................2 mA

Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA

Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8 mA

Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins.......................2 mA

Maximum current sunk by all ports combined.......................................................................................................200 mA

Note 1: Power dissipation is calcu la t ed as follows :

DDCORE with respect to VSS...................................................................................................-0.3V to 2.75V

DD with respect to VSS ........................................................................................................... -0.3V to 3.6V

SS pin...........................................................................................................................300 mA

DD pin..............................................................................................................................250 mA

Pdis = V

DD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

(†)

with respect to VSS (except VDD) ...........................................-0.3V to 6.0V

SS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 39

PIC18F87J93 FAMILY

Frequency

Voltage (VDD)

4.0V

2.0V

48 MHz

3.5V

3.0V

2.5V

3.6V

2.35V

0

Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset

before V

DD reaches a level at which full-speed operation is not possible.

8 MHz

PIC18LF87J93 Family

Frequency

V oltage (VDDCORE)

3.00V

2.00V

48 MHz

2.75V

2.50V

2.25V

2.7V

8 MHz

2.35V

Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that

V

DDCORE ≤ VDD ≤ 3.6V.

PIC18LF87J93 Family

FIGURE 4-1: VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL)

(1)

FIGURE 4-2: VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL)

(1)

DS39948A-page 40 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T A B LE 4- 1 : A/D CONVERTER CHARA CTE RI STI C S:PIC18F87J93 FAMILY (INDUSTRIAL)

Param

A01 N
A03 E
A04 E
A06 E
A07 E
A10 — Monotonicity Guaranteed
A20 ΔVREF Reference Voltage Range

A21 V
A22 V
A25 V
A30 Z

A50 I

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

Sym Characteristic Min Typ Max Units Conditions

No.

R Resolution — — 12 bit ΔVREF ≥ 3.0V
IL Integral Linearity Error — <±1 ±2.0 LSB ΔVREF ≥ 3.0V
DL Differential Linearity Error — <±1 ±1.5 LSB ΔVREF ≥ 3.0V
OFF Offset Error — <±1 ±5 LSB ΔVREF ≥ 3.0V
GN Gain Error — <±1 ±3 LSB ΔVREF ≥ 3.0V

3—V

REFH – VREFL)

(V

REFH Reference Voltage High V SS + 3.0V — VDD + 0.3V V For 12-bit resolution

REFL Reference Voltage Low V SS – 0.3V — VDD – 3.0V V For 12-bit resolution
AIN Analog Input Voltage VREFL —VREFH V Note 2
AIN Recommended

——2.5kΩ

(1)

DD – VSS V For 12-bit resolution

—VSS ≤ VAIN ≤ VREF

Impedance of Analog
Voltage Source

REF VREF Input Current

2: V

REFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from

the RA2/AN2/V

(2)

REF-/CVREF pin or VSS, whichever is selected as the VREFL source.

—
—

—
—

5

150

μAμADuring V AIN acqui si tion.

During A/D conversion cycle.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 41

PIC18F87J93 FAMILY

131

130

132

BSF ADCON0, GO

Q4

A/D CLK

(1)

A/D DATA

ADRES

ADIF

GO

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

11 10 9 3 2 1

Note 1: If the A/D clock source is selected as RC, a time of T

CY is added before the A/D clock starts. This allows the SLEEP instruction

to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . .

. . .

TCY

0

FIGURE 4-3: A/D CONVERSION TIMING

TABLE 4-2: A/D CONVERSION REQUIREMENTS

Param

130 T
131 TCNV Conversion Time

132 TACQ Acquisition Time
135 TSWC Switching Time from Convert → Sample — (Note 4)
137 TDIS Discharge Time 0.2 — μs

Note 1: The time of the A/D clock period is dependent on the device frequency and the T

Symbol Characteristic Min Max Units Conditions

No.

AD A/D Clock Period 0.8 12.5

(not including acquisition time)

(3)

(2)

2: ADRES registers may be read on the following T

13 14 TAD

1.4 — μs

CY cycle.

(1)

μsTOSC based, VREF ≥ 3.0V

AD clock divider.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes f ull scale

after the conversion (V

DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.

DS39948A-page 42 Preliminary © 2009 Microchip Technology Inc.

5.0 PACKAGING INFORMATION

For packaging information, see the “PIC18F87J93
Family Data Sheet” (DS39933).

PIC18F87J93 FAMILY

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 43

PIC18F87J93 FAMILY

NOTES:

DS39948A-page 44 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

APPENDIX A: REVISI ON HISTORY

APPENDIX B: DEVICE

DIFFERENCES

Revision A (June 2009)

Original data sheet for PIC18F87J93 family devices.

TABLE B-1: PIC18F87J93 FAMILY DEVICE DIFFERENCES

Features PIC18F66J93 PIC18F67J93 PIC18F86J93 PIC18F87J93

Program Memory ( Byt es) 64K 128K 64K 128K
Program Memory (In st ru ct i ons ) 32768 65536 32768 65536
Interrupt Sources 28 28 29 29
I/O Ports Ports A, B, C, D, E,

F, G
Capture/Compare/PWM Modules2222
Enhanced

Capture/Compare/PWM Modules
Packages 64-Pin TQFP 64-Pin TQFP 80-Pin TQFP 80-Pin TQFP

3333

The differences between the devices listed in this data
sheet are shown in Table B-1.

Ports A, B, C, D, E,

F, G

Ports A, B, C, D, E,

F, G, H, J

Ports A, B, C, D, E,

F, G, H, J

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 45

PIC18F87J93 FAMILY

APPENDIX C: CONVERSION

CONSIDERATIONS

This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.

Not Applicable

APPENDIX D: MIGRATION FROM

BASELINE TO
ENHANCED DEVICES

This section di scusses how to migrate from a Baseline
device (such as the PIC16C5X) to an Enhanced MCU
device (such as the PIC18FXXX).

The following are the list of modifications over the
PIC16C5X microcontroller fam il y:

Not Currently Available

DS39948A-page 46 Preliminary © 2009 Microchip Technology Inc.

INDEX

PIC18F87J93 FAMILY

A

A/D

A/D Converter Interrupt, Conf ig u ring ..........................31

Acquisition Requirements ...........................................32

ADCAL Bit....................... .............. ............... ...............35

ADCON0 Register.......................................................27

ADCON1 Register.......................................................27

ADCON2 Register.......................................................27

ADRESH Register................................................. 27, 30

ADRESL Register.......................................................27

Analog Port Pins, Configur in g.............. .......................33

Associated Registers ....................................... ...........35

Configuring the Module...............................................31

Conversion Clock (T
Conversion Status (GO/DONE

Conversions................................................................34

Converter Calibration..................................................35

Converter Characteristics ...........................................41

Operation in Power-Managed Modes .........................35

Overview.....................................................................27

Selecting and Configuring Automatic

Acquisition Time.................. .............................. ..33

Special Event Trigger (CCP).......................................34

Use of the CCP2 Trigger.............................................34

Absolute Maximum Ratings ................................................39

ADCAL Bit........................................................ ............... ....35

ADCON0 Register...............................................................27

GO/DONE

ADCON1 Register...............................................................27

ADCON2 Register...............................................................27

ADRESH Register...............................................................27

ADRESL Register.........................................................27, 30

Analog-to-Digital Converter. See A/D.

Bit..............................................................30

AD)..............................................33

Bit).............................30

B

Block Diagrams

A/D..............................................................................30

Analog Input Model.....................................................31

PIC18F66J93/67J93.....................................................9

PIC18F86J93/87J93...................................................10

C

Compare (CCP Module)

Special Event Trigger..................................................34

Conversion Considerat io n s..................... ............................46

Customer Change Notification Service ...............................49

Customer Notification Service.............................................49

Customer Support...............................................................49

D

Device Differences..............................................................45

Device Overview

Detailed Features..........................................................7

Features (64-Pin Devic e s) ........................................ ....8

Features (80-Pin Devic e s) ........................................ ....8

Special Features...........................................................7

E

Electrical C h a ra c t e r i stics ................. ............. ............. ......... 3 9

Equations

A/D Acquisition Time..................................................32

A/D Minimum Charging Time...................................... 32

Calculating the Minimum Required

Acquisition Ti me .............. ............. ............. ......... 3 2

Errata....................................................................................6

F

Features Summary

Device Overview........................................................... 1

Flexible Oscillator Structure..........................................1

LCD Driver and Keypad Interface................................. 1

Low Power.................................................................... 1

Peripheral Highlights.....................................................1

Special Microcontroller Attributes .................................2

I

Internet Addres s.................................... .............................49

Interrupt Sources

A/D Conversion Complete.......................................... 31

M

Microchip Internet Web Site............... .............. ............... .... 49

Migration From Baseline to Enhanced Devices.................. 46

P

Packaging Informatio n.................. ............... ....................... 43

Pin Diagrams

PIC18F66J93/67J93..................................................... 3

PIC18F86J93/87J93..................................................... 4

Pin Functions

DD...........................................................................17

AV

DD...........................................................................26

AV
AV

SS...........................................................................17

SS...........................................................................26

AV

ENVREG ..................... .. ............. .............. ............ 17, 26

LCDBIAS3 .. ............. .............. ............. .................. 15, 2 2

...................................................................11, 18

MCLR

OSC1/CLKI/RA7...................................................11, 18

OSC2/CLKO/RA6.................................................11, 18

RA0/AN0....... .. ............. ............. .............. .............. 11, 18

RA1/AN1/S E G 1 8 ....... .. ............. .............. .............. 11, 18

RA2/AN2/V
RA3/AN3/V

RA4/T0CKI/SEG14...............................................11, 18

RA5/AN4/S E G 1 5 ....... .. ............. .............. .............. 11, 18

RB0/INT0/ S E G30 ........ .. ......................... .............. 12, 19

RB1/INT1/SEG8................................................... 12, 19

RB2/INT2/ SEG9/CTED1 ............. .............. ............ 12, 19

RB3/INT3/ S E G10/CTED2 ..................................... 12, 19

RB4/KBI0/S EG11 .................... ............. ................ 12, 19

RB5/KBI1/S EG29 .................... ............. ................ 12, 19

RB6/KBI2/PGC.....................................................12, 19

RB7/KBI3/PGD.....................................................12, 19

RC0/T1OS O /T13CKI ............. .. ............. ............. ... 13, 20

REF- ....................................................11, 18

REF+ ................................................... 11, 18

DS39948A-page 47 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

RC1/T1OSI/CCP2/SEG32....................................13, 20

RC2/CCP1/SEG13................................................13, 20

RC3/SCK/SCL/SEG17..........................................13, 20

RC4/SDI/SDA/SEG16...........................................13, 20

RC5/SDO/SEG12 .................................................13, 20

RC6/TX1/CK1/SEG27...........................................13, 20

RC7/RX1/DT1/SEG28 ..........................................13, 20

RD0/SEG0/CTPLS................................................14, 21

RD0/SEG1..................................................................14

RD1/SEG1..................................................................21

RD2/SEG2............................................................ 14, 21

RD3/SEG3............................................................ 14, 21

RD4/SEG4............................................................ 14, 21

RD5/SEG5............................................................ 14, 21

RD6/SEG6............................................................ 14, 21

RD7/SEG7............................................................ 14, 21

RE0/LCDBIAS1..................................................... 15, 22

RE1/LCDBIAS2..................................................... 15, 22

RE3/COM0............................................................15, 22

RE4/COM1............................................................15, 22

RE5/COM2............................................................15, 22

RE6/COM3............................................................15, 22

RE7/CCP2/SEG31................................................15, 22

RF1/AN6/C2OUT/SEG19 .....................................16, 23

RF2/AN7/C1OUT/SEG20 .....................................16, 23

RF3/AN8/SEG21/C2INB.......................................16, 23

RF4/AN9/SEG22/C2INA.......................................16, 23

RF5/AN10/CV

RF6/AN11/SEG24/C1INA.....................................16, 23

RF7/AN5/SS

RG0/LCDBIAS0....................................................17, 24

RG1/TX2/CK2....................................................... 17, 24

RG2/RX2/DT2/V
RG3/V

RG4/SEG26/RTCC...............................................17, 24

RH0/SEG47................................................................25

RH1/SEG46................................................................25

RH2/SEG45................................................................25

RH3/SEG44................................................................25

RH4/SEG40................................................................25

RH5/SEG41................................................................25

RH6/SEG42................................................................25

RH7/SEG43................................................................25

RJ0..............................................................................26

RJ1/SEG33.................................................................26

RJ2/SEG34.................................................................26

RJ3/SEG35.................................................................26

RJ4/SEG39.................................................................26

RJ5/SEG38.................................................................26

RJ6/SEG37.................................................................26

RJ7/SEG36.................................................................26

DD .............................................................................17

V
V

DD .............................................................................26

DDCORE/VCAP...................................................... 17, 26

V
V

SS..............................................................................17

SS..............................................................................26

V

REF/SEG23/C1INB.........................16, 23

/SEG25.............................................16, 23

LCAP1..........................................17, 24

LCAP2..........................................................17, 24

Pinout I/O Descriptions

PIC18F6XJ93.............................................................11

PIC18F8XJ93.............................................................18

Product Identification System .............................................51

R

Reader Response ............................................................... 50

Registers

ADCON0 (A/D Control 0)............................................ 27

ADCON1 (A/D Control 1)............................................ 28

ADCON2 (A/D Control 2)............................................ 29

DEVID1 (Device ID 1)................................................. 38

DEVID2 (Device ID 2)................................................. 38

Revision History.................................................................. 45

S

Special Features of the CPU .............................................. 37

T

Timing Diagrams

A/D Conversion...........................................................42

Timing Diagrams and Specifications

A/D Conversion Requirements ...................................42

V

Voltage-Frequency Graphs

Regulator Disabled, Industrial..................................... 40

Regulator Enabled, Industrial .....................................40

W

Worldwide Sales and Service Offices................................. 52

WWW Address................................................................... 49

WWW, On-Line Support....................................................... 6

DS39948A-page 48 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

THE MICROCHIP WEB SITE

Microchip provides onlin e support v ia our W WW site at
www.m ic roc hi p.c om . Thi s web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:

• Product Support – Data sheets and errata,

application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,
listing of s eminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

CUSTOMER SUPPORT

Users of Microchip products can receive assistance
through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line
Customers should contact their distributor,

representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.

T echnic al suppo rt is avail able throug h the web si te
at: http://support.microchip.com

Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified produ ct family or develo pment tool of inte rest.

To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 49

PIC18F87J93 FAMILY

To:

Technical Publications Manager

RE: Reader Response

Total Pages Sent ________

From:

Name
Company

Address
City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):
Would you like a reply? Y N

Device: Literature Number:
Questions:

FAX: (______) _________ - _________

DS39948APIC18F87J93 Family

READER RESPONSE

It is our intentio n to pro vi de you with the best docu mentation possib le to e ns ure suc c es sfu l u se of y ou r Mic r oc hip pro d­uct. If you wish to provid e your c omment s on org anizatio n, clarity, subject matter, a nd ways in whic h our doc umenta tion
can better serve you, please FAX your comments to the Technical Publications Manager at [phone].

Please list the following information, and use this outline to provide us with your comments about this document.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39948A-page 50 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

PART NO. X /XX XXX

PatternPackageTemperature

Range

Device

Device

(1,2)

PIC18F66J93, PIC18F66J93T
PIC18F67J93, PIC18F67J93T
PIC18F86J93, PIC18F86J93T
PIC18F87J93, PIC18F87J93T

Temperature Range I = -40°C to +85°C (Industrial)

Package PT =TQFP (Thin Quad F latpack)

Pattern QTP, SQTP, Code or Special Requirements

(blank otherwise)

Examples:

a) PIC18F87J93-I/PT 301 = Industrial temperature,

TQFP package, QTP pattern #301.

b) PIC18F87J93T-I/PT = T ape and reel, Industrial

temperature, TQFP package.

Note 1: F = Standard Voltage Range

2: T = In Tape and Reel

PRODUCT IDENTIFICATION SYSTEM

To order or obtain purchasing information such as pricing or delivery, refer to the factory or the listed sales office.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 51

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com

Atlanta

Duluth, GA
Tel: [phone]
Fax: [phone]

Boston

Westborough, MA
Tel: [phone]
Fax: [phone]

Chicago

Itasca, IL
Tel: [phone]
Fax: [phone]

Cleveland

Independence, OH
Tel: [phone]
Fax: [phone]

Dallas

Addison, TX
Tel: [phone]
Fax: [phone]

Detroit

Farmington Hills, MI
Tel: [phone]
Fax: [phone]

Kokomo

Kokomo, IN
Tel: [phone]
Fax: [phone]

Los Angeles

Mission Viejo, CA
Tel: [phone]
Fax: [phone]

Santa Clara

Santa Clara, CA
Tel: [phone]
Fax: [phone]

Toronto

Mississauga, Ontario,
Canada
Tel: [phone]
Fax: [phone]

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: [phone]
Fax: [phone]

Australia - Sydney

Tel: [phone]
Fax: [phone]

China - Beijing

Tel: [phone]
Fax: [phone]

China - Chengdu

Tel: [phone]
Fax: [phone]

China - Hong Kong SAR

Tel: [phone]
Fax: [phone]

China - Nanjing

Tel: [phone]
Fax: [phone]

China - Qingdao

Tel: [phone]
Fax: [phone]

China - Shanghai

Tel: [phone]
Fax: [phone]

China - Shenyang

Tel: [phone]
Fax: [phone]

China - Shenzhen

Tel: [phone]
Fax: [phone]

China - Wuhan

Tel: [phone]
Fax: [phone]

China - Xiamen

Tel: [phone]
Fax: [phone]

China - Xian

Tel: [phone]
Fax: [phone]

China - Zhuhai

Tel: [phone]
Fax: [phone]

ASIA/PACIFIC

India - Bangalore

Tel: [phone]
Fax: [phone]

India - New Delhi

Tel: [phone]
Fax: [phone]

India - Pune

Tel: [phone]
Fax: [phone]

Japan - Yokohama

Tel: [phone]
Fax: [phone]

Korea - Daegu

Tel: [phone]
Fax: [phone]

Korea - Seoul

Tel: [phone]
Fax: [phone] or
82-2-558-5934

Malaysia - Kuala Lumpur

Tel: [phone]
Fax: [phone]

Malaysia - Penang

Tel: [phone]
Fax: [phone]

Philippines - Manila

Tel: [phone]
Fax: [phone]

Singapore

Tel: [phone]
Fax: [phone]

Tai wan - Hsin Chu

Tel: [phone]
Fax: [phone]

Taiwan - Kaohsiung

Tel: [phone]
Fax: [phone]

Taiwan - Taipei

Tel: [phone]
Fax: [phone]

Thailand - Bangkok

Tel: [phone]
Fax: [phone]

EUROPE

Austria - Wels

Tel: [phone]
Fax: [phone]

Denmark - Copenhagen

Tel: [phone]
Fax: [phone]

France - Paris

Tel: [phone]
Fax: [phone]

Germany - Munich

Tel: [phone]
Fax: [phone]

Italy - Milan

Tel: [phone]
Fax: [phone]

Netherlands - Drunen

Tel: [phone]
Fax: [phone]

Spain - Madrid

Tel: [phone]
Fax: [phone]

UK - Wokingham

Tel: [phone]
Fax: [phone]

03/26/09

DS39948A-page 52 Preliminary © 2009 Microchip Technology Inc.