Datasheet PIC18F8722 Datasheet

PIC18F8722 Family

Data Sheet

64/80-Pin, 1-Mbit,

Enhanced Flash Microcontrollers

with 10-Bit A/D and nanoWatt Technology

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programmin g , IC SP, ICEPIC, Mindi, MiW i , MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC

32

logo, PowerCal, PowerInfo, PowerMate, PowerT ool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

PIC18F8722 FAMILY

64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with

10-Bit A/D and nanoWatt Technology

Power Management Features:

• Run: CPU On, Peripherals On

• Idle: CPU Off, Peripherals On

• Sleep: CPU Off, Peripherals Off

• Ultra Low 50 nA Input Leakage

• Run mode Currents Down to 25 μA Typical

• Idle mode Currents Dow n to 6.8μA Typical

• Sleep mode Current Down to 120 nA Typical

• Timer1 Oscillator: 900 nA, 32 kHz, 2V

• Watchdog Timer: 1.6 μA, 2V Typical

• Two-Speed Oscillator Start-up

Flexible Oscillator Struc ture:

• Four Crystal modes, up to 40 MHz

• 4x Phase Lock Loop (PLL) – Available for Crystal and Internal Oscillators

• Internal Oscillator Block:

- Fast wake from Sleep and Idle, 1 μs typical

- Provides a complete range of clock speeds

from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock stops

Peripheral Highlights:

• High-Current Sink/Source 25 mA/25 mA

• Three Programmable External Interrupts

• Four Input Change Interrupts

• Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only):

- One, two or four PWM outputs

- Programmable dead time

- Auto-shutdown and auto-restart

Peripheral Highlight s (Continued):

• Up to 2 Capture/Compare/PWM (CCP) modules, one with Auto-Shutdown (28-pin devices)

• Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I Master and Slave modes

• Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN/J2602

- RS-232 operation using internal oscillator

block (no external crystal required)

• 10-Bit, up to 13-Channel Analog-to-Digital (A/D) Converter module:

- Conversion available during Sleep

• Dual Analog Comparators with Input Multiplexing

• Programmable 16-Level High/Low-Voltage Detection (HLVD) module

2

C™

Special Microcontroller Features:

• C Compiler Optimized Arch itecture

• 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical

• 1,000,000 Erase/Write Cycle Data EEPROM Memory Typical

• Flash/Data EEPROM Retention: 100 Y ears Typical

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single-Supply 5V In-Circuit Se rial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Wide Operating Voltage Range: 2.0V to 5.5V

• Programmable Brown-out Reset (BOR) with Software Enable Option

Program Memory

Device

PIC18F6527 48K 24576 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6622 64K 32768 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6627 96K 49152 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6722 128K 65536 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F8527 48K 24576 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8622 64K 32768 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8627 96K 49152 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8722 128K 65536 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y

Flash

(bytes)

# Single-Word

Instructions

Data Memory

SRAM

EEPROM

(bytes)

I/O

10-Bit

A/D (ch)

CCP/

ECCP

(PWM)

MSSP

SPI

Master

2

C™

I

Timers

EUSART

Comparators

8/16-Bit

External Bus

PIC18F8722 FAMILY

Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

38 37 36 35 34 33

50 49

17 18 19 20 21 22 23 24 25 26

RE2/CS/P2B

RE3/P3C

RE4/P3B

RE5/P1C

RE6/P1B

RE7/ECCP2

(1)

/P2A

(1)

RD0/PSP0

VDDVSS

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4/SDO2

RD5/PSP5/SDI2/SDA2

RD6/PSP6/SCK2/SCL2

RD7/PSP7/SS2

RE1/WR/P2C

RE0/RD

/P2D

RG0/ECCP3/P3A

RG1/TX2/CK2

RG2/RX2/DT2 RG3/CCP4/P3D RG5/MCLR

/VPP

RG4/CCP5/P1D

VSS VDD

RF7/SS1

RF6/AN11

RF5/AN10/CV

REF

RF4/AN9 RF3/AN8

RF2/AN7/C1OUT

RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC V

SS

OSC2/CLKO/RA6 OSC1/CLKI/RA7 V

DD

RB7/KBI3/PGD

RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A

RF0/AN5

RF1/AN6/C2OUT

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1

RA0/AN0

V

SS

VDD

RA4/T0CKI

RA5/AN4/HLVDIN

RC1/T1OSI/ECCP2

(1)

/P2A

(1)

RC0/T1OSO/T13CKI

RC7/RX1/DT1

RC6/TX1/CK1

RC5/SDO1

15 16

31

40 39

27 28 29 30 32

48 47 46 45 44 43 42 41

54 53 52 5158 57 56 5560 5964 63 62 61

64-Pin TQFP

PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722

Pin Diagrams

PIC18F8527

3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41

40

39

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

RE2/AD10/CS/P2B

RE3/AD11/P3C

(2)

RE4/AD12/P3B

(2)

RE5/AD13/P1C

(2)

RE6/AD14/P1B

(2)

RE7/AD15/ECCP2

(1)

/P2A

(1)

RD0/AD0/PSP0

VDDVSS

RD1/AD1/PSP1

RD2/AD2/PSP2

RD3/AD3/PSP3

RD4/AD4/PSP4/SDO2

RD5/AD5/PSP5/SDI2/SDA2

RD6/AD6/PSP6/SCK2/SCL2

RD7/AD7/PSP7/SS2

RE1/AD9/WR/P2C

RE0/AD8/RD

/P2D

RG0/ECCP3/P3A

RG1/TX2/CK2

RG2/RX2/DT2 RG3/CCP4/P3D RG5/MCLR

/VPP

RG4/CCP5/P1D

V

SS

VDD

RF7/SS1

RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/ECCP2

(1)

/P2A

(1)

RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC V

SS

OSC2/CLKO/RA6 OSC1/CLKI/RA7 V

DD

RB7/KBI3/PGD

RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A

RF0/AN5

RF1/AN6/C2OUT

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1

RA0/AN0

V

SS

VDD

RA4/T0CKI

RA5/AN4/HLVDIN

RC1/T1OSI/ECCP2

(1)

/P2A

(1)

RC0/T1OSO/T13CKI

RC7/RX1/DT1

RC6/TX1/CK1

RC5/SDO1

RJ0/ALE

RJ1/OE

RH1/A17

RH0/A16

1 2

RH2/A18 RH3/A19

17 18

RH7/AN15/P1B

(2)

RH6/AN14/P1C

(2)

RH5/AN13/P3B

(2)

RH4/AN12/P3C

(2)

RJ5/CE

RJ4/BA0

37

RJ7/UB RJ6/LB

50 49

RJ2/WRL RJ3/WRH

19 20

33 34

35 36

38

58 57 56 55 54 53 52 51

60 59

68 67 66 6572 71 70 6974 7378 77 76 757980

80-Pin TQFP

Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings.

2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit.

RF5/AN10/CVREF

RF4/AN9 RF3/AN8

RF2/AN7/C1OUT

RF6/AN11

PIC18F8622 PIC18F8627 PIC18F8722

Pin Diagrams (Continued)

PIC18F8722 FAMILY

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, please contact the Marketing Communications Department via E-mail at docerrors@.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

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PIC18F8722 FAMILY

NOTES:

PIC18F8722 FAMILY

1.0 DEVICE OVERVIEW

This document co nta i ns dev ic e spec if i c in for m at ion fo r the following devices:

• PIC18F6527 • PIC18LF6527

• PIC18F6622 • PIC18LF6622

• PIC18F6627 • PIC18LF6627

• PIC18F6722 • PIC18LF6722

• PIC18F8527 • PIC18LF8527

• PIC18F8622 • PIC18LF8622

• PIC18F8627 • PIC18LF8627

• PIC18F8722 • PIC18LF8722

This family offers the advantages of all PIC18 microcontrollers – namely, high computa tional performance at an economical price – with the addition of highendurance, Enhanced Flash program memory . On top of these features, the PIC18F8722 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18 F8722 fami ly incorp orate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be significantly redu ce d.

• Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these st ates, powe r consumpt ion can be reduced even further.

• On-the-fly Mode Switching: The powermanaged modes a re invo ked b y user code durin g operation, allowing the user to incorporate powersaving ideas into their application’s software design.

• Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 28.0 “Electrical Characteristics” for values.

1.1.2 EXPANDED MEMORY

The PIC18F8722 family provides ample room for application code and includes members with 48, 64, 96 or 128 Kbytes of code space.

• Data RAM and Data EEPROM: The PIC18F872 2 family also p rov ide s ple nty o f room for applicati on data. The devices have 3936bytes of data RAM, as well as 1024 bytes of data EEPROM, for long term retention of nonvolatile data.

• Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles, up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

1.1.3 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F8722 family offer ten different osci llator option s, all owin g users a w ide range of choices in developing application hardware. These include:

• Four Crystal modes, using crystals or ceramic resonators

• Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same pin options as the External Clock modes

• An internal oscillator block which provides an 8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of 6 user selectable cl ock fre quenc ies, be tween 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier, available to both the high-speed crystal and internal oscillator m odes, which a llows clo ck speeds o f up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz – all without us ing an external crystal or clock circuit.

PIC18F8722 FAMILY

Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option co nst ant ly monitors the m ai n c l oc k source against a reference signal provide d by th e internal osci ll at or. If a cl oc k failure occu rs , t he co nt rol le r i s s witc h ed to th e internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

1.1.4 EXTERNAL MEMORY INTERFACE

In the unlikely event that 128 Kbytes of program memory is inadequate for an application, the PIC18F8527/8622/8627/8722 members of the family also implement an external memory interface. This allows the controller’s internal program counter to address a memory space of up to 2 Mbytes, permitting a level of data access that few 8-bit devices can claim.

With the addition of new operat ing mod es, the ext erna l memory interface offers many new options, including:

• Operating the microcontrol le r entirel y from external memory

• Using combinations of on-chip and external memory, up to the 2-Mbyte limit

• Using external Flash memory for reprogrammable application code or large data tables

• Using external RAM devices for storing large amounts of variable data

1.1.5 EASY MIGRATION

Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve.

The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. Thi s is true when mo ving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices.

1.2 Other Special Features

• Communications: The PIC18F8722 family incorporates a range of serial communication peripherals, including 2 independent Enhanced USARTs and 2 Master SSP modules capable of both SPI and I operation. Also, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications.

• CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and three Enhanced CCP (ECCP) modules to maximize flexibility in control applications. Up to four different time bases may be used to perform severa l di f fe rent operations at once. Each of the three ECCP modul es offer up to four PWM outputs, allowing for a total of 12 PWMs. The ECCPs also offer many beneficial features, including polarity selection, Programmable Dead-Time, Auto-Shutdown and Restart and Half-Bridge and Full-Bridge Output modes.

• Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected boot block at the top of program memory, it becomes possible to create an application that can update itself in the field.

• Extended Instruction Set: The PIC18F8722 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifi cally des igned to opti mize re-entrant applica tion code original ly deve loped in high-level language s, su ch as C.

• 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without w ait ing for a sampling period and thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This enhanced version in corpora tes a 16 -bit pre scale r, allowing an exte nded time-o ut rang e that is s ta ble across operating voltage and temperature. See Section 28.0 “Electrical Characteristics” for time-out periods.

2

C (Master and Slave) modes of

PIC18F8722 FAMILY

1.3 Details on Individual Family Members

Devices in the PIC18F8722 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in five ways:

1. Flash program memory (48 Kbytes for

PIC18F6527/8527 devices, 64 Kbytes for PIC18F6622/8622 devices, 96 Kbytes for PIC18F6627/8627 devices and 128 Kbytes for

All other features fo r device s in this family are identi cal. These are summarized in Table1-2 and Table 1-2.

The pinouts for all devices are listed in Table 1-3 and Table 1-4.

Like all Microchip PIC18 devices, members of the PIC18F8722 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F6627), accommodate an operating V

DD range of 4.2V to 5.5V. Low-voltage

parts, designated by “LF” (such as PIC18LF6627), function over an extended VDD range of 2.0V to 5.5V.

PIC18F6722/8722).

2. A/D channels (12 for 64-pin devices, 16 for

80-pin devices).

3. I/O ports (7 bidirectional por ts on 64-pin de vices,

9 bidirectional ports on 80-pin devices).

4. External Memory Bus, configurable for 8 and

16-bit operation, is available on PIC18F8527/ 8622/8627/8722 devices.

T ABLE 1-1: DEVICE FEATURES (PIC18F6527/6622/6627/6722)

Features PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Data Memory (Bytes) 3936 3936 3936 3936 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 Interrupt Sources 28282828 I/O Ports Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Timers 5 5 5 5 Capture/Co mp a re/PWM

Modules Enhanced Capture/Compare/

PWM Modules Enhanced USART 2 2 2 2 Serial Communications MSSP,

Parallel Communications (PSP) Y es Y es Ye s Yes 10-bit Analog-to-Digit al Modul e 12 Input Channels 12 Input Channels 12 In put Cha nnel s 12 Input Chann els Resets (and Delays) POR, BOR,

RESET Instruction,

Underflow (PWRT , OST),

MCLR

Programmable High/Low-Voltage Detect

Programmable Brown-out Reset

Instruction Set 75 Instructions;

Instruction Set enabled

Packages 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP

2222

3333

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

(optional), WDT

Yes Yes Yes Yes

83 with Extended

Stack Full, Stack

Underflow (PWRT , OST),

(optional), WDT

MCLR

75 Instructions;

83 with Exten ded

Instruction Set enabled

Underflow (PWRT , OST),

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

(optional), WDT

MCLR

75 Instructions;

83 with Extended

Instruction Set enabled

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT , OST),

(optional), WDT

MCLR

75 Instructions;

83 with Extended

Instruction Set enabled

PIC18F8722 FAMILY

TABLE 1-2: DEVICE FEATURES (PIC18F8527/8622/8627/8722)

Features PI C18 F8 527 PIC18F8622 PIC18F8627 PIC18F8722

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Data Memory (Bytes) 3936 3936 3936 3936 Data EEPROM Memo ry (Byte s) 1024 1024 1024 1024 Interrup t Sou r ce s 29 29 29 29 I/O Ports Ports A, B, C, D, E,

F, G, H, J Timers 5 5 5 5 Capture/Compare/PWM

Modules Enhanced Capture/Comp are/

PWM Modules Enhanced USART 2 2 2 2 Serial Communications MSSP,

Parallel Communications (PSP)

10-bit Analog-to-Digit al Modul e 16 Input Channels 16 Input Chann els 16 Input Channels 16 Input Channels Resets (and Delays) POR, BOR,

2222

3333

Enhanced USART

Yes Yes Yes Yes

RESET Instruction,

Stack Full, Stack

Underflow (PWRT , OST),

(optional), WDT

MCLR

Programmable High/Low-Voltage Detect

Programmable Brown-out Reset

Instruction Set 75 Instructions;

Instruction Set enabled

Packages 80-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP

Yes Yes Yes Yes

83 with Extended

Ports A, B, C, D, E,

F, G, H, J

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT , OST),

(optional), WDT

MCLR

75 Instructions;

83 with Extended

Instruction Set enabled

Ports A, B, C, D, E,

F, G, H, J

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT , OST),

(optional), WDT

MCLR

75 Instructions;

83 with Extended

Instruction Set e nabled

Ports A, B, C, D, E,

F, G, H, J

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT , OST),

(optional), WDT

MCLR

75 Instructions;

83 with Exten ded

Instruction Set enabled

PIC18F8722 FAMILY

Instruction

Decode and

Control

PORTA

Data Latch

Data Memory

(3.9Kbytes)

Address Latch

Data Address< 12>

12

Access

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

ALU<8>

Address Latch

Program Memory

(48/64/96/128

Data Latch

20

8

T able Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

Note 1: See Table 1-3 for I/O port pin descriptions.

2: RG5 is only available when MCLR

functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as

digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0

HLVD

ECCP1

BOR

ADC

10-bit

W

Instruction Bus <16>

STKPTR

Bank

8

State M achine Control Signals

Decode

8

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

V

SS

MCLR

(2)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

EUSART2

ECCP2

ROM Latch

ECCP3

MSSP2CCP4 CCP5

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1)

RC0:RC7

(1)

RD0:RD7

(1)

RE0:RE7

(1)

RF0:RF7

(1)

RG0:RG5

(1)

PORTB

RB0:RB7

(1)

Timer4

Kbytes)

FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM

PIC18F8722 FAMILY

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

ALU<8>

8

3

W

8

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

V

SS

MCLR

(2)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply Programming

In-Circuit

Debugger

T1OSI

T1OSO

Instruction

Decode &

Control

Data Latch

Data Memory

(3.9 Kbytes)

Address Lat ch

Data Address<12>

12

Access

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

4124

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

Address Latch

Program Memory

(48/64/96/ 128

Data Latch

20

T able Pointer<21>

inc/dec logic

21

8

Data Bus<8>

T able Latch

8

IR

12

ROM Latch

PCLATU

PCU

Instruction Bus <16>

STKPTR

Bank

State Machine Control Signals

Decode

System Bus Interface

AD15:AD0, A19:A16 (Multiplexed with PORTD, PORTE and PORTH)

PORTA

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1)

RC0:RC7

(1)

RD0:RD7

(1)

RE0:RE7

(1)

RF0:RF7

(1)

RG0:RG5

(1)

PORTB

RB0:RB7

(1)

PORTH

RH0:RH7

(1)

PORTJ

RJ0:RJ7

(1)

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0

HLVD

ECCP1

BOR

ADC

10-bit

EUSART2

ECCP2 ECCP3

MSSP2CCP4 CCP5

Timer4

Note 1: See Table 1-4 for I/O port pin descriptions.

2: RG5 is only available when MCLR

functionality is disabled.

3: OSC1/CLKI and OS C2/CLKO are only available i n sele ct os ci llat or mo des and when the s e p ins ar e no t be i ng u sed as

digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

Kbytes)

FIGURE 1-2: PIC18F8527/8622/8627/8722 (80-PI N) BLOCK DIAGRAM

PIC18F8722 FAMILY

T ABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

RG5/MCLR

RG5 MCLR

VPP

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2 CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

/VPP

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

39

40

7

I I

P

I

CMOS

I/O

O O

I/O

2

C™ = I2C/SMBus input buffer

Master Clear (input) or programming voltage (input). ST ST

ST

TTL

— —

TTL

Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

PIC18F8722 FAMILY

TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTA is a bidirectional I/O port.

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA2 AN2 V

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI

RA4 T0CKI

RA5/AN4/HLVDIN

RA5 AN4

HLVDIN RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

REF-

REF+

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

24

23

22

21

28

27

I/O

I

I/O

I

I/O

I I

I/O

I I

I/O

I

I/O

I I

2

TTL

Analog

TTL

Analog

TTL Analog Analog

ST ST

TTL Analog Analog

C™ = I2C/SMBus input buffer

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

Digital I/O. Timer0 external clock input.

Digital I/O. Analog input 4. High/Low-Voltage Detect input.

PIC18F8722 FAMILY

T ABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0

RB0 INT0 FLT0

Pin Number

TQFP

48

Type

I/O

I I

Buffer

Type

TTL

ST ST

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0. PWM Fault input for ECCPx.

RB1/INT1

RB1 INT1

RB2/INT2

RB2 INT2

RB3/INT3

RB3 INT3

RB4/KBI0

RB4 KBI0

RB5/KBI1/PGM

RB5 KBI1 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

47

46

45

44

43

42

37

I/O

I/O I/O

2

TTL

I

C™ = I2C/SMBus input buffer

ST

TTL

ST

TTL

ST

TTL TTL

ST

TTL TTL

ST

TTL TTL

ST

Digital I/O. External interrupt 1.

Digital I/O. External interrupt 2.

Digital I/O. External interrupt 3.

Digital I/O. Interrupt-on-change pin.

Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F8722 FAMILY

TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/ECCP2/P2A

RC1 T1OSI

(1)

ECCP2

(1)

P2A

RC2/ECCP1/P1A

RC2 ECCP1

P1A

RC3/SCK1/SCL1

RC3 SCK1 SCL1

RC4/SDI1/SDA1

RC4 SDI1 SDA1

RC5/SDO1

RC5 SDO1

30

29

33

34

35

36

I/O

O

I/O I/O

O

I/O I/O

O

I/O I/O I/O

I/O I/O

I/O

O

ST

—

I

ST

CMOS

ST

—

ST ST

—

ST ST ST

ST

—

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A.

Digital I/O. Enhanced Capture 1 input/Compare 1 output/ PWM 1 output. ECCP1 PWM output A.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchron ous serial clock input/ou tput for I

Digital I/O. SPI data in.

2

C data I/O.

I

Digital I/O. SPI data out.

2

C™ mode.

RC6/TX1/CK1

RC6 TX1 CK1

RC7/RX1/DT1

RC7 RX1 DT1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

31

32

I/O

O

I/O

I

I/O

2

C™ = I2C/SMBus input buffer

ST

—

ST

ST ST ST

Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1).

Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1).

PIC18F8722 FAMILY

T ABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/PSP0

RD0 PSP0

RD1/PSP1

RD1 PSP1

RD2/PSP2

RD2 PSP2

RD3/PSP3

RD3 PSP3

RD4/PSP4/SDO2

RD4 PSP4 SDO2

RD5/PSP5/SDI2/SDA2

RD5 PSP5 SDI2 SDA2

RD6/PSP6/SCK2/SCL2

RD6 PSP6 SCK2 SCL2

58

55

54

53

52

51

50

I/O I/O

O

I/O I/O

I/O

I/O I/O I/O I/O

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

—

ST

TTL

I

ST

2

C/SMB

I

ST

TTL

ST

2

I

C/SMB

Digital I/O. Parallel Slave Port data.

Digital I/O. Parallel Slave Port data. SPI data out.

Digital I/O. Parallel Slave Port data. SPI data in. I2C™ data I/O.

Digital I/O. Parallel Slave Port data. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode.

RD7/PSP7/SS2

RD7 PSP7 SS2

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

49

I/O I/O

I

2

C™ = I2C/SMBus input buffer

ST TTL TTL

Digital I/O. Parallel Slave Port data. SPI slave select input.

PIC18F8722 FAMILY

TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

RE0/RD

RE0 RD P2D

RE1/WR

RE1 WR P2C

RE2/CS

RE2 CS P2B

RE3/P3C

RE3 P3C

RE4/P3B

RE4 P3B

RE5/P1C

RE5 P1C

RE6/P1B

RE6 P1B

/P2D

/P2C

/P2B

64

63

62

61

60

2

I/O

I

O

1

I/O

I

O

I/O

I

O

I/O

O

I/O

O

I/O

O

I/O

O

ST

TTL

—

ST

TTL

—

ST

TTL

—

ST

—

ST

—

ST

—

ST

—

Digital I/O. Read control for Parallel Slave Port. ECCP2 PWM output D.

Digital I/O. Write control for Parallel Slave Port. ECCP2 PWM output C.

Digital I/O. Chip select control for Parallel Slave Port. ECCP2 PWM output B.

Digital I/O. ECCP3 PWM output C.

Digital I/O. ECCP3 PWM output B.

Digital I/O. ECCP1 PWM output C.

Digital I/O. ECCP1 PWM output B.

RE7/ECCP2/P2A

RE7

(2)

ECCP2

(2)

P2A

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

59

I/O I/O

O

2

C™ = I2C/SMBus input buffer

ST ST

—

Digital I/O. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A.

PIC18F8722 FAMILY

T ABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF0/AN5

RF0 AN5

RF1/AN6/C2OUT

RF1 AN6 C2OUT

RF2/AN7/C1OUT

RF2 AN7 C1OUT

RF3/AN8

RF3 AN8

RF4/AN9

RF4 AN9

RF5/AN10/CV

RF5 AN10 CVREF

RF6/AN11

RF6 AN11

REF

18

17

16

15

14

13

12

I/O

O

I/O

O

I/O

O

I/O

ST

I

Analog

ST

I

Analog

—

ST

I

Analog

—

ST

I

Analog

ST

I

Analog

ST

I

Analog Analog

ST

I

Analog

Digital I/O. Analog input 5.

Digital I/O. Analog input 6. Comparator 2 output.

Digital I/O. Analog input 7. Comparator 1 output.

Digital I/O. Analog input 8.

Digital I/O. Analog input 9.

Digital I/O. Analog input 10. Comparator reference voltage output.

Digital I/O. Analog input 11.

RF7/SS1

RF7 SS1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

11

I/O

I

2

C™ = I2C/SMBus input buffer

ST TTL

Digital I/O. SPI slave select input.

PIC18F8722 FAMILY

TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/ECCP3/P3A

RG0 ECCP3

P3A

RG1/TX2/CK2

RG1 TX2 CK2

RG2/RX2/DT2

RG2 RX2 DT2

RG3/CCP4/P3D

RG3 CCP4 P3D

RG4/CCP5/P1D

RG4 CCP5 P1D

RG5 See RG5/MCLR

SS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.

V VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins. AVSS 20 P — Ground reference for analog modules.

DD 19 P — Positive supply for analog modules.

AV Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Default assignment for ECCP2 when Conf iguration bit, CCP2MX, is set.

2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

3

I/O I/O

O

4

I/O

O

I/O

5

I/O

I

I/O

6

I/O I/O

O

8

I/O I/O

O

2

C™ = I2C/SMBus input buffer

ST ST

—

ST

—

ST

ST ST ST

ST ST

—

ST ST

—

Digital I/O. Enhanced Capture 3 input/Compare 3 output/ PWM 3 output. ECCP3 PWM output A.

Digital I/O. EUSART2 asynchronous transmit. EUSART2 synchronous clock (see related RX2/DT2).

Digital I/O. EUSART2 asynchronous receive. EUSART2 synchronous data (see related TX2/CK2).

Digital I/O. Capture 4 input/Compare 4 output/PWM 4 output. ECCP3 PWM output D.

Digital I/O. Capture 5 input/Compare 5 output/PWM 5 output. ECCP1 PWM output D.

/VPP pin.

PIC18F8722 FAMILY

T ABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

RG5/MCLR

RG5 MCLR

VPP

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2 CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

/VPP

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

49

50

9

I I

P

I

CMOS

I/O

O O

I/O

2

C™/SMB = I2C/SMBus input buffer

Master Clear (input) or programming voltage (input). ST ST

ST

TTL

— —

TTL

Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crysta l or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin out put s CLKO, whi ch has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

PIC18F8722 FAMILY

TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTA is a bidirectional I/O port.

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA2 AN2 V

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI

RA4 T0CKI

RA5/AN4/HLVDIN

RA5 AN4

HLVDIN RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

REF-

REF+

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

30

29

28

27

34

33

I/O

I/OIST/ODSTDigital I/O. Open-drain when configured as output.

I/O

TTL

I

Analog

TTL

I

Analog

TTL

I

Analog

I

Analog

TTL

I

Analog

I

Analog

TTL

I

Analog

I

Analog

2

C™/SMB = I2C/SMBus input buffer

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

Timer0 external clock input.

Digital I/O. Analog input 4. High/Low-Voltage Detect inpu t.

PIC18F8722 FAMILY

T ABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0

RB0 INT0 FLT0

Pin Number

TQFP

58

Type

I/O

I I

Buffer

Type

TTL

ST ST

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0. PWM Fault input for ECCPx.

RB1/INT1

RB1 INT1

RB2/INT2

RB2 INT2

RB3/INT3/ECCP2/P2A

RB3 INT3

(1)

ECCP2

(1)

P2A

RB4/KBI0

RB4 KBI0

RB5/KBI1/PGM

RB5 KBI1 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

57

56

55

54

53

52

47

I/O

O O

I/O

I/O I/O

TTL

I

2

ST

TTL

ST

TTL

ST

— —

TTL TTL

ST

TTL TTL

ST

TTL TTL

ST

C™/SMB = I2C/SMBus input buffer

Digital I/O. External interrupt 1.

Digital I/O. External interrupt 2.

Digital I/O. External interrupt 3. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output . ECCP2 PWM output A.

Digital I/O. Interrupt-on-change pin.

Digital I/O. Interrupt-on-change pin. Low-V o lt ag e ICSP™ Prog rammi ng ena ble pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F8722 FAMILY

TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI RC1/T1OSI/ECCP2/P2A

RC1

T1OSI

(2)

ECCP2

(2)

P2A RC2/ECCP1/P1A

RC2

ECCP1

P1A RC3/SCK1/SCL1

RC3

SCK1

SCL1 RC4/SDI1/SDA1

RC4

SDI1

SDA1 RC5/SDO1

RC5

SDO1 RC6/TX1/CK1

RC6

TX1

CK1

36

35

43

44

45

46

37

I/O

O

I/O I/O

O

I/O I/O

O

I/O I/O I/O

I/O I/O

I/O

O

I/O

O

I/O

ST

—

I

ST

CMOS

ST

—

ST ST

—

ST ST ST

ST

—

ST

—

ST

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output . ECCP2 PWM output A.

Digital I/O. Enhanced Capture 1 input/Compare 1 output/ PWM 1 output . ECCP1 PWM output A.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. SPI data in.

2

C data I/O.

I

Digital I/O. SPI data out.

Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1).

2

C™ mode.

RC7/RX1/DT1

RC7

RX1

DT1 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

38

I/O

I

I/O

2

ST ST ST

C™/SMB = I2C/SMBus input buffer

Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1).

PIC18F8722 FAMILY

T ABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/AD0/PSP0

RD0 AD0 PSP0

RD1/AD1/PSP1

RD1 AD1 PSP1

RD2/AD2/PSP2

RD2 AD2 PSP2

RD3/AD3/PSP3

RD3 AD3 PSP3

RD4/AD4/PSP4/SDO2

RD4 AD4 PSP4 SDO2

RD5/AD5/PSP5/ SDI2/SDA2

RD5 AD5 PSP5 SDI2 SDA2

RD6/AD6/PSP6/ SCK2/SCL2

RD6 AD6 PSP6 SCK2 SCL2

72

69

68

67

66

65

64

I/O I/O I/O

O

I/O I/O I/O

I/O

I/O I/O I/O I/O I/O

ST TTL TTL

—

ST TTL TTL

I

ST

2

C/SMB

I

ST TTL TTL

ST

2

C/SMB

I

Digital I/O. External memory address/data 0. Parallel Slave Port data.

Digital I/O. External memory address/data 1. Parallel Slave Port data.

Digital I/O. External memory address/data 2. Parallel Slave Port data.

Digital I/O. External memory address/data 3. Parallel Slave Port data.

Digital I/O. External memory address/data 4. Parallel Slave Port data. SPI data out.

Digital I/O. External memory address/data 5. Parallel Slave Port data. SPI data in.

2

C™ data I/O.

I

Digital I/O. External memory address/data 6. Parallel Slave Port data. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode.

RD7/AD7/PSP7/SS2

RD7 AD7 PSP7 SS2

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

63

I/O I/O I/O

I

2

ST TTL TTL TTL

C™/SMB = I2C/SMBus input buffer

Digital I/O. External memory address/data 7. Parallel Slave Port data. SPI slave select input.

PIC18F8722 FAMILY

TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

RE0/AD8/RD

RE0 AD8 RD P2D

RE1/AD9/WR

RE1 AD9 WR P2C

RE2/AD10/CS

RE2 AD10 CS P2B

RE3/AD11/P3C

RE3 AD11 P3C

RE4/AD12/P3B

RE4 AD12 P3B

RE5/AD13/P1C

RE5 AD13 P1C

/P2D

(4)

/P2C

/P2B

78

77

76

75

4

I/O I/O

I

O

3

I/O I/O

I

O

I/O I/O

I

O

I/O I/O

O

I/O I/O

O

I/O I/O

O

ST TTL TTL

—

ST TTL TTL

—

ST TTL TTL

—

ST TTL

—

ST TTL

—

ST TTL

—

Digital I/O. External memory address/data 8. Read control for Parallel Slave Port. ECCP2 PWM output D.

Digital I/O. External memory address/data 9. Write control for Parallel Slave Port. ECCP2 PWM output C.

Digital I/O. External memory address/data 10. Chip select control for Parallel Slave Port. ECCP2 PWM output B.

Digital I/O. External memory address/data 11. ECCP3 PWM output C.

Digital I/O. External memory address/data 12. ECCP3 PWM output B.

Digital I/O. External memory address/data 13. ECCP1 PWM output C.

RE6/AD14/P1B

RE6 AD14

(4)

P1B

RE7/AD15/ECCP2/P2A

RE7 AD15

(3)

ECCP2

(3)

P2A

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

74

73

I/O I/O

O

I/O I/O I/O

O

2

ST TTL

—

ST TTL

ST

—

C™/SMB = I2C/SMBus input buffer

Digital I/O. External memory address/data 14. ECCP1 PWM output B.

Digital I/O. External memory address/data 15. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A.

PIC18F8722 FAMILY

T ABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF0/AN5

RF0 AN5

RF1/AN6/C2OUT

RF1 AN6 C2OUT

RF2/AN7/C1OUT

RF2 AN7 C1OUT

RF3/AN8

RF3 AN8

RF4/AN9

RF4 AN9

RF5/AN10/CV

RF5 AN10 CVREF

RF6/AN11

RF6 AN11

REF

24

23

18

17

16

15

14

I/O

O

I/O

O

I/O

O

I/O

ST

I

Analog

ST

I

Analog

—

ST

I

Analog

—

ST

I

Analog

ST

I

Analog

ST

I

Analog Analog

ST

I

Analog

Digital I/O. Analog input 5.

Digital I/O. Analog input 6. Comparator 2 output.

Digital I/O. Analog input 7. Comparator 1 output.

Digital I/O. Analog input 8.

Digital I/O. Analog input 9.

Digital I/O. Analog input 10. Comparator reference voltage output.

Digital I/O. Analog input 11.

RF7/SS1

RF7 SS1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

13

I/O

I

2

ST

TTL

C™/SMB = I2C/SMBus input buffer

Digital I/O. SPI slave select input.

PIC18F8722 FAMILY

TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/ECCP3/P3A

RG0 ECCP3

P3A

RG1/TX2/CK2

RG1 TX2 CK2

RG2/RX2/DT2

RG2 RX2 DT2

RG3/CCP4/P3D

RG3 CCP4 P3D

RG4/CCP5/P1D

RG4 CCP5 P1D

RG5 See RG5/ MC LR Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P= Power I

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except

Microcontroller mode).

2: Default assignment fo r ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

10

5

I/O I/O

O

6

I/O

O

I/O

7

I/O

I

I/O

8

I/O I/O

O

I/O I/O

O

2

ST

—

ST

—

ST

—

ST

—

C™/SMB = I2C/SMBus input buffer

Digital I/O. Enhanced Capture 3 input/Compare 3 output/ PWM 3 output . ECCP3 PWM output A.

Digital I/O. EUSART2 asynchronous transmit. EUSART2 synchronous clock (see related RX2/DT2).

Digital I/O. EUSART2 asynchronous receive. EUSART2 synchronous data (see related TX2/CK2).

Digital I/O. Capture 4 input/Compare 4 output/PWM 4 output. ECCP3 PWM output D.

Digital I/O. Capture 5 input/Compare 5 output/PWM 5 output. ECCP1 PWM output D.

/VPP pin.

Datasheet PIC18F8722 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Power Management Features:

Flexible Oscillator Struc ture:

Peripheral Highlights:

Peripheral Highlight s (Continued):

Special Microcontroller Features:

Pin Diagrams

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

1.1.2 EXPANDED MEMORY

1.1.4 EXTERNAL MEMORY INTERFACE

1.1.5 EASY MIGRATION

1.2 Other Special Features

1.3 Details on Individual Family Members

T ABLE 1-1: DEVICE FEATURES (PIC18F6527/6622/6627/6722)

TABLE 1-2: DEVICE FEATURES (PIC18F8527/8622/8627/8722)

FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM

FIGURE 1-2: PIC18F8527/8622/8627/8722 (80-PI N) BLOCK DIAGRAM

T ABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS

T ABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS