Datasheet PIC18F66J93, PIC18F67J93, PIC18F86J93, PIC18F87J93 Datasheet

PIC18F87J93 Family

Data Sheet

64/80-Pin, High-Performance Microcontrollers

with LCD Driver, 12-Bit A/D

and nanoWatt Technology

© 2009 Microchip Technology Inc. Preliminary DS39948A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and t he lik e is provided only for your convenience
and may be su perseded by upda t es . It is y our responsibility to
ensure that your application meets with your specifications.
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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programmin g , IC SP, ICEPIC, Mindi , MiW i , MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
Omniscient Code Generation, PICC, PICC-18, PICkit,
PICDEM, PICDEM.net, PICtail, PIC

32

logo, REAL ICE, rfLAB,
Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS39948A-page ii Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

64/80-Pin, High-Performance Microcontrollers with

LCD Driver, 12-Bit A/D and nanoWatt Technology

LCD Driver and Keypad Interface Features:

• Direct LCD Panel Drive Capability:

- Can drive LCD panel while in Sleep mode

• Up to 48 Segments and 192 Pixels, Software
Selectable

• Programmable LCD Timing module:

- Multiple LCD timing sources available

- Up to four commons: static, 1/2, 1/3 or

1/4 multiplex

- Static, 1/2 or 1/3 bias configuration

• On-Chip LCD Boost Voltage Regulator for
Contrast Control

• Charge Time Measu rem ent Unit (C TMU) for
Capacitive Touch Sensing

• ADC for Resistive Touch Sensing

Low-Power Features:

• Power-Managed modes:

- Run: CPU On, Peripherals On

- Idle: CPU Off, Peripherals On

- Sleep: CPU Off, Peripherals Off

• Two-Speed Oscillator Start-up

Flexible Oscillator Struc ture:

• Two Crystal modes, 4-25 MHz

• Two External Clock modes, up to 48 MHz

• 4x Phase Lock Loop (PLL)

• Internal Oscillator Block with PLL:

- Eight user-selectable frequencies from

31.25 kHz to 8 MHz

• Secondary Oscillator using Timer1 at 32 kHz

• Fail-Safe Clock Monitor (FSCM):

- Allows for safe shutdown if peripheral clock fails

Peripheral Highlight s:

• High-Current Sink/Source 25 m A/25mA
(PORTB and PORTC)

• Up to Four External Interrupts

• Four 8-Bit/16-Bit Timer/Counter modules

• Two Capture/Compare/PWM (CCP) modules

• Master Synchronous Serial Port (MSSP) module
with Two Modes of Operation:

- 3-Wire/4-Wire SPI (supports all four SPI modes)

2

-I

C™ Master and Slave mode

• One Addressable USART module

• One Enhanced Addressable USAR T mod ule :

- LIN/J2602 support

- Auto-wake-up on Start bit and Break character

- Auto-Baud Detect (ABD)

• 12-Bit, up to 12-Channel A/D Converter:

- Auto-acquisition

- Conversion available during Sleep

• Two Analog Comparators

• Programmable Reference Voltage for Comparators

• Hardware Real-Time Clock and Calendar (RTCC)
with Clock, Calendar and Alarm Functions

• Charge Time Measurement Unit (CTMU):

- Capacitance measurement

- Time measuremen t with 1 ns typical resolution

Note: This document is supplemented by the

“PIC18F87J90 Family Data Sheet”

(DS39933). See Section 1.0 “Device
Overview”.

SPI

MSSP

Master

I

2

C™

EUSART

AUSART

12-Bit A/D

RTCC

(Channels)

BOR/LVD

Comparators

CTMU

Flash

Device

PIC18F66J93 64K 3,923 51 132 1/3 2 Y es Yes 1/1 12 2 Yes Yes Yes
PIC18F67J93 128K 3,923 51 132 1/3 2 Yes Yes 1/1 12 2 Yes Yes Yes
PIC18F86J93 64K 3,923 67 192 1/3 2 Y es Yes 1/1 12 2 Y es Yes Y es
PIC18F87J93 128K 3,923 67 192 1/3 2 Yes Yes 1/1 12 2 Yes Yes Yes

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 1

Program

Memory

(Bytes)

SRAM

Data

Memory

(Bytes)

I/O

LCD

(Pixels)

Timers

8/16-Bit

CCP

PIC18F87J93 FAMILY

Special Microcontroller Features:

• 10,000 Erase/Write Cycle Flash Program
Memory, T ypical

• Flash Retention 20 Years, Minimum

• Self-Programmable under Software Control

• Flash Program Memory has Word Write
Capability for Data EEPROM Emulators

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• In-Circuit Serial Programming™ (ICSP™) via
Two Pins

• In-Circuit Debug via Two Pins

• Operating Voltage Range: 2.0V to 3.6V

• 5.5V Tolerant Input (digital pins only)

• Selectable Open- Dr ain Conf igu rati on for Serial
Communication an d CCP Pins for Driving Output s
up to 5V

• On-Chip 2.5V Regulator

DS39948A-page 2 Preliminary © 2009 Microchip Technology Inc.

64-Pin TQFP

50 49

LCDBIAS3

RE3/COM0

RE4/COM1

RE5/COM2

RE6/COM3

RE7/CCP2

(1)

/SEG31

RD0/SEG0/CTPLS

V

DD

VSS

RD1/SEG1

RD2/SEG2

RD3/SEG3

RD4/SEG4

RD5/SEG5

RD6/SEG6

RD7/SEG7

RE1/LCDBIAS2
RE0/LCDBIAS1

RG0/LCDBIAS0

RG1/TX2/CK2

RG2/RX2/DT2/V

LCAP1

RG3/V

LCAP2

MCLR

RG4/SEG26/RTCC

VSS

VDDCORE/VCAP

RF7/AN5/SS/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CV

REF/SEG23/C1INB

RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB

RF2/AN7/C1OUT/SEG20

RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
V

SS

OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

DD

RB7/KBI3/PGD

RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13

ENVREG

RF1/AN6/C2OUT/SEG19

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1/SEG18

RA0/AN0

V

SS

VDD

RA4/T0CKI/SEG14

RA5/AN4/SEG15

RC1/T1OSI/CCP2

(1)

/SEG32

RC0/T1OSO/T13CKI

RC7/RX1/DT1/SEG28

RC6/TX1/CK1/SEG27

RC5/SDO/SEG12

54 53 52 5158 57 56 5560 59

64

63 62 61

Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting.

PIC18F66J93
PIC18F67J93

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 263127 28

29 30 32

38
37
36
35
34
33

40
39

48
47
46
45
44
43
42
41

Pin Diagrams – PIC18F6XJ93

PIC18F87J93 FAMILY

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 3

PIC18F87J93 FAMILY

80-Pin TQFP

3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41

40

39

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

LCDBIAS3

RE3/COM0

RE4/COM1

RE5/COM2

RE6/COM3

RE7/CCP2

(1)

/SEG31

RD0/SEG0/CTPLS

VDD

VSS

RD1/SEG1

RD2/SEG2

RD3/SEG3

RD4/SEG4

RD5/SEG5

RD6/SEG6

RD7/SEG7

RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0

RG1/TX2/CK2

RG2/RX2/DT2/V

LCAP1

RG3/V

LCAP2

MCLR

RG4/SEG26/RTCC

VSS

VDDCORE/VCAP

VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

DD

ENVREG

RF1/AN6/C2OUT/SEG19

AV

DD

AVSS

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1/SEG18

RA0/AN0

V

SS

VDD

RJ0

RJ1/SEG33

RH1/SEG46

RH0/SEG47

1
2

RH2/SEG45
RH3/SEG44

17

18
RH7/SEG43
RH6/SEG42

RH5/SEG41

RH4/SEG40

RJ5/SEG38

RJ4/SEG39

37

RJ7/SEG36
RJ6/SEG37

50
49

RJ2/SEG34
RJ3/SEG35

19

20

33 34

35 36

38

58
57
56
55
54
53
52
51

60
59

68 67 66 6572 71 70 6974 73

78

77 76 75

79

80

RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC

RB7/KBI3/PGD

RC2/CCP1/SEG13

RC5/SDO/SEG12

RA4/T0CKI/SEG14

RA5/AN4/SEG15

RC1/T1OSI/CCP2

(1)

I/SEG32

RC0/T1OSO/T13CKI

RC7/RX1/DT1/SEG28

RC6/TX1/CK1/SEG27

RF7/AN5/SS/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CV

REF/SEG23/C1INB

RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB

RF2/AN7/C1OUT/SEG20

RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17

Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting.

PIC18F86J93
PIC18F87J93

Pin Diagrams – PIC18F8XJ93

DS39948A-page 4 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 7

2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 27

3.0 Special Features of the CPU........................... .............. .............................. .............. ................................................................. 37

4.0 Electrical Characteristics............................................................................................................................................................39

5.0 Packaging Information... ............... .............. ............... .............................. .............. ..................................................................... 43

Appendix A: Revision History............................................................................................................................................................... 45

Appendix B: Device Differences .......................................................................................................................................................... 45

Appendix C: Conversion Considerations ............................................................................................................................................. 46

Appendix D: Migration From Baseline to Enhanced Devices .............................................................................................................. 46

Index .................................................................................................................................................................................................... 47

The Microchip Web Site.............. ............... ............... .............. ............... ............... .............. ................................................................. 49

Customer Change Notification Service ................................................................................................................................................ 49

Customer Support................................................................................................................................................................................49

Reader Response................................................................................................................................................................................ 50

Product Identification System.............................................................................................................................................................. 51

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 5

PIC18F87J93 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS39948A-page 6 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

1.0 DEVICE OVERVIEW

This document cont a ins dev ice -specific information for
the following devices:

• PIC18F66J93 • PIC18F67J93

• PIC18F86J93 • PIC18F87J93

Note: This data sheet documents only the devices’

features and specific ations that are in addi tion
to the features and specifications of the
PIC18F87J90 family devices. For information
on the features and specifications shared by
the PIC18F87J93 family and PIC18F87J90
family devices, see the “PIC18F87J90 Family
Data Sheet” (DS39933).

The PIC18F87J93 family of devices offers the
advantages of all PIC18 microcontrollers – high compu­tatio n al pe r fo rm a nc e, a rich fea ture set an d econ omica l
price – with the addition of a versatile, on-chip LCD
driver . These feat ures ma ke the PIC18 F87 J93 famil y a
logical choice for many high-performance applications
where price is a primary consideration.

1.1 Special Features

• 12-Bit A/D Converter: The PIC18F87J93 family
implements a 12-bit A/D converter. A/D converters
in both families incorporate programmable acquisi­tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting for
a sampling period and thus, reducing code

overhead.

• Data RAM: The PIC18F87J93 family devices have
3,923 bytes of RAM.

1.2 Details on Individual Family Members

Devices in the PIC18F87J93 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in the
following ways:

• Flash Program Memory (64 Kbytes for

PIC18FX6J93 devices and 128 Kbytes for
PIC18FX7J93).

• LCD Pixels:

- 64-pin devices – 132 pixels
(33 SEGs x 4 COMs)

- 80-pin devices – 192 pixels
(48 SEGs x 4 COMs)

• I/O Ports (seven bidirectional ports on
PIC18F6XJ93 devices and nine bidirection al ports
on PIC18F8XJ93 devices).

All other features for devic es in this fam il y ar e id enti ca l
and are summarized in Table 1-1 and Table 1-2.

The devices’ block diagrams are given in Figure 1-1
and Figure 1-2.

The pinouts for all devices are listed in Table 1-3 and
Table 1-4.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 7

PIC18F87J93 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XJ93 (64-PIN DEVICES)

Features PIC18F66J93 PIC18F67J93

Operating Frequency DC – 48 MHz
Program Memory (Bytes) 64K 128K
Program Memory (Instructions) 32,768 65,536
Data Memory (Bytes) 3,923 3,923
Interrupt Sources 29
I/O Ports Ports A, B, C, D , E, F, G
LCD Driver (available pixels to drive) 132 (33 SEGs x 4 COMs)
Timers 4
Comparators 2
CTMU Yes
RTCC Y es
Capture/Compare/PWM Modules 2
Serial Communications MSSP, Addressable USART, Enhanced USART
12-Bit Analog-to-Digital Module 12 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow , MCLR

(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 64-Pin TQFP

, WDT

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F8XJ93 (80-PIN DEVICES)

Features PIC18F86J93 PIC18F87J93

Operating Frequency DC – 48 MHz
Program Memory (Bytes) 64K 128K
Prog r a m M e m o r y ( I n s t r u c t i on s ) 32,768 65,536
Data Memory (Bytes) 3,923 3,923
Interrupt Sources 29
I/O Ports Ports A, B, C , D, E, F, G, H, J
LCD Driver (available pixels to drive) 192 (48 SEGs x 4 COMs)
Timers 4
Comparators 2
CTMU Yes
RTCC Y es
Capture/Compare/PWM Modules 2
Serial Communications MSSP, Addressable USART, Enhanced USART
12-Bit Analog-to-Digital Module 12 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow , MCLR

(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 80-Pin TQFP

, WDT

DS39948A-page 8 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

Instruction

Decode and

Control

PORTA

Data Latch

Data Memory

(2.0, 3.9

Address Latc h

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

Address Latch

Program Memory

(96 Kbytes)

Data Latch

20

8

8

T able Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

Note 1: See Table 1-3 for I/O port pin descriptions.

2: RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.

AUSART

Comparators

MSSP

Timer3Timer2 CTMUTimer1

CCP2

ADC

12-Bit

W

Instruction Bus <16>

STKPTR

Bank

8

State Machine
Control Signals

Decode

8

8

EUSART

ROM Latch

LCD

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1,2)

RC0:RC7

(1)

RD0:RD7

(1)

RE0:RE1,

RF1:RF7

(1)

RG0:RG4

(1)

PORTB

RB0:RB7

(1)

OSC1/CLKI

OSC2/CLKO

V

DD,

Timing

Generation

V

SS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

BOR and

LVD

(3)

Precision

Reference

Band Gap

INTRC

Oscillator

Regulator

Voltage

VDDCORE/VCAP

ENVREG

Kbytes)

Driver

8 MHz

Oscillator

RE3:RE7

(1)

Timer0

CCP1

RTCC

FIGURE 1-1: PIC18F6XJ93 (64-PIN) BLOCK DIAGRAM

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 9

PIC18F87J93 FAMILY

Instruction

Decode and

Control

Data Latch

Data Memory

(2.0, 3.9

Address Latc h

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

Address Latch

Program Memory

(96 Kbytes)
Data Latch

20

8

8

Table Po in t er <2 1 >

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

W

Instruction Bus <16>

STKPTR

Bank

8

State Machine
Control Signals

Decode

8

8

ROM Latch

OSC1/CLKI

OSC2/CLKO

V

DD,VSS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Precision

Reference

Band Gap

Regulator

Voltage

VDDCORE/VCAP

ENVREG

Kbytes)

PORTA

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7

(1,2)

RC0:RC7

(1)

RD0:RD7

(1)

RF1:RF7

(1)

RG0:RG4

(1)

PORTB

RB0:RB7

(1)

PORTH

RH0:RH7

(1)

PORTJ

RJ0:RJ7

(1)

Note 1: See Table1-3 for I/O port pin descriptions.

2: RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.

Timing

Generation

INTRC

Oscillator

8 MHz

Oscillator

RE0:RE1,

RE3:RE7

(1)

BOR and

LVD

(3)

AUSART

Comparators

MSSP

Timer3Timer2 CTMUTimer1

CCP2

ADC

12-Bit

EUSART

LCD

Driver

Timer0

CCP1

RTCC

FIGURE 1-2: PIC18F8XJ93 (80-PIN) BLOCK DIAGRAM

DS39948A-page 10 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

MCLR

OSC1/CLKI/RA7

OSC1
CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO

RA6

RA0/AN0

RA0
AN0

RA1/AN1/SEG18

RA1
AN1
SEG18

RA2/AN2/V

RA2
AN2
V

REF-

REF-

7 I ST Master Clear (input) or programming voltage (input). This

pin is an active-low Reset to the device.

39

40

24

23

22

I

CMOS

I

CMOS

I/O

O
O

I/O

I/OITTL

Analog

I/O

I

Analog

O

Analog

I/O

I

Analog

I

Analog

Oscillator crystal or external clock input.

Oscillator cryst al inp ut.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)

TTL

—
—

TTL

TTL

TTL

General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Osc ill ato r mode .
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog In put 0.

Digital I/O.
Analog In put 1.
SEG18 output for LCD.

Digital I/O.
Analog In put 2.
A/D reference voltage (l ow) input.

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/SEG14

RA4
T0CKI
SEG14

RA5/AN4/SEG15

RA5
AN4

SEG15
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

REF+

REF+

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

21

28

27

I/O

I/O

O

I/O

O

I
I

I

I

TTL
Analog
Analog

ST
ST

Analog

TTL
Analog
Analog

Digital I/O.
Analog In put 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.

Digital I/O.
Analog In put 4.
SEG15 output for LCD.

DD)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 11

PIC18F87J93 FAMILY

TABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/SEG30

RB0
INT0
SEG30

Pin Number

TQFP

48

Pin

Type

I/O

I

O

Buffer

Type

TTL

ST

Analog

Description

PORTB is a bidirectional I/O port. PORTB can be software
programme d for internal weak pull-ups on all inputs.

Digital I/O.
External Interrupt 0.
SEG30 output for LCD.

RB1/INT1/SEG8

RB1
INT1
SEG8

RB2/INT2/SEG9/CTED1

RB2
INT2
SEG9
CTED1

RB3/INT3/SEG10/CTED2

RB3
INT3
SEG10
CTED2

RB4/KBI0/SEG11

RB4
KBI0
SEG11

RB5/KBI1/SEG29

RB5
KBI1
SEG29

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

47

46

45

44

43

42

37

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O
I/O

I/O
I/O

I

I
I

I
I

I

I

I

I

TTL

ST

Analog

TTL

ST

Analog

ST

TTL

ST

Analog

ST

TTL
TTL

Analog

TTL
TTL

Analog

TTL
TTL

ST

TTL
TTL

ST

Digital I/O.
External Interrupt 1.
SEG8 output for LCD.

Digital I/O.
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.

Digital I/O.
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.

Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.

Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DD)

DS39948A-page 12 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/SEG32

RC1
T1OSI

(1)

CCP2
SEG32

RC2/CCP1/SEG13

RC2
CCP1
SEG13

RC3/SCK/SCL/SEG17

RC3
SCK
SCL
SEG17

RC4/SDI/SDA/SEG16

RC4
SDI
SDA
SEG16

RC5/SDO/SEG12

RC5
SDO
SEG12

30

29

33

34

35

36

I/O

O

I/O
I/O

O

I/O
I/O

O

I/O
I/O
I/O

O

I/O
I/O

O

I/O

O
O

I

I

I

ST

—

ST

ST

CMOS

ST

Analog

ST
ST

Analog

ST
ST
ST

Analog

ST
ST
ST

Analog

ST

—

Analog

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.

Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchron ous serial clock input/ou tput for I
SEG17 output for LCD.

Digital I/O.
SPI data in.

2

C data I/O.

I
SEG16 output for LCD.

Digital I/O.
SPI data out.
SEG12 output for LCD.

2

C™ mode.

RC6/TX1/CK1/SEG27

RC6
TX1
CK1
SEG27

RC7/RX1/DT1/SEG28

RC7
RX1
DT1
SEG28

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 13

31

32

I/O

O

I/O

O

I/O
I/O

O

I

ST

—

ST

Analog

ST
ST
ST

Analog

Digital I/O.
EUSART asynchronous transm it.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.

Digital I/O.
EUSART asynchronous rece iv e.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.

DD)

PIC18F87J93 FAMILY

TABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/SEG0/CTPLS

RD0
SEG0
CTPLS

RD1/SEG1

RD1
SEG1

RD2/SEG2

RD2
SEG2

RD3/SEG3

RD3
SEG3

RD4/SEG4

RD4
SEG4

RD5/SEG5

RD5
SEG5

RD6/SEG6

RD6
SEG6

RD7/SEG7

RD7
SEG7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

58

55

54

53

52

51

50

49

I/O

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

I/OOST

ST

O

Analog

O

—

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.

Digital I/O.
SEG1 output for LCD.

Digital I/O.
SEG2 output for LCD.

Digital I/O.
SEG3 output for LCD.

Digital I/O.
SEG4 output for LCD.

Digital I/O.
SEG5 output for LCD.

Digital I/O.
SEG6 output for LCD.

Digital I/O.
SEG7 output for LCD.

DD)

DS39948A-page 14 Preliminary © 2009 Microchip Technology Inc.

PIC18F87J93 FAMILY

T ABLE 1-3: PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

RE0/LCDBIAS1

RE0
LCDBIAS1

RE1/LCDBIAS2

RE1

LCDBIAS2
LCDBIAS3 64 I Analog BIAS3 input for LCD.
RE3/COM0

RE3

COM0
RE4/COM1

RE4

COM1
RE5/COM2

RE5

COM2
RE6/COM3

RE6

COM3
RE7/CCP2/SEG31

RE7

(2)

CCP2

SEG31
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

63

62

61

60

59

2

I/OIST

Analog

1

I/OIST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/O
I/O

ST
ST

O

Analog

Digital I/O.
BIAS1 input for LCD.

Digital I/O.
BIAS2 input for LCD.

Digital I/O.
COM0 output for LCD.

Digital I/O.
COM1 output for LCD.

Digital I/O.
COM2 output for LCD.

Digital I/O.
COM3 output for LCD.

Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.

DD)

© 2009 Microchip Technology Inc. Preliminary DS39948A-page 15