Page 1
PIC18F66K80 Family
Data Sheet
28/40/44/64-Pin, Enhanced Flash
Microcontrollers, with ECAN™
and nanoWatt XLP Technology
2011 Microchip Technology Inc. Preliminary DS39977C
Page 2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC
logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-851-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS39977C-page 2 Preliminary 2011 Microchip Technology Inc.
Page 3
PIC18F66K80 FAMILY
28/40/44/64-Pin, Enhanced Flash Microcontrol lers
with ECAN™ and nanoWatt XLP Technology
Power-Managed Modes:
• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
• Two-Speed Oscillator Start-up
• Fail-Safe Clock Monitor (FSCM)
• Power-Saving Peripheral Module Disable (PMD)
• Ultra Low-Power Wake-up
• Fast Wake-up, 1 s, Typical
• Low-Power WDT, 300 nA, Typical
• Run mode Currents Down to Very Low 3.8 A, Typical
• Idle mode Currents Down to Very Low 880 nA, Typical
• Sleep mode Current Down to Very Low 13 nA, Typical
ECAN Bus Module Features:
• Conforms to CAN 2.0B Active Specification
• Three Operating modes:
- Legacy mode (full backward compatibility with
existing PIC18CXX8/FXX8 CAN modules)
- Enhanced mode
- FIFO mode or programmable TX/RX buffers
• Message Bit Rates up to 1 Mbps
• DeviceNet™ Data Byte Filter Support
• Six Programmable Receive/Transmit Buffers
• Three Dedicated Transmit Buffers with Prioritization
• Two Dedicated Receive Buffers
TABLE 1: DEVICE COMPARISON
ECAN Bus Module Features (Continued):
• 16 Full, 29-Bit Acceptance Filters with Dynamic
Association
• Three Full, 29-Bit Acceptance Masks
• Automatic Remote Frame Handling
• Advanced Error Management Features
Special Microcontroller Features:
• Operating Voltage Range: 1.8V to 5.5V
• On-Chip 3.3V Regulator
• Operating Speed up to 64 MHz
• Up to 64 Kbytes On-Chip Flash Program Memory:
- 10,000 erase/write cycle, typical
- 20 years minimum retention, typical
• 1,024 Bytes of Data EEPROM:
- 100,000 Erase/write cycle data EEPROM
memory, typical
• 3.6 Kbytes of General Purpose Registers (SRAM)
• Three Internal Oscillators: LF-INTOSC (31 KHz),
MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz)
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 4,194s
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug via Two Pins
• Programmable BOR
• Programmable LVD
Device
PIC18F25K80 32 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF25K80 32 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F26K80 64 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF26K80 64 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F45K80 32 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF45K80 32 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F46K80 64 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF46K80 64 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F65K80 32 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
PIC18LF65K80 32 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
PIC18F66K80 64 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
PIC18LF66K80 64 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
2011 Microchip Technology Inc. Preliminary DS39977C-page 3
Program
Memory
Data
Memory
(Bytes)
Data EE
(Bytes)
Pins I/O
CCP/
CTMU
12-Bit A/D
ECCP
Timers
Channels
EUSART
8-Bit/16-Bit
Comparators
ECAN™
MSSP
BORMV/LVD
DSM
Page 4
PIC18F66K80 FAMILY
Peripheral Highlights:
• Five CCP/ECCP modules:
- Four Capture/Compare/PWM (CCP) modules
- One Enhanced Capture/Compare/PWM
(ECCP) module
• Five 8/16-Bit Timer/Counter modules:
- Timer0: 8/16-bit timer/counter with 8-bit
programmable prescaler
- Timer1, 3: 16-bit timer/counter
- Timer2, 4: 8-bit timer/counter
• Two Analog Comparators
• Configurable Reference Clock Output
• Charge Time Measurement Unit (CTMU):
- Capacitance measurement
- Time measurement with 1 ns typical resolution
- Integrated voltage reference
• High-Current Sink/Source 25 mA/25 mA (PORTB
and PORTC)
• Up to Four External Interrupts
• One Master Synchronous Serial Port
(MSSP) module:
- 3/4-wire SPI (supports all four SPI modes)
2
C™ Master and Slave modes
-I
• Two Enhanced Addressable USART modules:
- LIN/J2602 support
- Auto-Baud Detect (ABD)
• 12-Bit A/D Converter with up to 11 Channels:
- Auto-acquisition and Sleep operation
- Differential Input mode of operation
• Data Signal Modulator module:
- Select modulator and carrier sources from vari-
ous module outputs
• Integrated Voltage Reference
DS39977C-page 4 Preliminary 2011 Microchip Technology Inc.
Page 5
Pin Diagrams
RA1/AN1
RB3/CANRX/C2OUT/P1D/CTED2/INT3
RA2/V
REF-/AN2
V
DDCORE/VCAP
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI
OSC1/CLKIN/RA7
28-Pin QFN
(1)
1
2
3
4
7
5
6
21
20
19
18
15
17
16
28
272625
24
23
22
8
9
101112
13
14
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RB7/PGD/T3G/RX2/DT2/KBI3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F2XK80
PIC18LF2XK80
RA3/VREF+/AN3
V
SS
OSC2/CLKOUT/RA6
RB2/CANTX/C1OUT/P1C/CTED1/INT2
RB1/AN8/C1INB/P1B/CTDIN/INT1
RB0/AN10/C1INA/FLT0/INT0
V
DD
VSS
RC7/CANRX/RX1/DT1/CCP4
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/TX2/CK2/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
PIC18F66K80 FAMILY
2011 Microchip Technology Inc. Preliminary DS39977C-page 5
Page 6
PIC18F66K80 FAMILY
RA1/AN1
RB3/CANRX/C2OUT/P1D/CTED2/INT3
RA2/V
REF-/AN2
V
DDCORE/VCAP
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI
OSC1/CLKIN/RA7
28-Pin SSOP/SPDIP/SOIC
RB7/PGD/T3G/RX2/DT2/KBI31
2
3
4
7
5
6
8
9
10
11
14
12
13
19
18
15
17
16
24
23
20
22
21
25
26
27
28
PIC18F2XK80
PIC18LF2XK80
RA3/VREF+/AN3
V
SS
OSC2/CLKOUT/RA6
RB2/CANTX/C1OUT/P1C/CTED1/INT2
RB1/AN8/C1INB/P1B/CTDIN/INT1
RB0/AN10/C1INA/FLT0/INT0
V
DD
VSS
RC7/CANRX/RX1/DT1/CCP4
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/TX2/CK2/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
1
2
3
4
7
5
6
8
9
10
11
14
12
13
19
18
15
17
16
24
23
20
22
21
25
26
27
28
PIC18F4XK80
PIC18LF4XK80
40-Pin PDIP
MCLR/RE3
RA0/CV
REF/AN0/ULPWU
RC0/SOSCO/SCLKI
RC1/ISOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
32
31
30
29
33
34
35
36
37
38
39
40
MCLR/RE3
RA0/CV
REF/AN0/ULPWU
RA1/AN1/C1INC
RA2/V
REF-/AN2/C2INC
RA3/V
REF+/AN3
V
DDCORE/VCAP
RA5/AN4/HLVDIN/T1CKI/SS
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
VDD
VSS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RB3/CANRX/CTED2/INT3
RB7/PGD/T3G/KBI3
RB2/CANTX/CTED1/INT2
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
V
DD
VSS
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
RD7/RX2/DT2/P1D/PSP7
RD6/TX2/CK2/P1C/PSP6
RD5/P1B/PSP5
RD4/ECCP1/P1A/PSP4
RC7/CANRX/RX1/DT1/CCP4
RC6/CANTX/TX1/CK1/CCP3
RC5/SDO
RC4/SDA/SDI
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
Pin Diagrams (Continued)
DS39977C-page 6 Preliminary 2011 Microchip Technology Inc.
Page 7
44-Pin TQFP
RA1/AN1/C1INC
RB3/CANRX/CTED2/INT3
RA2/VREF-/AN2/C2INC
VDDCORE/VCAP
RA5/AN4/HLVDIN/T1CKI/SS
1
2
3
4
7
5
6
33
32
19
18
15
17
28
27
26
25
24
23
22
8
9
10
11
121314
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RB7/PGD/T3G/KBI3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F4XK80
PIC18LF4XK80
RA3/VREF+/AN3
VSS
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
V
SS
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
16
20
21
29
30
31
37
38
41
39
34
444342
40
36
35
RC7/CANRX/RX1/DT1/CCP4
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
RD6/TX2/CK2/P1C/PSP6
RD7/RX2/DT2/P1D/PSP7
V
DD
RB2/CANTX/CTED1/INT2
N/C
VDD
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
N/C
N/C
N/C
PIC18F66K80 FAMILY
Pin Diagrams (Continued)
2011 Microchip Technology Inc. Preliminary DS39977C-page 7
Page 8
PIC18F66K80 FAMILY
44-Pin QFN
(1)
Note 1: For the QFN package, it is recommended that the bottom pad be connected to V
SS.
RA1/AN1/C1INC
RB3/CANRX/CTED2/INT3
RA2/VREF-/AN2/C2INC
VDDCORE/VCAP
RA5/AN4/HLVDIN/T1CKI/SS
1
2
3
4
7
5
6
33
32
19
18
15
17
28
27
26
25
24
23
22
8
9
10
11
121314
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RB7/PGD/T3G/KBI3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F4XK80
PIC18LF4XK80
RA3/VREF+/AN3
VSS
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
V
SS
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
16
20
21
29
30
31
37
38
41
39
34
444342
40
36
35
RC7/CANRX/RX1/DT1/CCP4
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
RD6/TX2/CK2/P1C/PSP6
RD7/RX2/DT2/P1D/PSP7
V
DD
RB2/CANTX/CTED1/INT2
N/C
VDD
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
N/C
N/C
N/C
Pin Diagrams (Continued)
DS39977C-page 8 Preliminary 2011 Microchip Technology Inc.
Page 9
Pin Diagrams (Continued)
64-Pin QFN
(1)
/TQFP
RA1/AN1/C1INC
RB3/CANRX/CTED2/INT3
RA2/VREF-/AN2/C2INC
RA5/AN4/HLVDIN/T1CKI/SS
1
2
3
4
7
5
6
43
42
24
23
20
22
38
37
36
35
34
33
27
8
9
10
11
171819
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F6XK80
PIC18LF6XK80
RA3/VREF+/AN3
VSS
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
RC4/SDA/SDI
RC5/SDO
RC6/CCP3
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
21
25
26
39
40
41
57
58
61
59
54
646362
60
56
55
RC7/CCP4
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
RD6/P1C/PSP6
RD7/P1D/PSP7
AV
DD
RB2/CANTX/CTED1/INT2
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
RF0/MDMIN
12
13
14
15
16
29
28
32
30
31
48
47
44
45
46
52
53
49
51
50
RG0/RX1/DT1
RG1/CANTX2
V
DD
RG2/T3CKI
RG3/TX1/CK1
RG4/T0CKI
RF1
RE5/CANTX
V
DD
VSS
RE4/CANRX
VDDCORE/VCAP
RF2/MDCIN1
RF3
A
VDD
VDD
AVSS
VSS
RF4/MDCIN2
RF5
RF6/MDOUT
RF7
VSSVDD
RE6/RX2/DT2
RE7/TX2/CK2
RB7/PGD/T3G/KBI3
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
PIC18F66K80 FAMILY
2011 Microchip Technology Inc. Preliminary DS39977C-page 9
Page 10
PIC18F66K80 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers......................................................................................... 47
3.0 Oscillator Configurations ............................................................................................................................................................ 53
4.0 Power-Managed Modes ............................................................................................................................................................. 67
5.0 Reset.......................................................................................................................................................................................... 81
6.0 Memory Organization ............................................................................................................................................................... 105
7.0 Flash Program Memory............................................................................................................................................................ 135
8.0 Data EEPROM Memory ........................................................................................................................................................... 145
9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 151
10.0 Interrupts .................................................................................................................................................................................. 153
11.0 I/O Ports ................................................................................................................................................................................... 177
12.0 Data Signal Modulator .............................................................................................................................................................. 201
13.0 Timer0 Module ......................................................................................................................................................................... 211
14.0 Timer1 Module ......................................................................................................................................................................... 215
15.0 Timer2 Module ......................................................................................................................................................................... 227
16.0 Timer3 Module ......................................................................................................................................................................... 229
17.0 Timer4 Modules........................................................................................................................................................................ 239
18.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 241
19.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 259
20.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 271
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 293
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 339
23.0 12-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 363
24.0 Comparator Module.................................................................................................................................................................. 377
25.0 Comparator Voltage Reference Module ................................................................................................................................... 385
26.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 389
27.0 ECAN Module........................................................................................................................................................................... 395
28.0 Special Features of the CPU.................................................................................................................................................... 461
29.0 Instruction Set Summary.......................................................................................................................................................... 487
30.0 Development Support............................................................................................................................................................... 537
31.0 Electrical Characteristics.......................................................................................................................................................... 541
32.0 Packaging Information.............................................................................................................................................................. 589
Appendix A: Revision History............................................................................................................................................................. 609
Appendix B: Migration to PIC18F66K80 Family ................................................................................................................................. 609
Index ................................................................................................................................................................................................. 611
The Microchip Web Site..................................................................................................................................................................... 625
Customer Change Notification Service .............................................................................................................................................. 625
Customer Support .............................................................................................................................................................................. 625
Reader Response .............................................................................................................................................................................. 626
Product Identification System............................................................................................................................................................. 627
DS39977C-page 10 Preliminary 2011 Microchip Technology Inc.
Page 11
PIC18F66K80 FAMILY
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2011 Microchip Technology Inc. Preliminary DS39977C-page 11
Page 12
PIC18F66K80 FAMILY
NOTES:
DS39977C-page 12 Preliminary 2011 Microchip Technology Inc.
Page 13
PIC18F66K80 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F25K80 • PIC18LF25K80
• PIC18F26K80 • PIC18LF26K80
• PIC18F45K80 • PIC18LF45K80
• PIC18F46K80 • PIC18LF46K80
• PIC18F65K80 • PIC18LF65K80
• PIC18F66K80 • PIC18LF66K80
This family combines the traditional advantages of all
PIC18 microcontrollers – namely, high computational
performance and a rich feature set – with an extremely
competitive price point. These features make the
PIC18F66K80 family a logical choice for many
high-performance applications where price is a primary
consideration.
1.1 Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F66K80 family incorporate a range of features that can significantly reduce
power consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the Internal RC oscillator, power consumption during code execution
can be reduced.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further.
• On-the-Fly Mo de Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• nanoW at t XL P: An extra low-power BOR and
low-power Watchdog timer
1.1.2 OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F66K80 family offer
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• External Resistor/Capacitor (RC); RA6 available
• External Resistor/Capacitor with Clock Out
(RCIO)
• Three External Clock modes:
- External Clock (EC); RA6 available
- External Clock with Clock Out (ECIO)
- External Crystal (XT, HS, LP)
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes which
allows clock speeds of up to 64 MHz. PLL can
also be used with the internal oscillator.
• An internal oscillator block that provides a 16 MHz
clock (±2% accuracy) and an INTOSC source
(approximately 31 kHz, stable over temperature
DD)
and V
- Operates as HF-INTOSC or MF-INTOSC
when block is selected for 16 MHz or
500 kHz
- Frees the two oscillator pins for use as
additional general purpose I/O
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.3 MEMORY OPTIONS
The PIC18F66K80 family provides ample room for
application code, from 32 Kbytes to 64 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 10,000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
The Flash program memory is readable and writable.
During normal operation, the PIC18F66K80 family also
provides plenty of room for dynamic application data
with up to 3.6 Kbytes of data RAM.
1.1.4 EXTENDED INSTRUCTION SET
The PIC18F66K80 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
2011 Microchip Technology Inc. Preliminary DS39977C-page 13
Page 14
PIC18F66K80 FAMILY
1.1.5 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 28-pin,
40-pin, 44-pin and 64-pin members, or even jumping
from smaller to larger memory devices.
The PIC18F66K80 family is also largely pin compatible
with other PIC18 families, such as the PIC18F4580,
PIC18F4680, and PIC18F8680 families of microcontrollers with an ECAN module. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining a similar
feature set.
1.2 Other Special Features
• Communications: The PIC18F66K80 family incor-
porates a range of serial communication peripherals
including two Enhanced USART that support
LIN/J2602, one Master SSP module capable of both
SPI and I
operation and an Enhanced CAN module.
• CCP Modules: PIC18F66K80 family devices
incorporate four Capture/Compare/PWM (CCP)
modules. Up to four different time bases can be
used to perform several different operations at
once.
• ECCP Modules: The PIC18F66K80 family has
one Enhanced CCP (ECCP) module to maximize
flexibility in control applications:
- Up to four different time bases for performing
- Up to four PWM outputs
- Other beneficial features, such as polarity
• 12-Bit A/D Converter: The PIC18F66K80 family
has a differential ADC. It incorporates programmable acquisition time, allowing for a channel to
be selected and a conversion to be initiated
without waiting for a sampling period, and thus,
reducing code overhead.
2
C™ (Master and Slave) modes of
several different operations at once
selection, programmable dead time,
auto-shutdown and restart, and Half-Bridge
and Full-Bridge Output modes
• Charge Time Measurement Unit (CTMU): The
CTMU is a flexible analog module that provides
accurate differential time measurement between
pulse sources, as well as asynchronous pulse
generation.
Together with other on-chip analog modules, the
CTMU can precisely measure time, measure
capacitance or relative changes in capacitance, or
generate output pulses that are independent of the
system clock.
• LP Watchdog T im er (WDT): This enhanced
version incorporates a 22-bit prescaler, allowing
an extended time-out range that is stable across
operating voltage and temperature. See
Section 31.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family Members
Devices in the PIC18F66K80 family are available in
28-pin, 40/44-pin and 64-pin packages. Block diagrams
for each package are shown in Figure 1-1, Figure 1-2
and Figure 1-3, respectively.
The devices are differentiated from each other in these
ways:
• Flash Program Memory:
- PIC18FX5K80 (PIC18F25K80, PIC18F45K80
and PIC18F45K80) – 32 Kbytes
- PIC18FX6K80 (PIC18F26K80, PIC18F46K80
and PIC18F66K80) – 64 Kbytes
• I/O Ports:
- PIC18F2XK80 (28-pin devices) – Three
bidirectional ports
- PIC18F4XK80 (40/44-pin devices) – Five
bidirectional ports
- PIC18F6XK80 (64-pin devices) – Seven
bidirectional ports
All other features for devices in this family are identical.
These are summarized in Table 1-1, Tab le 1 -2 and
Table 1-3.
The pinouts for all devices are listed in Ta bl e 1 -4 ,
Table 1-5 and Tab le 1 -6 .
DS39977C-page 14 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XK80 (28-PIN DEVICES)
Features PIC18F25K80 PIC18F26K80
Operating Frequency DC – 64 MHz
Program Memory (Bytes) 32K 64K
Program Memory (Instructions) 16,384 32,768
Data Memory (Bytes) 3.6K
Interrupt Sources 31
I/O Ports Ports A, B, C
Parallel Communications Parallel Slave Port (PSP)
Timers Five
Comparators Two
CTMU Yes
Capture/Compare/PWM (CCP)
Modules
Enhanced CCP (ECCP) Modules One
Serial Communications One MSSP and Two Enhanced USARTs (EUSART)
12-Bit Analog-to-Digital Module Eight Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 28-Pin QFN-S, SOIC, SPDIP and SSOP
Four
WDT (PWRT, OST)
,
TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XK80 (40/44-PIN DEVICES)
Features PIC18F45K80 PIC18F46K80
Operating Frequency DC – 64 MHz
Program Memory (Bytes) 32K 64K
Program Memory (Instructions) 16,384 32,768
Data Memory (Bytes) 3.6K
Interrupt Sources 32
I/O Ports Ports A, B, C, D, E
Parallel Communications Parallel Slave Port (PSP)
Timers Five
Comparators Two
CTMU Yes
Capture/Compare/PWM (CCP)
Modules
Enhanced CCP (ECCP) Modules One
Serial Communications One MSSP and Two Enhanced USARTs (EUSART)
12-Bit Analog-to-Digital Module Eleven Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 40-Pin PDIP and 44-Pin QFN and TQFP
Four
WDT (PWRT, OST)
,
2011 Microchip Technology Inc. Preliminary DS39977C-page 15
Page 16
PIC18F66K80 FAMILY
TABLE 1-3: DEVICE FEATURES FOR THE PIC18F6XK80 (64-PIN DEVICES)
Features PIC18F65K80 PIC18F66K80
Operating Frequency DC – 64 MHz
Program Memory (Bytes) 32K 64K
Program Memory (Instructions) 16,384 32,768
Data Memory (Bytes) 3.6K
Interrupt Sources 32
I/O Ports Ports A, B, C, D, E, F, G
Parallel Communications Parallel Slave Port (PSP)
Timers Five
Comparators Two
CTMU Yes
Capture/Compare/PWM (CCP)
Modules
Enhanced CCP (ECCP) Modules One
DSM Yes Yes
Serial Communications One MSSP and Two Enhanced USARTs (EUSART)
12-Bit Analog-to-Digital Module Eleven Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 64-Pin QFN and TQFP
Four
WDT (PWRT, OST)
,
DS39977C-page 16 Preliminary 2011 Microchip Technology Inc.
Page 17
PIC18F66K80 FAMILY
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-4 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
ADC
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
RC0:RC7
(1)
PORTB
RB0:RB7
(1)
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Volt ag e
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
Timer 2/4
Timer 3
1/2
CCP2/3/4/5
ECCP1
PORTA
RA0:RA3
RA5:RA7
(1,2)
PORTE
RE3
(1,3)
ECAN
MSSP
FIGURE 1-1: PIC18F2XK80 (28-PIN) BLOCK DIAGRAM
2011 Microchip Technology Inc. Preliminary DS39977C-page 17
Page 18
PIC18F66K80 FAMILY
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-5 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
ADC
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
PORTD
RC0:RC7
(1)
RD0:RD7
(1)
PORTB
RB0:RB7
(1)
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Volt ag e
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
2/3/4/5
Timer2/4
Timer3
1/2
CCP
ECCP1
PORTA
RA0:RA3
RA5:RA7
(1,2)
PORTE
RE0:RE3
(1,3)
ECAN
PSP
MSSP
FIGURE 1-2: PIC18F4XK80 (40/44-PIN) BLOCK DIAGRAM
DS39977C-page 18 Preliminary 2011 Microchip Technology Inc.
Page 19
PIC18F66K80 FAMILY
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Ta b le 1 - 6 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section3.0 “Oscillator
Configurations”.
3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
ADC
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
PORTD
PORTF
PORTG
RC0:RC7
(1)
RD0:RD7
(1)
RF0:RF7
(1)
RG0:RG4
(1)
PORTB
RB0:RB7
(1)
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Time r
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Time r
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Vol tage
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
Timer2/4
Timer3
1/2
CCP2/3/4/5
ECCP1
PORTA
RA0:RA3
RA5:RA7
(1,2)
PORTE
RE0:RE7
(1,3)
ECAN
DSM
PSP
MSSP
FIGURE 1-3: PIC18F6XK80 (64-PIN) BLOCK DIAGRAM
2011 Microchip Technology Inc. Preliminary DS39977C-page 19
Page 20
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS
Pin Number
Pin
Buffer
Type
Type
I ST Master Clear (input) or programming voltage (input).This
pin is an active-low Reset to the device.
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
General purpose I/O pin.
CMOS
Connects to crystal or resonator in Crystal Oscillator mode.
has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
CMOS
2
C™ = I2C/SMBus input buffer
Description
Pin Name
MCLR/RE3 26 1
MCLR
RE3 I ST General purpose, input only pin.
OSC1/CLKIN/RA7 6 9
OSC1 I ST Oscillator crystal input.
CLKIN I CMOS External clock source input. Always associated with pin
RA7 I/O ST/
OSC2/CLKOUT/RA6 7 10
OSC2 O — Oscillator crystal output.
CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which
RA6 I/O ST/
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
QFN
SSOP/
SPDIP/
SOIC
DS39977C-page 20 Preliminary 2011 Microchip Technology Inc.
Page 21
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
RA0/CVREF/AN0/ULPWU 27 2
RA0 I/O ST/
REF O Analog Comparator reference voltage output.
CV
AN0 I Analog Analog Input 0.
ULPWU I Analog Ultra low-power wake-up input.
RA1/AN1 28 3
RA1 I/O ST/
AN1 I Analog Analog Input 1.
REF-/AN2 1 4
RA2/V
RA2 I/O ST/
V
REF- I Analog A/D reference voltage (low) input.
AN2 I Analog Analog Input 2.
RA3/VREF+/AN3 2 5
RA3 I/O ST/
REF+ I Analog A/D reference voltage (high) input.
V
AN3 I Analog Analog Input 3.
RA5/AN4/C2INB/HLVDIN/
T1CKI/SS
Legend: CMOS = CMOS compatible input or output I
/CTMUI
RA5 I/O ST/
AN4 I Analog Analog Input 4.
C2INB I Analog Comparator 2 Input B.
HLVDIN I Analog High/Low-Voltage Detect input.
T1CKI I ST Timer1 clock input.
SS
CTMUI CTMU pulse generator charger for the C2INB.
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
SSOP/
QFN
SPDIP/
SOIC
47
Buffer
Type
Type
PORTA is a bidirectional I/O port.
General purpose I/O pin.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
I ST SPI slave select input.
2
C™ = I2C/SMBus input buffer
Description
2011 Microchip Technology Inc. Preliminary DS39977C-page 21
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PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
RB0/AN10/C1INA/FLT0/
INT0
RB0 I/O ST/
AN10 I Analog Analog Input 10.
C1INA I Analog Comparator 1 Input A.
FLT0 I ST Enhanced PWM Fault input for ECCP1.
INT0 I ST External Interrupt 0.
RB1/AN8/C1INB/P1B/
CTDIN/INT1
RB1 I/O ST/
AN8 I Analog Analog Input 8.
C1INB I Analog Comparator 1 Input B.
P1B O CMOS Enhanced PWM1 Output B.
CTDIN I ST CTMU pulse delay input.
INT1 I ST External Interrupt 1.
RB2/CANTX/C1OUT/
P1C/CTED1/INT2
RB2 I/O ST/
CANTX O CMOS CAN bus TX.
C1OUT O CMOS Comparator 1 output.
P1C O CMOS Enhanced PWM1 Output C.
CTED1 I ST CTMU Edge 1 input.
INT2 I ST External Interrupt 2.
RB3/CANRX/C2OUT/
P1D/CTED2/INT3
RB3 I/O ST/
CANRX I ST CAN bus RX.
C2OUT O CMOS Comparator 2 output.
P1D O CMOS Enhanced PWM1 Output D.
CTED2 I ST CTMU Edge 2 input.
INT3 I ST External Interrupt 3.
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
SSOP/
QFN
SPDIP/
18 21
19 22
20 23
21 24
SOIC
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
Description
PORTB is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
2
C™ = I2C/SMBus input buffer
DS39977C-page 22 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
QFN
SSOP/
SPDIP/
SOIC
Type
Buffer
Type
Description
RB4/AN9/C2INA/ECCP1/
P1A/CTPLS/KBI0
RB4 I/O ST/
AN9 I Analog Analog Input 9.
C2INA I Analog Comparator 2 Input A.
ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
P1A O CMOS Enhanced PWM1 Output A.
CTPLS O ST CTMU pulse generator output.
KBI0 I ST Interrupt-on-change pin.
RB5/T0CKI/T3CKI/CCP5/
KBI1
RB5 I/O ST/
T0CKI I ST Timer0 external clock input.
T3CKI I ST Timer3 external clock input.
CCP5 I/O ST/
KBI1 I ST Interrupt-on-change pin.
RB6/PGC/TX2/CK2/KBI2 24 27
RB6 I/O ST/
PGC I ST In-Circuit Debugger and ICSP™ programming clock input
TX2 O CMOS EUSART asynchronous transmit.
CK2 I/O ST EUSART synchronous clock (see related RX2/DT2).
KBI2 I ST Interrupt-on-change pin.
RB7/PGD/T3G/RX2/DT2/
KBI3
RB7 I/O ST/
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.
T3G I ST Timer3 external clock gate input.
RX2 I ST EUSART asynchronous receive.
DT2 I/O ST EUSART synchronous data (see related TX2/CK2).
KBI3 I ST Interrupt-on-change pin.
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
22 25
23 26
25 28
CMOS
CMOS
CMOS
CMOS
CMOS
Digital I/O.
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
Digital I/O.
pin.
Digital I/O.
2
C™ = I2C/SMBus input buffer
2011 Microchip Technology Inc. Preliminary DS39977C-page 23
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PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
RC0/SOSCO/SCLKI 8 11
RC0 I/O ST/
SOSCO I ST Timer1 oscillator output.
SCLKI I ST Digital SOSC input.
RC1/SOSCI 9 12
RC1 I/O ST/
SOSCI I CMOS SOSC oscillator input.
RC2/T1G/CCP2 10 13
RC2 I/O ST/
T1G I ST Timer1 external clock gate input.
CCP2 I/O ST Capture 2 input/Compare 2 output/PWM2 output.
RC3/REFO/SCL/SCK 11 14
RC3 I/O ST/
REFO O — Reference clock out.
SCL I/O I
SCK I/O ST Synchronous serial clock input/output for SPI mode.
RC4/SDA/SDI 12 15
RC4 I/O ST/
SDA I/O I2CI2C data input/output.
SDI I ST SPI data in.
RC5/SDO 13 16
RC5 I/O ST/
SDO O CMOS SPI data out.
RC6/CANTX/TX1/CK1/
CCP3
RC6 I/O ST/
CANTX O CMOS CAN bus TX.
TX1 O CMOS EUSART asynchronous transmit.
CK1 I/O ST EUSART synchronous clock. (See related RX1/DT1.)
CCP3 I/O ST/
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
SSOP/
QFN
SPDIP/
14 17
SOIC
Type
Buffer
Type
PORTC is a bidirectional I/O port.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
2
C Synchronous serial clock input/output for I2C mode.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Capture 3 input/Compare 3 output/PWM3 output.
CMOS
2
C™ = I2C/SMBus input buffer
Description
DS39977C-page 24 Preliminary 2011 Microchip Technology Inc.
Page 25
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
QFN
SSOP/
SPDIP/
SOIC
Type
Buffer
Type
Description
RC7/CANRX/RX1/DT1/
CCP4
RC7 I/O ST/
CANRX I ST CAN bus RX.
RX1 I ST EUSART asynchronous receive.
DT1 I/O ST EUSART synchronous data (see related TX2/CK2).
CCP4 I/O ST
VSS 58P
VSS Ground reference for logic and I/O pins.
SS 16 19
V
VSS Ground reference for logic and I/O pins.
VDDCORE/VCAP 36P
DDCORE External filter capacitor connection.
V
VCAP External filter capacitor connection
VDD 17 20 P
DD Positive supply for logic and I/O pins.
V
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
15 18
CMOS
CMOS
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
2
C™ = I2C/SMBus input buffer
2011 Microchip Technology Inc. Preliminary DS39977C-page 25
Page 26
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
/RE3 1 18
MCLR
MCLR
RE3 I ST General purpose, input only pin.
OSC1/CLKIN/RA7 13 30
OSC1 I ST Oscillator crystal input.
CLKIN I CMOS External clock source input. Always associated with pin
RA7 I/O ST/
OSC2/CLKOUT/RA6 14 31
OSC2 O — Oscillator crystal output. Connects to crystal or resonator in
CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which
RA6 I/O ST/
Legend: I
2
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
QFN/
TQFP
Pin
Buffer
Type
Type
I ST Master Clear (input) or programming voltage (input).This
pin is an active-low Reset to the device.
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.
General purpose I/O pin.
CMOS
Crystal Oscillator mode.
has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
CMOS
Description
DS39977C-page 26 Preliminary 2011 Microchip Technology Inc.
Page 27
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RA0/CVREF/AN0/ULPWU 2 19
RA0 I/O ST/
CV
REF O Analog Comparator reference voltage output.
AN0 I Analog Analog Input 0.
ULPWU I Analog Ultra low-power wake-up input.
RA1/AN1/C1INC 3 20
RA1 I/O ST/
AN1 I Analog Analog Input 1.
C1INC I Analog Comparator 1 Input C.
REF-/AN2/C2INC 4 21
RA2/V
RA2 I/O ST/
V
REF- I Analog A/D reference voltage (low) input.
AN2 I Analog Analog Input 2.
C2INC I Analog Comparator 2 Input C.
REF+/AN3 5 22
RA3/V
RA3 I/O ST/
V
REF+ I Analog A/D reference voltage (high) input.
AN3 I Analog Analog Input 3.
RA5/AN4/HLVDIN/T1CKI/SS724
PDIP
QFN/
TQFP
Pin
Type
Buffer
Type
PORTA is a bidirectional I/O port.
General purpose I/O pin.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Description
RA5 I/O ST/
CMOS
AN4 I Analog Analog Input 4.
HLVDIN I Analog High/Low-Voltage Detect input.
T1CKI I ST Timer1 clock input.
SS
2
Legend: I
2011 Microchip Technology Inc. Preliminary DS39977C-page 27
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
I ST SPI slave select input.
Digital I/O.
Page 28
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB0/AN10/FLT0/INT0 33 8
RB0 I/O ST/
AN10 I Analog Analog Input 10.
FLT0 I ST Enhanced PWM Fault input for ECCP1.
INT0 I ST External Interrupt 0.
RB1/AN8/CTDIN/INT1 34 9
RB1 I/O ST/
AN8 I Analog Analog Input 8.
CTDIN I ST CTMU pulse delay input.
INT1 I ST External Interrupt 1.
RB2/CANTX/CTED1/
INT2
RB2 I/O ST/
CANTX O CMOS CAN bus TX.
CTED1 I ST CTMU Edge 1 input.
INT2 I ST External Interrupt 2.
RB3/CANRX/CTED2/
INT3
RB3 I/O ST/
CANRX I ST CAN bus RX.
CTED2 I ST CTMU Edge 2 input.
INT3 I ST External Interrupt 3.
RB4/AN9/CTPLS/KBI0 37 14
RB4 I/O ST/
AN9 I Analog Analog Input 9.
CTPLS O ST CTMU pulse generator output.
KBI0 I ST Interrupt-on-change pin.
RB5/T0CKI/T3CKI/CCP5/
KBI1
RB5 I/O ST/
T0CKI I ST Timer0 external clock input.
T3CKI I ST Timer3 external clock input.
CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output.
KBI1 I ST Interrupt-on-change pin.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
35 10
36 11
38 15
QFN/
TQFP
Pin
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTB is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
DS39977C-page 28 Preliminary 2011 Microchip Technology Inc.
Page 29
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB6/PGC/KBI2 39 16
RB6 I/O ST/
PGC I ST In-Circuit Debugger and ICSP™ programming clock input
KBI2 I ST Interrupt-on-change pin.
RB7/PGD/T3G/KBI3 40 17
RB7 I/O ST/
PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin.
T3G I ST Timer3 external clock gate input.
KBI3 I ST Interrupt-on-change pin.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
QFN/
TQFP
Pin
Type
Buffer
Type
CMOS
CMOS
Description
Digital I/O.
pin.
Digital I/O.
2011 Microchip Technology Inc. Preliminary DS39977C-page 29
Page 30
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC0/SOSCO/SCLKI 15 32
RC0 I/O ST/
SOSCO I ST SOSC oscillator output.
SCLKI I ST Digital SOSC input.
RC1/SOSCI 16 35
RC1 I/O ST/
SOSCI I CMOS SOSC oscillator input.
RC2/T1G/CCP2 17 36
RC2 I/O ST/
T1G I ST Timer1 external clock gate input.
CCP2 I/O ST/
RC3/REFO/SCL/SCK 18 37
RC3 I/O ST/
REFO O CMOS Reference clock out.
SCL I/O I
SCK I/O ST Synchronous serial clock input/output for SPI mode.
RC4/SDA/SDI 23 42
RC4 I/O ST/
SDA I/O I2CI2C data input/output.
SDI I ST SPI data in.
RC5/SDO 24 43
RC5 I/O ST/
SDO O CMOS SPI data out.
RC6/CANTX/TX1/CK1/
CCP3
RC6 I/O ST/
CANTX O CMOS CAN bus TX.
TX1 O CMOS EUSART synchronous transmit.
CK1 I/O ST EUSART synchronous clock (see related RX2/DT2).
CCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
25 44
QFN/
TQFP
Pin
Type
Buffer
Type
PORTC is a bidirectional I/O port.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Capture 2 input/Compare 2 output/PWM2 output.
CMOS
Digital I/O.
CMOS
2
C Synchronous serial clock input/output for I2C mode.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Description
DS39977C-page 30 Preliminary 2011 Microchip Technology Inc.
Page 31
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC7/CANRX/RX1/DT1/
CCP4
RC7 I/O ST/
CANRX I ST CAN bus RX.
RX1 I ST EUSART asynchronous receive.
DT1 I/O ST EUSART synchronous data (see related TX2/CK2).
CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
QFN/
TQFP
26 1
Pin
Type
Buffer
Type
CMOS
Description
Digital I/O.
2011 Microchip Technology Inc. Preliminary DS39977C-page 31
Page 32
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RD0/C1INA/PSP0 19 38
RD0 I/O ST/
C1INA I Analog Comparator 1 Input A.
PSP0 I/O ST/
RD1/C1INB/PSP1 20 39
RD1 I/O ST/
C1INB I Analog Comparator 1 Input B.
PSP1 I/O ST/
RD2/C2INA/PSP2 21 40
RD2 I/O ST/
C2INA I Analog Comparator 2 Input A.
PSP2 I/O ST/
RD3/C2INB/CTMUI/
PSP3
RD3 I/O ST/
C2INB I Analog Comparator 2 Input B.
CTMUI CTMU pulse generator charger for the C2INB.
PSP3 I/O ST/
RD4/ECCP1/P1A/PSP4 27 2
RD4 I/O ST/
ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
P1A O CMOS Enhanced PWM1 Output A.
PSP4 I/O ST/
RD5/P1B/PSP5 28 3
RD5 I/O ST/
P1B O CMOS Enhanced PWM1 Output B.
PSP5 I/O ST/
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
22 41
QFN/
TQFP
Pin
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTD is a bidirectional I/O port.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
DS39977C-page 32 Preliminary 2011 Microchip Technology Inc.
Page 33
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RD6/TX2/CK2/P1C/PSP6 29 4
RD6 I/O ST/
TX2 I ST EUSART asynchronous transmit.
CK2 I/O ST EUSART synchronous clock (see related RX2/DT2).
P1C O CMOS Enhanced PWM1 Output C.
PSP6 I/O ST/
RD7/RX2/DT2/P1D/PSP7 30 5
RD7 I/O ST/
RX2 I ST EUSART asynchronous receive.
DT2 I/O ST EUSART synchronous data (see related TX2/CK2).
P1D O CMOS Enhanced PWM1 Output D.
PSP7 I/O ST/
RE0/AN5/RD
RE0 I/O ST/
AN5 I Analog Analog Input 5.
RD I ST Parallel Slave Port read strobe.
RE1/AN6/C1OUT/WR
RE1 I/O ST/
AN6 I Analog Analog Input 6.
C1OUT O CMOS Comparator 1 output.
WR I ST Parallel Slave Port write strobe.
RE2/AN7/C2OUT/CS
RE2 I/O ST/
AN7 I Analog Analog Input 7.
C2OUT O CMOS Comparator 2 output.
CS
RE3 See the MCLR
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
QFN/
TQFP
825
926
10 27
Pin
Buffer
Type
Type
Digital I/O.
CMOS
Parallel Slave Port data.
CMOS
Digital I/O.
CMOS
Parallel Slave Port data.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
I ST Parallel Slave Port chip select.
/RE3 pin.
Description
2011 Microchip Technology Inc. Preliminary DS39977C-page 33
Page 34
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
VSS 12 29 P
VSS Ground reference for logic and I/O pins.
VSS 31 6
SS Ground reference for logic and I/O pins.
V
VDDCORE/VCAP 623P
VDDCORE External filter capacitor connection
CAP External filter capacitor connection
V
VDD 11 28 P
VDD Positive supply for logic and I/O pins.
DD 327P
V
V
DD Positive supply for logic and I/O pins.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
QFN/
TQFP
Pin
Type
Buffer
Type
Description
DS39977C-page 34 Preliminary 2011 Microchip Technology Inc.
Page 35
PIC18F66K80 FAMILY
T ABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS
Pin
Pin
Pin Name
/RE3 28
MCLR
MCLR
RE3 I ST General purpose, input only pin.
OSC1/CLKIN/RA7 46
OSC1 I ST Oscillator crystal input.
CLKIN I CMOS External clock source input. Always associated with pin function,
RA7 I/O ST/
OSC2/CLKOUT/RA6 47
OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal
CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4
RA6 I/O ST/
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
Type
Buffer
Type
I ST Master Clear (input) or programming voltage (input).This pin is an
active-low Reset to the device.
OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
General purpose I/O pin.
CMOS
Oscillator mode.
the frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
CMOS
Description
2011 Microchip Technology Inc. Preliminary DS39977C-page 35
Page 36
PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RA0/CVREF/AN0/
ULPWU
RA0 I/O ST/
CVREF O Analog Comparator reference voltage output.
AN0 I Analog Analog Input 0.
ULPWU I Analog Ultra low-power wake-up input.
RA1/AN1/C1INC 30
RA1 I/O ST/
AN1 I Analog Analog Input 1.
C1INC I Analog Comparator 1 Input C.
REF-/AN2/C2INC 31
RA2/V
RA2 I/O ST/
V
REF- I Analog A/D reference voltage (low) input.
AN2 I Analog Analog Input 2.
C2INC I Analog Comparator 2 Input C.
REF+/AN3 32
RA3/V
RA3 I/O ST/
V
REF+ I Analog A/D reference voltage (high) input.
AN3 I Analog Analog Input 3.
RA5/AN4/HLVDIN/
T1CKI/SS
RA5 I/O ST/
AN4 I Analog Analog Input 4.
HLVDIN I Analog High/Low-Voltage Detect input.
T1CKI I ST Timer1 clock input.
SS
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
29
34
Buffer
Type
Type
PORTA is a bidirectional I/O port.
General purpose I/O pin.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
I ST SPI slave select input.
Description
DS39977C-page 36 Preliminary 2011 Microchip Technology Inc.
Page 37
PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RB0/AN10/FLT0/INT0 13
RB0 I/O ST/
AN10 I Analog Analog Input 10.
FLT0 I ST Enhanced PWM Fault input for ECCP1.
INT0 I ST External Interrupt 0.
RB1/AN8/CTDIN/INT1 14
RB1 I/O ST/
AN8 I Analog Analog Input 8.
CTDIN I ST CTMU pulse delay input.
INT1 I ST External Interrupt 1.
RB2/CANTX/CTED1/
INT2
RB2 I/O ST/
CANTX O CMOS CAN bus TX.
CTED1 I ST CTMU Edge 1 input.
INT2 I ST External Interrupt 2.
RB3/CANRX/CTED2/
INT3
RB3 I/O ST/
CANRX I ST CAN bus RX.
CTED2 I ST CTMU Edge 2 input.
INT3 I ST External Interrupt 3.
RB4/AN9/CTPLS/KBI0 20
RB4 I/O ST/
AN9 I Analog Analog Input 9.
CTPLS O ST CTMU pulse generator output.
KBI0 I ST Interrupt-on-change pin.
RB5/T0CKI/T3CKI/CCP5/
KBI1
RB5 I/O ST/
T0CKI I ST Timer0 external clock input.
T3CKI I ST Timer3 external clock input.
CCP5 I/O ST/
KBI1 I ST Interrupt-on-change pin.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
15
16
21
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTB is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
2011 Microchip Technology Inc. Preliminary DS39977C-page 37
Page 38
PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RB6/PGC/KBI2 22
RB6 I/O ST/
PGC I ST In-Circuit Debugger and ICSP™ programming clock input pin.
KBI2 I ST Interrupt-on-change pin.
RB7/PGD/T3G/KBI3 23
RB7 I/O ST/
PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin.
T3G I ST Timer3 external clock gate input.
KBI3 I ST Interrupt-on-change pin.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
Type
Buffer
Type
CMOS
CMOS
Description
Digital I/O.
Digital I/O.
DS39977C-page 38 Preliminary 2011 Microchip Technology Inc.
Page 39
PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RC0/SOSCO/SCLKI 48
RC0 I/O ST/
SOSCO I ST Timer1 oscillator output.
SCLKI I ST Digital SOSC input.
RC1/SOSCI 49
RC1 I/O ST/
SOSCI I CMOS SOSC oscillator input.
RC2/T1G/CCP2 50
RC2 I/O ST/
T1G I ST Timer1 external clock gate input.
CCP2 I/O ST Capture 2 input/Compare 2 output/PWM2 output.
RC3/REFO/SCL/SCK 51
RC3 I/O ST/
REFO O CMOS Reference clock out.
SCL I/O I
SCK I/O ST Synchronous serial clock input/output for SPI mode.
RC4/SDA/SDI 62
RC4 I/O ST/
SDA I/O I2CI2C data input/output.
SDI I ST SPI data in.
RC5/SDO 63
RC5 I/O ST/
SDO O CMOS SPI data out.
RC6/CCP3 64
RC6 I/O ST/
CCP3 I/O ST/
RC7/CCP4 1
RC7 I/O ST/
CCP4 I/O ST/
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
Type
Buffer
Type
PORTC is a bidirectional I/O port.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
2
C Synchronous serial clock input/output for I2C mode.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Capture 3 input/Compare 3 output/PWM3 output.
CMOS
Digital I/O.
CMOS
Capture 4 input/Compare 4 output/PWM4 output.
CMOS
Description
2011 Microchip Technology Inc. Preliminary DS39977C-page 39
Page 40
PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RD0/C1INA/PSP0 54
RD0 I/O ST/
C1INA I Analog Comparator 1 Input A.
PSP0 I/O ST/
RD1/C1INB/PSP1 55
RD1 I/O ST/
C1INB I Analog Comparator 1 Input B.
PSP1 I/O ST/
RD2/C2INA/PSP2 58
RD2 I/O ST/
C2INA I Analog Comparator 2 Input A.
PSP2 I/O ST/
RD3/C2INB/CTMUI/
PSP3
RD3 I/O ST/
C2INB I Analog Comparator 2 Input B.
CTMUI O CMOS CTMU pulse generator charger for the C2INB.
PSP3 I/O ST/
RD4/ECCP1/P1A/PSP4 2
RD4 I/O ST/
ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
P1A O CMOS Enhanced PWM1 Output A.
PSP4 I/O ST/
RD5/P1B/PSP5 3
RD5 I/O ST/
P1B O CMOS Enhanced PWM1 Output B.
PSP5 I/O ST/
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
59
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTD is a bidirectional I/O port.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
DS39977C-page 40 Preliminary 2011 Microchip Technology Inc.
Page 41
PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RD6/P1C/PSP6 4
RD6 I/O ST/
P1C O CMOS Enhanced PWM1 Output C.
PSP6 I/O ST/
RD7/P1D/PSP7 5
RD7 I/O ST/
P1D O CMOS Enhanced PWM1 Output D.
PSP7 I/O ST/
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
Description
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
2011 Microchip Technology Inc. Preliminary DS39977C-page 41
Page 42
PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RE0/AN5/RD
RE0 I/O ST/
AN5 I Analog Analog Input 5.
RD I ST Parallel Slave Port read strobe.
RE1/AN6/C1OUT/WR
RE1 I/O ST/
AN6 I Analog Analog Input 6.
C1OUT O CMOS Comparator 1 output.
WR I ST Parallel Slave Port write strobe.
RE2/AN7/C2OUT/CS
RE2 I/O ST/
AN7 I Analog Analog Input 7.
C2OUT O CMOS Comparator 2 output.
CS I ST Parallel Slave Port chip select.
RE3 See the MCLR
RE4/CANRX 27
RE4 I/O ST/
CANRX I ST CAN bus RX.
RE5/CANTX 24
RE5 I/O ST/
CANTX O CMOS CAN bus TX.
RE6/RX2/DT2 60
RE6 I/O ST/
RX2 I ST EUSART asynchronous receive.
DT2 I/O ST EUSART synchronous data (see related TX2/CK2).
RE7/TX2/CK2 61
RE7 I/O ST/
TX2 O CMOS EUSART asynchronous transmit.
CK2 I/O ST EUSART synchronous clock (see related RX2/DT2).
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
37
38
39
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTE is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
/RE3 pin.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
DS39977C-page 42 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RF0/MDMIN 17
RF0 I/O ST/
MDMIN I CMOS Modulator source input.
RF1 19
RF1 I/O ST/
RF2/MDCIN1 35
RF2 I/O ST/
MDCIN1 I ST Modulator Carrier Input 1.
RF3 36
RF3 I/O ST/
RF4/MDCIN2 44
RF4 I/O ST/
MDCIN2 I ST Modulator Carrier Input 2.
RF5 45
RF5 I/O ST/
RF6/MDOUT 52
RF6 I/O ST/
MDOUT O CMOS Modulator output.
RF7 53
RF7 I/O ST/
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTF is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
2011 Microchip Technology Inc. Preliminary DS39977C-page 43
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PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
RG0/RX1/DT1 6
RG0 I/O ST/
RX1 I ST EUSART asynchronous receive.
DT1 I/O ST EUSART synchronous data (see related TX2/CK2).
RG1/CANTX2 7
RG1 I/O ST/
CANTX2 O CMOS CAN bus complimentary transmit output or CAN bus time clock.
RG2/T3CKI 11
RG2 I/O ST/
T3CKI I ST Timer3 clock input.
RG3/TX1/CK1 12
RG3 I/O ST/
TX1 O CMOS EUSART asynchronous transmit.
CK1 I/O ST EUSART synchronous clock (see related RX2/DT2).
RG4/T0CKI 18
RG4 I/O ST/
T0CKI I ST Timer0 external clock input.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Num
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTG is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
DS39977C-page 44 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Pin
Pin Name
Num
VSS 8P
VSS Ground reference for logic and I/O pins.
VSS 26 P
SS Ground reference for logic and I/O pins.
V
AVSS 42 P
AVSS Ground reference for analog modules.
SS 43 P
V
VSS Ground reference for logic and I/O pins.
VSS 56 P
SS Ground reference for logic and I/O pins.
V
AVDD 9P
AVDD Positive supply for analog modules.
DD 10 P
V
VDD Positive supply for logic and I/O pins.
VDD 25 P
DD Positive supply for logic and I/O pins.
V
VDDCORE/VCAP 33 P
VDDCORE External filter capacitor connection.
CAP External filter capacitor connection.
V
AVDD 40 P
AVDD Positive supply for analog modules.
DD 41 P
V
VDD Positive supply for logic and I/O pins.
VDD 57 P
DD Positive supply for logic and I/O pins.
V
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
Type
Buffer
Type
Description
2011 Microchip Technology Inc. Preliminary DS39977C-page 45
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PIC18F66K80 FAMILY
NOTES:
DS39977C-page 46 Preliminary 2011 Microchip Technology Inc.
Page 47
PIC18F66K80 FAMILY
PIC18FXXKXX
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
C1
R1
V
DD
MCLR
VCAP/VDDCORE
R2
C7
(1)
C2
(1)
C3
(1)
C4
(1)
C5
(1)
C6
(1)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1: The example shown is for a PIC18F device
with five V
DD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
2.0 GUIDELINES FOR GETTING
STARTED WITH PIC18FXXKXX
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC18F66K80 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
The following pins must always be connected:
DD and VSS pins
•All V
(see Section 2.2 “Power Supply Pins”)
•All AV
•MCLR
These pins must also be connected if they are being
used in the end application:
• PGC/PGD pins used for In-Circuit Serial
• OSCI and OSCO pins when an external oscillator
Additionally, the following pins may be required:
•V
The minimum mandatory connections are shown in
Figure 2-1.
DD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
source is used
(see Section 2.6 “External Oscillator Pins”)
REF+/VREF- pins are used when external voltage
reference for analog modules is implemented
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
2011 Microchip Technology Inc. Preliminary DS39977C-page 47
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PIC18F66K80 FAMILY
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR
pin VIH and VIL specifications are met.
2: R2 470 will limit any current flowing into
MCLR
from the external capacitor, C, in the
event of MCLR
pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin
V
IH and VIL specifications are met.
C1
R2
R1
V
DD
MCLR
PIC18FXXKXX
JP
2.2 Power Supply Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as V
SS, is required.
AV
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
DD, VSS, AVDD and
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to V
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR
levels (V
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
DD may be all that is required. The
pin. Consequently, specific voltage
IH and VIL) and fast signal transitions must
pin during programming and
pin
CONNECTIONS
2.2.2 TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS39977C-page 48 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
10
1
0.1
0.01
0.001
0.01 0.1 1 10 100 1000 10,000
Frequency (MHz)
ESR ()
Note: Typical data measurement at 25°C, 0V DC bias.
2.4 Voltage Regulator Pins
(V
CAP/VDDCORE)
On the PIC18F66K80 family devices, the regulator is
enabled and a low-ESR (< 5Ω) capacitor is required on
the VCAP/VDDCORE pin to stabilize the voltage regulator
output voltage. The V
connected to V
connected to ground. The type can be ceramic or
tantalum. Suitable examples of capacitors are shown in
Table 2-1. Capacitors with equivalent specifications
can be used. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 31.0 “Electrical
Characteristics” for additional information.
When the regulator is disabled, a 0.1F capacitor
should be connected from the V
ground. This capacitor’s characteristics must be similar
to those of the “decoupling” capacitors explained in
Section 2.2.1. For details on the V
when the regulator is disabled, see Parameter D001 in
Section 31.0 “Electrical Characteristics”.
Some PIC18FXXKXX families or some devices within
a family do not provide the option of enabling or
disabling the on-chip voltage regulator:
•The PIC18LFXXKXX devices permanently
disable the voltage regulator.
These devices require a 0.1F capacitor on the
CAP/VDDCORE pin. The VDD level of these
V
devices must comply with the “voltage regulator
disabled” specification for Parameter D001, in
Section 31.0 “Electrical Characteristics”.
• PIC18FXXKXX devices permanently enable the
voltage regulator.
These devices require a 10 F capacitor on the
CAP/VDDCORE pin.
V
For details on all members of the PIC18F66K80 family,
see Section 28.3 “On-Chip Voltage Regulator”.
CAP/VDDCORE pin must not be
DD and must use a capacitor of 10 μF
CAP/VDDCORE pin to
DD requirement,
FIGURE 2-3: FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED V
CAP
2.5 ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
IH) and input low (VIL) requirements.
(V
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 “Development Support”.
2011 Microchip Technology Inc. Preliminary DS39977C-page 49
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PIC18F66K80 FAMILY
TABLE 2-1 SUITABLE CAPACITOR EQUIVALENTS
Make Part #
TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC
TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC
Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC
Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC
Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC
Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC
Nominal
Capacitance
Base Tolerance Rated Voltage Temp. Range
2.6 External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to
Section 3.0 “Oscillator Configurations” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
DS39977C-page 50 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
GND
`
`
`
OSC1
OSC2
T1OSO
T1OS I
Copper Pour
Primary Oscillator
Crystal
Timer1 Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
T1 Oscillator: C1
T1 Oscillator: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
In planning the application’s routing and I/O assignments, ensure that adjacent port pins and other signals
in close proximity to the oscillator are benign (i.e., free
of high frequencies, short rise and fall times, and other
similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro
• AN849, “Basic PICmicro
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work ”
2.7 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
®
®
Oscillator Design”
Devices”
FIGURE 2-4: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
2011 Microchip Technology Inc. Preliminary DS39977C-page 51
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PIC18F66K80 FAMILY
NOTES:
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PIC18F66K80 FAMILY
3.0 OSCILLATOR CONFIGURATIONS
3.1 Oscillator Types
The PIC18F66K80 family of devices can be operated in
the following oscillator modes:
• EC External Clock, RA6 Available
• ECIO External Clock, Clock Out RA6 (F
on RA6)
• HS High-Speed Crystal/Resonator
• XT Crystal/Resonator
• LP Low-Power Crystal
• RC External Resistor/Capacitor, RA6
Available
• RCIO External Resistor/Capacitor, Clock Out
RA6 (F
OSC/4 on RA6)
• INTIO2 Internal Oscillator with I/O on RA6 and
RA7
• INTIO1 Internal Oscillator with F
RA6 and I/O on RA7
There is also an option for running the 4xPLL on any of
the clock sources in the input frequency range of 4 to
16 MHz.
The PLL is enabled by setting the PLLCFG bit
(CONFIG1H<4>) or the PLLEN bit (OSCTUNE<6>).
For the EC and HS modes, the PLLEN (software) or
PLLCFG (CONFIG1H<4>) bit can be used to enable
the PLL.
For the INTIOx modes (HF-INTOSC):
• Only the PLLEN can enable the PLL (PLLCFG is
ignored).
• When the oscillator is configured for the internal
oscillator (FOSC<3:0> = 100x), the PLL can be
enabled only when the HF-INTOSC frequency is
4, 8 or 16 MHz.
When the RA6 and RA7 pins are not used for an oscillator function or CLKOUT function, they are available
as general purpose I/Os.
OSC/4 Output on
OSC/4
To optimize power consumption when using EC/HS/
XT/LP/RC as the primary oscillator, the frequency input
range can be configured to yield an optimized power
bias:
• Low-Power Bias – External frequency less than
160 kHz
• Medium Power Bias – External frequency
between 160 kHz and 16 MHz
• High-Power Bias – External frequency greater
than 16 MHz
All of these modes are selected by the user by
programming the FOSC<3:0> Configuration bits
(CONFIG1H<3:0>). In addition, PIC18F66K80 family
devices can switch between different clock sources,
either under software control, or under certain conditions, automatically. This allows for additional power
savings by managing device clock speed in real time
without resetting the application. The clock sources for
the PIC18F66K80 family of devices are shown in
Figure 3-1.
For the HS and EC mode, there are additional power
modes of operation, depending on the frequency of
operation.
HS1 is the Medium Power mode with a frequency
range of 4 MHz to 16 MHz. HS2 is the High-Power
mode, where the oscillator frequency can go from
16 MHz to 25 MHz. HS1 and HS2 are achieved by
setting the CONFIG1H<3:0> bits correctly. (For details,
see Register 28-2 on page 464.)
EC mode has these modes of operation:
• EC1 – For low power with a frequency range up to
160 kHz
• EC2 – Medium power with a frequency range of
160 kHz to 16 MHz
• EC3 – High power with a frequency range of
16 MHz to 64 MHz
EC1, EC2 and EC3 are achieved by setting the
CONFIG1H<3:0> correctly. (For details, see
Register 28-2 on page 464.)
Table 3-1 shows the HS and EC modes’ frequency
range and FOSC<3:0> settings.
2011 Microchip Technology Inc. Preliminary DS39977C-page 53
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PIC18F66K80 FAMILY
OSC2
OSC1
SOSCO
SOSCI
HF-INTOSC
16 MHz to
31 kHz
MF-INTOSC
500 kHz to
31 kHz
LF-INTOSC
31 kHz
Postscaler
Postscaler
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
31 kHz
500 kHz
250 kHz
31 kHz
31 kHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
31 kHz
4x PLL
FOSC<3:0>
INTSRC
MUX
MUX
MUX
MUX
MFIOSEL
MUX
Peripherals
CPU
IDLEN
Clock Control
FOSC<3:0>
SCS<1:0>
111
110
101
100
011
010
001
000
IRCF<2:0>
MUX
PLLEN
and PLLCFG
TABLE 3-1: HS, EC, XT, LP AND RC MODES: RANGES AND SETTINGS
Mode Frequency Range FOSC<3:0> Setting
EC1 (low power)
(EC1 & EC1IO) 1100
EC2 (medium power)
(EC2 & EC2IO) 1010
EC3 (high power)
(EC3 & EC3IO) 0100
DC-160 kHz
160kHz-16MHz
16 MHz-64 MHz
HS1 (medium power) 4 MHz-16 MHz 0011
HS2 (high power) 16 MHz-25 MHz 0010
XT 100 kHz-4 MHz 0001
LP 31.25 kHz 0000
RC (External) 0-4 MHz 001x
INTIO 32kHz-16MHz
(and OSCCON, OSCCON2)
FIGURE 3-1 : PIC18F66K80 FA MIL Y CL OCK DI AG R AM
1101
1011
0101
100x
DS39977C-page 54 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
3.2 Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
The OSCTUNE register (Register 3-3) controls the
tuning and operation of the internal oscillator block. It also
implements the PLLEN bit which controls the operation of
the Phase Locked Loop (PLL) (see
Frequency Multiplier”
).
Section 3.5.3 “PLL
INTOSC source. It also provides status on the oscillators.
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-1 R/W-0 R/W-0 R
IDLEN IRCF2
(2)
IRCF1
(2)
IRCF0
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters an Idle mode when a SLEEP instruction is executed
0 = Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = HF-INTOSC output frequency is used (16 MHz)
110 = HF-INTOSC/2 output frequency is used (8 MHz, default)
101 = HF-INTOSC/4 output frequency is used (4 MHz)
100 = HF-INTOSC/8 output frequency is used (2 MHz)
011 = HF-INTOSC/16 output frequency is used (1 MHz)
If INTSRC =
0 and MFIOSEL = 0:
(3,5)
010 = HF-INTOSC/32 output frequency is used (500 kHz)
001 = HF-INTOSC/64 output frequency is used (250 kHz)
000 = LF-INTOSC output frequency is used (31.25 kHz)
If INTSRC =
1 and MFIOSEL = 0:
(3,5)
010 = HF-INTOSC/32 output frequency is used (500 kHz)
001 = HF-INTOSC/64 output frequency is used (250 kHz)
000 = HF-INTOSC/512 output frequency is used (31.25 kHz)
If INTSRC = 0 and MFIOSEL = 1:
(3,5)
010 = MF-INTOSC output frequency is used (500 kHz)
001 = MF-INTOSC/2 output frequency is used (250 kHz)
000 = LF-INTOSC output frequency is used (31.25 kHz)
If INTSRC =
1 and MFIOSEL = 1:
(3,5)
010 = MF-INTOSC output frequency is used (500 kHz)
001 = MF-INTOSC/2 output frequency is used (250 kHz)
000 = MF-INTOSC/16 output frequency is used (31.25 kHz)
bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit
1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running, as defined by
FOSC<3:0>
0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready – device is
running from internal oscillator (HF-INTOSC, MF-INTOSC or LF-INTOSC)
(1)
R-0 R/W-0 R/W-0
OSTS HFIOFS SCS1
(2)
(6)
(6)
(1)
(4)
SCS0
(4)
Note 1: Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>).
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>).
4: Modifying these bits will cause an immediate clock source switch.
5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>.
6: Lowest power option for an internal source.
2011 Microchip Technology Inc. Preliminary DS39977C-page 55
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PIC18F66K80 FAMILY
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 2 HFIOFS: HF-INTOSC Frequency Stable bit
1 = HF-INTOSC oscillator frequency is stable
0 = HF-INTOSC oscillator frequency is not stable
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC)
01 = SOSC oscillator
00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL. Defined by the
FOSC<3:0> Configuration bits, CONFIG1H<3:0>.)
Note 1: Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>).
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>).
4: Modifying these bits will cause an immediate clock source switch.
5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>.
6: Lowest power option for an internal source.
REGISTER 3-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2
(4)
U-0 R-0 U-0 R/W-0 R/W-0 U-0 R-x R/W-0
— SOSCRUN —SOSCDRV
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 SOSCRUN: SOSC Run Status bit
1 = System clock comes from a secondary SOSC
0 = System clock comes from an oscillator other than SOSC
bit 5 Unimplemented: Read as ‘0’
bit 4 SOSCDRV: Secondary Oscillator Drive Control bit
1 = High-Power SOSC circuit is selected
0 = Low/High-Power select is done via the SOSCSEL<1:0> Configuration bits
bit 3 SOSCGO: Oscillator Start Control bit
1 = Oscillator is running even if no other sources are requesting it.
0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from
a digital clock input, rather than an external crystal, this bit has no effect.)
bit 2 Unimplemented: Read as ‘0’
bit 1 MFIOFS: MF-INTOSC Frequency Stable bit
1 = MF-INTOSC is stable
0 = MF-INTOSC is not stable
bit 0 MFIOSEL: MF-INTOSC Select bit
1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz
0 = MF-INTOSC is not used
Note 1: When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no
effect.
(1)
SOSCGO — MFIOFS MFIOSEL
(1)
DS39977C-page 56 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
REGISTER 3-3: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 16 MHz INTOSC source (divide-by-512 enabled, HF-INTOSC)
0 = 31 kHz device clock derived from INTOSC 31 kHz oscillator (LF-INTOSC)
bit 6 PLLEN: Frequency Multiplier PLL Enable bit
1 = PLL is enabled
0 = PLL is disabled
bit 5-0 TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111 = Maximum frequency
• •
• •
000001
000000 = Center frequency; fast RC oscillator is running at the calibrated frequency
111111
• •
• •
100000 = Minimum frequency
2011 Microchip Technology Inc. Preliminary DS39977C-page 57
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PIC18F66K80 FAMILY
3.3 Clock Sources and Oscillator Switching
Essentially, PIC18F66K80 family devices have these
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. If selected by the FOSC<3:0>
Configuration bits (CONFIG1H<3:0>), the internal
oscillator block may be considered a primary oscillator.
The internal oscillator block can be one of the following:
• 31 kHz LF-INTOSC source
• 31 kHz to 500 kHz MF-INTOSC source
• 31 kHz to 16 MHz HF-INTOSC source
The particular mode is defined by the FOSC
Configuration bits. The details of these modes are
covered in Section 3.5 “External Oscillator Modes”.
The secondary oscillators are external clock
sources that are not connected to the OSC1 or OSC2
pin. These sources may continue to operate, even
after the controller is placed in a power-managed
mode. PIC18F66K80 family devices offer the SOSC
(Timer1/3/5/7) oscillator as a secondary oscillator
source.
The SOSC can be enabled from any peripheral that
requests it. The SOSC can be enabled several ways by
doing one of the following:
• The SOSC is selected as the source by either of
the odd timers, which is done by each respective
SOSCEN bit (TxCON<3>)
• The SOSC is selected as the CPU clock source
by the SCS bits (OSCCON<1:0>)
• The SOSCGO bit is set (OSCCON2<3>)
The SOSCGO bit is used to warm up the SOSC so that
it is ready before any peripheral requests it.
The secondary oscillator has three Run modes. The
SOSCSEL<1:0> bits (CONFIG1L<4:3>) decide the
SOSC mode of operation:
• 11 = High-Power SOSC Circuit
• 10 = Digital (SCLKI) mode
• 11 = Low-Power SOSC Circuit
If a secondary oscillator is not desired and digital I/O on
port pins, RC0 and RC1, is needed, the SOSCSEL bits
must be set to Digital mode.
In addition to being a primary clock source in some
circumstances, the internal oscillator is available as a
power-managed mode clock source. The LF-INTOSC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 3.6 “Internal Oscillator
Block”.
The PIC18F66K80 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
3.3.1 OSC1/OSC2 OSCILLATOR
The OSC1/OSC2 oscillator block is used to provide the
oscillator modes and frequency ranges:
Mode Design Operating Frequency
LP 31.25-100 kHz
XT 100 kHz to 4 MHz
HS 4 MHz to 25 MHz
EC 0 to 64 MHz (external clock)
EXTRC 0 to 4 MHz (external RC)
The crystal-based oscillators (XT, HS and LP) have a
built-in start-up time. The operation of the EC and
EXTRC clocks is immediate.
3.3.2 CLOCK SOURCE SELECTION
The System Clock Select bits, SCS<1:0>
(OSCCON<1:0>), select the clock source. The available clock sources are the primary clock defined by the
FOSC<3:0> Configuration bits, the secondary clock
(SOSC oscillator) and the internal oscillator. The clock
source changes after one or more of the bits is written
to, following a brief clock transition interval.
The OSTS (OSCCON<3>) and SOSCRUN
(OSCCON2<6>) bits indicate which clock source is
currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The SOSCRUN bit indicates when the SOSC oscillator (from Timer1/3/5/7) is
providing the device clock in secondary clock modes.
In power-managed modes, only one of these bits will
be set at any time. If neither of these bits is set, the
INTOSC is providing the clock or the internal oscillator
has just started and is not yet stable.
The IDLEN bit (OSCCON<7>) determines if the device
goes into Sleep mode or one of the Idle modes when
the SLEEP instruction is executed.
DS39977C-page 58 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
OSC2/CLKO
CEXT
REXT
PIC18F66K80
OSC1
F
OSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k REXT 100 k
20 pF C
EXT 300 pF
CEXT
REXT
PIC18F66K80
OSC1
Internal
Clock
VDD
VSS
Recommended values: 3 k REXT 100 k
20 pF C
EXT 300 pF
I/O (OSC2)
RA6
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
Note 1: The Timer1/3/5/7 oscillator must be
enabled to select the secondary clock
source. The Timerx oscillator is enabled
by setting the SOSCEN bit in the Timerx
Control register (TxCON<3>). If the Timerx oscillator is not enabled, then any
attempt to select a secondary clock
source when executing a SLEEP instruction will be ignored.
2: It is recommended that the Timerx
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timerx
oscillator starts.
3.3.2.1 System Clock Selection and Device
Resets
Since the SCS bits are cleared on all forms of Reset,
this means the primary oscillator defined by the
FOSC<3:0> Configuration bits is used as the primary
clock source on device Resets. This could either be the
internal oscillator block by itself, or one of the other
primary clock sources (HS, EC, XT, LP, External RC
and PLL-enabled modes).
In those cases when the internal oscillator block, without PLL, is the default clock on Reset, the Fast RC
Oscillator (INTOSC) will be used as the device clock
source. It will initially start at 8 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF<2:0> bits (‘110’).
Regardless of which primary oscillator is selected,
INTOSC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the FOSC Configuration bits are read and the
oscillator selection of the operational mode is made.
Note that either the primary clock source or the internal
oscillator will have two bit setting options for the possible
values of the SCS<1:0> bits, at any given time.
3.4 RC Oscillator
For timing-insensitive applications, the RC and RCIO
Oscillator modes offer additional cost savings. The
actual oscillator frequency is a function of several
factors:
• Supply voltage
• Values of the external resistor (R
(C
EXT)
• Operating temperature
Given the same device, operating voltage and temperature, and component values, there will also be unit to
unit frequency variations. These are due to factors
such as:
• Normal manufacturing variation
• Difference in lead frame capacitance between
package types (especially for low C
• Variations within the tolerance of the limits of
EXT and CEXT
R
In the RC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-2 shows how the R/C combination is
connected.
FIGURE 3-2: RC OSCILLAT OR MO DE
The RCIO Oscillator mode (Figure 3-3) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
EXT) and capacitor
EXT values)
3.3.3 OSCILLATOR TRANSITIONS
PIC18F66K80 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
2011 Microchip Technology Inc. Preliminary DS39977C-page 59
FIGURE 3-3: RCIO OSCILLATOR MODE
Page 60
PIC18F66K80 FAMILY
Note 1: See Tab l e 3 - 2 and Table 3-3 for initial values of
C1 and C2.
2: A series resistor (R
S) may be required for AT
strip cut crystals.
3: R
F varies with the oscillator mode chosen.
C1
(1)
C2
(1)
XTAL
OSC2
OSC1
RF
(3)
Sleep
To
Logic
RS
(2)
Internal
PIC18F66K80
3.5 External Oscillator Modes
3.5.1 CRYSTAL OSCILLATOR/CERAMIC RESONATORS (HS MODES)
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 3-4 shows the pin
connections.
The oscillator design requires the use of a crystal rated
for parallel resonant operation.
Note: Use of a crystal rated for series resonant
operation may give a frequency out of the
crystal manufacturer’s specifications.
TABLE 3-2: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode Freq. OSC1 OSC2
HS 8.0 MHz
16.0 MHz
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application. Refer
V
to the following application notes for oscillator-specific
information:
®
• AN588, “PIC
Microcont roller Oscillator Design
Guide”
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC
• AN849, “Basic PIC
®
®
• AN943, “Practical PIC® Oscillator Analysis and
Design”
• AN949, “Making Your Oscillator Work”
See the notes following Tab le 3 -3 for additional
information.
27 pF
22 pF
and PIC® Devices”
Oscillator Design”
27 pF
22 pF
T ABLE 3-3: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq.
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
Refer to the Microchip application notes cited in
Table 3-2 for oscillator specific information. Also see
the notes following this table for additional
information.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
DD and temperature range that is
the V
expected for the application.
T ypical Cap acitor V alues
Tested:
C1 C2
FIGURE 3-4: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR HSPLL
CONFIGURATION)
DS39977C-page 60 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
OSC1/CLKI
OSC2/CLKO
F
OSC/4
Clock from
Ext. System
PIC18F66K80
OSC1
OSC2
Open
Clock from
Ext. System
(HS Mode)
PIC18F66K80
MUX
VCO
Loop
Filter
OSC2
OSC1
PLL Enable (OSCTUNE<6>)
F
IN
FOUT
SYSCLK
Phase
Comparator
PLLCFG (CONFIG1H<4>)
4
HS or EC
Mode
3.5.2 EXTERNAL CLOCK INPUT (EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-5 : EXTERNAL C LOC K
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-6. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
3.5.3.1 HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at four times the external
oscillating source to produce frequencies up to
64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>).
For the HF-INTOSC as primary, the PLL must be
enabled with the PLLEN. This provides a software control for the PLL, enabling even if PLLCFG is set to ‘1’,
so that the PLL is enabled only when the HF-INTOSC
frequency is within the 4 MHz to16 MHz input range.
This also enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HF-INTOSC mode only if the
input frequency is in the range of 4 MHz-16 MHz.
FIGURE 3-7: PLL BLOCK DIAGRAM
FIGURE 3-6: EXTERNAL CLOCK INPUT
3.5.3 PLL FREQUENCY MULTIPLIER
A Phase Lock Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
OPERATION (HS OSC
CONFIGURATION)
3.5.3.2 PLL and HF-INTOSC
The PLL is available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 64 MHz.
The operation of INTOSC with the PLL is described in
Section 3.6.2 “INTPLL Modes”. Care should be taken
that the PLL is enabled only if the HF-INTOSC
postscaler is configured for 4 MHz, 8 MHz or 16 MHz
.
2011 Microchip Technology Inc. Preliminary DS39977C-page 61
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PIC18F66K80 FAMILY
OSC2
F
OSC/4
I/O (OSC1)
RA7
PIC18F66K80
I/O (OSC2)
RA6
I/O (OSC1)
RA7
PIC18F66K80
3.6 Internal Oscillator Block
The PIC18F66K80 family of devices includes an internal
oscillator block which generates two different clock
signals. Either clock can be used as the microcontroller’s
clock source, which may eliminate the need for an
external oscillator circuit on the OSC1 and/or OSC2 pins.
The Internal oscillator consists of three blocks,
depending on the frequency of operation. They are
HF-INTOSC, MF-INTOSC and LF-INTOSC.
In HF-INTOSC mode, the internal oscillator can provide
a frequency ranging from 31 KHz to 16 MHz, with the
postscaler deciding the selected frequency
(IRCF<2:0>).
The INTSRC bit (OSCTUNE<7>) and MFIOSEL bit
(OSCCON2<0>) also decide which INTOSC provides
the lower frequency (500 kHz to 31 KHz). For the
HF-INTOSC to provide these frequencies, INTSRC = 1
and MFIOSEL = 0.
In HF-INTOSC, the postscaler (IRCF<2:0>) provides
the frequency range of 31 kHz to 16 MHz. If
HF-INTOSC is used with the PLL, the input frequency
to the PLL should be 4 MHz to 16 MHz
(IRCF<2:0> = 111, 110 or 101).
For MF-INTOSC mode to provide a frequency range of
500 kHz to 31 kHz, INTSRC = 1 and MFIOSEL = 1.
The postscaler (IRCF<2:0>), in this mode, provides the
frequency range of 31 kHz to 500 kHz.
The LF-INTOSC can provide only 31 kHz if INTSRC = 0.
The LF-INTOSC provides 31 kHz and is enabled if it is
selected as the device clock source. The mode is
enabled automatically when any of the following are
enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 28.0 “Special Features of the CPU”.
The clock source frequency (HF-INTOSC, MF-INTOSC
or LF-INTOSC direct) is selected by configuring the
IRCF bits of the OSCCON register, as well the INTSRC
and MFIOSEL bits. The default frequency on device
Resets is 8 MHz.
FIGURE 3-8: INTIO1 OSCILLATOR MODE
FIGURE 3-9: INTIO2 OSCILLATOR MODE
3.6.2 INTPLL MODES
The 4x Phase Lock Loop (PLL) can be used with the
HF-INTOSC to produce faster device clock speeds
than are normally possible with the internal oscillator
sources. When enabled, the PLL produces a clock
speed of 16 MHz or 64 MHz.
PLL operation is controlled through software. The
control bits, PLLEN (OSCTUNE<6>) and PLLCFG
(CONFIG1H<4>), are used to enable or disable its
operation. The PLL is available only to HF-INTOSC.
The other oscillator is set with HS and EC modes. Additionally, the PLL will only function when the selected
output frequency is either 4 MHz or 16 MHz
(OSCCON<6:4> = 111, 110 or 101).
Like the INTIO modes, there are two distinct INTPLL
modes available:
• In INTPLL1 mode, the OSC2 pin outputs F
while OSC1 functions as RA7 for digital input and
output. Externally, this is identical in appearance
to INTIO1 (Figure 3-8).
• In INTPLL2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output. Externally, this is identical to INTIO2
(Figure 3-9).
OSC/4,
3.6.1 INTIO MODES
Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
oscillator configurations, which are determined by the
FOSC Configuration bits, are available:
• In INTIO1 mode, the OSC2 pin (RA6) outputs
OSC/4, while OSC1 functions as RA7 (see
F
Figure 3-8) for digital input and output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6 (see Figure 3-9). Both
are available as digital input and output ports.
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PIC18F66K80 FAMILY
3.6.3 INTERNAL OSCILLATOR OUTPUT FREQUENCY AND TUNING
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 16 MHz. It
can be adjusted in the user’s application by writing to
TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE
register (Register 3-3).
When the OSCTUNE register is modified, the INTOSC
(HF-INTOSC and MF-INTOSC) frequency will begin
shifting to the new frequency. The oscillator will require
some time to stabilize. Code execution continues
during this shift and there is no indication that the shift
has occurred.
The LF-INTOSC oscillator operates independently of
the HF-INTOSC or the MF-INTOSC source. Any
changes in the HF-INTOSC or the MF-INTOSC source,
across voltage and temperature, are not necessarily
reflected by changes in LF-INTOSC or vice versa. The
frequency of LF-INTOSC is not affected by OSCTUNE.
3.6.4 INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as VDD or temperature changes and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. Depending on the device, this may have no
effect on the LF-INTOSC clock source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
3.6.4.1 Compensating with the EUSART
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
3.6.4.2 Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the SOSC
oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
3.6.4.3 Compensating with the CCP Module
in Capture Mode
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
3.7 Reference Clock Output
In addition to the FOSC/4 clock output, in certain
oscillator modes, the device clock in the PIC18F66K80
family can also be configured to provide a reference
clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user
to select a greater range of clock submultiples to drive
external devices in the application.
This reference clock output is controlled by the
REFOCON register (Register 3-4). Setting the ROON
bit (REFOCON<7>) makes the clock signal available
on the REFO (RC3) pin. The RODIV<3:0> bits enable
the selection of 16 different clock divider options.
The ROSSLP and ROSEL bits (REFOCON<5:4>) control the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode. If
not, the oscillator on OSC1 and OSC2 will be powered
down when the device enters Sleep mode. Clearing the
ROSEL bit allows the reference output frequency to
change as the system clock changes during any clock
switches.
2011 Microchip Technology Inc. Preliminary DS39977C-page 63
Page 64
PIC18F66K80 FAMILY
REGISTER 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ROON: Reference Oscillator Output Enable bit
bit 6 Unimplemented: Read as ‘0’
bit 5 ROSSLP: Reference Oscillator Output Stop in Sleep bit
bit 4 ROSEL: Reference Oscillator Source Select bit
bit 3-0 RODIV<3:0>: Reference Oscillator Divisor Select bits
— ROSSLP ROSEL
1 = Reference oscillator output available on REFO pin
0 = Reference oscillator output disabled
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
1 = Primary oscillator (EC or HS) used as the base clock
0 = System clock used as the base clock; base clock reflects any clock switching of the device
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value
(1)
RODIV3 RODIV2 RODIV1 RODIV0
(1)
Note 1: For ROSEL (REFOCON<4>), the primary oscillator is available only when configured as the default via the
FOSC settings. This is regardless of whether the device is in Sleep mode.
DS39977C-page 64 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
3.8 Effects of Power-Managed Modes on the Various Clock Sources
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the SOSC oscillator is operating and
providing the device clock. The SOSC oscillator may
also run in all power-managed modes if required to
clock SOSC.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
LF-INTOSC output can be used directly to provide the
clock and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 28.2 “Watchdog Timer (WDT)” through
Section 28.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTOSC is required to support WDT operation. The
SOSC oscillator may be operating to support Timer1 or
3. Other features may be operating that do not require a
device clock source (i.e., MSSP slave, INTx pins and
others). Peripherals that may add significant current
consumption are listed in Section 3 1.2 “DC Character-
istics: Power-Down and Supply Current
PIC18F66K80 Fam ily (I ndu str i al/ Extended)”.
3.9 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applications. The delays ensure that the device is kept in
Reset until the device power supply is stable under normal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 5.6.1 “Power-up Timer
(PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up time of about 64 ms
(Parameter 33, Tab l e 3 1- 11 ); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS, XT or LP modes). The
OST does this by counting 1,024 oscillator cycles
before allowing the oscillator to clock the device.
There is a delay of interval, T
Table 31-11), following POR, while the controller
becomes ready to execute instructions.
CSD (Parameter 38,
TABLE 3-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output)
HS, HSPLL Feedback inverter disabled at quiescent
voltage level
INTOSC, INTPLL1/2 I/O pin, RA6, direction controlled by
TRISA<6>
Note: See Section 5.0 “Reset” for time-outs due to Sleep and MCLR
2011 Microchip Technology Inc. Preliminary DS39977C-page 65
Feedback inverter disabled at quiescent
voltage level
I/O pin, RA6, direction controlled by
TRISA<7>
Reset.
Page 66
PIC18F66K80 FAMILY
NOTES:
DS39977C-page 66 Preliminary 2011 Microchip Technology Inc.
Page 67
PIC18F66K80 FAMILY
4.0 POWER-MANAGED MODES
The PIC18F66K80 family of devices offers a total of
seven operating modes for more efficient power management. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (such as battery-powered
devices).
There are three categories of power-managed mode:
• Run modes
• Idle modes
• Sleep mode
There is an Ultra Low-Power Wake-up (ULPWU) for
waking from Sleep mode.
These categories define which portions of the device
are clocked, and sometimes, at what speed. The Run
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator
block). The Sleep mode does not use a clock source.
The ULPWU mode, on the RA0 pin, enables a slow falling voltage to generate a wake-up, even from Sleep,
without excess current consumption. (See Section 4.7
“Ultra Low-Power Wake-up”.)
The power-managed modes include several powersaving features offered on previous PIC
is the clock switching feature, offered in other PIC18
devices. This feature allows the controller to use the
SOSC oscillator instead of the primary one. Another
power-saving feature is Sleep mode, offered by all PIC
devices, where all device clocks are stopped.
4.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
• Will the CPU be clocked or not
• What will be the clock source
®
devices. One
The IDLEN bit (OSCCON<7>) controls CPU clocking,
while the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Ta bl e 4- 1 .
4.1.1 CLOCK SOURCES
The SCS<1:0> bits select one of three clock sources
for power-managed modes. Those sources are:
• The primary clock as defined by the FOSC<3:0>
Configuration bits
• The secondary clock (the SOSC oscillator)
• The internal oscillator block (for LF-INTOSC
modes)
4.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is used. Changing these bits
causes an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These considerations
are discussed in Section 4.1.3 “Clock Transitions
and Status Indicators” and subsequent sections.
Entering the power-managed Idle or Sleep modes is
triggered by the execution of a SLEE P instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current and impending mode, a
change to a power-managed mode does not always
require setting all of the previously discussed bits. Many
transitions can be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
desired, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 4-1: POWER-MANAGED MODES
Mode
Sleep 0 N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked
SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator
RC_RUN N/A 1x Clocked Clocked Internal oscillator block
PRI_IDLE 100Off Clocked Primary – LP, XT, HS, RC, EC
SEC_IDLE 101Off Clocked Secondary – SOSC oscillator
RC_IDLE 11xOff Clocked Internal oscillator block
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC
source.
2011 Microchip Technology Inc. Preliminary DS39977C-page 67
OSCCON Bits Module Clocking
IDLEN<7>
(1)
SCS<1:0> CPU Peripherals
Available Clock and Oscillator Source
Primary – XT, LP, HS, EC, RC and PLL modes.
This is the normal, full-power execution mode.
(2)
(2)
Page 68
PIC18F66K80 FAMILY
4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable. The HFINTOSC and MF-INTOSC are termed as INTOSC in
this chapter.
Three bits indicate the current clock source and its
status, as shown in Tab le 4- 2. The three bits are:
• OSTS (OSCCON<3>)
• HFIOFS (OSCCON<2>)
• SOSCRUN (OSCCON2<6>)
TABLE 4-2: SYSTEM CLOCK INDICATOR
Main Clock Source OSTS
Primary Oscillator 10 0
INTOSC (HF-INTOSC
or MF-INTOSC)
Secondary Oscillator 00 1
MF-INTOSC or
HF-INTOSC as
Primary Clock Source
LF-INTOSC is
Running or INTOSC is
not yet Stable
When the OSTS bit is set, the primary clock is providing
the device clock. When the HFIOFS or MFIOFS bit is
set, the INTOSC output is providing a stable clock
source to a divider that actually drives the device clock.
When the SOSCRUN bit is set, the SOSC oscillator is
providing the clock. If none of these bits are set, either
the LF-INTOSC clock source is clocking the device or
the INTOSC source is not yet stable.
If the internal oscillator block is configured as the
primary clock source by the FOSC<3:0> Configuration
bits (CONFIG1H<3:0>). Then, the OSTS and HFIOFS
or MFIOFS bits can be set when in PRI_RUN or
PRI_IDLE mode. This indicates that the primary clock
(INTOSC output) is generating a stable output. Entering another INTOSC power-managed mode at the
same frequency would clear the OSTS bit.
Note 1: Caution should be used when modifying
a single IRCF bit. At a lower V
possible to select a higher clock speed
than is supportable by that V
device operation may result if the V
F
OSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
HFIOFS or
MFIOFS
01 0
11 0
00 0
SOSCRUN
DD, it is
DD. Improper
DD/
4.1.4 MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
4.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled. (For details, see Section 28.4 “Two-Speed
Start-up”.) In this mode, the OSTS bit is set. The
HFIOFS or MFIOFS bit may be set if the internal
oscillator block is the primary clock source. (See
Section 3.2 “Control Registers”.)
4.2.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock-switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the SOSC oscillator. This enables lower
power consumption while retaining a high-accuracy
clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
SOSC oscillator (see Figure 4-1), the primary oscillator
is shut down, the SOSCRUN bit (OSCCON2<6>) is set
and the OSTS bit is cleared.
Note: The SOSC oscillator can be enabled by
setting the SOSCGO bit (OSCCON2<3>).
If this bit is set, the clock switch to the
SEC_RUN mode can switch immediately
once SCS<1:0> are set to ‘01’.
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the SOSC oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
SOSCRUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up and the
SOSC oscillator continues to run.
DS39977C-page 68 Preliminary 2011 Microchip Technology Inc.
Page 69
PIC18F66K80 FAMILY
Q4Q3Q2
OSC1
Peripheral
Program
Q1
SOSCI
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
(1)
Q4Q3Q2 Q1 Q3Q2
PC + 4
Note 1: Clock transition typically occurs within 2-4 T
OSC.
Q1 Q3 Q4
OSC1
Peripheral
Program
PC
SOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 T
OSC.
SCS<1:0> Bits Changed
TPLL
(1)
12 n-1n
Clock
OSTS Bit Set
Transition
(2)
TOST
(1)
FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC _RUN MOD E
FIGURE 4-2: TRA NSI TION T I MING FR OM SEC_ RU N MODE TO PRI_RU N MODE ( HSP LL)
4.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the LF-INTOSC source, this
mode provides the best power conservation of all the
Run modes, while still executing code. It works well for
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block – either LF-INTOSC or INTOSC (MF-INTOSC or
HF-INTOSC) – there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
2011 Microchip Technology Inc. Preliminary DS39977C-page 69
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it is
recommended that the SCS0 bit also be cleared, even
though the bit is ignored. When the clock source is
switched to the INTOSC multiplexer (see Figure 4-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
Note: Caution should be used when modifying a
single IRCF bit. At a lower V
possible to select a higher clock speed
than is supportable by that V
device operation may result if the V
OSC specifications are violated.
F
DD, it is
DD. Improper
DD/
Page 70
PIC18F66K80 FAMILY
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
Table 4-3.
TABLE 4-3: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
IRCF<2:0> INTSRC MFIOSEL Status of MFIOFS or HFIOFS when INTOSC is Stable
000 0 x MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC
000 1 0 MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
000 1 1 MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Non-Zero x0MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
Non-Zero x1MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Clocks to the device continue while the INTOSC source
stabilizes after an interval of T
Table 31-11).
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
IOBST (Parameter 39,
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor (FSCM) is enabled.
DS39977C-page 70 Preliminary 2011 Microchip Technology Inc.
Page 71
PIC18F66K80 FAMILY
Q4Q3Q2
OSC1
Peripheral
Program
Q1
LF-INTOSC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
(1)
Q4Q3Q2 Q1 Q3Q2
PC + 4
Note 1: Clock transition typically occurs within 2-4 T
OSC.
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q2
Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 T
OSC.
SCS<1:0> Bits Changed
TPLL
(1)
12 n-1n
Clock
OSTS Bit Set
Transition
(2)
Multiplexer
TOST
(1)
FIGURE 4-3 : TRA NSI T ION TIMING TO RC _R UN MOD E
FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
2011 Microchip Technology Inc. Preliminary DS39977C-page 71
Page 72
PIC18F66K80 FAMILY
Q4Q3Q2
OSC1
Peripheral
Sleep
Program
Q1Q1
Counter
Clock
CPU
Clock
PC + 2PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program
PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter
PC + 6
PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note 1:T
OST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST
(1)
TPLL
(1)
OSTS Bit Set
PC + 2
4.3 Sleep Mode
The power-managed Sleep mode in the PIC18F66K80
family of devices is identical to the legacy Sleep mode
offered in all other PIC devices. It is entered by clearing
the IDLEN bit (the default state on device Reset) and
executing the SLEEP instruction. This shuts down the
selected oscillator (Figure 4-5). All clock source status
bits are cleared.
Entering Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the LF-INTOSC source will continue
to operate. If the SOSC oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6). Alternately, the device
will be clocked from the internal oscillator block if either
the Two-Speed Start-up or the Fail-Safe Clock Monitor is
enabled (see Section 28.0 “Special Features of the
CPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The IDLEN
and SCS bits are not affected by the wake-up.
4.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits. The CPU,
however, will not be clocked. The clock source status bits
are not affected. This approach is a quick method to
switch from a given Run mode to its corresponding Idle
mode.
If the WDT is selected, the LF-INTOSC source will
continue to operate. If the SOSC oscillator is enabled,
it will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
(Parameter 38, Tab le 3 1 -1 1) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT timeout will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
CSD
FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 4-6: TRANSITION TIMING FOR W AKE FROM SLEEP (HSPLL)
DS39977C-page 72 Preliminary 2011 Microchip Technology Inc.
Page 73
PIC18F66K80 FAMILY
Q1
Peripheral
Program
PC PC + 2
OSC1
Q3
Q4
Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program
PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Even t
TCSD
4.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate, primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see Figure 4-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, T
(Parameter 39, Tab le 31 -11 ), is required between the
wake event and the start of code execution. This is
required to allow the CPU to become ready to execute
instructions. After the wake-up, the OSTS bit remains
set. The IDLEN and SCS bits are not affected by the
wake-up (see Figure 4-8).
CSD
4.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP . When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
CSD following the wake event, the CPU begins
of T
executing code that is being clocked by the SOSC
oscillator. The IDLEN and SCS bits are not affected by
the wake-up and the SOSC oscillator continues to run
(see Figure 4-8).
FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 4-8: T RANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
2011 Microchip Technology Inc. Preliminary DS39977C-page 73
Page 74
PIC18F66K80 FAMILY
4.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode
provides controllable power conservation during Idle
periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. To maintain software
compatibility with future devices, it is recommended
that SCS0 also be cleared, though its value is ignored.
The INTOSC multiplexer may be used to select a
higher clock frequency by modifying the IRCF bits
before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC/MFIOSEL bit is set, the INTOSC output is
enabled. The HFIOFS/MFIOFS bits become set, after
the INTOSC output becomes stable, after an interval of
IOBST (Parameter 38, Ta bl e 3 1 -11 ). For information on
T
the HFIOFS/MFIOFS bits, see Ta bl e 4- 3.
Clocks to the peripherals continue while the INTOSC
source stabilizes. The HFIOFS/MFIOFS bits will
remain set if the IRCF bits were previously at a nonzero value or if INTSRC was set before the SLEEP
instruction was executed and the INTOSC source was
already stable. If the IRCF bits and INTSRC are all
clear, the INTOSC output will not be enabled, the
HFIOFS/MFIOFS bits will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
CSD (Parameter 38, Tab le 31 -11 ) following the wake
of T
event, the CPU begins executing code clocked by the
INTOSC multiplexer. The IDLEN and SCS bits are not
affected by the wake-up. The INTOSC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
4.5 Selective Peripheral Module Control
Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus, consume power. There may be cases where the application
needs what this mode does not provide: the allocation of
power resources to the CPU processing with minimal
power consumption from the peripherals.
PIC18F66K80 family devices address this requirement
by allowing peripheral modules to be selectively
disabled, reducing or eliminating their power
consumption. This can be done with two control bits:
• Peripheral Enable bit, generically named XXXEN –
Located in the respective module’s main control
register
• Peripheral Module Disable (PMD) bit, generically
named, XXXMD – Located in one of the PMDx
Control registers (PMD0, PMD1 or PMD2)
Disabling a module by clearing its XXXEN bit disables
the module’s functionality, but leaves its registers
available to be read and written to. This reduces power
consumption, but not by as much as the second
approach.
Most peripheral modules have an enable bit.
In contrast, setting the PMD bit for a module disables
all clock sources to that module, reducing its power
consumption to an absolute minimum. In this state, the
control and status registers associated with the peripheral are also disabled, so writes to those registers have
no effect and read values are invalid. Many peripheral
modules have a corresponding PMD bit.
There are three PMD registers in PIC18F66K80 family
devices: PMD0, PMD1 and PMD2. These registers
have bits associated with each module for disabling or
enabling a particular peripheral.
DS39977C-page 74 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
REGISTER 4-1: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — MODMD ECANMD CMP2MD CMP1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
(1)
bit 3 MODMD: Modulator Output Module Disable bit
1 = The modulator output module is disabled. All Modulator Output registers are held in Reset and
are not writable.
0 = The modulator output module is enabled
bit 2 ECANMD: Enhanced CAN Module Disable bit
1 = The Enhanced CAN module is disabled. All Enhanced CAN registers are held in Reset and are
not writable.
0 = The Enhanced CAN module is enabled
bit 1 CMP2MD: Comparator 2 Module Disable bit
1 = The Comparator 2 module is disabled. All Comparator 2 registers are held in Reset and are not
writable.
0 = The Comparator 2 module is enabled
bit 0 CMP1MD: Comparator 1 Module Disable bit
1 = The Comparator 1 module is disabled. All Comparator 1 registers are held in Reset and are not
writable.
0 = The Comparator 1 module is enabled
Note 1: Only implemented on devices with 64 pins (PIC18F6XK80, PIC18LF6XK80).
2011 Microchip Technology Inc. Preliminary DS39977C-page 75
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REGISTER 4-2: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPMD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD
bit 7 PSPMD: Peripheral Module Disable bit
1 = The PSP module is disabled. All PSP registers are held in Reset and are not writable.
0 = The PSP module is enabled
bit 6 CTMUMD: PMD CTMU Disable bit
1 = The CTMU module is disabled. All CTMU registers are held in Reset and are not writable.
0 = The CTMU module is enabled
bit 5 ADCMD: ADC Module Disable bit
1 = The ADC module is disabled. All ADC registers are held in Reset and are not writable.
0 = The ADC module is enabled
bit 4 TMR4MD: TMR4MD Disable bit
1 = The Timer4 module is disabled. All Timer4 registers are held in Reset and are not writable.
0 = The Timer4 module is enabled
bit 3 TMR3MD: TMR3MD Disable bit
1 = The Timer3 module is disabled. All Timer3 registers are held in Reset and are not writable.
0 = The Timer3 module is enabled
bit 2 TMR2MD: TMR2MD Disable bit
1 = The Timer2 module is disabled. All Timer2 registers are held in Reset and are not writable.
0 = The Timer2 module is enabled
bit 1 TMR1MD: TMR1MD Disable bit
1 = The Timer1 module is disabled. All Timer1 registers are held in Reset and are not writable.
0 = The Timer1 module is enabled
bit 0 TMR0MD: Timer0 Module Disable bit
1 = The Timer0 module is disabled. All Timer0 registers are held in Reset and are not writable.
0 = The Timer0 module is enabled
(1)
Note 1: Unimplemented on devices with 28-pin devices (PIC18F2XK80, PIC18LF2XK80).
DS39977C-page 76 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
REGISTER 4-3: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CCP5MD: CCP5 Module Disable bit
1 = The CCP5 module is disabled. All CCP5 registers are held in Reset and are not writable.
0 = The CCP5 module is enabled
bit 6 CCP4MD: CCP4 Module Disable bit
1 = The CCP4 module is disabled. All CCP4 registers are held in Reset and are not writable.
0 = The CCP4 module is enabled
bit 5 CCP3MD: CCP3 Module Disable bit
1 = The CCP3 module is disabled. All CCP3 registers are held in Reset and are not writable.
0 = The CCP3 module is enabled
bit 4 CCP2MD: CCP2 Module Disable bit
1 = The CCP2 module is disabled. All CCP2 registers are held in Reset and are not writable.
0 = The CCP2 module is enabled
bit 3 CCP1MD: ECCP1 Module Disable bit
1 = The ECCP1 module is disabled. All ECCP1 registers are held in Reset and are not writable.
0 = The ECCP1 module is enabled
bit 2 UART2MD: EUSART2 Module Disable bit
1 = The USART2 module is disabled. All USART2 registers are held in Reset and are not writable.
0 = The USART2 module is enabled
bit 1 UART1MD: EUSART1 Module Disable bit
1 = The USART1 module is disabled. All USART1 registers are held in Reset and are not writable.
0 = The USART1 module is enabled
bit 0 SSPMD: MSSP Module Disable bit
1 = The MSSP module is disabled. All SSP registers are held in Reset and are not writable.
0 = The MSSP module is enabled
2011 Microchip Technology Inc. Preliminary DS39977C-page 77
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PIC18F66K80 FAMILY
4.6 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 4.2 “Run Modes”, Section 4.3
“Sleep Mode” and Section 4.4 “Idle Modes”).
4.6.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or Sleep mode to a
Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCONx or PIEx registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see
Section 10.0 “Interrupts”).
4.6.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 28.2 “Watchdog
Timer (WDT)”).
Executing a SLEEP or CLRWDT instruction clears the
WDT timer and postscaler, loses the currently selected
clock source (if the Fail-Safe Clock Monitor is enabled)
and modifies the IRCF bits in the OSCCON register (if
the internal oscillator block is the device clock source).
4.6.3 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the HFIOFS/MFIOFS bits are set
instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up, and the type of oscillator, if the
new clock source is the primary clock. Exit delays are
summarized in Ta bl e 4- 4.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 28.4 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 28.5 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal
oscillator block until either the primary clock becomes
ready or a power-managed mode is entered before the
primary clock becomes ready; the primary clock is then
shut down.
4.6.4 EXIT WITHOUT AN OSCILLATOR
START-UP DE LAY
Certain exits from power-managed modes do not
invoke the OST at all. The two cases are:
• When in PRI_IDLE mode, where the primary
clock source is not stopped
• When the primary clock source is not any of the
LP, XT, HS or HSPLL modes
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally, does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
CSD, following the wake event is still required when
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
DS39977C-page 78 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
RA0/CVREF/AN0/ULPWU
4.7 Ultra Low-Power Wake-up
The Ultra Low-Power Wake-up (ULPWU) on pin, RA0,
allows a slow falling voltage to generate an interrupt
without excess current consumption.
To use this feature:
1. Charge the capacitor on RA0 by configuring the
2. Stop charging the capacitor by configuring RA0
3. Discharge the capacitor by setting the ULPEN
4. Configure Sleep mode.
5. Enter Sleep mode.
When the voltage on RA0 drops below V
wakes up and executes the next instruction.
This feature provides a low-power technique for
periodically waking up the device from Sleep mode.
The time-out is dependent on the discharge time of the
RC circuit on RA0.
When the ULPWU module wakes the device from
Sleep mode, the ULPLVL bit (WDTCON<5>) is set.
Software can check this bit upon wake-up to determine
the wake-up source.
See Example 4-1 for initializing the ULPWU module.
EXAMPLE 4-1: ULTRA LOW-POWER
TRISAbits.TRISA0 = 0;
PORTAbits.RA0 = 1;
for(i = 0; i < 10000; i++) Nop();
TRISAbits.TRISA0 = 1;
WDTCONbits.ULPEN = 1;
WDTCONbits.ULPSINK = 1;
OSCCONbits.IDLEN = 0;
Sleep();
RA0 pin to an output and setting it to ‘1’.
as an input.
and ULPSINK bits in the WDTCON register.
IL, the device
WAKE-U P INITIA LIZA TION
//***************************
//Charge the capacitor on RA0
//***************************
//*****************************
//Stop Charging the capacitor
//on RA0
//*****************************
//*****************************
//Enable the Ultra Low Power
//Wakeup module and allow
//capacitor discharge
//*****************************
//For Sleep
//Enter Sleep Mode
//
//for sleep, execution will
//resume here
A series resistor, between RA0 and the external
capacitor, provides overcurrent protection for the RA0/
CVREF/AN0/ULPWU pin and enables software
calibration of the time-out (see Figure 4-9).
FIGURE 4-9: ULTRA LOW-POWER
WAKE-UP INITIALIZATION
A timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired delay in Sleep.
This technique compensates for the affects of
temperature, voltage and component accuracy. The
peripheral can also be configured as a simple
programmable Low-Voltage Detect (LVD) or temperature
sensor.
Note: For more information, see AN879, “Using
the Microchip Ultra Low-Power Wake-up
Module” (DS00879).
2011 Microchip Technology Inc. Preliminary DS39977C-page 79
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TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Power-Managed
Mode
PRI_IDLE mode
SEC_IDLE mode SOSC T
RC_IDLE mode
Sleep mode
Note 1: TCSD (Parameter 38, Tab le 31- 11) is a required delay when waking from Sleep and all Idle modes, and
runs concurrently with any other required delays (see
2: Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
3: TOST is the Oscillator Start-up Timer (Parameter 32, Tab le 3 1- 11 ). TRC is the PLL Lock-out Timer
(Parameter F12, Table 31-7); it is also designated as T
4: Execution continues during TIOBST (Parameter 39, Table 31-11), the INTOSC stabilization period.
5: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>)
and FOSC (CONFIG1H<3:0>) bits.
Clock Source
(5)
Exit Delay
Clock Ready
Status Bits
LP, XT, HS
OSTSHSPLL
EC, RC
HF-INTOSC
MF-INTOSC
(2)
(2)
TCSD
(1)
HFIOFS
MFIOFS
LF-INTOSC None
(1)
HF-INTOSC
MF-INTOSC
(2)
(2)
CSD
TCSD
(1)
SOSCRUN
HFIOFS
MFIOFS
LF-INTOSC None
LP, XT, HS T
EC, RC TCSD
HF-INTOSC
MF-INTOSC
(2)
(2)
OST
TIOBST
(3)
(1)
(3)
rc
OSTSHSPLL TOST + t
HFIOFS
(4)
MFIOFS
LF-INTOSC None
Section 4.4 “Idle Modes”).
PLL.
DS39977C-page 80 Preliminary 2011 Microchip Technology Inc.
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PIC18F66K80 FAMILY
S
R
Q
External Reset
MCLR
VDD
OSC1
WDT
Time-out
V
DD Rise
Detect
OST/PWRT
INTOSC
(1)
POR Pulse
OST
10-Bit Ripple Counter
PWRT
Chip_Reset
11-Bit Ripple Counter
Enable OST
(2)
Enable PWRT
Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 5-2 for time-out situations.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32 s
MCLRE
5.0 RESET
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
The PIC18F66K80 family devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR
c) MCLR
Reset during Normal Operation
Reset during Power-Managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Configuration Mismatch (CM) Reset
f) Programmable Brown-out Reset (BOR)
g)
RESET Instruction
h) Stack Full Reset
i) Stack Underflow Reset
This section discusses Resets generated by MCLR
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
,
5.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in
of Registers”
.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 10.0 “Interrupts”. BOR is covered in
Section 5.4 “Brown-out Reset (BOR)”.
Section 5 .7 “Reset State
Section 6.1.3.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in
Timer (WDT)”
.
Section 28.2 “Watchdog
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
2011 Microchip Technology Inc. Preliminary DS39977C-page 81
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PIC18F66K80 FAMILY
REGISTER 5-1: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1
IPEN SBOREN CM
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
(1)
R/W-1 R/W-1 R-1 R-1 R/W-0
RI TO PD POR BOR
(2)
R/W-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit
If BOREN<1:0> = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN
Bit is disabled and reads as ‘0’.
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred.
0 = A Configuration Mismatch Reset occurred. Must be set in software once the Reset occurs.
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
<1:0> = 00, 10 or 11:
Brown-out Reset occurs)
(1)
(2)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘
1’ by software immediately after a Power-on Reset).
DS39977C-page 82 Preliminary 2011 Microchip Technology Inc.
Section 5.7 “Reset State of Registers” for additional information.
Page 83
PIC18F66K80 FAMILY
Note 1: External Power-on Reset circuit is required
only if the V
DD power-up slope is too slow.
The diode, D, helps discharge the capacitor
quickly when V
DD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 1 k will limit any current flowing into
MCLR
from external capacitor, C, in the event
of MCLR
/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
V
DD
MCLR
PIC18FXX80
VDD
5.2 Master Clear Reset (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR
Reset path which detects and ignores small
pulses.
The MCLR
pin is not driven low by any internal Resets,
including the WDT.
In PIC18F66K80 family devices, the MCLR
input can
be disabled with the MCLRE Configuration bit. When
MCLR
is disabled, the pin becomes a digital input. See
Section 11.6 “PORTE, TRISE and LATE Registers”
for more information.
5.3 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
V
DD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
DD is specified (Parameter D004). For a slow rise
time, see Figure 5-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR
The state of the bit is set to ‘
Reset occurs; it does not change for any other Reset
event. POR
To capture multiple events, the user manually resets
the bit to ‘
DD rises above a certain threshold. This
bit (RCON<1>).
0’ whenever a Power-on
is not reset to ‘1’ by any hardware event.
1’ in software following any Power-on Reset.
FIGURE 5-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD POWER-UP)
2011 Microchip Technology Inc. Preliminary DS39977C-page 83
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PIC18F66K80 FAMILY
5.4 Brown-out Reset (BOR)
The PIC18F66K80 family has four BOR Power modes:
• High-Power BOR
• Medium Power BOR
• Low-Power BOR
• Zero-Power BOR
Each power mode is selected by the BORPWR<1:0>
setting (CONFIG2L<6:5>). For low, medium and
high-power BOR, the module monitors the V
ing on the BORV<1:0> setting (CONFIG1L<3:2>). The
typical current draw (
power BOR is 200 nA, 750 nA and 3
BOR event re-arms the Power-on Reset. It also causes
a Reset, depending on which of the trip levels has been
set: 1.8V, 2V, 2.7V or 3V.
BOR is enabled by BOREN<1:0> (CONFIG2L<2:1>)
and the SBOREN bit (RCON<6>). The four BOR
configurations are summarized in Tab l e 5- 1 .
In Zero-Power BOR (ZPBORMV), the module monitors
the V
DD voltage and re-arms the POR at about 2V.
ZPBORMV does not cause a Reset, but re-arms the
POR.
The BOR accuracy varies with its power level. The lower
the power setting, the less accurate the BOR trip levels
are. Therefore, the high-power BOR has the highest
accuracy and the low-power BOR has the lowest accuracy. The trip levels (B
consumption (
Power-Down and Supply Current PIC18F66K80
Family (Industrial/Extended)”
below B
Section 31.0 “Electrical Characteristics”.
VDD (TBOR, Parameter 35) can all be found in
IBOR) for zero, low and medium
VDD, Parameter D005), current
Section 31.2 “DC Characteristics:
) and time required
5.4.1 SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<6>). Setting SBOREN
enables the BOR to function as previously described.
Clearing SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise it is
read as ‘
0’.
DD depend-
A, respectively. A
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by eliminating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
Note: Even when BOR is under software con-
trol, the Brown-out Reset voltage level is
still set by the BORV<1:0> Configuration
bits; it cannot be changed in software.
5.4.2 DETECTING BOR
When Brown-out Reset is enabled, the BOR bit always
resets to ‘
Reset event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR
simultaneously check the state of both POR
This assumes that the POR
immediately after any Power-on Reset event. IF BOR
is ‘0’ while POR is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
0’ on any Brown-out Reset or Power-on
alone. A more reliable method is to
and BOR.
bit is reset to ‘1’ in software
5.4.3 DISABLING BOR IN SLEEP MODE
When BOREN<1:0> = 10, the BOR remains under
hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 5-1: BOR CONFIGURATIONS
BOR Configuration Status of
BOREN1 BOREN0
00
01Available BOR enabled in software; operation controlled by SBOREN.
10Unavailable BOR enabled in hardware in Run and Idle modes; disabled during Sleep
11Unavailable BOR enabled in hardware; must be disabled by reprogramming the
DS39977C-page 84 Preliminary 2011 Microchip Technology Inc.
SBOREN
(RCON<6>)
Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
mode.
Configuration bits.
BOR Operation
Page 85
PIC18F66K80 FAMILY
5.5 Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXKXX Flash devices, the device Configuration registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary Shadow registers. If a mismatch is detected between the two sets
of registers, a CM Reset automatically occurs. These
events are captured by the CM
set to ‘
0’.
This bit does not change for any other Reset event. A
CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
bit (RCON<5>) being
5.6 Device Reset Timers
PIC18F66K80 family devices incorporate three separate on-chip timers that help regulate the Power-on
Reset process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.6.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of the PIC18F66K80
family devices is an 11-bit counter which uses the
INTOSC source as the clock input. This yields an
approximate time interval of 2048 x 32
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the INTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See DC Parameter 33 for
details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
s=65.6ms.
2011 Microchip Technology Inc. Preliminary DS39977C-page 85
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PIC18F66K80 FAMILY
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
5.6.2 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (Parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
5.6.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (T
oscillator start-up time-out.
PLL) is typically 2 ms and follows the
5.6.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT
time-out is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 5-3,
Figure 5-4, Figure 5-5, Figure 5-6 and Figure 5-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 5-3 through 5-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing MCLR
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
HSPLL 66 ms
PWRTEN
(1)
+ 1024 TOSC + 2 ms
HS, XT, LP 66 ms
EC, ECIO 66 ms
RC, RCIO 66 ms
INTIO1, INTIO2 66 ms
Power-up
= 0 PWRTEN = 1
(1)
+ 1024 TOSC 1024 TOSC 1024 TOSC
(1)
(1)
(1)
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
and Brown-out
(2)
1024 TOSC + 2 ms
high will begin execution immediately
Exit from
Power-Managed Mode
(2)
1024 TOSC + 2 ms
(2)
——
——
——
FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR
DS39977C-page 86 Preliminary 2011 Microchip Technology Inc.
TIED TO VDD, VDD RISE < TPWRT)
Page 87
PIC18F66K80 FAMILY
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
T
PWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
1V
5V
T
PWRT
TOST
FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR
FIGURE 5-6: SLOW RISE TIME (MCLR
TIED TO VDD, VDD RISE > TPWRT)
NOT TIED TO VDD): CASE 2
2011 Microchip Technology Inc. Preliminary DS39977C-page 87
Page 88
PIC18F66K80 FAMILY
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
T
PLL 2 ms max. First three stages of the PWRT timer.
FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
DS39977C-page 88 Preliminary 2011 Microchip Technology Inc.
Page 89
PIC18F66K80 FAMILY
5.7 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on a Power-on Reset and unchanged by all
other Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
ferent Reset situations, as indicated in Tab le 5-3 .
These bits are used in software to determine the nature
of the Reset.
Table 5-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI
CM
, POR and BOR, are set or cleared differently in dif-
, TO, PD,
TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter
(1)
SBOREN CM
Power-on Reset 0000h 1 111100 0 0
Instruction 0000h u
RESET
Brown-out Reset 0000h u
MCLR Reset during
0000h u
(2)
(2)
(2)
Power-Managed Run modes
MCLR Reset during
0000h u
(2)
Power-Managed Idle modes and
Sleep mode
WDT Time-out during Full Power
0000h u
(2)
or Power-Managed Run modes
MCLR Reset during Full-Power
0000h u
(2)
execution
Stack Full Reset (STVREN = 1) 0000h u
Stack Underflow Reset
(STVREN =
1)
Stack Underflow Error (not an
actual Reset, STVREN =
0)
WDT Time-out during
0000h
0000h
PC + 2 u
(2)
(2)
u
(2)
u
(2)
Power-Managed Idle or Sleep
modes
Interrupt Exit from
PC + 2 u
(2)
Power-Managed modes
Legend: u
= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits =
01 and SBOREN = 1); otherwise, the Reset state is ‘0’.
RCON Register STKPTR Register
RI TO PD POR BOR STKFUL STKUNF
u0uuuu u u
1111u0 u u
uu1uuu u u
uu10uu u u
uu0uuu u u
uuuuuu u u
uuuuuu 1 u
uuuuuu u 1
uuuuuu u 1
uu00uu u u
uuu0uu u u
2011 Microchip Technology Inc. Preliminary DS39977C-page 89
Page 90
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on
Register Applicable Devices
TOSU PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---0 0000 ---0 uuuu
TOSH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
TOSL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
STKPTR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 00-0 0000 uu-0 0000 uu-u uuuu
PCLATU PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---0 0000 ---u uuuu
PCLATH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PCL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 PC + 2
TBLPTRU PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu
TBLPTRH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
TBLPTRL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
TABLAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PRODH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 000x 0000 000u uuuu uuuu
INTCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 -1-1 1111 -1-1 uuuu -u-u
INTCON3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 11x0 0x00 11x0 0x00 uuuu uuuu
INDF0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
POSTINC0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
POSTDEC0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
PREINC0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
PLUSW0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
FSR0H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- xxxx ---- uuuu ---- uuuu
FSR0L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
WREG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
POSTINC1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
POSTDEC1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
PREINC1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
PLUSW1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
FSR1H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- xxxx ---- uuuu ---- uuuu
FSR1L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
BSR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- 0000 ---- 0000 ---- uuuu
INDF2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
(3)
(3)
(3)
(3)
(2)
(1)
(1)
(1)
DS39977C-page 90 Preliminary 2011 Microchip Technology Inc.
Page 91
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
POSTINC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
POSTDEC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
PREINC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
PLUSW2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A
FSR2H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- xxxx ---- uuuu ---- uuuu
FSR2L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx ---u uuuu ---u uuuu
TMR0H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 uuuu uuuu uuuu uuuu
TMR0L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
OSCCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0100 q000 0100 00q0 uuuu uuqu
OSCCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -x-x x-xx -0-0 0-01 -u-u u-uu
WDTCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-x0 -xx0 0-x0 -xx0 u-u0 -uu0
(4)
RCON
TMR1H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 u0uu uuuu uuuu uuuu
TMR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
T2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu
SSPBUF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 uuuu uuuu uuuu uuuu
SSPADD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
SSPSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
SSPCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
SSPCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
ADRESH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu
ADCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0qqq 0000 0qqq uuuu uuuu
ADCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-00 0000 0-00 0000 u-uu uuuu
ECCP1AS PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 xxxx xxxx
CCPR1H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0111 11q0 0111 qquu uuuu qquu
Shaded cells indicate conditions do not apply for the designated device.
vector (0008h or 0018h).
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
enabled as PORTA pins, they are disabled and read ‘0’.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
2011 Microchip Technology Inc. Preliminary DS39977C-page 91
Page 92
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
TXSTA2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0010 0000 0010 uuuu uuuu
BAUDCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 01x0 0-00 01x0 0-00 uuuu u-uu
IPR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 -111 1111 -111 uuuu -uuu
PIR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 -000 0000 -000 uuuu -uuu
PIE4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 -000 0000 -000 uuuu -uuu
CVRCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CMSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 11-- ---- 11-- ---- uu-- ----
TMR3H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
T3GCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0x00 0000 0x00 uuuu u-uu
SPBRG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
RCREG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
TXREG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx 0000 0000 uuuu uuuu
TXSTA1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0010 0000 0010 uuuu uuuu
RCSTA1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 000x 0000 000x uuuu uuuu
T1GCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0x00 0000 0x00 uuuu u-uu
PR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
HLVDCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 01x0 0-00 01x0 0-00 uuuu u-uu
RCSTA2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 000x 0000 000x uuuu uuuu
IPR3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --11 111- --11 111- --uu uuu-
PIR3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --x0 xxx- --x0 xxx- --uu uuu-
PIE3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
IPR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1--- 111x 1--- 111x u--- uuuu
PIR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0--- 000x 0--- 000x u--- uuuu
PIE2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0--- 000x 0--- 0000 u--- uuuu
IPR1
PIR1
PIE1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PSTR1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 00-0 0001 xx-x xxxx —
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
PIC18F2XK80
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu
PIC18F2XK80
Shaded cells indicate conditions do not apply for the designated device.
vector (0008h or 0018h).
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
enabled as PORTA pins, they are disabled and read ‘0’.
PIC18F4XK80 PIC18F6XK80 -111 1111 -111 1111 -uuu uuuu
PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
(1)
(1)
DS39977C-page 92 Preliminary 2011 Microchip Technology Inc.
Page 93
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
Reset,
Brown-out
RESET Instruction,
Reset
OSCTUNE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
REFOCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-00 0000 0-00 0000 u-uu uuuu
CCPTMRS PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---1 1111 ---1 1111 ---u uuuu
TRISG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---1 111 ---1 1111 ---u uuuu
TRISF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
TRISE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 -111 1111 -111 uuuu -uuu
TRISD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
TRISB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
TRISA
(5)
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 111- 1111
(5)
ODCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
SLRCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -111 1111 -111 1111 -111 1111
LATG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx ---x xxxx ---u uuuu
LATF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx -xxx xxxx -xxx uuuu -uuu
LATE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
LATD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
LATC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
LATB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
LATA
(5)
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- xxxx
(5)
T4CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu
TMR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PORTG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx ---x xxxx ---u uuuu
PORTF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
PORTE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
PORTD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
PORTC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
PORTB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
PORTA
(5)
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- xxxx
(5)
EECON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xx-0 x000 uu-0 u000 uu-u uuuu
EECON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
SPBRGH1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
SPBRGH2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
SPBRG2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
RCREG2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Resets,
MCLR
WDT Reset,
Stack Resets
111- 1111
xxx- xxxx
xxx- xxxx
(5)
(5)
(5)
Wake-up via
WDT
or Interrupt
uuu- uuuu
uuu- uuuu
uuu- uuuu
(5)
(5)
(5)
2011 Microchip Technology Inc. Preliminary DS39977C-page 93
Page 94
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
TXREG2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
IPR5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
PIR5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PIE5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
EEADRH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- --00 ---- --00 ---- --00
EEADR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
EEDATA PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
ECANCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 0000 0001 0000 uuuu uuuu
COMSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CIOCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---0 0000 ---0 uuuu ---u
CANCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
RXB0D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0xxx xxxx 0uuu uuuu uuuu uuuu
RXB0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu
RXB0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
RXB0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CM1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 1111 0001 1111 uuuu uuuu
CM2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 1111 0001 1111 uuuu uuuu
ANCON0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
ANCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -111 1111 -111 1111 -uuu uuuu
WPUB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu
IOCB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 ---- 1111 ---- uuuu ----
PMD0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
DS39977C-page 94 Preliminary 2011 Microchip Technology Inc.
Page 95
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
PMD1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
PMD2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- 0000 ---- 0000 ---- uuuu
PADCFG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---0 0000 ---0 uuuu ---u
CTMUCONH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-00 0000 0-00 0000 u-uu uuuu
CTMUCONL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CTMUICONH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CCPR2H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCPR2L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCP2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu
CCPR3H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCPR3L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCP3CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu
CCPR4H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCPR4L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCP4CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu
CCPR5H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCPR5L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
CCP5CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu
PSPCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---- 0000 ---- uuuu ----
MDCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0010 0--0 0010 0--0 uuuu u--u
MDSRC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0--- xxxx 0--- xxxx u--- uuuu
MDCARH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0xx- xxxx 0xx- xxxx uuu- uuuu
MDCARL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0xx- xxxx 0xx- xxxx uuu- uuuu
CANCON_RO0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT_RO0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
RXB1D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0xxx xxxx 0uuu uuuu xxxx xxxx
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
2011 Microchip Technology Inc. Preliminary DS39977C-page 95
Page 96
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
RXB1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x0xx uuuu u0uu uuuu uuuu
RXB1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXB1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CANCON_RO1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT_RO1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
TXB0D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB0DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
TXB0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
TXB0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
TXB0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx xxx- x-xx uuuu uuuu
TXB0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu
TXB0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu u-uu
CANCON_RO2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT_RO2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
TXB1D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -x-- xxxx -u-- uuuu -u-- uuuu
TXB1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
DS39977C-page 96 Preliminary 2011 Microchip Technology Inc.
Page 97
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
TXB1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu
TXB1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CANCON_RO3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT_RO3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
TXB2D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -x-- xxxx -u-- uuuu -u-- uuuu
TXB2EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
TXB2SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
TXB2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0-00 0000 0-00 uuuu u-uu
RXM1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXM1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXM1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
RXM1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXM0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXM0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXM0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
RXM0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF5EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF5EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF5SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
RXF5SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF4EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF4EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF4SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
2011 Microchip Technology Inc. Preliminary DS39977C-page 97
Page 98
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
RXF4SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF3EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF3EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF3SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
RXF3SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF2EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF2EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF2SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
RXF2SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
RXF1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
RXF0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu
RXF0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
CANCON_RO4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT_RO4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
B5D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu uuuu uuuu
B5EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu uuuu
B5SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B5CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CANCON_RO5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
DS39977C-page 98 Preliminary 2011 Microchip Technology Inc.
Page 99
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
CANSTAT_RO5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
B4D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu
B4EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B4SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu
B4SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu xxxx xxxx
B4CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CANCON_RO6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT_RO6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
B3D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu
B3EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu
B3SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B3CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CANCON_RO7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
B2D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
2011 Microchip Technology Inc. Preliminary DS39977C-page 99
Page 100
PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on
Register Applicable Devices
B2D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu
B2EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu
B2SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CANCON_RO8 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
B1D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu
B1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu
B1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu
CANCON_RO9 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
CANSTAT_RO PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu
B0D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B0D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B0D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B0D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
B0D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
Reset,
Brown-out
Reset
RESET Instruction,
Resets,
MCLR
WDT Reset,
Stack Resets
Wake-up via
WDT
or Interrupt
DS39977C-page 100 Preliminary 2011 Microchip Technology Inc.
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