PIC18F66K80 Family
Data Sheet
28/40/44/64-Pin, Enhanced Flash
Microcontrollers, with ECAN™
and nanoWatt XLP Technology
2011 Microchip Technology Inc. Preliminary DS39977C
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC
logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-851-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS39977C-page 2 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
28/40/44/64-Pin, Enhanced Flash Microcontrol lers
with ECAN™ and nanoWatt XLP Technology
Power-Managed Modes:
• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
• Two-Speed Oscillator Start-up
• Fail-Safe Clock Monitor (FSCM)
• Power-Saving Peripheral Module Disable (PMD)
• Ultra Low-Power Wake-up
• Fast Wake-up, 1 s, Typical
• Low-Power WDT, 300 nA, Typical
• Run mode Currents Down to Very Low 3.8 A, Typical
• Idle mode Currents Down to Very Low 880 nA, Typical
• Sleep mode Current Down to Very Low 13 nA, Typical
ECAN Bus Module Features:
• Conforms to CAN 2.0B Active Specification
• Three Operating modes:
- Legacy mode (full backward compatibility with
existing PIC18CXX8/FXX8 CAN modules)
- Enhanced mode
- FIFO mode or programmable TX/RX buffers
• Message Bit Rates up to 1 Mbps
• DeviceNet™ Data Byte Filter Support
• Six Programmable Receive/Transmit Buffers
• Three Dedicated Transmit Buffers with Prioritization
• Two Dedicated Receive Buffers
TABLE 1: DEVICE COMPARISON
ECAN Bus Module Features (Continued):
• 16 Full, 29-Bit Acceptance Filters with Dynamic
Association
• Three Full, 29-Bit Acceptance Masks
• Automatic Remote Frame Handling
• Advanced Error Management Features
Special Microcontroller Features:
• Operating Voltage Range: 1.8V to 5.5V
• On-Chip 3.3V Regulator
• Operating Speed up to 64 MHz
• Up to 64 Kbytes On-Chip Flash Program Memory:
- 10,000 erase/write cycle, typical
- 20 years minimum retention, typical
• 1,024 Bytes of Data EEPROM:
- 100,000 Erase/write cycle data EEPROM
memory, typical
• 3.6 Kbytes of General Purpose Registers (SRAM)
• Three Internal Oscillators: LF-INTOSC (31 KHz),
MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz)
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 4,194s
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug via Two Pins
• Programmable BOR
• Programmable LVD
Device
PIC18F25K80 32 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF25K80 32 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F26K80 64 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF26K80 64 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F45K80 32 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF45K80 32 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F46K80 64 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18LF46K80 64 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No
PIC18F65K80 32 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
PIC18LF65K80 32 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
PIC18F66K80 64 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
PIC18LF66K80 64 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes
2011 Microchip Technology Inc. Preliminary DS39977C-page 3
Program
Memory
Data
Memory
(Bytes)
Data EE
(Bytes)
Pins I/O
CCP/
CTMU
12-Bit A/D
ECCP
Timers
Channels
EUSART
8-Bit/16-Bit
Comparators
ECAN™
MSSP
BORMV/LVD
DSM
PIC18F66K80 FAMILY
Peripheral Highlights:
• Five CCP/ECCP modules:
- Four Capture/Compare/PWM (CCP) modules
- One Enhanced Capture/Compare/PWM
(ECCP) module
• Five 8/16-Bit Timer/Counter modules:
- Timer0: 8/16-bit timer/counter with 8-bit
programmable prescaler
- Timer1, 3: 16-bit timer/counter
- Timer2, 4: 8-bit timer/counter
• Two Analog Comparators
• Configurable Reference Clock Output
• Charge Time Measurement Unit (CTMU):
- Capacitance measurement
- Time measurement with 1 ns typical resolution
- Integrated voltage reference
• High-Current Sink/Source 25 mA/25 mA (PORTB
and PORTC)
• Up to Four External Interrupts
• One Master Synchronous Serial Port
(MSSP) module:
- 3/4-wire SPI (supports all four SPI modes)
2
C™ Master and Slave modes
-I
• Two Enhanced Addressable USART modules:
- LIN/J2602 support
- Auto-Baud Detect (ABD)
• 12-Bit A/D Converter with up to 11 Channels:
- Auto-acquisition and Sleep operation
- Differential Input mode of operation
• Data Signal Modulator module:
- Select modulator and carrier sources from vari-
ous module outputs
• Integrated Voltage Reference
DS39977C-page 4 Preliminary 2011 Microchip Technology Inc.
Pin Diagrams
RA1/AN1
RB3/CANRX/C2OUT/P1D/CTED2/INT3
RA2/V
REF-/AN2
V
DDCORE/VCAP
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI
OSC1/CLKIN/RA7
28-Pin QFN
(1)
1
2
3
4
7
5
6
21
20
19
18
15
17
16
28
272625
24
23
22
8
9
101112
13
14
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RB7/PGD/T3G/RX2/DT2/KBI3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F2XK80
PIC18LF2XK80
RA3/VREF+/AN3
V
SS
OSC2/CLKOUT/RA6
RB2/CANTX/C1OUT/P1C/CTED1/INT2
RB1/AN8/C1INB/P1B/CTDIN/INT1
RB0/AN10/C1INA/FLT0/INT0
V
DD
VSS
RC7/CANRX/RX1/DT1/CCP4
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/TX2/CK2/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
PIC18F66K80 FAMILY
2011 Microchip Technology Inc. Preliminary DS39977C-page 5
PIC18F66K80 FAMILY
RA1/AN1
RB3/CANRX/C2OUT/P1D/CTED2/INT3
RA2/V
REF-/AN2
V
DDCORE/VCAP
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI
OSC1/CLKIN/RA7
28-Pin SSOP/SPDIP/SOIC
RB7/PGD/T3G/RX2/DT2/KBI31
2
3
4
7
5
6
8
9
10
11
14
12
13
19
18
15
17
16
24
23
20
22
21
25
26
27
28
PIC18F2XK80
PIC18LF2XK80
RA3/VREF+/AN3
V
SS
OSC2/CLKOUT/RA6
RB2/CANTX/C1OUT/P1C/CTED1/INT2
RB1/AN8/C1INB/P1B/CTDIN/INT1
RB0/AN10/C1INA/FLT0/INT0
V
DD
VSS
RC7/CANRX/RX1/DT1/CCP4
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/TX2/CK2/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
1
2
3
4
7
5
6
8
9
10
11
14
12
13
19
18
15
17
16
24
23
20
22
21
25
26
27
28
PIC18F4XK80
PIC18LF4XK80
40-Pin PDIP
MCLR/RE3
RA0/CV
REF/AN0/ULPWU
RC0/SOSCO/SCLKI
RC1/ISOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
32
31
30
29
33
34
35
36
37
38
39
40
MCLR/RE3
RA0/CV
REF/AN0/ULPWU
RA1/AN1/C1INC
RA2/V
REF-/AN2/C2INC
RA3/V
REF+/AN3
V
DDCORE/VCAP
RA5/AN4/HLVDIN/T1CKI/SS
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
VDD
VSS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RB3/CANRX/CTED2/INT3
RB7/PGD/T3G/KBI3
RB2/CANTX/CTED1/INT2
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
V
DD
VSS
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
RD7/RX2/DT2/P1D/PSP7
RD6/TX2/CK2/P1C/PSP6
RD5/P1B/PSP5
RD4/ECCP1/P1A/PSP4
RC7/CANRX/RX1/DT1/CCP4
RC6/CANTX/TX1/CK1/CCP3
RC5/SDO
RC4/SDA/SDI
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
Pin Diagrams (Continued)
DS39977C-page 6 Preliminary 2011 Microchip Technology Inc.
44-Pin TQFP
RA1/AN1/C1INC
RB3/CANRX/CTED2/INT3
RA2/VREF-/AN2/C2INC
VDDCORE/VCAP
RA5/AN4/HLVDIN/T1CKI/SS
1
2
3
4
7
5
6
33
32
19
18
15
17
28
27
26
25
24
23
22
8
9
10
11
121314
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RB7/PGD/T3G/KBI3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F4XK80
PIC18LF4XK80
RA3/VREF+/AN3
VSS
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
V
SS
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
16
20
21
29
30
31
37
38
41
39
34
444342
40
36
35
RC7/CANRX/RX1/DT1/CCP4
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
RD6/TX2/CK2/P1C/PSP6
RD7/RX2/DT2/P1D/PSP7
V
DD
RB2/CANTX/CTED1/INT2
N/C
VDD
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
N/C
N/C
N/C
PIC18F66K80 FAMILY
Pin Diagrams (Continued)
2011 Microchip Technology Inc. Preliminary DS39977C-page 7
PIC18F66K80 FAMILY
44-Pin QFN
(1)
Note 1: For the QFN package, it is recommended that the bottom pad be connected to V
SS.
RA1/AN1/C1INC
RB3/CANRX/CTED2/INT3
RA2/VREF-/AN2/C2INC
VDDCORE/VCAP
RA5/AN4/HLVDIN/T1CKI/SS
1
2
3
4
7
5
6
33
32
19
18
15
17
28
27
26
25
24
23
22
8
9
10
11
121314
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RB7/PGD/T3G/KBI3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F4XK80
PIC18LF4XK80
RA3/VREF+/AN3
VSS
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
V
SS
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
16
20
21
29
30
31
37
38
41
39
34
444342
40
36
35
RC7/CANRX/RX1/DT1/CCP4
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
RD6/TX2/CK2/P1C/PSP6
RD7/RX2/DT2/P1D/PSP7
V
DD
RB2/CANTX/CTED1/INT2
N/C
VDD
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
N/C
N/C
N/C
Pin Diagrams (Continued)
DS39977C-page 8 Preliminary 2011 Microchip Technology Inc.
Pin Diagrams (Continued)
64-Pin QFN
(1)
/TQFP
RA1/AN1/C1INC
RB3/CANRX/CTED2/INT3
RA2/VREF-/AN2/C2INC
RA5/AN4/HLVDIN/T1CKI/SS
1
2
3
4
7
5
6
43
42
24
23
20
22
38
37
36
35
34
33
27
8
9
10
11
171819
RA0/CVREF/AN0/ULPWU
MCLR
/RE3
RC0/SOSCO/SCLKI
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
PIC18F6XK80
PIC18LF6XK80
RA3/VREF+/AN3
VSS
RB1/AN8/CTDIN/INT1
RB0/AN10/FLT0/INT0
RC4/SDA/SDI
RC5/SDO
RC6/CCP3
RB6/PGC/KBI2
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
21
25
26
39
40
41
57
58
61
59
54
646362
60
56
55
RC7/CCP4
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
RD6/P1C/PSP6
RD7/P1D/PSP7
AV
DD
RB2/CANTX/CTED1/INT2
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RE0/AN5/RD
RE1/AN6/C1OUT/WR
RE2/AN7/C2OUT/CS
RD0/C1INA/PSP0
RD1/C1INB/PSP1
RD3/C2INB/CTMUI/PSP3
RD2/C2INA/PSP2
RF0/MDMIN
12
13
14
15
16
29
28
32
30
31
48
47
44
45
46
52
53
49
51
50
RG0/RX1/DT1
RG1/CANTX2
V
DD
RG2/T3CKI
RG3/TX1/CK1
RG4/T0CKI
RF1
RE5/CANTX
V
DD
VSS
RE4/CANRX
VDDCORE/VCAP
RF2/MDCIN1
RF3
A
VDD
VDD
AVSS
VSS
RF4/MDCIN2
RF5
RF6/MDOUT
RF7
VSSVDD
RE6/RX2/DT2
RE7/TX2/CK2
RB7/PGD/T3G/KBI3
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
PIC18F66K80 FAMILY
2011 Microchip Technology Inc. Preliminary DS39977C-page 9
PIC18F66K80 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers......................................................................................... 47
3.0 Oscillator Configurations ............................................................................................................................................................ 53
4.0 Power-Managed Modes ............................................................................................................................................................. 67
5.0 Reset.......................................................................................................................................................................................... 81
6.0 Memory Organization ............................................................................................................................................................... 105
7.0 Flash Program Memory............................................................................................................................................................ 135
8.0 Data EEPROM Memory ........................................................................................................................................................... 145
9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 151
10.0 Interrupts .................................................................................................................................................................................. 153
11.0 I/O Ports ................................................................................................................................................................................... 177
12.0 Data Signal Modulator .............................................................................................................................................................. 201
13.0 Timer0 Module ......................................................................................................................................................................... 211
14.0 Timer1 Module ......................................................................................................................................................................... 215
15.0 Timer2 Module ......................................................................................................................................................................... 227
16.0 Timer3 Module ......................................................................................................................................................................... 229
17.0 Timer4 Modules........................................................................................................................................................................ 239
18.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 241
19.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 259
20.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 271
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 293
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 339
23.0 12-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 363
24.0 Comparator Module.................................................................................................................................................................. 377
25.0 Comparator Voltage Reference Module ................................................................................................................................... 385
26.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 389
27.0 ECAN Module........................................................................................................................................................................... 395
28.0 Special Features of the CPU.................................................................................................................................................... 461
29.0 Instruction Set Summary.......................................................................................................................................................... 487
30.0 Development Support............................................................................................................................................................... 537
31.0 Electrical Characteristics.......................................................................................................................................................... 541
32.0 Packaging Information.............................................................................................................................................................. 589
Appendix A: Revision History............................................................................................................................................................. 609
Appendix B: Migration to PIC18F66K80 Family ................................................................................................................................. 609
Index ................................................................................................................................................................................................. 611
The Microchip Web Site..................................................................................................................................................................... 625
Customer Change Notification Service .............................................................................................................................................. 625
Customer Support .............................................................................................................................................................................. 625
Reader Response .............................................................................................................................................................................. 626
Product Identification System............................................................................................................................................................. 627
DS39977C-page 10 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2011 Microchip Technology Inc. Preliminary DS39977C-page 11
PIC18F66K80 FAMILY
NOTES:
DS39977C-page 12 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F25K80 • PIC18LF25K80
• PIC18F26K80 • PIC18LF26K80
• PIC18F45K80 • PIC18LF45K80
• PIC18F46K80 • PIC18LF46K80
• PIC18F65K80 • PIC18LF65K80
• PIC18F66K80 • PIC18LF66K80
This family combines the traditional advantages of all
PIC18 microcontrollers – namely, high computational
performance and a rich feature set – with an extremely
competitive price point. These features make the
PIC18F66K80 family a logical choice for many
high-performance applications where price is a primary
consideration.
1.1 Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F66K80 family incorporate a range of features that can significantly reduce
power consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the Internal RC oscillator, power consumption during code execution
can be reduced.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further.
• On-the-Fly Mo de Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• nanoW at t XL P: An extra low-power BOR and
low-power Watchdog timer
1.1.2 OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F66K80 family offer
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• External Resistor/Capacitor (RC); RA6 available
• External Resistor/Capacitor with Clock Out
(RCIO)
• Three External Clock modes:
- External Clock (EC); RA6 available
- External Clock with Clock Out (ECIO)
- External Crystal (XT, HS, LP)
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes which
allows clock speeds of up to 64 MHz. PLL can
also be used with the internal oscillator.
• An internal oscillator block that provides a 16 MHz
clock (±2% accuracy) and an INTOSC source
(approximately 31 kHz, stable over temperature
DD)
and V
- Operates as HF-INTOSC or MF-INTOSC
when block is selected for 16 MHz or
500 kHz
- Frees the two oscillator pins for use as
additional general purpose I/O
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.3 MEMORY OPTIONS
The PIC18F66K80 family provides ample room for
application code, from 32 Kbytes to 64 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 10,000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
The Flash program memory is readable and writable.
During normal operation, the PIC18F66K80 family also
provides plenty of room for dynamic application data
with up to 3.6 Kbytes of data RAM.
1.1.4 EXTENDED INSTRUCTION SET
The PIC18F66K80 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
2011 Microchip Technology Inc. Preliminary DS39977C-page 13
PIC18F66K80 FAMILY
1.1.5 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 28-pin,
40-pin, 44-pin and 64-pin members, or even jumping
from smaller to larger memory devices.
The PIC18F66K80 family is also largely pin compatible
with other PIC18 families, such as the PIC18F4580,
PIC18F4680, and PIC18F8680 families of microcontrollers with an ECAN module. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining a similar
feature set.
1.2 Other Special Features
• Communications: The PIC18F66K80 family incor-
porates a range of serial communication peripherals
including two Enhanced USART that support
LIN/J2602, one Master SSP module capable of both
SPI and I
operation and an Enhanced CAN module.
• CCP Modules: PIC18F66K80 family devices
incorporate four Capture/Compare/PWM (CCP)
modules. Up to four different time bases can be
used to perform several different operations at
once.
• ECCP Modules: The PIC18F66K80 family has
one Enhanced CCP (ECCP) module to maximize
flexibility in control applications:
- Up to four different time bases for performing
- Up to four PWM outputs
- Other beneficial features, such as polarity
• 12-Bit A/D Converter: The PIC18F66K80 family
has a differential ADC. It incorporates programmable acquisition time, allowing for a channel to
be selected and a conversion to be initiated
without waiting for a sampling period, and thus,
reducing code overhead.
2
C™ (Master and Slave) modes of
several different operations at once
selection, programmable dead time,
auto-shutdown and restart, and Half-Bridge
and Full-Bridge Output modes
• Charge Time Measurement Unit (CTMU): The
CTMU is a flexible analog module that provides
accurate differential time measurement between
pulse sources, as well as asynchronous pulse
generation.
Together with other on-chip analog modules, the
CTMU can precisely measure time, measure
capacitance or relative changes in capacitance, or
generate output pulses that are independent of the
system clock.
• LP Watchdog T im er (WDT): This enhanced
version incorporates a 22-bit prescaler, allowing
an extended time-out range that is stable across
operating voltage and temperature. See
Section 31.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family Members
Devices in the PIC18F66K80 family are available in
28-pin, 40/44-pin and 64-pin packages. Block diagrams
for each package are shown in Figure 1-1, Figure 1-2
and Figure 1-3, respectively.
The devices are differentiated from each other in these
ways:
• Flash Program Memory:
- PIC18FX5K80 (PIC18F25K80, PIC18F45K80
and PIC18F45K80) – 32 Kbytes
- PIC18FX6K80 (PIC18F26K80, PIC18F46K80
and PIC18F66K80) – 64 Kbytes
• I/O Ports:
- PIC18F2XK80 (28-pin devices) – Three
bidirectional ports
- PIC18F4XK80 (40/44-pin devices) – Five
bidirectional ports
- PIC18F6XK80 (64-pin devices) – Seven
bidirectional ports
All other features for devices in this family are identical.
These are summarized in Table 1-1, Tab le 1 -2 and
Table 1-3.
The pinouts for all devices are listed in Ta bl e 1 -4 ,
Table 1-5 and Tab le 1 -6 .
DS39977C-page 14 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XK80 (28-PIN DEVICES)
Features PIC18F25K80 PIC18F26K80
Operating Frequency DC – 64 MHz
Program Memory (Bytes) 32K 64K
Program Memory (Instructions) 16,384 32,768
Data Memory (Bytes) 3.6K
Interrupt Sources 31
I/O Ports Ports A, B, C
Parallel Communications Parallel Slave Port (PSP)
Timers Five
Comparators Two
CTMU Yes
Capture/Compare/PWM (CCP)
Modules
Enhanced CCP (ECCP) Modules One
Serial Communications One MSSP and Two Enhanced USARTs (EUSART)
12-Bit Analog-to-Digital Module Eight Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 28-Pin QFN-S, SOIC, SPDIP and SSOP
Four
WDT (PWRT, OST)
,
TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XK80 (40/44-PIN DEVICES)
Features PIC18F45K80 PIC18F46K80
Operating Frequency DC – 64 MHz
Program Memory (Bytes) 32K 64K
Program Memory (Instructions) 16,384 32,768
Data Memory (Bytes) 3.6K
Interrupt Sources 32
I/O Ports Ports A, B, C, D, E
Parallel Communications Parallel Slave Port (PSP)
Timers Five
Comparators Two
CTMU Yes
Capture/Compare/PWM (CCP)
Modules
Enhanced CCP (ECCP) Modules One
Serial Communications One MSSP and Two Enhanced USARTs (EUSART)
12-Bit Analog-to-Digital Module Eleven Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 40-Pin PDIP and 44-Pin QFN and TQFP
Four
WDT (PWRT, OST)
,
2011 Microchip Technology Inc. Preliminary DS39977C-page 15
PIC18F66K80 FAMILY
TABLE 1-3: DEVICE FEATURES FOR THE PIC18F6XK80 (64-PIN DEVICES)
Features PIC18F65K80 PIC18F66K80
Operating Frequency DC – 64 MHz
Program Memory (Bytes) 32K 64K
Program Memory (Instructions) 16,384 32,768
Data Memory (Bytes) 3.6K
Interrupt Sources 32
I/O Ports Ports A, B, C, D, E, F, G
Parallel Communications Parallel Slave Port (PSP)
Timers Five
Comparators Two
CTMU Yes
Capture/Compare/PWM (CCP)
Modules
Enhanced CCP (ECCP) Modules One
DSM Yes Yes
Serial Communications One MSSP and Two Enhanced USARTs (EUSART)
12-Bit Analog-to-Digital Module Eleven Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 64-Pin QFN and TQFP
Four
WDT (PWRT, OST)
,
DS39977C-page 16 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-4 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
ADC
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
RC0:RC7
(1)
PORTB
RB0:RB7
(1)
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Volt ag e
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
Timer 2/4
Timer 3
1/2
CCP2/3/4/5
ECCP1
PORTA
RA0:RA3
RA5:RA7
(1,2)
PORTE
RE3
(1,3)
ECAN
MSSP
FIGURE 1-1: PIC18F2XK80 (28-PIN) BLOCK DIAGRAM
2011 Microchip Technology Inc. Preliminary DS39977C-page 17
PIC18F66K80 FAMILY
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-5 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
ADC
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
PORTD
RC0:RC7
(1)
RD0:RD7
(1)
PORTB
RB0:RB7
(1)
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Volt ag e
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
2/3/4/5
Timer2/4
Timer3
1/2
CCP
ECCP1
PORTA
RA0:RA3
RA5:RA7
(1,2)
PORTE
RE0:RE3
(1,3)
ECAN
PSP
MSSP
FIGURE 1-2: PIC18F4XK80 (40/44-PIN) BLOCK DIAGRAM
DS39977C-page 18 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Ta b le 1 - 6 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section3.0 “Oscillator
Configurations”.
3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
ADC
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
PORTD
PORTF
PORTG
RC0:RC7
(1)
RD0:RD7
(1)
RF0:RF7
(1)
RG0:RG4
(1)
PORTB
RB0:RB7
(1)
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Time r
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Time r
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Vol tage
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
Timer2/4
Timer3
1/2
CCP2/3/4/5
ECCP1
PORTA
RA0:RA3
RA5:RA7
(1,2)
PORTE
RE0:RE7
(1,3)
ECAN
DSM
PSP
MSSP
FIGURE 1-3: PIC18F6XK80 (64-PIN) BLOCK DIAGRAM
2011 Microchip Technology Inc. Preliminary DS39977C-page 19
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS
Pin Number
Pin
Buffer
Type
Type
I ST Master Clear (input) or programming voltage (input).This
pin is an active-low Reset to the device.
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
General purpose I/O pin.
CMOS
Connects to crystal or resonator in Crystal Oscillator mode.
has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
CMOS
2
C™ = I2C/SMBus input buffer
Description
Pin Name
MCLR/RE3 26 1
MCLR
RE3 I ST General purpose, input only pin.
OSC1/CLKIN/RA7 6 9
OSC1 I ST Oscillator crystal input.
CLKIN I CMOS External clock source input. Always associated with pin
RA7 I/O ST/
OSC2/CLKOUT/RA6 7 10
OSC2 O — Oscillator crystal output.
CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which
RA6 I/O ST/
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
QFN
SSOP/
SPDIP/
SOIC
DS39977C-page 20 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
RA0/CVREF/AN0/ULPWU 27 2
RA0 I/O ST/
REF O Analog Comparator reference voltage output.
CV
AN0 I Analog Analog Input 0.
ULPWU I Analog Ultra low-power wake-up input.
RA1/AN1 28 3
RA1 I/O ST/
AN1 I Analog Analog Input 1.
REF-/AN2 1 4
RA2/V
RA2 I/O ST/
V
REF- I Analog A/D reference voltage (low) input.
AN2 I Analog Analog Input 2.
RA3/VREF+/AN3 2 5
RA3 I/O ST/
REF+ I Analog A/D reference voltage (high) input.
V
AN3 I Analog Analog Input 3.
RA5/AN4/C2INB/HLVDIN/
T1CKI/SS
Legend: CMOS = CMOS compatible input or output I
/CTMUI
RA5 I/O ST/
AN4 I Analog Analog Input 4.
C2INB I Analog Comparator 2 Input B.
HLVDIN I Analog High/Low-Voltage Detect input.
T1CKI I ST Timer1 clock input.
SS
CTMUI CTMU pulse generator charger for the C2INB.
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
SSOP/
QFN
SPDIP/
SOIC
47
Buffer
Type
Type
PORTA is a bidirectional I/O port.
General purpose I/O pin.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
I ST SPI slave select input.
2
C™ = I2C/SMBus input buffer
Description
2011 Microchip Technology Inc. Preliminary DS39977C-page 21
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
RB0/AN10/C1INA/FLT0/
INT0
RB0 I/O ST/
AN10 I Analog Analog Input 10.
C1INA I Analog Comparator 1 Input A.
FLT0 I ST Enhanced PWM Fault input for ECCP1.
INT0 I ST External Interrupt 0.
RB1/AN8/C1INB/P1B/
CTDIN/INT1
RB1 I/O ST/
AN8 I Analog Analog Input 8.
C1INB I Analog Comparator 1 Input B.
P1B O CMOS Enhanced PWM1 Output B.
CTDIN I ST CTMU pulse delay input.
INT1 I ST External Interrupt 1.
RB2/CANTX/C1OUT/
P1C/CTED1/INT2
RB2 I/O ST/
CANTX O CMOS CAN bus TX.
C1OUT O CMOS Comparator 1 output.
P1C O CMOS Enhanced PWM1 Output C.
CTED1 I ST CTMU Edge 1 input.
INT2 I ST External Interrupt 2.
RB3/CANRX/C2OUT/
P1D/CTED2/INT3
RB3 I/O ST/
CANRX I ST CAN bus RX.
C2OUT O CMOS Comparator 2 output.
P1D O CMOS Enhanced PWM1 Output D.
CTED2 I ST CTMU Edge 2 input.
INT3 I ST External Interrupt 3.
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
SSOP/
QFN
SPDIP/
18 21
19 22
20 23
21 24
SOIC
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
Description
PORTB is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
2
C™ = I2C/SMBus input buffer
DS39977C-page 22 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
QFN
SSOP/
SPDIP/
SOIC
Type
Buffer
Type
Description
RB4/AN9/C2INA/ECCP1/
P1A/CTPLS/KBI0
RB4 I/O ST/
AN9 I Analog Analog Input 9.
C2INA I Analog Comparator 2 Input A.
ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
P1A O CMOS Enhanced PWM1 Output A.
CTPLS O ST CTMU pulse generator output.
KBI0 I ST Interrupt-on-change pin.
RB5/T0CKI/T3CKI/CCP5/
KBI1
RB5 I/O ST/
T0CKI I ST Timer0 external clock input.
T3CKI I ST Timer3 external clock input.
CCP5 I/O ST/
KBI1 I ST Interrupt-on-change pin.
RB6/PGC/TX2/CK2/KBI2 24 27
RB6 I/O ST/
PGC I ST In-Circuit Debugger and ICSP™ programming clock input
TX2 O CMOS EUSART asynchronous transmit.
CK2 I/O ST EUSART synchronous clock (see related RX2/DT2).
KBI2 I ST Interrupt-on-change pin.
RB7/PGD/T3G/RX2/DT2/
KBI3
RB7 I/O ST/
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.
T3G I ST Timer3 external clock gate input.
RX2 I ST EUSART asynchronous receive.
DT2 I/O ST EUSART synchronous data (see related TX2/CK2).
KBI3 I ST Interrupt-on-change pin.
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
22 25
23 26
25 28
CMOS
CMOS
CMOS
CMOS
CMOS
Digital I/O.
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
Digital I/O.
pin.
Digital I/O.
2
C™ = I2C/SMBus input buffer
2011 Microchip Technology Inc. Preliminary DS39977C-page 23
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
RC0/SOSCO/SCLKI 8 11
RC0 I/O ST/
SOSCO I ST Timer1 oscillator output.
SCLKI I ST Digital SOSC input.
RC1/SOSCI 9 12
RC1 I/O ST/
SOSCI I CMOS SOSC oscillator input.
RC2/T1G/CCP2 10 13
RC2 I/O ST/
T1G I ST Timer1 external clock gate input.
CCP2 I/O ST Capture 2 input/Compare 2 output/PWM2 output.
RC3/REFO/SCL/SCK 11 14
RC3 I/O ST/
REFO O — Reference clock out.
SCL I/O I
SCK I/O ST Synchronous serial clock input/output for SPI mode.
RC4/SDA/SDI 12 15
RC4 I/O ST/
SDA I/O I2CI2C data input/output.
SDI I ST SPI data in.
RC5/SDO 13 16
RC5 I/O ST/
SDO O CMOS SPI data out.
RC6/CANTX/TX1/CK1/
CCP3
RC6 I/O ST/
CANTX O CMOS CAN bus TX.
TX1 O CMOS EUSART asynchronous transmit.
CK1 I/O ST EUSART synchronous clock. (See related RX1/DT1.)
CCP3 I/O ST/
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
SSOP/
QFN
SPDIP/
14 17
SOIC
Type
Buffer
Type
PORTC is a bidirectional I/O port.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
2
C Synchronous serial clock input/output for I2C mode.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Capture 3 input/Compare 3 output/PWM3 output.
CMOS
2
C™ = I2C/SMBus input buffer
Description
DS39977C-page 24 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
QFN
SSOP/
SPDIP/
SOIC
Type
Buffer
Type
Description
RC7/CANRX/RX1/DT1/
CCP4
RC7 I/O ST/
CANRX I ST CAN bus RX.
RX1 I ST EUSART asynchronous receive.
DT1 I/O ST EUSART synchronous data (see related TX2/CK2).
CCP4 I/O ST
VSS 58P
VSS Ground reference for logic and I/O pins.
SS 16 19
V
VSS Ground reference for logic and I/O pins.
VDDCORE/VCAP 36P
DDCORE External filter capacitor connection.
V
VCAP External filter capacitor connection
VDD 17 20 P
DD Positive supply for logic and I/O pins.
V
Legend: CMOS = CMOS compatible input or output I
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
15 18
CMOS
CMOS
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
2
C™ = I2C/SMBus input buffer
2011 Microchip Technology Inc. Preliminary DS39977C-page 25
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
/RE3 1 18
MCLR
MCLR
RE3 I ST General purpose, input only pin.
OSC1/CLKIN/RA7 13 30
OSC1 I ST Oscillator crystal input.
CLKIN I CMOS External clock source input. Always associated with pin
RA7 I/O ST/
OSC2/CLKOUT/RA6 14 31
OSC2 O — Oscillator crystal output. Connects to crystal or resonator in
CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which
RA6 I/O ST/
Legend: I
2
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
QFN/
TQFP
Pin
Buffer
Type
Type
I ST Master Clear (input) or programming voltage (input).This
pin is an active-low Reset to the device.
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.
General purpose I/O pin.
CMOS
Crystal Oscillator mode.
has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
CMOS
Description
DS39977C-page 26 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RA0/CVREF/AN0/ULPWU 2 19
RA0 I/O ST/
CV
REF O Analog Comparator reference voltage output.
AN0 I Analog Analog Input 0.
ULPWU I Analog Ultra low-power wake-up input.
RA1/AN1/C1INC 3 20
RA1 I/O ST/
AN1 I Analog Analog Input 1.
C1INC I Analog Comparator 1 Input C.
REF-/AN2/C2INC 4 21
RA2/V
RA2 I/O ST/
V
REF- I Analog A/D reference voltage (low) input.
AN2 I Analog Analog Input 2.
C2INC I Analog Comparator 2 Input C.
REF+/AN3 5 22
RA3/V
RA3 I/O ST/
V
REF+ I Analog A/D reference voltage (high) input.
AN3 I Analog Analog Input 3.
RA5/AN4/HLVDIN/T1CKI/SS724
PDIP
QFN/
TQFP
Pin
Type
Buffer
Type
PORTA is a bidirectional I/O port.
General purpose I/O pin.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Description
RA5 I/O ST/
CMOS
AN4 I Analog Analog Input 4.
HLVDIN I Analog High/Low-Voltage Detect input.
T1CKI I ST Timer1 clock input.
SS
2
Legend: I
2011 Microchip Technology Inc. Preliminary DS39977C-page 27
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
I ST SPI slave select input.
Digital I/O.
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB0/AN10/FLT0/INT0 33 8
RB0 I/O ST/
AN10 I Analog Analog Input 10.
FLT0 I ST Enhanced PWM Fault input for ECCP1.
INT0 I ST External Interrupt 0.
RB1/AN8/CTDIN/INT1 34 9
RB1 I/O ST/
AN8 I Analog Analog Input 8.
CTDIN I ST CTMU pulse delay input.
INT1 I ST External Interrupt 1.
RB2/CANTX/CTED1/
INT2
RB2 I/O ST/
CANTX O CMOS CAN bus TX.
CTED1 I ST CTMU Edge 1 input.
INT2 I ST External Interrupt 2.
RB3/CANRX/CTED2/
INT3
RB3 I/O ST/
CANRX I ST CAN bus RX.
CTED2 I ST CTMU Edge 2 input.
INT3 I ST External Interrupt 3.
RB4/AN9/CTPLS/KBI0 37 14
RB4 I/O ST/
AN9 I Analog Analog Input 9.
CTPLS O ST CTMU pulse generator output.
KBI0 I ST Interrupt-on-change pin.
RB5/T0CKI/T3CKI/CCP5/
KBI1
RB5 I/O ST/
T0CKI I ST Timer0 external clock input.
T3CKI I ST Timer3 external clock input.
CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output.
KBI1 I ST Interrupt-on-change pin.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
35 10
36 11
38 15
QFN/
TQFP
Pin
Type
Buffer
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
PORTB is a bidirectional I/O port.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
DS39977C-page 28 Preliminary 2011 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB6/PGC/KBI2 39 16
RB6 I/O ST/
PGC I ST In-Circuit Debugger and ICSP™ programming clock input
KBI2 I ST Interrupt-on-change pin.
RB7/PGD/T3G/KBI3 40 17
RB7 I/O ST/
PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin.
T3G I ST Timer3 external clock gate input.
KBI3 I ST Interrupt-on-change pin.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
QFN/
TQFP
Pin
Type
Buffer
Type
CMOS
CMOS
Description
Digital I/O.
pin.
Digital I/O.
2011 Microchip Technology Inc. Preliminary DS39977C-page 29
PIC18F66K80 FAMILY
TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC0/SOSCO/SCLKI 15 32
RC0 I/O ST/
SOSCO I ST SOSC oscillator output.
SCLKI I ST Digital SOSC input.
RC1/SOSCI 16 35
RC1 I/O ST/
SOSCI I CMOS SOSC oscillator input.
RC2/T1G/CCP2 17 36
RC2 I/O ST/
T1G I ST Timer1 external clock gate input.
CCP2 I/O ST/
RC3/REFO/SCL/SCK 18 37
RC3 I/O ST/
REFO O CMOS Reference clock out.
SCL I/O I
SCK I/O ST Synchronous serial clock input/output for SPI mode.
RC4/SDA/SDI 23 42
RC4 I/O ST/
SDA I/O I2CI2C data input/output.
SDI I ST SPI data in.
RC5/SDO 24 43
RC5 I/O ST/
SDO O CMOS SPI data out.
RC6/CANTX/TX1/CK1/
CCP3
RC6 I/O ST/
CANTX O CMOS CAN bus TX.
TX1 O CMOS EUSART synchronous transmit.
CK1 I/O ST EUSART synchronous clock (see related RX2/DT2).
CCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output.
2
Legend: I
C™ = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P= Power
PDIP
25 44
QFN/
TQFP
Pin
Type
Buffer
Type
PORTC is a bidirectional I/O port.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Capture 2 input/Compare 2 output/PWM2 output.
CMOS
Digital I/O.
CMOS
2
C Synchronous serial clock input/output for I2C mode.
Digital I/O.
CMOS
Digital I/O.
CMOS
Digital I/O.
CMOS
Description
DS39977C-page 30 Preliminary 2011 Microchip Technology Inc.
Loading...