Datasheet PIC18F47J13 Datasheet
PIC18F47J13 Family
Data Sheet
28/44-Pin, High-Performance
Microcontrollers with
nanoWatt XLP Technology
2010 Microchip Technology Inc. Preliminary DS39974A
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC
logo, rfPIC and UNI/O are registered trademarks of
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MXDEV, MXLAB, SEEVAL and The Embedded Control
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
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© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-304-2
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS39974A-page 2 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
PIC18F47J13 Family 28/44-Pi n, High- Perf ormance Mi crocontrollers
with nanoWatt XLP Technology
Power Management Features with nanoWatt XLP for Extreme Low Power:
• Deep Sleep mode: CPU Off, Peripherals Off, SRAM Off,
Currents Down to 9 nA and 700 nA with RTCC:
- Able to wake-up on external triggers, programmable WDT
or RTCC alarm
- Ultra Low-Power Wake-up (ULPWU)
• Sleep mode: CPU Off, Peripherals Off, SRAM On, Fast
Wake-up, Currents Down to 0.2 A, 2V Typical
• Idle: CPU Off, SRAM On, Currents Down to
1.7 A Typical
• Run: CPU On, SRAM On, Currents Down to
5.8 A Typical
• Timer1 Oscillator w/RTCC: 0.7 A, 32 kHz Typical
• Watchdog Timer: 0.33 A, 2V Typical
Flexible Oscillator Struc ture:
• Two External Clock modes, Up to 48 MHz (12 MIPS)
• Integrated Crystal/Resonator Driver
• Low-Power 31 kHz Internal RC Oscillator
• Tunable Internal Oscillator (31 kHz to 8 MHz,
±0.15% Typical, ±1% Max.)
• Precision 48 MHz PLL or 4x PLL Options
• Low-Power Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor (FSCM):
- Allows for safe shutdown if any clock stops
• Programmable Reference Clock Output Generator
Peripheral Highlights:
• Peripheral Pin Select:
- Allows independent I/O mapping of many peripherals
- Continuous hardware integrity checking and safety
interlocks prevent unintentional configuration changes
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions
• High-Current Sink/Source 25 mA/25mA
(PORTB and PORTC)
• Four Programmable External Interrupts
• Four Input Change Interrupts
• Three Enhanced Capture/Compare/PWM
(ECCP) modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
- Pulse steering control
Peripheral Highlight s (cont.):
• Seven Capture/Compare/PWM (CCP) modules
• Two Master Synchronous Serial Port (MSSP) modules
featuring:
- 3-wire SPI (all 4 modes)
- SPI Direct Memory Access (DMA) channel
w/1024 byte count
2
C™ Master and Slave modes
-I
• 8-Bit Parallel Master Port/Enhanced Parallel Slave Port
• Three Analog Comparators with Input Multiplexing
• 12-Bit Analog-to-Digital (A/D) Converter module:
- Up to 13 input channels
- Auto-acquisition capability
- 10-bit mode for 100 ksps conversion speed
- Conversion available during Sleep
• High/Low-Voltage Detect module
• Charge Time Measurement Unit (CTMU):
- Provides a precise resolution time measurement
for both flow measurement and simple temperature
sensing
- Supports capacitive touch sensing for touch
screens and capacitive switches
• Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN/J2602
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
Special Microcontroller Features:
• 5.5V Tolerant Inputs (digital only pins)
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant Code
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™ (ICSP™)
via Two Pins
• In-Circuit Debug (ICD) with 3 Breakpoints via Two Pins
• Operating Voltage Range of 2.0V to 3.6V
• On-Chip 2.5V Regulator
• Flash Program Memory of 10,000 Erase/Write Cycles
Minimum and 20-Year Data Retention
2010 Microchip Technology Inc. Preliminary DS39974A-page 3
PIC18F47J13 FAMILY
MSSP
PIC18F
Device
PIC18F26J13 28 64K 3760 19 4/4 3/7 2 2 Y Y 10 3 Y N Y Y
PIC18F27J13 28 128K 3760 19 4/4 3/7 2 2 Y Y 10 3 Y N Y Y
PIC18F46J13 44 64K 3760 25 4/4 3/7 2 2 Y Y 13 3 Y Y Y Y
PIC18F47J13 44 128K 3760 25 4/4 3/7 2 2 Y Y 13 3 Y Y Y Y
PIC18LF26J13 28 64K 3760 19 4/4 3/7 2 2 Y Y 10 3 N N Y Y
PIC18LF27J13 28 128K 3760 19 4/4 3/7 2 2 Y Y 10 3 N N Y Y
PIC18LF46J13 44 64K 3760 25 4/4 3/7 2 2 Y Y 13 3 N Y Y Y
PIC18LF47J13 44 128K 3760 25 4/4 3/7 2 2 Y Y 13 3 N Y Y Y
Pins
Program
SRAM
(bytes)
Memory
Pins
(bytes)
Timers
Remappable
8/16-Bit
ECCP/CCP
EUSART
SPI
w/DMA
2
C™
I
12-Bit
A/D (ch)
Deep Sleep
Comparators
PMP/PSP
CTMU
RTCC
DS39974A-page 4 Preliminary 2010 Microchip Technology Inc.
Pin Diagrams
44-Pin TQFP
Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin
Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and
output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module,
see Section 10.7 “Peripheral Pin Select (PPS)”.
10
11
2
3
6
1
1819202122
121314
15
38
8
7
4443424140
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
PIC18F4XJ13
37
RA3/AN3/C1INB/VREF+
RA2/AN2/C2INB/C1IND/C3INB/V
REF-/CVREF
RA1/AN1/C2INA/VBG/CTDIN/PMA7/RP1
RA0/AN0/C1INA/ULPWU/PMA6/RP0
MCLR
NC
RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RB5/CCP5/PMA0/KBI1/RP8
RB4/CCP4/PMA1/KBI0/RP7
NC
RC6/CCP9/PMA5/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
RD3/PMD3/RP20
RD2/PMD2/RP19
RD1/PMD1/SDA2
RD0/PMD0/SCL2
RC3/SCK1/SCL1/RP14
RC2/AN11/C2IND/CTPLS/RP13
RC1/CCP8/T1OSI/RP12
NC
NC
RC0/T1OSO/T1CKI/RP11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V
SS2
V
DD2
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/C1INC/SS1
/HLVDIN/RP2
V
DDCORE/VCAP
RC7/CCP10/PMA4/RX1/DT1/RP18
RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23
V
SS1
V
DD1
RB0/AN12/C3IND/INT0/RP3
RB1/AN10/C3INC/PMBE/RTCC/RP4
RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5
RB3/AN9/C3INA/CTED2/PMA2/RP6
RD7/PMD7/RP24
5
4
= Pins are up to 5.5V tolerant
PIC18F47J13 FAMILY
2010 Microchip Technology Inc. Preliminary DS39974A-page 5
PIC18F47J13 FAMILY
44-Pin QFN
Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin
Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and
output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module,
see Section 10.7 “Peripheral Pin Select (PPS)”.
Note: For the QFN package, it is recommended that the bottom pad be connected to V
SS.
10
11
2
3
6
1
1819202122
12
131415
38
8
7
4443424140
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
PIC18F4XJ13
37
RA3/AN3/C1INB/VREF+
RA2/AN2/C2INB/C1IND/C3INB/V
REF-/CVREF
RA1/AN1/C2INA/VBG/CTDIN/PMA7/RP1
RA0/AN0/C1INA/ULPWU/PMA6/RP0
MCLR
RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RB5/CCP5/PMA0/KBI1/RP8
RB4/CCP4/PMA1/KBI0/RP7
NC
RC6/CCP9/PMA5/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
RD3/PMD3/RP20
RD2/PMD2/RP1
RD1/PMD1/SDA2
RD0/PMD0/SCL2
RC3/SCK1/SCL1/RP14
RC2/AN11/C2IND/CTPLS/RP13
RC1/CCP8/T1OSI/RP12
RC0/T1OSO/T1CKI/RP11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V
SS2
AV
DD2
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/C1INC/SS1
/HLVDIN/RP2
V
DDCORE/VCAP
RC7/CCP10/PMA4/RX1/DT1/RP18
RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23
V
SS1
V
DD1
RB0/AN12/C3IND/INT0/RP3
RB1/AN10/C3INC/PMBE/RTCC/RP4
RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5
RB3/AN9/C3INA/CTED2/PMA2/RP6
RD7/PMD7/RP24
5
4
AVSS1
V
DD2
AV
DD1
= Pins are up to 5.5V tolerant
Pin Diagrams (Continued)
DS39974A-page 6 Preliminary 2010 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin SPDIP/SOIC/SS OP
28-Pin QFN
Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin
Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and
output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module,
see Section 10.7 “Peripheral Pin Select (PPS)”.
Note: For the QFN package, it is recommended that the bottom pad be connected to V
SS.
PIC18F2XJ13
10
11
2
3
4
5
6
1
8
7
9
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR
RA0/AN0/C1INA/ULPWU/RP0
RA1/AN1/C2INA/V
BG/CTDIN/RP1
RA2/AN2/C2INB/C1IND/C3INB/V
REF-/CVREF
RA3/AN3/C1INB/VREF+
V
DDCORE/VCAP
RA5/AN4/C1INC/SS1/HLVDIN/RP2
V
SS1
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI/RP11
RC1/CCP8/T1OSI/RP12
RC2/AN11/C2IND/CTPLS/RP13
RC3/SCK1/SCL1/RP14
RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RB5/CCP5/KBI1/SDA2/RP8
RB4/CCP4/KBI0/SCL2/RP7
RB3/AN9/C3INA/CTED2/RP6
RB2/AN8/C2INC/CTED1/REFO/RP5
RB1/AN10/C3INC/RTCC/RP4
RB0/AN12/C3IND/INT0/RP3
V
DD
VSS2
RC7/CCP10/RX1/DT1/RP18
RC6/CCP9/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
= Pins are up to 5.5V tolerant
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
PIC18F2XJ13
RC0/T1OSO/T1CKI/RP11
5
4
RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RB5/CCP5/KBI1/SDA2/RP8
RB4/CCP4/KBI0/SCL2/RP7
RB3/AN9/C3INA/CTED2/RP6
RB2/AN8/C2INC/CTED1/REFO/RP5
RB1/AN10/C3INC/RTCC/RP4
RB0/AN12/C3IND/INT0/RP3
V
DD
VSS2
RC7/CCP10/RX1/DT1/RP18
RC6/CCP9/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
MCLR
RA0/AN0/C1INA/ULPWU/RP0
RA1/AN1/C2INA/V
BG/CTDIN/RP1
RA2/AN2/C1INB/C1IND/C3INB/VREF-/CVREF
RA3/AN3/C1INB/VREF+
V
DDCORE/VCAP
RA5/AN4/C1INC/SS1/HLVDIN/RP2
V
SS1
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC1/CCP8/T1OSI/RP12
RC2/AN11/C2IND/CTPLS/RP13
RC3/SCK1/SCL1/RP14
PIC18F47J13 FAMILY
2010 Microchip Technology Inc. Preliminary DS39974A-page 7
PIC18F47J13 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31
3.0 Oscillator Configurations ............................................................................................................................................................ 35
4.0 Low-Power Modes...................................................................................................................................................................... 47
5.0 Reset .......................................................................................................................................................................................... 65
6.0 Memory Organization ................................................................................................................................................................. 81
7.0 Flash Program Memory............................................................................................................................................................ 107
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 117
9.0 Interrupts .................................................................................................................................................................................. 119
10.0 I/O Ports ................................................................................................................................................................................... 139
11.0 Parallel Master Port (PMP)....................................................................................................................................................... 179
12.0 Timer0 Module ......................................................................................................................................................................... 205
13.0 Timer1 Module ......................................................................................................................................................................... 209
14.0 Timer2 Module ......................................................................................................................................................................... 219
15.0 Timer3/5 Module ...................................................................................................................................................................... 221
16.0 Timer4/6/8 Module ................................................................................................................................................................... 233
17.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 237
18.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 257
19.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 269
20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 291
21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 345
22.0 10/12-bit Analog-to-Digital Converter (A/D) Module................................................................................................................. 367
23.0 Comparator Module.................................................................................................................................................................. 379
24.0 Comparator Voltage Reference Module ................................................................................................................................... 387
25.0 High/Low Voltage Detect (HLVD)............................................................................................................................................. 391
26.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 397
27.0 Special Features of the CPU.................................................................................................................................................... 415
28.0 Instruction Set Summary.......................................................................................................................................................... 433
29.0 Development Support............................................................................................................................................................... 483
30.0 Electrical Characteristics.......................................................................................................................................................... 487
31.0 Packaging Information.............................................................................................................................................................. 529
Appendix A: Revision History............................................................................................................................................................. 541
Appendix B: Migration From PIC18F46J11 to PIC18F47J13............................................................................................................. 541
The Microchip Web Site..................................................................................................................................................................... 555
Customer Change Notification Service .............................................................................................................................................. 555
Customer Support .............................................................................................................................................................................. 555
Reader Response .............................................................................................................................................................................. 556
Product Identification System............................................................................................................................................................. 557
DS39974A-page 8 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
TO OUR VALUED CUSTOMERS
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2010 Microchip Technology Inc. Preliminary DS39974A-page 9
PIC18F47J13 FAMILY
NOTES:
DS39974A-page 10 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• P IC 18 F2 6J1 3 • PIC1 8LF 26J 13
• PIC18F27J13 • PIC18LF27J13
• PIC18F46J13 • PIC18LF46J13
• PIC18F47J13 • PIC18LF47J13
1.1 Core Features
1.1.1 nanoWatt XLP TECHNOLOGY
All of the devices in the PIC18F47J13 family incorporate a range of features that can significantly reduce
power consumption during operation. Key features are:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operational requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the users to incorporate
power-saving ideas into their application’s
software design.
• Deep Sleep: The 2.5V internal core voltage regu-
lator on F parts can be shutdown to cut power
consumption to as low as 15 nA (typical). Certain
features can remain operating during Deep Sleep,
such as the Real-Time Clock Calendar.
• Ultra Low Power Wake-Up: Waking from Sleep
or Deep Sleep modes after a period of time can
be done without an oscillator/clock source, saving
power for applications requiring periodic activity.
1.1.2 OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F47J13 family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• An internal oscillator block, which provides an
8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and V
as well as a range of six user selectable clock
frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees
an oscillator pin for use as an additional general
purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier
available to the high-speed crystal, and external
and internal oscillators, providing a clock speed
up to 48 MHz.
The internal oscillator block provides a stable reference
source that gives the PIC18F47J13 family additional
features for robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed S tart-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset (POR), or wake-up from
Sleep mode, until the primary clock source is
available.
DD),
2010 Microchip Technology Inc. Preliminary DS39974A-page 11
PIC18F47J13 FAMILY
1.1.3 EXPANDED MEMORY
The PIC18F47J13 family provides ample room for
application code, from 64 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last in excess of 10000 erase/write cycles. Data
retention without refresh is conservatively estimated to
be greater than 20 years.
The Flash program memory is readable and writable
during normal operation. The PIC18F47J13 family also
provides plenty of room for dynamic application data
with up to 3.8 Kbytes of data RAM.
1.1.4 EXTENDED INSTRUCTION SET
The PIC18F47J13 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as C.
1.1.5 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the entire
family also aids in migrating to the next larger device.
The PIC18F47J13 family is also pin compatible with
other PIC18 families, such as the PIC18F4550,
PIC18F2450 and PIC18F46J50. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining the
same feature set.
1.2 Other Special Features
• Communications: The PIC18F47J13 family
incorporates a range of serial and parallel communication peripherals. This device includes two
independent Enhanced USARTs and two Master
Synchronous Serial Port (MSSP) modules,
capable of both Serial Peripheral Interface (SPI)
2
C™ (Master and Slave) modes of opera-
and I
tion. The device also has a parallel port and can
be configured to serve as either a Parallel Master
Port (PMP) or as a Parallel Slave Port (PSP).
• CCP/ECCP Modules: All devices in the family
incorporate seven Capture/Compare/PWM (CCP)
modules and three Enhanced Capture/Compare/PWM (ECCP) modules to maximize flexibility
in control applications. ECCPs offer up to four
PWM output signals each. The ECCPs also offer
many beneficial features, including polarity
selection, programmable dead time,
auto-shutdown and restart and Half-Bridge and
Full-Bridge Output modes.
• 10/12-Bit A/D Converter: This module incorpo-
rates programmable acquisition time, allowing for
a channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 30.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family Devices
Devices in the PIC18F47J13 family are available in
28-pin and 44-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in
two ways:
• Flash program memory (two sizes: 64 Kbytes for
the PIC18FX6J13 and 128 Kbytes for
PIC18FX7J13)
• I/O ports (three bidirectional ports on 28-pin
devices, five bidirectional ports on 44-pin devices)
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for the PIC18F2XJ13 devices are listed in
Table 1-3. The pinouts for the PIC18F4XJ13 devices
are shown in Table 1-4.
The PIC18F47J13 family of devices provides an
on-chip voltage regulator to supply the correct voltage
levels to the core. Parts designated with an “F” part
number (such as PIC18F47J13) have the voltage
regulator enabled.
These parts can run from 2.15V-3.6V on V
have the V
low-ESR capacitor. Parts designated with an “LF” part
number (such as PIC18LF47J13) do not enable the volt-
age regulator nor support Deep Sleep mode. For “LF”
parts, an external supply of 2.0V-2.7V has to be supplied
to the V
DD (VDDCORE should never exceed VDD).
V
For more details about the internal voltage regulator,
see Section 27.3 “On-Chip Voltage Regulator”.
DDCORE pin connected to VSS through a
DDCORE pin while 2.0V-3.6V can be supplied to
DD, but should
DS39974A-page 12 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ13 (28-PIN DEVICES)
Features PIC18F26J13 PIC18F27J13
Operating Frequency DC – 48 MHz DC – 48 MHz
Program Memory (Kbytes) 64 128
Program Memory (Instructions) 32,768 65,536
Data Memory (Kbytes) 3.8 3.8
Interrupt Sources 30
I/O Ports Ports A, B, C
Timers 8
Enhanced Capture/Compare/PWM Modules 3 ECCP and 7 CCP
Serial Communications MSSP (2), Enhanced USART (2)
Parallel Communications (PMP/PSP) No
10/12-Bit Analog-to-Digital Module 10 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil)
, WDT
TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XJ13 (44-PIN DEVICES)
Features PIC18F46J13 PIC18F47J13
Operating Frequency DC – 48 MHz DC – 48 MHz
Program Memory (Kbytes) 64 128
Program Memory (Instructions) 32,768 65,536
Data Memory (Kbytes) 3.8 3.8
Interrupt Sources 30
I/O Ports Ports A, B, C, D, E
Timers 8
Enhanced Capture/Compare/PWM Modules 3 ECCP and 7 CCP
Serial Communications MSSP (2), Enhanced USART (2)
Parallel Communications (PMP/PSP) Yes
10/12-Bit Analog-to-Digital Module 13 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 44-Pin QFN and TQFP
, WDT
2010 Microchip Technology Inc. Preliminary DS39974A-page 13
PIC18F47J13 FAMILY
Instruction
Decode and
Control
PORTA
Data Latch
Data Memory
(3.8 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-3 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ADC
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
MSSP2
PORTC
RA0:RA7
(1)
RC0:RC7
(1)
PORTB
RB0:RB7
(1)
Timer4
OSC1/CLKI
OSC2/CLKO
V
DD,
8 MHz
INTOSC
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
CTMU
Timing
Generation
HLVD
RTCC
ECCP1 ECCP2
ECCP3
CCP4 CCP5 CCP6 CCP7 CCP8
CCP9 CCP10
Timer5
Timer6 Timer8
FIGURE 1-1 : PIC18F2XJ13 (28-PIN) BLOCK DI AG R AM
DS39974A-page 14 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W
8
8
8
Instruction
Decode and
Control
Data Latch
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
Address Latch
Program Memory
Data Latch
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
ROM Latch
PCLATU
PCU
Instruction Bus <16>
STKPTR
Bank
State Machine
Control Signals
Decode
System Bus Interface
AD<15:0>, A<19:16>
(Multiplexed with PORTD
and PORTE)
PORTA
PORTC
PORTD
PORTE
RA0:RA7
(1)
RC0:RC7
(1)
RD0:RD7
(1)
RE0:RE2
(1)
PORTB
RB0:RB7
(1)
Note 1: See Table 1-3 for I/O port pin descriptions.
2: The on-chip voltage regulator is always enabled by default.
Data Memory
(3.8 Kbytes)
OSC1/CLKI
OSC2/CLKO
V
DD,VSS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
VDDCORE/VCAP
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ADC
EUSART2
MSSP2
Timer4
CTMU
HLVD
RTCC
ECCP1 ECCP2
ECCP3
CCP4 CCP5 CCP6 CCP7 CCP8
CCP9 CCP10
Timer5
Timer6 Timer8
8 MHz
INTOSC
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Vol tage
Timing
Generation
FIGURE 1-2 : PIC18F4XJ13 (44-PIN) BLOCK DI AG R AM
2010 Microchip Technology Inc. Preliminary DS39974A-page 15
PIC18F47J13 FAMILY
TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Pin Name
MCLR
OSC1/CLKI/RA7
OSC1
CLKI
RA7
OSC2/CLKO/RA6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
(1)
OSC2
CLKO
(1)
RA6
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
2: 5.5V tolerant.
28-SPDIP/
SSOP/
SOIC
1
28-QFN
(2)
96
10 7
26
(2)
I ST Master Clear (Reset) input. This pin is an
Type
I
I
I/O
O
O
I/O
Buffer
Type
ST
CMOS
TTL/DIG
—
DIG
TTL/DIG
Description
active-low Reset to the device.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
CMOS otherwise. Main oscillator input
connection.
External clock source input; always associated
with pin function, OSC1 (see related
OSC1/CLKI pins).
Digital I/O.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
Digital I/O.
2
C™ = Open-Drain, I2C specific
DD)
DS39974A-page 16 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
T ABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
RA0/AN0/C1INA/ULPWU/RP0
227
RA0
AN0
C1INA
ULPWU
RP0
RA1/AN1/C2INA/V
BG/CTDIN/
328
RP1
RA1
AN1
C2INA
BG
V
CTDIN
RP1
RA2/AN2/C2INB/C1IND/
41
C3INB/VREF-/CVREF
RA2
AN2
C2INB
C1IND
C3INB
REF-
V
REF
CV
RA3/AN3/C1INB/V
REF+
52
RA3
AN3
C1INB
REF+
V
RA5/AN4/C1INC/SS1
/
74
HLVDIN/RP2
RA5
AN4
C1INC
SS1
HLVDIN
RP2
(1)
RA6
(1)
RA7
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.
Type
I/O
I
I
I
I/O
I/O
O
I
O
I
I/O
I/O
I
I
I
I
O
I
I/O
I
I
I
I/O
I
I
I
I
I/O
Buffer
Type
TTL/DIG
Analog
Analog
Analog
ST/DIG
TTL/DIG
Analog
Analog
Analog
ST
ST/DIG
TTL/DIG
Analog
Analog
Analog
Analog
Analog
Analog
TTL/DIG
Analog
Analog
Analog
TTL/DIG
Analog
Analog
TTL
Analog
ST/DIG
Description
PORTA is a bidirectional I/O port.
Digital I/O.
Analog Input 0.
Comparator 1 Input A.
Ultra low-power wake-up input.
Remappable Peripheral Pin 0 input/output.
Digital I/O.
Analog Input 1.
Comparator 2 Input A.
Band Gap Reference Voltage (V
CTMU pulse delay input.
Remappable Peripheral Pin 1 input/output.
Digital I/O.
Analog Input 2.
Comparator 2 Input B.
Comparator 1 Input D.
Comparator 3 Input B.
A/D reference voltage (low) input.
Comparator reference voltage output.
Digital I/O.
Analog Input 3.
Comparator 1 Input B.
A/D reference voltage (high) input.
Digital I/O.
Analog Input 4.
Comparator 1 Input C.
SPI slave select input.
High/Low-Voltage Detect input.
Remappable Peripheral Pin 2 input/output.
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
2
C™ = Open-Drain, I2C specific
BG) output.
DD)
2010 Microchip Technology Inc. Preliminary DS39974A-page 17
PIC18F47J13 FAMILY
TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
RB0/AN12/C3IND/INT0/RP3
RB0
AN12
C3IND
INT0
RP3
RB1/AN10/C3INC/RTCC/RP4
RB1
AN10
C3INC
RTCC
RP4
RB2/AN8/C2INC/CTED1/
REFO/RP5
RB2
AN8
C2INC
CTED1
REFO
RP5
RB3/AN9/C3INA/CTED2/
RP6
RB3
AN9
C3INA
CTED2
RP6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.
28-SPDIP/
SSOP/
SOIC
21 18
22 19
23 20
24 21
28-QFN
Type
I/O
I
I
I
I/O
I/O
I
I
O
I/O
I/O
I
I
I
O
I/O
I/O
I
I
I
I
Buffer
Type
TTL/DIG
Analog
Analog
ST
ST/DIG
TTL/DIG
Analog
Analog
DIG
ST/DIG
TTL/DIG
Analog
Analog
ST
DIG
ST/DIG
TTL/DIG
Analog
Analog
ST
ST/DIG
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups
on all inputs.
Digital I/O.
Analog Input 12.
Comparator 3 Input D.
External Interrupt 0.
Remappable Peripheral Pin 3 input/output.
Digital I/O.
Analog Input 10.
Comparator 3 input.
Real-Time Clock Calendar output.
Remappable Peripheral Pin 4 input/output.
Digital I/O.
Analog Input 8.
Comparator 2 Input C.
CTMU Edge 1 input.
Reference output clock.
Remappable Peripheral Pin 5 input/output.
Digital I/O.
Analog Input 9.
Comparator 3 Input A.
CTMU edge 2 Input.
Remappable Peripheral Pin 6 input/output.
2
C™ = Open-Drain, I2C specific
DD)
DS39974A-page 18 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
T ABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
RB4/CCP4/KBI0/SCL2/RP7
25
(2)
22
(2)
RB4
CCP4
KBI0
SCL2
RP7
RB5/CCP5/KBI1/SDA2/RP8
26
(2)
23
(2)
RB5
CCP5
KBI1
SDA2
RP8
RB6/CCP6/KBI2/PGC/RP9
27
(2)
24
(2)
RB6
CCP6
KBI2
PGC
RP9
RB7/CCP7/KBI3/PGD/RP10
28
(2)
25
(2)
RB7
CCP7
KBI3
PGD
RP10
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.
Type
I/O
I/O
I
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I
I/O
I/O
Buffer
Type
TTL/DIG
ST/DIG
TTL
2
C™
I
ST/DIG
TTL/DIG
ST/DIG
TTL
2
C
I
ST/DIG
TTL/DIG
ST/DIG
TTL
ST
ST/DIG
TTL/DIG
ST/DIG
TTL
ST/DIG
ST/DIG
Description
PORTB (continued)
Digital I/O.
Capture/Compare/PWM input/output.
Interrupt-on-change pin.
I2C clock input/output.
Remappable Peripheral Pin 7 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Interrupt-on-change pin.
2
C data input/output.
I
Remappable Peripheral Pin 8 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Interrupt-on-change pin.
ICSP™ clock input.
Remappable Peripheral Pin 9 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Remappable Peripheral Pin 10 input/output.
2
C™ = Open-Drain, I2C specific
DD)
2010 Microchip Technology Inc. Preliminary DS39974A-page 19
PIC18F47J13 FAMILY
TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
RC0/T1OSO/T1CKI/RP11
11 8
RC0
T1OSO
T1CKI
RP11
RC1/CCP8/T1OSI/RP12
12 9
RC1
CCP8
T1OSI
RP12
RC2/AN11/C2IND/CTPLS/RP13
13 10
RC2
AN11
C2IND
CTPLS
RP13
RC3/SCK1/SCL1/RP14
14 11
RC3
SCK1
SCL1
RP14
RC4/SDI1/SDA1/RP15
15 12
RC4
SDI1
SDA1
RP15
RC5/SDO1/RP16
16 13
RC5
SDO1
RP16
RC6/CCP9/TX1/CK1/RP17
17
(2)
14
(2)
RC6
CCP9
TX1
CK1
RP17
RC7/CCP10/RX1/DT1/RP18
18
(2)
15
(2)
RC7
CCP10
RX1
DT1
RP18
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.
Type
I/O
O
I
I/O
I/O
I/O
I
I/O
I/O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I
I/O
I/O
Buffer
Type
ST/DIG
Analog
ST
ST/DIG
ST/DIG
ST/DIG
Analog
ST/DIG
ST/DIG
Analog
Analog
DIG
ST/DIG
ST/DIG
ST/DIG
2
C
I
ST/DIG
ST/DIG
ST
2
C™
I
ST/DIG
ST/DIG
DIG
ST/DIG
ST/DIG
ST/DIG
DIG
ST/DIG
ST/DIG
ST/DIG
ST/DIG
ST
ST/DIG
ST/DIG
Description
PORTC is a bidirectional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1 external digital clock input.
Remappable Peripheral Pin 11 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Timer1 oscillator input.
Remappable Peripheral Pin 12 input/output.
Digital I/O.
Analog Input 11.
Comparator 2 Input D.
CTMU pulse generator output.
Remappable Peripheral Pin 13 input/output.
Digital I/O.
SPI clock input/output.
2
C clock input/output.
I
Remappable Peripheral Pin 14 input/output.
Digital I/O.
SPI data input.
2
C data input/output.
I
Remappable Peripheral Pin 15 input/output.
Digital I/O.
SPI data output.
Remappable Peripheral Pin 16 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related
RX1/DT1).
Remappable Peripheral Pin 17 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Asynchronous serial receive data input.
Synchronous serial data output/input.
Remappable Peripheral Pin 18 input/output.
2
C™ = Open-Drain, I2C specific
DD)
DS39974A-page 20 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
T ABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Pin Name
VSS1 8 5 P — Ground reference for logic and I/O pins.
SS21916——
V
VDD 20 17 P — Positive supply for peripheral digital logic and I/O
DDCORE/VCAP
V
VDDCORE
VCAP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.
28-SPDIP/
SSOP/
SOIC
28-QFN
63—
Type
P
P
Buffer
Type
pins.
—
Core logic power or external filter capacitor
connection.
—
—
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
2
C™ = Open-Drain, I2C specific
Description
2010 Microchip Technology Inc. Preliminary DS39974A-page 21
PIC18F47J13 FAMILY
TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
MCLR
OSC1/CLKI/RA7
OSC1
CLKI
(1)
RA7
OSC2/CLKO/RA6
OSC2
CLKO
(1)
RA6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
QFN
(3)
18
32 30
33 31
TQFP
Pin
Type
I
I
I/O
O
O
I/O
Buffer
Type
ST
CMOS
TTL/DIG
—
—
TTL/DIG
Reset to the device.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
otherwise CMOS. Main oscillator input
connection.
External clock source input; always associated
with pin function, OSC1 (see related OSC1/CLKI
pins).
Digital I/O.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection
in RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
Digital I/O.
2
C™ = Open-Drain, I2C specific
44-
18 I ST Master Clear (Reset) input; this is an active-low
Description
DD)
DS39974A-page 22 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
T ABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RA0/AN0/C1INA/ULPWU/PMA6/
44-
QFN
19 19
TQFP
RP0
RA0
AN0
C1INA
ULPWU
PMA6
RP0
RA1/AN1/C2INA/V
BG/CTDIN/
20 20
PMA7/RP1
RA1
AN1
C2INA
BG
V
CTDIN
PMA7
RP1
RA2/AN2/C2INB/C1IND/C3INB/
REF-/CVREF
V
21 21
RA2
AN2
C2INB
C1IND
C3INB
REF-
V
REF
CV
RA3/AN3/C1INB/V
REF+
22 22
RA3
AN3
C1INB
REF+
V
RA5/AN4/C1INC/SS1
/HLVDIN/RP2
24 24
RA5
AN4
C1INC
SS1
HLVDIN
RP2
(1)
RA6
(1)
RA7
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
Pin
Type
I/O
I
I
I
I/O
I/O
I/O
O
I
O
I
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I
I
I
I/O
I
I
I
I
I/O
Buffer
Type
TTL/DIG
Analog
Analog
Analog
ST/TTL/
DIG
ST/DIG
TTL/DIG
Analog
Analog
Analog
ST
ST/TTL/
DIG
ST/DIG
TTL/DIG
Analog
Analog
Analog
Analog
Analog
Analog
TTL/DIG
Analog
Analog
Analog
TTL/DIG
Analog
Analog
TTL
Analog
ST/DIG
Description
PORTA is a bidirectional I/O port.
Digital I/O.
Analog Input 0.
Comparator 1 Input A.
Ultra low-power wake-up input.
Parallel Master Port digital I/O.
Remappable Peripheral Pin 0 input/output.
Digital I/O.
Analog Input 1.
Comparator 2 Input A.
Band Gap Reference Voltage (V
BG) output.
CTMU pulse delay input.
Parallel Master Port digital I/O.
Remappable Peripheral Pin 1 input/output.
Digital I/O.
Analog Input 2.
Comparator 2 Input B.
Comparator 1 Input D.
Comparator 3 Input B.
A/D reference voltage (low) input.
Comparator reference voltage output.
Digital I/O.
Analog Input 3.
Comparator 1 Input B.
A/D reference voltage (high) input.
Digital I/O.
Analog Input 4.
SPI slave select input.
Comparator 1 Input C.
High/Low-Voltage Detect input.
Remappable Peripheral Pin 2 input/output.
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
2
C™ = Open-Drain, I2C specific
2010 Microchip Technology Inc. Preliminary DS39974A-page 23
PIC18F47J13 FAMILY
TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB0/AN12/C3IND/INT0/RP3
RB0
AN12
C3IND
INT0
RP3
RB1/AN10/C3INC/PMBE/RTCC/
RP4
RB1
AN10
C3INC
(2)
PMBE
RTCC
RP4
RB2/AN8/C2INC/CTED1/PMA3/
REFO/RP5
RB2
AN8
C2INC
CTED1
PMA3
REFO
RP5
RB3/AN9/C3INA/CTED2/PMA2/
RP6
RB3
AN9
C3INA
CTED2
PMA2
RP6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
(2)
(2)
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
QFN
TQFP
98
10 9
11 10
12 11
44-
Pin
Type
I/O
I
I
I
I/O
I/O
I
I
O
O
I/O
I/O
I
I
I
O
O
I/O
I/O
I
I
I
O
I/O
Buffer
Type
TTL/DIG
Analog
Analog
ST
ST/DIG
TTL/DIG
Analog
Analog
DIG
DIG
ST/DIG
TTL/DIG
Analog
Analog
ST
DIG
DIG
ST/DIG
TTL/DIG
Analog
Analog
ST
DIG
ST/DIG
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
Digital I/O.
Analog Input 12.
Comparator 3 Input D.
External Interrupt 0.
Remappable Peripheral Pin 3 input/output.
Digital I/O.
Analog Input 10.
Comparator 3 Input C.
Parallel Master Port byte enable.
Asynchronous serial transmit data output.
Remappable Peripheral Pin 4 input/output.
Digital I/O.
Analog Input 8.
Comparator 2 Input C.
CTMU Edge 1 input.
Parallel Master Port address.
Reference output clock.
Remappable Peripheral Pin 5 input/output.
Digital I/O.
Analog Input 9.
Comparator 3 Input A.
CTMU Edge 2 input.
Parallel Master Port address.
Remappable Peripheral Pin 6 input/output.
2
C™ = Open-Drain, I2C specific
DD)
DS39974A-page 24 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
T ABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB4/CCP4/PMA1/KBI0/RP7
RB4
(2)
CCP4
PMA1
(2)
44-
QFN
(3)14(3)
14
TQFP
KBI0
RP7
RB5/CCP5/PMA0/KBI1/RP8
(3)15(3)
15
RB5
CCP5
(2)
PMA0
KBI1
RP8
RB6/CCP6/KBI2/PGC/RP9
(3)16(3)
16
RB6
CCP6
KBI2
PGC
RP9
RB7/CCP7/KBI3/PGD/RP10
(3)17(3)
17
RB7
CCP7
KBI3
PGD
RP10
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
Pin
Type
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I
I/O
I/O
Buffer
Type
TTL/DIG
ST/DIG
ST/TTL/
DIG
TTL
ST/DIG
TTL/DIG
ST/DIG
ST/TTL/
DIG
TTL
ST/DIG
TTL/DIG
ST/DIG
TTL
ST
ST/DIG
TTL/DIG
ST/DIG
TTL
ST/DIG
ST/DIG
Description
PORTB (continued)
Digital I/O.
Capture/Compare/PWM input/output.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable Peripheral Pin 7 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable Peripheral Pin 8 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Interrupt-on-change pin.
ICSP™ clock input.
Remappable Peripheral Pin 9 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Remappable Peripheral Pin 10 input/output.
2
C™ = Open-Drain, I2C specific
DD)
2010 Microchip Technology Inc. Preliminary DS39974A-page 25
PIC18F47J13 FAMILY
TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC0/T1OSO/T1CKI/RP11
RC0
T1OSO
T1CKI
RP11
RC1/CCP8/T1OSI/RP12
RC1
CCP8
T1OSI
RP12
RC2/AN11/C2IND/CTPLS/RP13
RC2
AN11
C2IND
CTPLS
RP13
RC3/SCK1/SCL1/RP14
RC3
SCK1
SCL1
RP14
RC4/SDI1/SDA1/RP15
RC4
SDI1
SDA1
RP15
RC5/SDO1/RP16
RC5
SDO1
RP16
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
QFN
34 32
35 35
36 36
37 37
42 42
43 43
TQFP
44-
Pin
Type
I/O
O
I
I/O
I/O
I/O
I
I/O
I/O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
O
I/O
Buffer
Type
STDIG
Analog
ST
ST/DIG
ST/DIG
ST/DIG
Analog
ST/DIG
ST/DIG
Analog
Analog
DIG
ST/DIG
ST/DIG
ST/DIG
2
C
I
ST/DIG
ST/DIG
ST
2
C™
I
ST/DIG
ST/DIG
DIG
ST/DIG
Description
PORTC is a bidirectional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Remappable Peripheral Pin 11 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Timer1 oscillator input.
Remappable Peripheral Pin 12 input/output.
Digital I/O.
Analog Input 11.
Comparator 2 Input D.
CTMU pulse generator output.
Remappable Peripheral Pin 13 input/output.
Digital I/O.
SPI clock input/output.
2
C clock input/output.
I
Remappable Peripheral Pin 14 input/output.
Digital I/O.
SPI data input.
I2C data input/output.
Remappable Peripheral Pin 15 input/output.
Digital I/O.
SPI data output.
Remappable Peripheral Pin 16 input/output.
2
C™ = Open-Drain, I2C specific
DD)
DS39974A-page 26 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
T ABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC6/CCP9/PMA5/TX1/CK1/RP17
RC6
CCP9
PMA5
TX1
CK1
RP17
RC7/CCP10/PMA4/RX1/DT1/RP18
RC7
CCP10
PMA4
RX1
DT1
RP18
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
QFN
(3)44(3)
44
(3)1(3)
1
TQFP
44-
Pin
Type
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
Buffer
Type
ST/DIG
ST/DIG
DIG
ST/TTL/
DIG
ST/DIG
ST/DIG
ST/DIG
ST/DIG
ST/TTL/
DIG
ST
ST/DIG
ST/DIG
Description
PORTC (continued)
Digital I/O.
Capture/Compare/PWM input/output.
Parallel Master Port address.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related
RX1/DT1).
Remappable Peripheral Pin 17 input/output.
Digital I/O.
Capture/Compare/PWM input/output.
Parallel Master Port address.
EUSART1 asynchronous receive.
EUSART Synchronous data (see related
TX1/CK1).
Remappable Peripheral Pin 18 input/output.
2
C™ = Open-Drain, I2C specific
DD)
2010 Microchip Technology Inc. Preliminary DS39974A-page 27
PIC18F47J13 FAMILY
TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RD0/PMD0/SCL2
44-
QFN
(3)38(3)
38
TQFP
RD0
PMD0
SCL2
RD1/PMD1/SDA2
(3)39(3)
39
RD1
PMD1
SDA2
RD2/PMD2/RP19
(3)40(3)
40
RD2
PMD2
RP19
RD3/PMD3/RP20
(3)41(3)
41
RD3
PMD3
RP20
RD4/PMD4/RP21
(3)2(3)
2
RD4
PMD4
RP21
RD5/PMD5/RP22
(3)3(3)
3
RD5
PMD5
RP22
RD6/PMD6/RP23
(3)4(3)
4
RD6
PMD6
RP23
RD7/PMD7/RP24
(3)5(3)
5
RD7
PMD7
RP24
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
ST/DIG
ST/TTL/
DIG
2
I
C
ST/DIG
ST/TTL/
DIG
2
I
C
ST/DIG
ST/TTL/
DIG
ST/DIG
ST/DIG
ST/TTL/
DIG
ST/DIG
ST/DIG
ST/TTL/
DIG
ST/DIG
ST/DIG
ST/TTL/
DIG
ST/DIG
ST/DIG
ST/TTL/
DIG
ST/DIG
ST/DIG
ST/TTL/
DIG
ST/DIG
Description
PORTD is a bidirectional I/O port.
Digital I/O.
Parallel Master Port data.
2
I
C™ data input/output.
Digital I/O.
Parallel Master Port data.
2
I
C data input/output.
Digital I/O.
Parallel Master Port data.
Remappable Peripheral Pin 19 input/output.
Digital I/O.
Parallel Master Port data.
Remappable Peripheral Pin 20 input/output.
Digital I/O.
Parallel Master Port data.
Remappable Peripheral Pin 21 input/output.
Digital I/O.
Parallel Master Port data.
Remappable Peripheral Pin 22 input/output.
Digital I/O.
Parallel Master Port data.
Remappable Peripheral Pin 23 input/output.
Digital I/O.
Parallel Master Port data.
Remappable Peripheral Pin 24 input/output.
2
C™ = Open-Drain, I2C specific
DD)
DS39974A-page 28 Preliminary 2010 Microchip Technology Inc.
PIC18F47J13 FAMILY
T ABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RE0/AN5/PMRD
RE0
AN5
PMRD
RE1/AN6/PMWR
RE1
AN6
PMWR
RE2/AN7/PMCS
RE2
AN7
PMCS
SS1 6 6 P — Ground reference for logic and I/O pins.
V
SS23129——
V
AVSS1 30 — P — Ground reference for analog modules.
VDD1 8 7 P — Positive supply for peripheral digital logic and
V
DD22928P—
VDDCORE/VCAP
VDDCORE
VCAP
DD1 7 — P — Positive supply for analog modules.
AV
AVDD2 28 — — — Positive supply for analog modules.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.
44-
QFN
25 25
26 26
27 27
23 23
TQFP
44-
Pin
Type
I/O
I
I/O
I/O
I
I/O
I/O
I
O
P
P
Buffer
Type
ST/DIG
Analog
ST/TTL/
DIG
ST/DIG
Analog
ST/TTL/
DIG
ST/DIG
Analog
DIG
—
—
Description
PORTE is a bidirectional I/O port.
Digital I/O.
Analog Input 5.
Parallel Master Port input/output.
Digital I/O.
Analog Input 6.
Parallel Master Port write strobe.
Digital I/O.
Analog Input 7.
Parallel Master Port byte enable.
I/O pins.
Core logic power or external filter capacitor
connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
2
C™ = Open-Drain, I2C specific
DD)
2010 Microchip Technology Inc. Preliminary DS39974A-page 29
PIC18F47J13 FAMILY
NOTES:
DS39974A-page 30 Preliminary 2010 Microchip Technology Inc.
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