Datasheet PIC18F46J50 Datasheet

PIC18F46J50 Family

Data Sheet

28/44-Pin, Low-Power,

High-Performance USB Microcontrollers

with nanoWatt XLP Technology

© 2009 Microchip Technology Inc. DS39931C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC

32

logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS39931C-page 2 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

28/44-Pin, Low-Power, High-Performance USB Microcontrollers

Power Management Features with nanoWatt XLP™ for Extreme Low-Power:

• Deep Sleep mode: CPU off, Peripherals off,
Currents Down to 13 nA and 850 nA with RTCC

- Able to wake-up on external triggers,

programmable WDT or RTCC alarm

- Ultra Low-Power Wake-up (ULPWU)

• Sleep mode: CPU off, Peripherals off, SRAM on,
Fast Wake-up, Currents Down to 105 nA Typical

• Idle: CPU off, Peripherals on, Currents Down to

2.3 μA Typical

• Run: CPU on, Peripherals on, Currents Down to

6.2 μA Typical

• Timer1 Oscillator w/RTCC: 1 μA, 32 kHz Typical

• Watchdog Timer: 1.3 μA Typical

Special Microcontroller Features:

• 5.5V Tolerant Inputs (digital only pins)

• Low-Power, High-Speed CMOS Flash Technology

• C Compiler Optimized Architecture for Re-Entrant Code

• Priority Levels for Interrupts

• Self-Programmable under Software Control

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single-Supply In-Circuit Serial Programming™
(ICSP™) via two pins

• In-Circuit Debug (ICD) with Three Breakpoints via
Two Pins

• Operating Voltage Range of 2.0V to 3.6V

• On-Chip 2.5V Regulator

• Flash Program Memory of 10,000 Erase/Write
Cycles Minimum and 20-Year Data Retention

Universal Serial Bus (USB) Features

• USB V2.0 Compliant

• Full Speed (12 Mbps) and Low Speed (1.5 Mbps)

• Supports Control, Interrupt, Isochronous and Bulk
Transfers

• Supports up to 32 Endpoints (16 bidirectional)

• USB module can use any RAM Location on the
Device as USB Endpoint Buffers

• On-Chip USB Transceiver with Crystal-less operation

Flexible Oscillator Structure:

• High-Precision Internal Oscillator (±0.15% typ.) for USB

• Two External Clock modes, up to 48 MHz (12 MIPS)

• Internal 31 kHz Oscillator, Internal Oscillators
Tunable at 31 kHz and 8 MHz or 48 MHz with PLL

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if any clock stops

• Two-Speed Oscillator Start-up

• Programmable Reference Clock Output Generator

Peripheral Highlights:

• Peripheral Pin Select:

- Allows independent I/O mapping of many
peripherals

- Continuous hardware integrity checking and
safety interlocks prevent unintentional
configuration changes

• Hardware Real-Time Clock and Calendar (RTCC):

- Provides clock, calendar and alarm functions

• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)

• Four Programmable External Interrupts

• Four Input Change Interrupts

• Two Enhanced Capture/Compare/PWM (ECCP)
modules:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

- Pulse steering control

• Two Master Synchronous Serial Port (MSSP)
modules Supporting Three-Wire SPI (all four
modes) and I

• Full-Duplex Master/Slave SPI DMA Engine

• 8-Bit Parallel Master Port/Enhanced Parallel
Slave Port

• Two-Rail – Rail Analog Comparators with Input
Multiplexing

• 10-Bit, up to 13-Channel Analog-to-Digital (A/D)
Converter module:

- Auto-acquisition capability

- Conversion available during Sleep

- Self-calibration

• High/Low-Voltage Detect module

• Charge Time Measurement Unit (CTMU):

- Supports capacitive touch sensing for touch

screens and capacitive switches

- Provides a precise resolution time measure-

ment for both flow measurement and simple
temperature sensing

• Two Enhanced USART modules:

- Supports RS-485, RS-232 and LIN/J2602

- Auto-Wake-up on Start bit

• Auto-Baud Detect

2

C™ Master and Slave modes

© 2009 Microchip Technology Inc. DS39931C-page 3

PIC18F46J50 FAMILY

MSSP

PIC18F/LF

PIC18F24J50 28 16K 3776 16 2/3 2 2 2 Y Y 10 2 Y N Y Y Y

PIC18F25J50 28 32K 3776 16 2/3 2 2 2 Y Y 10 2 Y N Y Y Y

PIC18F26J50 28 64K 3776 16 2/3 2 2 2 Y Y 10 2 Y N Y Y Y

PIC18F44J50 44 16K 3776 22 2/3 2 2 2 Y Y 13 2 Y Y Y Y Y

PIC18F45J50 44 32K 3776 22 2/3 2 2 2 Y Y 13 2 Y Y Y Y Y

PIC18F46J50 44 64K 3776 22 2/3 2 2 2 Y Y 13 2 Y Y Y Y Y

PIC18LF24J50 28 16K 3776 16 2/3 2 2 2 Y Y 10 2 N N Y Y Y

PIC18LF25J50

PIC18LF26J50

PIC18LF44J50

PIC18LF45J50

PIC18LF46J50

Note 1: See Section 1.3 “Details on Individual Family Devices”, Section 3.6 “Deep Sleep Mode” and Section 26.3

(1)

Device

Pins

Program

28 32K 3776 16 2/3 2 2 2 Y Y 10 2

28 64K 3776 16 2/3 2 2 2 Y Y 10 2

44 16K 3776 22 2/3 2 2 2 Y Y 13 2

44 32K 3776 22 2/3 2 2 2 Y Y 13 2

44 64K 3776 22 2/3 2 2 2 Y Y 13 2

“On-Chip Voltage Regulator” for details describing the functional differences between PIC18F and PIC18LF
variants in this device family.

Memory (bytes)

SRAM (bytes)

Pins

Timers

Remappable

8/16-Bit

EUSART

ECCP/(PWM)

C™

2

I

SPI w/DMA

Deep Sleep

Comparators

10-Bit A/D (ch)

NYYY

N

NYYY

N

YYYY

N

YYYY

N

YYYY

N

PMP/PSP

RTCC

CTMU

USB

DS39931C-page 4 © 2009 Microchip Technology Inc.

Pin Diagrams

PIC18F2XJ50

10
11

2
3
4
5
6

1

8

7

9

12
13
14

15

16

17

18

19

20

23

24

25

26

27

28

22
21

MCLR

RA0/AN0/C1INA/ULPWU/RP0

RA1/AN1/C2INA/RP1

RA2/AN2/V

REF-/CVREF/C2INB

RA3/AN3/V

REF+/C1INB

V

DDCORE/VCAP

(2)

RA5/AN4/SS1/HLVDIN/RCV/RP2

V

SS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI/RP11

RC1/T1OSI/UOE

/RP12

RC2/AN11/CTPLS/RP13

V

USB

RB7/KBI3/PGD/RP10
RB6/KBI2/PGC/RP9
RB5/KBI1/SDI1/SDA1/RP8

RB4/KBI0/SCK1/SCL1/RP7
RB3/AN9/CTEDG2/VPO/RP6

RB2/AN8/CTEDG1/VMO/REFO/RP5
RB1/AN10/RTCC/RP4
RB0/AN12/INT0/RP3
V

DD

VSS
RC7/RX1/DT1/SDO1/RP18
RC6/TX1/CK1/RP17
RC5/D+/VP
RC4/D-/VM

28-Pin SPDIP/SOIC/SSOP

(1)

Legend: RPn represents remappable pins.
Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be

dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and
Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin

Select (PPS)”.

2: See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V

DDCORE/VCAP pin.

3: For the QFN package, it is recommended that the bottom pad be connected to V

SS.

28-Pin QFN

(1,3)

RC0/T1OSO/T1CKI/RP11

RB7/KBI3/PGD/RP10

RB6/KBI2/PGC/RP9

RB5/KBI1/SDI1/SDA1/RP8

RB4/KBI0/SCK1/SCL1/RP7

RB3/AN9/CTEDG2/VPO/RP6
RB2/AN8/CTEDG1/VMO/REFO/RP5
RB1/AN10/RTCC/RP4

RB0/AN12/INT0/RP3
V

DD

VSS
RC7/RX1/DT1/SDO1/RP18

RC6/TX1/CK1/RP17

RC5/D+/VP

RC4/D-/VM

MCLR

RA0/AN0/C1INA/ULPWU/RP0

RA1/AN1/C2INA/RP1

RA2/AN2/VREF-/CVREF/C2INB

RA3/AN3/V

REF+/C1INB

V

DDCORE/VCAP

(2)

RA5/AN4/SS1/HLVDIN/RCV/RP2

V

SS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC1/T1OSI/UOE/RP12

RC2/AN11/CTPLS/RP13

V

USB

= Pins are up to 5.5V tolerant

1011

2
3

6

1

18

19

20

21

22

12 13 14

15

8

7

16

17

232425262728

9

PIC18F2XJ50

5

4

PIC18F46J50 FAMILY

© 2009 Microchip Technology Inc. DS39931C-page 5

PIC18F46J50 FAMILY

44-Pin QFN

(1,3)

RA3/AN3/VREF+/C1INB

RA2/AN2/V

REF-/CVREF-/C2INB

RA1/AN1/C2INA/PMA7/RP1

RA0/AN0/C1INA/ULPWU/PMA6/RP0

MCLR

RB7/KBI3/PGD/RP10

RB6/KBI2/PGC/RP9

RB5/PMA0/KBI1/SDI1/SDA1/RP8

RB4/PMA1/KBI0/SCK1/SCL1/RP7

NC

RC6/PMA5/TX1/CK1/RP17

RC5/D+/VP

RC4/D-/VM

RD3/PMD3/RP20

RD2/PMD2/RP19

RD1/PMD1/SDA2

RD0/PMD0/SCL2

V

USB

RC2/AN11/CTPLS/RP13

RC1/T1OSI/U

OE/RP12

RC0/T1OSO/T1CKI/RP11

OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

SS

AVDD
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/SS1

/HLVDIN/RCV/RP2

V

DDCORE/VCAP

(2)

RC7/PMA4/RX1/DT1/SDO1/RP18

RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23

V

SS

VDD

RB0/AN12/INT0/RP3

RB1/AN10/PMBE/RTCC/RP4

RB2/AN8/CTEDG1/PMA3/VMO/REFO/RP5

RB3/AN9/CTEDG2/PMA2/VPO/RP6

RD7/PMD7/RP24

AV

SS

VDD

AVDD

Legend: RPn represents remappable pins.
Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be

dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and
Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin

Select (PPS)”.

2: See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V

DDCORE/VCAP pin.

3: For the QFN package, it is recommended that the bottom pad be connected to V

SS.

= Pins are up to 5.5V tolerant

10
11

2
3

6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

5

4

PIC18F4XJ50

Pin Diagrams (Continued)

DS39931C-page 6 © 2009 Microchip Technology Inc.

Pin Diagrams (Continued)

10
11

2
3

6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

PIC18F4XJ50

37

RA3/AN3/VREF+/C1INB

RA2/AN2/V

REF-/CVREF-/C2INB

RA1/AN1/C2INA/PMA7/RP1

RA0/AN0/C1INA/ULPWU/PMA6/RP0

MCLR

NC

RB7/KBI3/PGD/RP10

RB6/KBI2/PGC/RP9

RB5/PMA0/KBI1/SDI1/SDA1/RP8

RB4/PMA1/KBI0/SCK1/SCL1/RP7

NC

RC6/PMA5/TX1/CK1/RP17

RC5/D+/VP

RC4/D-/VM

RD3/PMD3/RP20

RD2/PMD2/RP19

RD1/PMD1/SDA2

RD0/PMD0/SCL2

V

USB

RC2/AN11/CTPLS/RP13

RC1/T1OSI/UOE

/RP12

NC

NC
RC0/T1OSO/T1CKI/RP11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

SS

VDD
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/SS1

/HLVDIN/RCV/RP2

V

DDCORE/VCAP

(2)

RC7/PMA4/RX1/DT1/SDO1/RP18

RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23

V

SS

VDD

RB0/AN12/INT0/RP3

RB1/AN10/PMBE/RTCC/RP4

RB2/AN8/CTEDG1/PMA3/VMO/REFO/RP5

RB3/AN9/CTEDG2/PMA2/VPO/RP6

44-Pin TQFP

(1)

RD7/PMD7/RP24

5

4

Legend: RPn represents remappable pins.
Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be

dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and
Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin

Select (PPS)”.

2: See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V

DDCORE/VCAP pin.

= Pins are up to 5.5V tolerant

PIC18F46J50 FAMILY

© 2009 Microchip Technology Inc. DS39931C-page 7

PIC18F46J50 FAMILY

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 Oscillator Configurations ............................................................................................................................................................ 29

3.0 Low-Power Modes...................................................................................................................................................................... 41

4.0 Reset .......................................................................................................................................................................................... 57

5.0 Memory Organization ................................................................................................................................................................. 71

6.0 Flash Program Memory.............................................................................................................................................................. 97

7.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 107

8.0 Interrupts .................................................................................................................................................................................. 109

9.0 I/O Ports ................................................................................................................................................................................... 125

10.0 Parallel Master Port (PMP)....................................................................................................................................................... 163

11.0 Timer0 Module ......................................................................................................................................................................... 189

12.0 Timer1 Module ......................................................................................................................................................................... 193

13.0 Timer2 Module ......................................................................................................................................................................... 205

14.0 Timer3 Module ......................................................................................................................................................................... 207

15.0 Timer4 Module ......................................................................................................................................................................... 217

16.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 219

17.0 Enhanced Capture/Compare/PWM (ECCP) Module ................................................................................................................ 239

18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 263

19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 317

20.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 341

21.0 Universal Serial Bus (USB) ...................................................................................................................................................... 351

22.0 Comparator Module.................................................................................................................................................................. 379

23.0 Comparator Voltage Reference Module ................................................................................................................................... 387

24.0 High/Low Voltage Detect (HLVD) ............................................................................................................................................. 391

25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 397

26.0 Special Features of the CPU.................................................................................................................................................... 413

27.0 Instruction Set Summary .......................................................................................................................................................... 431

28.0 Development Support............................................................................................................................................................... 481

29.0 Electrical Characteristics .......................................................................................................................................................... 485

30.0 Packaging Information.............................................................................................................................................................. 525

Appendix A: Revision History............................................................................................................................................................. 537

Appendix B: Device Differences......................................................................................................................................................... 537

The Microchip Web Site..................................................................................................................................................................... 551

Customer Change Notification Service .............................................................................................................................................. 551

Customer Support .............................................................................................................................................................................. 551

Reader Response .............................................................................................................................................................................. 552

Product Identification System............................................................................................................................................................. 553

DS39931C-page 8 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TO OUR VALUED CUSTOMERS

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

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© 2009 Microchip Technology Inc. DS39931C-page 9

PIC18F46J50 FAMILY

NOTES:

DS39931C-page 10 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC1 8F 24J5 0 • P IC 18 LF 24 J50

• PIC18F25J50 • PIC18LF25J50

• PIC18F26J50 • PIC18LF26J50

• PIC18F44J50 • PIC18LF44J50

• PIC18F45J50 • PIC18LF45J50

• PIC18F46J50 • PIC18LF46J50

This family introduces a new line of low-voltage
Universal Serial Bus (USB) microcontrollers with the
main traditional advantage of all PIC18 microcontrollers,
namely, high computational performance and a rich
feature set at an extremely competitive price point.
These features make the PIC18F46J50 Family a logical
choice for many high-performance applications, where
cost is a primary consideration.

1.1 Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F46J50 Family incorpo­rate a range of features that can significantly reduce
power consumption during operation. Key features are:

• Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operational requirements.

• On-the-Fly Mode Switching: The

power-managed modes are invoked by user code
during operation, allowing the users to incorporate
power-saving ideas into their application’s
software design.

1.1.3 OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC18F46J50 Family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:

• Two Crystal modes, using crystals or ceramic
resonators.

• Two External Clock modes, offering the option of
a divide-by-4 clock output.

• An internal oscillator block, which provides an
8 MHz clock and an INTRC source (approxi­mately 31 kHz, stable over temperature and V
as well as a range of six user-selectable clock
frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees
an oscillator pin for use as an additional general
purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,
available to the high-speed crystal, and external
and internal oscillators, providing a clock speed
up to 48 MHz.

• Dual clock operation, allowing the USB module to
run from a high-frequency oscillator while the rest
of the microcontroller is clocked at a different
frequency.

The internal oscillator block provides a stable reference
source that gives the PIC18F46J50 Family additional
features for robust operation:

• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset (POR), or wake-up from
Sleep mode, until the primary clock source is
available.

DD),

1.1.2 UNIVERSAL SERIAL BUS (USB)

Devices in the PIC18F46J50 Family incorporate a
fully-featured USB communications module with a
built-in transceiver that is compliant with the USB
Specification Revision 2.0. The module supports both
low-speed and full-speed communication for all
supported data transfer types.

© 2009 Microchip Technology Inc. DS39931C-page 11

1.1.4 EXPANDED MEMORY

The PIC18F46J50 Family provides ample room for
application code, from 16 Kbytes to 64 Kbytes of code
space. The Flash cells for program memory are rated
to last in excess of 10000 erase/write cycles. Data
retention without refresh is conservatively estimated to
be greater than 20 years.

The Flash program memory is readable and writable
during normal operation. The PIC18F46J50 Family
also provides plenty of room for dynamic application
data with up to 3.8 Kbytes of data RAM.

PIC18F46J50 FAMILY

1.1.5 EXTENDED INSTRUCTION SET

The PIC18F46J50 Family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as C.

1.1.6 EASY MIGRATION

Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.

The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device.

The PIC18F46J50 Family is also pin compatible with
other PIC18 families, such as the PIC18F4550,
PIC18F2450 and PIC18F45J10. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining the
same feature set.

1.2 Other Special Features

• Communications: The PIC18F46J50 Family

incorporates a range of serial and parallel com­munication peripherals, including a fully featured
USB communications module that is compliant
with the USB Specification Revision 2.0. This
device also includes two independent Enhanced
USARTs and two Master Synchronous Serial Port
(MSSP) modules, capable of both Serial
Peripheral Interface (SPI) and I
Slave) modes of operation. The device also has a
parallel port and can be configured to serve as
either a Parallel Master Port (PMP) or as a
Parallel Slave Port (PSP).

• ECCP Modules: All devices in the family incorpo-

rate three Enhanced Capture/Compare/PWM
(ECCP) modules to maximize flexibility in control
applications. Up to four different time bases may
be used to perform several different operations at
once. Each of the ECCPs offers up to four PWM
outputs, allowing for a total of eight PWMs. The
ECCPs also offer many beneficial features,
including polarity selection, programmable dead
time, auto-shutdown and restart and Half-Bridge
and Full-Bridge Output modes.

2

C™ (Master and

• 10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.

• Extended Watchdog Timer (WDT): This

enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 29.0 “Electrical Characteristics” for
time-out periods.

1.3 Details on Individual Family Devices

Devices in the PIC18F46J50 Family are available in
28-pin and 44-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in two
ways:

• Flash program memory (three sizes: 16 Kbytes

for the PIC18FX4J50, 32 Kbytes for
PIC18FX5J50 devices and 64 Kbytes for
PIC18FX6J50)

• I/O ports (three bidirectional ports on 28-pin

devices, five bidirectional ports on 44-pin devices)

All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.

The pinouts for the PIC18F2XJ50 devices are listed in
Table 1-3. The pinouts for the PIC18F4XJ50 devices
are shown in Table 1-4.

The PIC18F46J50 Family of devices provides an
on-chip voltage regulator to supply the correct voltage
levels to the core. Parts designated with an “F” part
number (such as PIC18F46J50) have the voltage
regulator enabled.

These parts can run from 2.15V-3.6V on V
have the V
low-ESR capacitor. Parts designated with an “LF” part
number (such as PIC18LF46J50) do not enable the volt­age regulator. For “LF” parts, an external supply of

2.0V-2.7V has to be supplied to the V

2.0V-3.6V can be supplied to V

never exceed V

For more details about the internal voltage regulator,
see Section 26.3 “On-Chip Voltage Regulator”.

DDCORE pin connected to VSS through a

DD).

DD, but should

DDCORE pin while

DD (VDDCORE should

DS39931C-page 12 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ50 (28-PIN DEVICES)

Features PIC18F24J50 PIC18F25J50 PIC18F26J50

Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz

Program Memory (Bytes) 16K 32K 64K

Program Memory (Instructions) 8,192 16,384 32,768

Data Memory (Bytes) 3.8K 3.8K 3.8K

Interrupt Sources 30

I/O Ports Ports A, B, C

Timers 5

Enhanced Capture/Compare/PWM Modules 2

Serial Communications MSSP (2), Enhanced USART (2), USB

Parallel Communications (PMP/PSP) No

10-Bit Analog-to-Digital Module 10 Input Channels

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR

(PWRT, OST)

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil)

, WDT

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XJ50 (44-PIN DEVICES)

Features PIC18F44J50 PIC18F45J50 PIC18F46J50

Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz

Program Memory (Bytes) 16K 32K 64K

Program Memory (Instructions) 8,192 16,384 32,768

Data Memory (Bytes) 3.8K 3.8K 3.8K

Interrupt Sources 30

I/O Ports Ports A, B, C, D, E

Timers 5

Enhanced Capture/Compare/PWM Modules 2

Serial Communications MSSP (2), Enhanced USART (2), USB

Parallel Communications (PMP/PSP) Yes

10-Bit Analog-to-Digital Module 13 Input Channels

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR

(PWRT, OST)

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 44-Pin QFN and TQFP

, WDT

© 2009 Microchip Technology Inc. DS39931C-page 13

PIC18F46J50 FAMILY

Instruction

Decode and

Control

PORTA

Data Latch

Data Memory

(3.8 Kbytes)

Address Latch

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

Address Latch

Program Memory

(16 Kbytes-64 Kbytes)

Data Latch

20

8

8

Table Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

PCLATU

PCU

Note 1: See Table 1-3 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0

ECCP1

ADC

10-Bit

W

Instruction Bus <16>

STKPTR

Bank

8

State Machine
Control Signals

Decode

8

8

EUSART2

ECCP2

ROM Latch

MSSP2

PORTC

RA0:RA7

(1)

RC0:RC7

(1)

PORTB

RB0:RB7

(1)

Timer4

OSC1/CLKI

OSC2/CLKO

V

DD,

8 MHz

INTOSC

V

SS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

(2)

Precision

Reference

Band Gap

INTRC

Oscillator

Regulator

Vol tage

VDDCORE/VCAP

USB

CTMU

Timing

Generation

USB

Module

VUSB

HLVD

RTCC

FIGURE 1-1: PIC18F2XJ50 (28-PIN) BLOCK DIAGRAM

DS39931C-page 14 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

8

8

3

W

8

8

8

Instruction

Decode and

Control

Data Latch

Address Latch

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

Address Latch

Program Memory

(16 Kbytes-64 Kbytes)

Data Latch

20

Table Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

ROM Latch

PCLATU

PCU

Instruction Bus <16>

STKPTR

Bank

State Machine
Control Signals

Decode

System Bus Interface

AD<15:0>, A<19:16>
(Multiplexed with PORTD
and PORTE)

PORTA

PORTC

PORTD

PORTE

RA0:RA7

(1)

RC0:RC7

(1)

RD0:RD7

(1)

RE0:RE2

(1)

PORTB

RB0:RB7

(1)

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0

ECCP1

ADC

10-Bit

EUSART2

ECCP2

MSSP2

Timer4

Note 1: See Table 1-3 for I/O port pin descriptions.

2: The on-chip voltage regulator is always enabled by default.

Data Memory

(3.8 Kbytes)

USB

PMP

OSC1/CLKI

OSC2/CLKO

V

DD,

8 MHz

INTOSC

V

SS

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

(2)

Precision

Reference

Band Gap

INTRC

Oscillator

Regulator

Voltage

VDDCORE/VCAP

Timing

Generation

USB

Module

VUSB

CTMU

HLVD

RTCC

FIGURE 1-2: PIC18F4XJ50 (44-PIN) BLOCK DIAGRAM

© 2009 Microchip Technology Inc. DS39931C-page 15

PIC18F46J50 FAMILY

TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS

Pin Number

Pin

Pin Name

28-SPDIP/

SSOP/

SOIC

28-QFN

Typ e

Buffer

Typ e

Description

MCLR

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

(1)

OSC2

CLKO

(1)

RA6

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

1 26 I ST Master Clear (Reset) input. This pin is an

active-low Reset to the device.

96

10 7

I/O

O

O

I/O

I

I

CMOS

Oscillator crystal or external clock input.

ST

TTL

—

—

TTL

Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
CMOS otherwise. Main oscillator input
connection.
External clock source input; always associated
with pin function OSC1 (see related OSC1/CLKI
pins).
Digital I/O.

Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.
Main oscillator feedback output connection.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
Digital I/O.

2

C™ = Open-Drain, I2C specific

DD)

DS39931C-page 16 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin

Pin Name

28-SPDIP/

SSOP/

28-QFN

SOIC

RA0/AN0/C1INA/ULPWU/RP0

227
RA0
AN0
C1INA
ULPWU
RP0

RA1/AN1/C2INA/RP1

328
RA1
AN1
C2INA
RP1

RA2/AN2/V

REF-/CVREF/C2INB

41
RA2
AN2

REF-

V

REF

CV
C2INB

RA3/AN3/V

REF+/C1INB

52
RA3
AN3

REF+

V
C1INB

RA5/AN4/SS1

/HLVDIN/

74

RCV/RP2

RA5
AN4
SS1
HLVDIN
RCV
RP2

(1)

RA6

(1)

RA7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

Typ e

I/O

I
I
I

I/O

I

O

I

I/O

I/O

I

O

I
I

I/O

I
I
I

I/O

I
I
I
I

I/O

Buffer

Typ e

PORTA is a bidirectional I/O port.

DIG
Analog
Analog
Analog

DIG

DIG
Analog
Analog

DIG

DIG
Analog
Analog
Analog
Analog

DIG
Analog
Analog
Analog

DIG
Analog

TTL
Analog
Analog

DIG

Digital I/O.
Analog input 0.
Comparator 1 input A.
Ultra low-power wake-up input.
Remappable peripheral pin 0 input/output.

Digital I/O.
Analog input 1.
Comparator 2 input A.
Remappable peripheral pin 1 input/output.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
Comparator 2 input B.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
Comparator 1 input B.

Digital I/O.
Analog input 4.
SPI slave select input.
Low-voltage detect input.
External USB transceiver RCV input.
Remappable peripheral pin 2 input/output.

See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.

2

C™ = Open-Drain, I2C specific

Description

DD)

© 2009 Microchip Technology Inc. DS39931C-page 17

PIC18F46J50 FAMILY

TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin

Pin Name

RB0/AN12/INT0/RP3

RB0
AN12
INT0
RP3

RB1/AN10/RTCC/RP4

RB1
AN10
RTCC
RP4

RB2/AN8/CTEDG1/VMO/
REFO/RP5

RB2
AN8
CTEDG1
VMO
REFO
RP5

RB3/AN9/CTEDG2/VPO/RP6

RB3
AN9
CTEDG2
VPO
RP6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

28-SPDIP/

SSOP/

SOIC

21 18

22 19

23 20

24 21

28-QFN

Typ e

I/O

I
I

I/O

I/O

I

O

I/O

I/O

I

I
O
O

I/O

I/O

I

I/O

O

I

Buffer

Typ e

PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups
on all inputs.

DIG

Analog

ST

DIG

DIG

Analog

DIG
DIG

DIG

Analog

ST
DIG
DIG
DIG

DIG

Analog

ST
DIG
DIG

Digital I/O.
Analog input 12.
External interrupt 0.
Remappable peripheral pin 3 input/output.

Digital I/O.
Analog input 10.
Asynchronous serial transmit data output.
Remappable peripheral pin 4 input/output.

Digital I/O.
Analog input 8.
CTMU edge 1 input.
External USB transceiver D- data output.
Reference output clock.
Remappable peripheral pin 5 input/output.

Digital I/O.
Analog input 9.
CTMU edge 2 input.
External USB transceiver D+ data output.
Remappable peripheral pin 6 input/output.

2

C™ = Open-Drain, I2C specific

Description

DD)

DS39931C-page 18 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin

Pin Name

RB4/KBI0/SCK1/SCL1/RP7

RB4
KBI0
SCK1
SCL1
RP7

RB5/KBI1/SDI1/SDA1/RP8

RB5
KBI1
SDI1
SDA1
RP8

RB6/KBI2/PGC/RP9

RB6
KBI2
PGC
RP9

RB7/KBI3/PGD/RP10

RB7
KBI3
PGD

RP10

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

28-SPDIP/

SSOP/

SOIC

25 22

26 23

27 24

28 25

28-QFN

Typ e

I/O

I
I/O
I/O
I/O

I/O
I/O

I
I/O
I/O

I/O

I

I
I/O

I/O

I
I/O

I/O

Buffer

Typ e

PORTB (continued)

DIG
TTL
DIG

2

C

I

DIG

DIG
DIG

ST

2

C

I

DIG

DIG
TTL

ST

DIG

DIG
TTL

ST

DIG

Digital I/O.
Interrupt-on-change pin.
Synchronous serial clock input/output.
I2C clock input/output.
Remappable peripheral pin 7 input/output.

Digital I/O.
Parallel Master Port address.
SPI data input.

2

C™ data input/output.

I
Remappable peripheral pin 8 input/output.

Digital I/O.
Interrupt-on-change pin.
ICSP™ clock input.
Remappable peripheral pin 9 input/output.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Remappable peripheral pin 10 input/output.

2

C™ = Open-Drain, I2C specific

Description

DD)

© 2009 Microchip Technology Inc. DS39931C-page 19

PIC18F46J50 FAMILY

TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin

Pin Name

RC0/T1OSO/T1CKI/RP11

RC0
T1OSO
T1CKI
RP11

RC1/T1OSI/UOE

RC1
T1OSI
UOE
RP12

RC2/AN11/CTPLS/RP13

RC2
AN11
CTPLS
RP13

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX1/CK1/RP17

RC6
TX1
CK1

RP17

RC7/RX1/DT1/SDO1/RP18

RC7
RX1
DT1
SDO1
RP18

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

/RP12

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

28-SPDIP/

SSOP/

SOIC

11 8

12 9

13 10

15 12

16 13

17 14

18 15

28-QFN

Typ e

I/O

O

I

I/O

I/O

I

O

I/O

I/O

I

O

I/O

I

I/O

I

I

I/O

I

I/O

O

I/O

I/O

I/O

I

I/O

O

I/O

Buffer

Typ e

PORTC is a bidirectional I/O port.

ST

Analog

ST

DIG

ST

Analog

DIG
DIG

ST

Analog

DIG
DIG

TTL

—

TTL

TTL
DIG
TTL

ST

DIG

ST

DIG

ST
ST

ST
DIG
DIG

Digital I/O.
Timer1 oscillator output.
Timer1 external digital clock input.
Remappable peripheral pin 11 input/output.

Digital I/O.
Timer1 oscillator input.
External USB transceiver NOE output.
Remappable peripheral pin 12 input/output.

Digital I/O.
Analog input 11.
CTMU pulse generator output.
Remappable peripheral pin 13 input/output.

Digital I.
USB bus minus line input/output.
External USB transceiver FM input.

Digital I.
USB bus plus line input/output.
External USB transceiver VP input.

Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related
RX1/DT1).
Remappable peripheral pin 17 input/output.

Digital I/O.
Asynchronous serial receive data input.
Synchronous serial data output/input.
SPI data output.
Remappable peripheral pin 18 input/output.

2

C™ = Open-Drain, I2C specific

Description

DD)

DS39931C-page 20 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin

Pin Name

VSS1 8 5 P — Ground reference for logic and I/O pins.

VSS21916——

DD 20 17 P — Positive supply for peripheral digital logic and I/O

V

DDCORE/VCAP

V

VDDCORE

VCAP

USB 14 11 P — USB voltage input pin.

V

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

28-SPDIP/

SSOP/

SOIC

28-QFN

63—

Typ e

P

P

Buffer

Typ e

pins.

—

Core logic power or external filter capacitor
connection.

—

—

Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).

2

C™ = Open-Drain, I2C specific

Description

DD)

© 2009 Microchip Technology Inc. DS39931C-page 21

PIC18F46J50 FAMILY

TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

44-

QFN

TQFP

44-

Pin

Type

Buffer

Type

Description

MCLR

OSC1/CLKI/RA7

OSC1

CLKI

(1)

RA7

OSC2/CLKO/RA6

OSC2

CLKO

(1)

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

18 18 I ST Master Clear (Reset) input; this is an active-low

Reset to the device.

32 30

I

I

I/O

33 31

O

O

I/O

Oscillator crystal or external clock input.

ST

CMOS

TTL

—

—

TTL

Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;

otherwise CMOS. Main oscillator input

connection.
External clock source input; always associated
with pin function OSC1 (see related OSC1/CLKI
pins).
Digital I/O.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection
in RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
Digital I/O.

2

C™ = Open-Drain, I2C specific

DD)

DS39931C-page 22 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0/C1INA/ULPWU/PMA6/

44-

QFN

19 19

TQFP

RP0

RA0
AN0
C1INA
ULPWU
PMA6
RP0

RA1/AN1/C2INA/PMA7/RP1

20 20
RA1
AN1
C2INA
PMA7
RP1

RA2/AN2/V

REF-/CVREF/C2INB

21 21
RA2
AN2

REF-

V
CV

REF

C2INB

RA3/AN3/V

REF+/C1INB

22 22
RA3
AN3

REF+

V
C1INB

RA5/AN4/SS1

/HLVDIN/RCV/RP2

24 24
RA5
AN4
SS1
HLVDIN
RCV
RP2

(1)

RA6

(1)

RA7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

44-

Pin

Type

I/O

I
I

I
I/O
I/O

I

O

I
I/O
I/O

I/O

I

O

I

I

I/O

I

I

I

I/O

I

I

I

I
I/O

Buffer

Type

DIG
Analog
Analog
Analog

DIG

DIG

DIG
Analog
Analog

DIG

DIG

DIG
Analog
Analog
Analog
Analog

DIG
Analog
Analog
Analog

DIG
Analog

TTL
Analog
Analog

DIG

Description

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.
Comparator 1 input A.
Ultra low-power wake-up input.
Parallel Master Port digital I/O.
Remappable peripheral pin 0 input/output.

Digital I/O.
Analog input 1.
Comparator 2 input A.
Parallel Master Port digital I/O.
Remappable peripheral pin 1 input/output.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
Comparator 2 input B.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
Comparator 1 input B.

Digital I/O.
Analog input 4.
SPI slave select input.
Low-voltage detect input.
External USB transceiver RCV input.
Remappable peripheral pin 2 input/output.

See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.

2

C™ = Open-Drain, I2C specific

DD)

© 2009 Microchip Technology Inc. DS39931C-page 23

PIC18F46J50 FAMILY

TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/AN12/INT0/RP3

RB0
AN12
INT0
RP3

RB1/AN10/PMBE/RTCC/RP4

RB1
AN10
PMBE
RTCC
RP4

RB2/AN8/CTEDG1/PMA3/VMO/
REFO/RP5

RB2
AN8
CTEDG1
PMA3
VMO
REFO
RP5

RB3/AN9/CTEDG2/PMA2/VPO/
RP6

RB3
AN9
CTEDG2
PMA2
VPO
RP6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

44-

QFN

TQFP

98

10 9

11 10

12 11

44-

Pin

Type

I/O

I
I

I/O

I/O

I
O
O

I/O

I/O

I

I
O
O
O

I/O

I/O

I

I
O
O

I/O

Buffer

Type

DIG

Analog

ST

DIG

DIG

Analog

DIG
DIG
DIG

DIG

Analog

ST
DIG
DIG
DIG
DIG

DIG

Analog

ST
DIG
DIG
DIG

Description

PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.

Digital I/O.
Analog input 12.
External interrupt 0.
Remappable peripheral pin 3 input/output.

Digital I/O.
Analog input 10.
Parallel Master Port byte enable.
Asynchronous serial transmit data output.
Remappable peripheral pin 4 input/output.

Digital I/O.
Analog input 8.
CTMU edge 1 input.
Parallel Master Port address.
External USB transceiver D- data output.
Reference output clock.
Remappable peripheral pin 5 input/output.

Digital I/O.
Analog input 9.
CTMU edge 2 input.
Parallel Master Port address.
External USB transceiver D+ data output.
Remappable peripheral pin 6 input/output.

2

C™ = Open-Drain, I2C specific

DD)

DS39931C-page 24 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB4/PMA1/KBI0/SCK1/SCL1/RP7

RB4
PMA1
KBI0
SCK1
SCL1
RP7

RB5/PMA0/KBI1/SDI1/SDA1/RP8

RB5
PMA0
KBI1
SDI1
SDA1
RP8

RB6/KBI2/PGC/RP9

RB6
KBI2
PGC
RP9

RB7/KBI3/PGD/RP10

RB7
KBI3
PGD

RP10

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

44-

QFN

14 14

15 15

16 16

17 17

TQFP

44-

Pin

Type

I/O
I/O

I
I/O
I/O
I/O

I/O
I/O

I

I
I/O
I/O

I/O

I

I
I/O

I/O

I
I/O

I/O

Buffer

Type

DIG
DIG
TTL
DIG

2

C

I

DIG

DIG
DIG
TTL

ST

2

C

I

DIG

DIG
TTL

ST

DIG

DIG
TTL

ST

DIG

Description

PORTB (continued)

Digital I/O.
Parallel Master Port address.
Interrupt-on-change pin.
Synchronous serial clock input/output.
I2C clock input/output.
Remappable peripheral pin 7 input/output.

Digital I/O.
Parallel Master Port address.
Interrupt-on-change pin.
SPI data input.
I2C™ data input/output.
Remappable peripheral pin 8 input/output.

Digital I/O.
Interrupt-on-change pin.
ICSP™ clock input.
Remappable peripheral pin 9 input/output.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Remappable peripheral pin 10 input/output.

2

C™ = Open-Drain, I2C specific

DD)

© 2009 Microchip Technology Inc. DS39931C-page 25

PIC18F46J50 FAMILY

TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T1CKI/RP11

RC0
T1OSO
T1CKI
RP11

RC1/T1OSI/UOE

RC1
T1OSI
UOE
RP12

RC2/AN11/CTPLS/RP13

RC2
AN11
CTPLS
RP13

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/PMA5/TX1/CK1/RP17

RC6
PMA5
TX1
CK1

RP17

RC7/PMA4/RX1/DT1/SDO1/RP18

RC7
PMA4
RX1

DT1
SDO1
RP18

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

/RP12

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

44-

QFN

TQFP

34 32

35 35

36 36

42 42

43 43

44 44

11

44-

Pin

Type

I/O

O

I

I/O

I/O

I

O

I/O

I/O

I

O

I/O

I

O

I

I

I/O

I

I/O
I/O

O

I/O

I/O

I/O
I/O

I

I/O

O

I/O

Buffer

Type

ST

Analog

ST

DIG

ST

Analog

DIG
DIG

ST

Analog

DIG
DIG

TTL

—

TTL

TTL
DIG
TTL

ST
DIG
DIG

ST

DIG

ST
DIG

ST

ST
DIG
DIG

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Remappable peripheral pin 11 input/output.

Digital I/O.
Timer1 oscillator input.
External USB transceiver NOE output.
Remappable peripheral pin 12 input/output.

Digital I/O.
Analog input 11.
CTMU pulse generator output.
Remappable peripheral pin 13 input/output.

Digital I.
USB bus minus line input/output.
External USB transceiver FM input.

Digital I.
USB bus plus line input/output.
External USB transceiver VP input.

Digital I/O.
Parallel Master Port address.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related
RX1/DT1).
Remappable peripheral pin 17 input/output.

EUSART1 asynchronous receive.
Parallel Master Port address.
EUSART1 synchronous data (see related
TX1/CK1).
Synchronous serial data output/input.
SPI data output.
Remappable peripheral pin 18 input/output.

2

C™ = Open-Drain, I2C specific

DD)

DS39931C-page 26 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RD0/PMD0/SCL2

RD0
PMD0
SCL2

RD1/PMD1/SDA2

RD1
PMD1
SDA2

RD2/PMD2/RP19

RD2
PMD2
RP19

RD3/PMD3/RP20

RD3
PMD3
RP20

RD4/PMD4/RP21

RD4
PMD4
RP21

RD5/PMD5/RP22

RD5
PMD5
RP22

RD6/PMD6/RP23

RD6
PMD6
RP23

RD7/PMD7/RP24

RD7
PMD7
RP24

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

44-

QFN

TQFP

38 38

39 39

40 40

41 41

22

33

44

55

44-

Pin

Type

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

Buffer

Type

ST
DIG
DIG

ST
DIG
DIG

ST
DIG
DIG

ST
DIG
DIG

ST
DIG
DIG

ST
DIG
DIG

ST
DIG
DIG

ST
DIG
DIG

Description

PORTD is a bidirectional I/O port.

Digital I/O.
Parallel Master Port data.
I2C™ data input/output.

Digital I/O.
Parallel Master Port data.
I2C data input/output.

Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 19 input/output.

Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 20 input/output.

Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 21 input/output.

Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 22 input/output.

Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 23 input/output.

Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 24 input/output.

2

C™ = Open-Drain, I2C specific

DD)

© 2009 Microchip Technology Inc. DS39931C-page 27

PIC18F46J50 FAMILY

TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RE0/AN5/PMRD

RE0
AN5
PMRD

RE1/AN6/PMWR

RE1
AN6
PMWR

RE2/AN7/PMCS

RE2
AN7
PMCS

SS1 6 6 P — Ground reference for logic and I/O pins.

V

VSS23129——

AVSS1 30 — P — Ground reference for analog modules.

DD1 8 7 P — Positive supply for peripheral digital logic and

V

VDD22928P—

VDDCORE/VCAP

VDDCORE

VCAP

DD1 7 — P — Positive supply for analog modules.

AV

DD2 28 — — — Positive supply for analog modules.

AV

VUSB 37 37 P — USB voltage input pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DIG = Digital output I

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

44-

QFN

25 25

26 26

27 27

23 23

TQFP

44-

Pin

Type

I/O

I

I/O

I/O

I

I/O

I/O

I

O

P

P

Buffer

Type

ST

Analog

DIG

ST

Analog

DIG

ST

Analog

—

—

—

Description

PORTE is a bidirectional I/O port.

Digital I/O.
Analog input 5.
Parallel Master Port input/output.

Digital I/O.
Analog input 6.
Parallel Master Port write strobe.

Digital I/O.
Analog input 7.
Parallel Master Port byte enable.

I/O pins.

Core logic power or external filter capacitor
connection.

Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).

2

C™ = Open-Drain, I2C specific

DD)

DS39931C-page 28 © 2009 Microchip Technology Inc.

PIC18F46J50 FAMILY

2.0 OSCILLATOR CONFIGURATIONS

2.1 Overview

Devices in the PIC18F46J50 Family incorporate a
different oscillator and microcontroller clock system
than general purpose PIC18F devices. Besides the
USB module, with its unique requirements for a stable
clock source, make it necessary to provide a separate
clock source that is compliant with both USB low-speed
and full-speed specifications.

The PIC18F46J50 Family has additional prescalers
and postscalers, which have been added to accommo­date a wide range of oscillator frequencies. Figure 2-1
provides an overview of the oscillator structure.

Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.

2.1.1 OSCILLATOR CONTROL

The operation of the oscillator in PIC18F46J50 Family
devices is controlled through three Configuration regis­ters and two control registers. Configuration registers,
CONFIG1L, CONFIG1H and CONFIG2L, select the
oscillator mode, PLL prescaler and CPU divider
options. As Configuration bits, these are set when the
device is programmed and left in that configuration until
the device is reprogrammed.

The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.5.1 “Oscillator Control
Register”.

The OSCTUNE register (Register 2-1) is used to trim the
INTOSC frequency source, and select the
low-frequency clock source that drives several special
features. The OSCTUNE register is also used to activate
or disable the Phase Locked Loop (PLL). Its use is
described in Section 2.2.5.1 “OSCTUNE Register”.

TABLE 2-1: OSCILLATOR MODES

Mode Description

ECPLL External Clock Input mode, the PLL can

be enabled or disabled in software,
CLKO on RA6, apply external clock
signal to RA7.

EC External Clock Input mode, the PLL is

always disabled, CLKO on RA6, apply
external clock signal to RA7.

HSPLL High-Speed Crystal/Resonator mode,

PLL can be enabled or disabled in
software, crystal/resonator connected
between RA6 and RA7.

HS High-Speed Crystal/Resonator mode,

PLL always disabled, crystal/resonator
connected between RA6 and RA7.

INTOSCPLLO Internal Oscillator mode, PLL can be

enabled or disabled in software, CLKO
on RA6, port function on RA7, the
internal oscillator block is used to derive
both the primary clock source and the
postscaled internal clock.

INTOSCPLL Internal Oscillator mode, PLL can be

enabled or disabled in software, port
function on RA6 and RA7, the internal
oscillator block is used to derive both the
primary clock source and the postscaled
internal clock.

INTOSCO Internal Oscillator mode, PLL is always

disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
postscaler serves as both the postscaled
internal clock and the primary clock
source.

INTOSC Internal Oscillator mode, PLL is always

disabled, port function on RA6 and RA7,
the output of the INTOSC postscaler
serves as both the postscaled internal
clock and the primary clock source.

2.2 Oscillator Types

PIC18F46J50 Family devices can be operated in eight
distinct oscillator modes. Users can program the
FOSC<2:0> Configuration bits to select one of the
modes listed in Table 2-1. For oscillator modes which
produce a clock output (CLKO) on pin RA6, the output
frequency will be one fourth of the peripheral clock
frequency. The clock output stops when in Sleep mode,
but will continue during Idle mode (see Figure 2-1).

© 2009 Microchip Technology Inc. DS39931C-page 29

PIC18F46J50 FAMILY

OSC1

OSC2

Primary Oscillator

CPU

Peripherals

IDLE

INTOSC Postscaler

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

111

110

101

100

011

010

001

000

31 kHz

INTRC
31 kHz

Internal

Oscillator

Block

8 MHz

8 MHz

0

1

OSCTUNE<7>

PLLDIV<2:0>

CPU Divider

÷ 1

÷ 2

÷ 3

÷ 6

USB Module

4 MHz

WDT, PWRT, FSCM
and Two-Speed Start-up

OSCCON<6:4>

PLLEN

1

0

F

OSC2

1

0

PLL Prescaler

96 MHz

PLL

(1)

÷ 2

1

0

FSEN

÷ 8

10

11

÷ 4

CPDIV<1:0>

00

01

10

11

CPDIV<1:0>

(Note 2)

00

FOSC<2:1>

Other

00

01

OSCCON<1:0>

11

÷ 4

RA6

CLKO

Enabled Modes

Timer1 Clock

(3)

Postscaled
Internal Clock

T1OSI

T1OSO

Secondary Oscillator

T1OSCEN

Clock

Needs 48 MHz for FS
Needs 6 MHz for LS

Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit

in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to t

rc

to lock. During this time, the

device continues to be clocked at the PLL bypassed frequency.

2: In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this

node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked
at 6 MHz.

3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the

reference clock of Section 2.6 “Reference Clock Output”) and PLL.

4: The USB module cannot be used to communicate unless the primary clock source is selected.

÷ 12
÷ 10

÷ 6
÷ 5
÷ 4
÷ 3
÷ 2
÷ 1

000
001
010
011
100
101

110
111

48 MHz

Primary Clock
Source

(4)

2.2.1 OSCILLATOR MODES AND USB OPERATION

Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
order to use the USB module, a fixed 6 MHz or 48 MHz
clock must be internally provided to the USB module for
operation in either Low-Speed or Full-Speed mode,
respectively. The microcontroller core need not be
clocked at the same frequency as the USB module.

FIGURE 2-1: PIC18F46J50 FAMILY CLOCK DIAGRAM

A network of MUXes, clock dividers and a fixed 96 MHz
output PLL have been provided, which can be used to
derive various microcontroller core and USB module
frequencies. Figure 2-1 helps in understanding the
oscillator structure of the PIC18F46J50 Family of
devices.

DS39931C-page 30 © 2009 Microchip Technology Inc.