Datasheet PIC18F23K20, PIC18F24K20, PIC18F25K20, PIC18F26K20, PIC18F43K20 Datasheet

PIC18F23K20/24K20/25K20/26K20/

43K20/44K20/45K20/46K20

Data Sheet

28/40/44-Pin Flash Microcontrollers

with nanoWatt XLP Technology

 2010 Microchip Technology Inc. DS41303G

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information c ontained in t his p ublication regarding d evice
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that yo ur ap plication me ets wi th yo ur sp ecifications.
MICROCHIP MAKES N O R EPRESENTATIONS OR
WARRANTIES OF AN Y KIN D W HETHER EXPRESS OR
IMPLIED, WR ITTEN O R O RAL, ST ATUTORY OR
OTHERWISE, RE LATED T O T HE I NFORMATION,
INCLUDING B UT NOT L IMITED T O IT S C ONDITION,
QUALITY, PE RFORMANCE, M ERCHANTABILITY OR
FITNESS FOR PU RPOSE. Microchip dis claims al l lia bility
arising f rom t his i nformation an d its use. U se o f Microchip
devices in li fe support a nd/or safety applications is e ntirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold h armless M icrochip f rom a ny an d al l da mages, claims,
suits, o r e xpenses re sulting f rom such u se. No li censes are
conveyed, im plicitly or ot herwise, under an y M icrochip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

K
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC

32

logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41303G-page 2  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

28/40/44-Pin Flash Microcontrollers

with nanoWatt XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture:

- Optional extended instruction set designed to
optimize re-entrant code

• Up to 1024 bytes Data EEPROM

• Up to 64 Kbytes Linear Program Memory
Addressing

• Up to 3936 bytes Linear Data Memory Addressing

• Up to 16 MIPS Operation

• 16-bit Wide Instructions, 8-bit Wide Data Path

• Priority Levels for Interrupts

• 31-Level, Software Accessible Hardware Stack

• 8 x 8 Single-Cycle Hardware Multiplier

Flexible Oscillator Struc ture:

• Precision 16 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%

- Software selectable frequencies range of

31 kHz to 16 MHz

- 64 MHz performance available using PLL –

no external components required

• Four Crystal modes up to 64 MHz

• Two External Clock modes up to 64 MHz

• 4X Phase Lock Loop (PLL)

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

- Two-Speed Oscillator Start-up

Special Microcontroller Features:

• Operating Voltage Range: 1.8V to 3.6V

• Self-Programmable under Software Control

• Programmable 16-Level High/Low-Voltage
Detection (HLVD) module:

- Interrupt on High/Low-Voltage Detection

• Programmable Brown-out Reset (BOR):

- With software enable option

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single-Supply 3V In-Circuit Serial
Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

Extreme Low-Power Management with nanoWatt XLP:

• Sleep mode: < 100 nA @ 1.8V

• Watchdog Timer: < 800 nA @ 1.8V

• Timer1 Oscillator: < 800 nA @ 32 kHz and 1.8V

Analog Features:

• Analog-to-Digital Converter (ADC) module:

- 10-bit resolution, 13 External Channels

- Auto-acquisition capability

- Conversion available during Sleep

- 1.2V Fixed Voltage Reference (FVR) channel

- Independent input multiplexing

• Analog Comparator module:

- Two rail-to-rail analog comparators

- Independent input multiplexing

• Voltage Reference (CV

- Programmable (% VDD), 16 steps

- Two 16-level voltage ranges using V

REF) module

REF pins

Peripheral Highlight s:

• Up to 35 I/O Pins plus 1 Input-only Pin:

- High-Current Sink/Source 25 mA/25 mA

- Three programmable external interrupts

- Four programmable interrupt-on-change

- Eight programmable weak pull-ups

- Programmable slew rate

• Capture/Compare/PWM (CCP) module

• Enhanced CCP (ECCP) module:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-Shutdown and Auto-Restart

• Master Synchronous Serial Port (MSSP) module

- 3-wire SPI (supports all 4 modes)

2

-I

C™ Master and Slave modes with address

mask

• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:

- Supports RS-485, RS-232 and LIN

- RS-232 operation using internal oscillator

- Auto-Wake-up on Break

- Auto-Baud Detect

 2010 Microchip Technology Inc. DS41303G-page 3

PIC18F2XK20/4XK20

-

Program Memory Data Memory

Device

PIC18F23K20 8K 4096 512 256 25 11 1/1 Y Y 1 2 1/3

PIC18F24K20 16K 8192 768 256 25 11 1/1 Y Y 1 2 1/3

PIC18F25K20 32K 16384 1536 256 25 11 1/1 Y Y 1 2 1/3

PIC18F26K20 64k 32768 3936 1024 25 11 1/1 Y Y 1 2 1/3

PIC18F43K20 8K 4096 512 256 36 14 1/1 Y Y 1 2 1/3

PIC18F44K20 16K 8192 768 256 36 14 1/1 Y Y 1 2 1/3

PIC18F45K20 32K 16384 1536 256 36 14 1/1 Y Y 1 2 1/3

PIC18F46K20 64k 32768 3936 1024 36 14 1/1 Y Y 1 2 1/3

Note 1: One pin is input only.

2: Channel count includes internal fixed voltage reference channel.

Flash

(bytes)

# Single-Word

Instructions

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-bit

(1)

A/D

(ch)

CCP/

ECCP

(2)

(PWM)

SPI

MSSP

Master

2

C™

I

Comp.

EUSART

Timers

8/16-bit

DS41303G-page 4  2010 Microchip Technology Inc.

Pin Diagrams

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/C12IN2-/CCP2

(1)

RB2/INT2/AN8
RB1/INT1/AN10/C12IN3­RB0/INT0/FLT0/AN12
V

DD

VSS
RD7/PSP7/P1D
RD6/PSP6/P1C

RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO

RC4/SDI/SDA
RD3/PSP3

RD2/PSP2

MCLR/VPP/RE3

RA0/AN0/C12IN0­RA1/AN1/C12IN1-

RA2/AN2/V

REF-/CVREF/C2IN+

RA3/AN3/V

REF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS

/HLVDIN/C2OUT

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS

/AN7

V

DD

VSS

OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

10
11

2
3
4
5
6

1

8

7

9

12
13
14

15

16

17

18

19

20

23

24

25

26

27

28

22
21

MCLR/VPP/RE3
RA0/AN0/C12IN0­RA1/AN1/C12IN1-

RA2/AN2/V

REF-/CVREF/C2IN+

RA3/AN3/V

REF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS

/HLVDIN/C2OUT

V

SS

OSC1/CLKIN/RA7

OSC2/CLKOUT/RA6
RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A

RC3/SCK/SCL

RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11/P1D
RB3/AN9/C12IN2-/CCP2

(1)

RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

40-pin PDIP

28-pin PDIP, SOIC, SSOP

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: UQFN package availability applies only to PIC18F23K20.

10 11

2
3

6

1

18

19

20

21

22

12 13 14

15

8

7

16

17

232425262728

9

RC0/T1OSO/T13CKI

5

4

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11/P1D

RB3/AN9/C12IN2-/CCP2

(1)

RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
V

DD

VSS
RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

MCLR

/VPP/RE3

RA0/AN0/C12IN0-

RA1/AN1/C12IN1-

RA2/AN2/VREF-/CVREF/C2IN+

RA3/AN3/V

REF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS

/HLVDIN/C2OUT

V

SS

OSC1/CLKIN/RA7

OSC2/CLKOUT/RA6

RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A

RC3/SCK/SCL

28-pin QFN/UQFN

(2)

PIC18F23K20

PIC18F24K20

PIC18F25K20

PIC18F26K20

PIC18F43K20

PIC18F44K20

PIC18F45K20

PIC18F46K20

PIC18F23K20
PIC18F24K20
PIC18F25K20
PIC18F26K20

PIC18F2XK20/4XK20

 2010 Microchip Technology Inc. DS41303G-page 5

PIC18F2XK20/4XK20

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

10
11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

RA3/AN3/V

REF+/C1IN+

RA2/AN2/V

REF-/CVREF/C2IN+

RA1/AN1/C12IN1-

RA0/AN0/C12IN0-

MCLR

/VPP/RE3

RB3/AN9/C12IN2-/CCP2

(1)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

NC

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

(1)

RC0/T1OSO/T13CKI

OSC2/CLKOUT/RA6
OSC1/CLKIN/RA7
V

SS

VSS
VDD
VDD
RE2/CS/AN7
RE1/WR

/AN6

RE0/RD

/AN5

RA5/AN4/SS

/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

V

SS

VDD
VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10/C12IN3-

RB2/INT2/AN8

44-pin QFN

10
11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

RA3/AN3/VREF+/C1IN+

RA2/AN2/V

REF-/CVREF/C2IN+

RA1/AN1/C12IN1-

RA0/AN0/C12IN0-

MCLR

/VPP/RE3

NC

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

NC

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

(1)

NC

NC
RC0/T1OSO/T13CKI
OSC2/CLKOUT/RA6
OSC1/CLKIN/RA7
V

SS

VDD
RE2/CS/AN7
RE1/WR

/AN6

RE0/RD

/AN5

RA5/AN4/SS

/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

V

SS

VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10/C12IN3-

RB2/INT2/AN8

RB3/AN9/C12IN2-/CCP2

(1)

44-pin TQFP

PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20

PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20

Pin Diagrams (Cont.’d)

DS41303G-page 6  2010 Microchip Technology Inc.

T ABLE 1: PIC18F4XK20 PIN SUMMARY

PIC18F2XK20/4XK20

DIL Pin

TQFP Pin

2 19 19 RA0 AN0 C12IN0- — — — — — — — — —
3 20 20 RA1 AN1 C12IN1- ———————— —

4 21 21 RA2 AN2 C2IN+ VREF-/

5 22 22 RA3 AN3 C1IN+ VREF+ ——————— —
6 23 23 RA4 C1OUT — — — — T0CKI — — — —

7 24 24 RA5 AN4 C2OUT HLVDIN

14 31 33 RA6 — — — — — — — — — — OSC2/

13 30 32 RA7
33 8 9 RB0 AN12 — — FLT0 — — — — INT0 Yes —
34 9 10 RB1 AN10 C12IN3- ———— — —INT1 Yes —
35 10 11 RB2 AN8 — — — — — — — INT2 Ye s —
36 11 12 RB3 AN9 C12IN2- — CCP2
37 14 14 RB4 AN11 — — — — — — — KBI0 Ye s —
38 15 15 RB5 ————————KBI1 Yes PGM
39 16 16 RB6 — — — — — — — — KBI2 Ye s PGC

40 17 17 RB7
15 32 34 RC0 — — — — — — T1OSO/

16 35 35 RC1 ———CCP2
17 36 36 RC2 — — — CCP1/

18 37 37 RC3 —————SCK/

23 42 42 RC4 — — — — — SDI/

24 43 43 RC5 —————SDO — ——— —
25 44 44 RC6 — — — — TX/CK — — — — — —
26 1 1 RC7 ————RX/DT ————— —
19 38 38 RD0 — — — — — — — PSP0 — — —
20 39 39 RD1 ———————PSP1 —— —
21 40 40 RD2 — — — — — — — PSP2 — — —
22 41 41 RD3 ———————PSP3 —— —
27 2 2 RD4 — — — — — — — PSP4 — — —
28 3 3 RD5 ———P1B —— —PSP5 —— —
29 4 4 RD6 — — — P1C — — — PSP6 — — —
30 5 5 RD7 ———P1D —— —PSP7 —— —

8 25 25 RE0 AN5

9 26 26 RE1 AN6

10 27 27 RE2 AN7

11818RE3

11 7 7 — — — — — — — — — — — VDD
32 28 28 — — —————— ——— VDD
12 6 6 — — — — — — — — — — — VSS
31 29 30 — — —————— ——— VSS

– NC 8 — — — — — — — — — — — VDD
–NC29 — — ————————— VDD

–- NC 31 — — — — — — — — — — — VSS

Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0

2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only.

I/O

QFN Pin

(3)

Analog

Comparator

CV

Reference

REF

— —————————OSC1/CLKIN

————————KBI3 Yes PGD

— — — — — —
——————
— — — — — —

— —————————

ECCP

EUSART

MSSP

Timers

— — — — — — — —

——

(1)

—— — — — Ye s —

(2)

——T1OSI ——— —

P1A

— — — — — — —

SS

———— —

T13CKI

———— —

SCL

— — — — —

SDA

Slave

Interrupts

Pull-up

CLKOUT

— — — —

RD

WR

CS

— — —
—— —
— — —

MCLR/VPP

Basic

 2010 Microchip Technology Inc. DS41303G-page 7

PIC18F2XK20/4XK20

TABLE 2: PIC18F2XK20 PIN SUMMARY

Pin DIL

2 27 RA0 AN0 C12IN0-

3 28 RA1 AN1 C12IN1-

4 1 RA2 AN2 C2IN+ VREF-/

5 2 RA3 AN3 C1IN+ VREF+

6 3 RA4 C1OUT T0CKI

7 4 RA5 AN4 C2OUT HLVDIN

10 7 RA6 OSC2/

9 6 RA7 OSC1/

21 18 RB0 AN12 FLT0 INT0 Yes

22 19 RB1 AN10 C12IN3- P1C INT1 Yes

23 20 RB2 AN8 P1B INT2 Yes

24 21 RB3 AN9 C12IN2- CCP2

25 22 RB4 AN11 P1D KBI0 Yes

26 23 RB5 KBI1 Yes PGM

27 24 RB6 KBI2 Yes PGC

28 25 RB7 KBI3 Yes PGD

11 8 RC0 T1OSO/

12 9 RC1 CCP2

13 10 RC2 CCP1/

14 11 RC3 SCK/

15 12 RC4 SDI/

16 13 RC5 SDO

17 14 RC6 TX/CK

18 15 RC7 RX/DT

126RE3

8 5 VSS

19 16 VSS

20 17 VDD

Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0

2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only

I/O

Pin QUAD

Analog

(3)

Comparator

CV

Reference

REF

P1A

ECCP

(1)

(2)

EUSART

SS

SCL

SDA

MSSP

Timers

T13CKI

T1OSI

Slave

Interrupts

Pull-up

CLKOUT

CLKIN

Yes

MCLR/

V

Basic

PP

DS41303G-page 8  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

Table of Contents

1.0 Device Overview ....................................................................................................................................................................... 11

2.0 Oscillator Module (With Fail-Safe Clock Monitor)...................................................................................................................... 27

3.0 Power-Managed Modes ............................................................................................................................................................ 43

4.0 Reset......................................................................................................................................................................................... 51

5.0 Memory Organization ................................................................................................................................................................ 65

6.0 Flash Program Memory............................................................................................................................................................. 89

7.0 Data EEPROM Memory............................................................................................................................................................ 99

8.0 8 x 8 Hardware Multiplier......................................................................................................................................................... 105

9.0 Interrupts................................................................................................................................................................................. 107

10.0 I/O Ports .................................................................................................................................................................................. 121

11.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................ 143

12.0 Timer0 Module ........................................................................................................................................................................ 155

13.0 Timer1 Module ........................................................................................................................................................................ 159

14.0 Timer2 Module ........................................................................................................................................................................ 167

15.0 Timer3 Module ........................................................................................................................................................................ 169

16.0 Enhanced Capture/Compare/PWM (ECCP) Module............................................................................................................... 173

17.0 Master Synchronous Serial Port (MSSP) Module ................................................................................................................... 193

18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................................................. 237

19.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 265

20.0 Comparator Module................................................................................................................................................................. 279

21.0 Voltage References ................................................................................................................................................................. 289

22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................ 293

23.0 Special Features of the CPU................................................................................................................................................... 299

24.0 Instruction Set Summary......................................................................................................................................................... 315

25.0 Development Support.............................................................................................................................................................. 365

26.0 Electrical Characteristics......................................................................................................................................................... 369

27.0 DC and AC Characteristics Graphs and Tables...................................................................................................................... 403

28.0 Packaging Information............................................................................................................................................................. 427

Appendix A: Revision History............................................................................................................................................................ 441

Appendix B: Device Differences ....................................................................................................................................................... 442

Index ................................................................................................................................................................................................. 443

The Microchip Web Site.................................................................................................................................................................... 453

Customer Change Notification Service ............................................................................................................................................. 453

Customer Support ............................................................................................................................................................................. 453

Reader Response ............................................................................................................................................................................. 454

Product Identification System ........................................................................................................................................................... 455

 2010 Microchip Technology Inc. DS41303G-page 9

PIC18F2XK20/4XK20

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: [phone]
When contacting a sales office or t he literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Notification System

Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.

DS41303G-page 10  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

1.0 DEVICE OVERVIEW

This document contains device specific information for
the following devices:

• PIC18F23K20 • PIC18F43K20

• PIC18F24K20 • PIC18F44K20

• PIC18F25K20 • PIC18F45K20

• PIC18F26K20 • PIC18F46K20

This fam ily of fers th e ad vantages of a ll PI C18
microcontrollers – na mely, hig h computational
performance at an economical price – with the addition
of high-endurance, Flash program memory. On top of
these fea tures, the PIC18F2XK20/4XK20 fam ily
introduces d esign en hancements t hat make t hese
microcontrollers a log ical ch oice for many hig h­performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of t he devices in the PIC18F2XK20/4XK20 family
incorporate a ra nge o f features that c an s ignificantly
reduce power c onsumption d uring operation. Ke y
items include:

• Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.

• On-the-fly Mode Switching: The power-

managed modes are invoked by user code during
operation, allowing the user to incorporate power­saving ideas into their application’s software
design.

• Low Consumption in Key Modules: The

power requirements for both Timer1 and the
Watchdog Timer are minimized. See

Section 26.0 “Electrical Characteristics”

for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of th e devices in the PIC18F2XK20/4XK20 family
offer ten d ifferent oscillator options, allowing us ers a
wide r ange o f ch oices in de veloping a pplication
hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same

pin options as the External Clock modes

• An internal oscillator block which contains a

16 MHz HFINTOSC oscillator and a 31 kHz
LFINTOSC oscillator which together provide 8
user selectable clock frequencies, from 31 kHz to
16 MHz. This option frees the two oscillator pins
for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and inter­nal oscillator modes, which allows clock speeds of
up to 64 MHz. Used with the internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 64 MHz – all without using
an external crystal or clock circuit.

Besides its availability as a cl ock so urce, the internal
oscillator block provides a stable reference source that
gives th e fam ily a dditional feat ures for ro bust
operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a refer­ence signal provided by the LFINTOSC. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
operation or a safe application shutdown.

• T wo-S pe ed Start-up: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

 2010 Microchip Technology Inc. DS41303G-page 11

PIC18F2XK20/4XK20

1.2 Other Special Features

• Memory Endurance: The Flash cells for both

program memory and data EEPROM are rated to
last for many thousands of erase/write cycles – up to
10K for program memory and 100K for EEPROM.
Data retention without refresh is conservatively
estimated to be greater than 40 years.

• Self-programmability: These devices can write

to their own program memory spaces under inter­nal software control. By using a bootloader rou­tine located in the protected Boot Block at the top
of program memory, it becomes possible to create
an application that can update itself in the field.

• Extended Instruction Set: The PIC18F2XK20/

4XK20 family introduces an optional extension to
the PIC18 instruction set, which adds 8 new
instructions and an Indexed Addressing mode.
This extension, enabled as a device configuration
option, has been specifically designed to optimize
re-entrant application code originally developed in
high-level languages, such as C.

• Enhanced CCP module: In PWM mode, this

module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include:

- Auto-Shutdown, for disabling PWM outputs
on interrupt or other select conditions

- Auto-Restart, to reactivate outputs once the
condition has cleared

- Output steering to selectively enable one or
more of 4 outputs to provide the PWM signal.

• Enhanced Addressable USART: This serial

communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the USART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).

• 10-bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This

enhanced version incorporates a 16-bit
postscaler, allowing an extended time-out range
that is stable across operating voltage and

temperature. See Section 26.0 “Electrical

Characteristics” for time-out periods.

1.3 Details on Individual Family Members

Devices in the PIC18F2XK20/4XK20 family are av ail­able in 28-pin and 40/44-pin packages. Block diagrams
for the tw o g roups are shown i n Fi gure 1-1 an d
Figure 1-2.

The devices are differentiated from each other in five
ways:

1. Flash program me mory (8 Kbytes for

PIC18F23K20/43K20 de vices, 16 Kbytes for
PIC18F24K20/44K20 de vices, 32 Kbytes for
PIC18F25K20/45K20 AN D 64 Kbytes for
PIC18F26K20/46K20).

2. A/D channels (11 for 28-pin devices, 14 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports on 28-pin devices,

5 bidirectional ports on 40/44-pin devices).

4. Parallel Sl ave Port (p resent only on 4 0/44-pin

devices).

All other features for devices in this family are identical.
These are summarized in Table 1-1.

The pinouts for all devices are listed in the pin summary
tables: Table 1 and Table 2, and I/O description tables:
Table 1-2 and Table 1-3.

DS41303G-page 12  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS41303G-page 13

TABLE 1-1: DEVICE FEATURES

Features PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20

Operating Frequency

Program Memory (Bytes) 8192 16384 32768 65536 8192 16384 32768 65536

Program Memory
(Instructions)

Data Memory (Bytes) 512 768 1536 3936 512 768 1536 3936

Data EEPROM Memory
(Bytes)

Interrupt Sources 19 19 19 19 20 20 20 20

I/O Ports A, B, C, (E)

Timers 4 4 44 44 44

Capture/Compare/PWM
Modules

Enhanced Capture/
Compare/PWM Modules

Serial Communications MSSP, Enhanced

Parallel Communica­tions (PSP)

10-bit Analog-to-Digital
Module

Resets (and Delays) POR, BOR, RESET

Programmable High/
Low-Voltage Detect

Programmable Brown­out Reset

Instruction Set 75 Instructions; 83

Packages 28-pin PDIP

Note 1: PORTE contains the single RE3 read-only bit. The LATE and TRISE registers are not implemented.

2: Frequency range shown applies to industrial range devices only. Maximum frequency for extended range devices is 48 MHz.

(2)

DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz

USART

1 internal plus 10

Input Channels

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

MCLR

with Extended
Instruction Set

enabled

28-pin SOIC

28-pin QFN
28-pin SSOP
28-pin UQFN

4096 8192 16384 32768 4096 8192 16384 32768

256 256 256 1024 256 256 256 1024

(1)

11111111

1 1 11 11 11

No No No No Yes Yes Yes Yes

(optional),

WDT

Yes Ye s Yes Ye s Yes Ye s Ye s Yes

Yes Ye s Yes Ye s Yes Ye s Ye s Yes

A, B, C, (E)

MSSP, Enhanced

1 internal plus 10

Input Channels

POR, BOR, RESET

Instruction, Stack
Full, Stack Underflow
(PWRT, OST), MCLR

(optional), WDT

75 Instructions; 83

with Extended

Instruction Set

28-pin PDIP

28-pin SOIC

28-pin QFN

28-pin SSOP

USART

enabled

(1)

MSSP, Enhanced

1 internal plus 10

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

75 Instructions; 83

A, B, C, (E)

USART

Input Channels

(PWRT, OST),

MCLR

(optional),

WDT

with Extended
Instruction Set

enabled

28-pin PDIP
28-pin SOIC
28-pin QFN

28-pin SSOP

(1)

MSSP, Enhanced

1 internal plus 10

POR, BOR, RESET

Instruction, Stack
Full, Stack Underflow
(PWRT, OST), MCLR

75 Instructions; 83

A, B, C, (E)

Input Channels

(optional), WDT

with Extended
Instruction Set

28-pin PDIP
28-pin SOIC

28-pin QFN

28-pin SSOP

(1)

USART

enabled

A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E

MSSP, Enhanced

USART

1 internal plus 13

Input Channels

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

MCLR

(optional),

WDT

75 Instructions; 83

with Extended

Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

MSSP, Enhanced

USART

1 internal plus 13

Input Channels

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

MCLR

(optional),

WDT

75 Instructions; 83

with Extended
Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

MSSP, Enhanced

USART

1 internal plus 13

Input Channels

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

MCLR

(optional),

WDT

75 Instructions; 83

with Extended
Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

POR, BOR, RESET

Full, Stack Underflow
(PWRT, OST), MCLR

MSSP, Enhanced

USART

1 internal plus 13

Input Channels

Instruction, Stack

(optional), WDT

75 Instructions; 83

with Extended
Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20

Instruction

Decode and

Control

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT
RA5/AN4/SS

/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

(1)

RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10/C12IN3-

Data Latch

Data Memory

Address Latch

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

20

8

8

Table Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

ROM Latch

RB2/INT2/AN8
RB3/AN9/CCP2

(1)

/C12IN2-

PCLATU

PCU

OSC2/CLKOUT

(3)

/RA6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

functionality is disabled.

3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.

RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

EUSARTComparator

MSSP

10-bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR

Data

EEPROM

W

Instruction Bus <16>

STKPTR

Bank

8

State machine
control signals

Decode

8

8

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

V

SS

MCLR

(2)

Block

LFINTOSC

Oscillator

16 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

T1OSO

OSC1/CLKIN

(3)

/RA7

T1OSI

PORTE

MCLR/VPP/RE3

(2)

FVR

FVR

FVR

CVREF

Address Latch

Program Memory

(8/16/32/64 Kbytes)

Data Latch

FIGURE 1-1: PIC18F2XK20 (28-PIN) BLOCK DIAGRAM

DS41303G-page 14  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

Instruction

Decode and

Control

Data Latch

Data Memory

Address Latch

Data Address<12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

Address Latch

Program Memory

(8/16/32/64 Kbytes)

Data Latch

20

8

8

Table Pointer<21>

inc/dec logic

21

Data Bus<8>

Table Latch

8

IR

12

3

ROM Latch

PORTD

RD0/PSP0

PCU

PORTE

MCLR/VPP/RE3

(2)

RE2/CS/AN7

RE0/RD/AN5
RE1/WR/AN6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

functionality is disabled.

3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.

EUSARTComparator

MSSP

10-bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR

Data

EEPROM

W

Instruction Bus <16>

STKPTR

Bank

8

State machine
control signals

Decode

8

8

Power-up

Time r

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Time r

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

V

SS

MCLR

(2)

Block

LFINTOSC

Oscillator

16 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

RD1/PSP1
RD2/PSP2
RD3/PSP3

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT
RA5/AN4/SS

/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A
RC3/SCK/SCL

RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10/C12IN3­RB2/INT2/AN8
RB3/AN9/CCP2

(1)

/C12IN2-

OSC2/CLKOUT

(3)

/RA6

RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

OSC1/CLKIN

(3)

/RA7

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

FVR

FVR

PSP

FVR

CVREF

PCLATH

8

8

PCLATU

FIGURE 1-2: PIC18F4XK20 (40/44-PIN) BLOCK DIAGRAM

 2010 Microchip Technology Inc. DS41303G-page 15

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

MCLR

/VPP/RE3
MCLR
VPP
RE3

OSC1/CLKIN/RA7

OSC1

CLKIN

RA7

OSC2/CLKOUT/RA6

OSC2

CLKOUT

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,
SOIC

126

96

10 7

QFN

Pin

Type

I

P

I

I

I

I/O

O

O

I/O

Buffer

Type

ST

ST

ST

CMOS

TTL

—

—

TTL

Description

Master Clear (input) or programming voltage (input)

Active-low Master Clear (device Reset) input
Programming voltage input
Digital input

Oscillator crystal or external clock input

Oscillator crystal input or external clock source input
ST buffer when configured in RC mode; CMOS otherwise
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT
pins)
General purpose I/O pin

Oscillator crystal or clock output

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate
General purpose I/O pin

DS41303G-page 16  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0/C12IN0-

RA0
AN0
C12IN0-

RA1/AN1/C12IN1-

RA1
AN1
C12IN1-

RA2/AN2/V
C2IN+

RA2
AN2
V
CV
C2IN+

RA3/AN3/V

RA3
AN3
V
C1IN+

RA4/T0CKI/C1OUT

RA4
T0CKI
C1OUT

RA5/AN4/SS
C2OUT

RA5
AN4
SS
HLVDIN
C2OUT

RA6 See the OSC2/CLKOUT/RA6 pin

RA7 See the OSC1/CLKIN/RA7 pin

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

REF-/CVREF/

REF-

REF

REF+/C1IN+

REF+

/HLVDIN/

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,
SOIC

QFN

227

328

41

52

63

74

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

O

I

I/O

I
I
I

I/O

I

O

I/O

I
I
I

O

Buffer

Type

TTL
Analog
Analog

TTL
Analog
Analog

TTL
Analog
Analog
Analog
Analog

TTL
Analog
Analog
Analog

ST
ST

CMOS

TTL
Analog

TTL
Analog

CMOS

Description

PORTA is a bidirectional I/O port.

Digital I/O
Analog input 0, ADC channel 0
Comparators C1 and C2 inverting input

Digital I/O
ADC input 1, ADC channel 1
Comparators C1 and C2 inverting input

Digital I/O
Analog input 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input

Digital I/O
Analog input 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input

Digital I/O
Timer0 external clock input
Comparator C1 output

Digital I/O
Analog input 4, ADC channel 4
SPI slave select input
High/Low-Voltage Detect input
Comparator C2 output

 2010 Microchip Technology Inc. DS41303G-page 17

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/INT0/FLT0/AN12

RB0
INT0
FLT0
AN12

RB1/INT1/AN10/C12IN3­/P1C

RB1
INT1
AN10
C12IN3­P1C

RB2/INT2/AN8/P1B

RB2
INT2
AN8
P1B

RB3/AN9/C12IN2-/CCP2

RB3
AN9
C12IN2-

(2)

CCP2

RB4/KBI0/AN11/P1D

RB4
KBI0
AN11
P1D

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,
SOIC

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Pin

Type

I/O

I
I
I

I/O

I
I
I

O

I/O

I
I

O

I/O

I
I

I/O

I/O

I
I

O

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

Buffer

Type

TTL

ST
ST

Analog

TTL

ST
Analog
Analog
CMOS

TTL

ST
Analog
CMOS

TTL
Analog
Analog

ST

TTL

TTL
Analog
CMOS

TTL

TTL

ST

TTL

TTL

ST

TTL

TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on each input.

Digital I/O
External interrupt 0
PWM Fault input for CCP1
Analog input 12, ADC channel 12

Digital I/O
External interrupt 1
Analog input 10, ADC channel 10
Comparators C1 and C2 inverting input
Enhanced CCP1 PWM output

Digital I/O
External interrupt 2
Analog input 8, ADC channel 8
Enhanced CCP1 PWM output

Digital I/O
Analog input 9, ADC channel 9
Comparators C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2 output

Digital I/O
Interrupt-on-change pin
Analog input 11, ADC channel 11
Enhanced CCP1 PWM output

Digital I/O
Interrupt-on-change pin
Low-Voltage ICSP™ Programming enable pin

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming clock pin

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming data pin

DS41303G-page 18  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(1)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

RE3 — — — — See MCLR

V

SS 8, 19 5, 16 P — Ground reference for logic and I/O pins

DD 20 17 P — Positive supply for logic and I/O pins

V

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,
SOIC

11 8

12 9

13 10

14 11

15 12

16 13

17 14

18 15

QFN

Pin

Buffer

Type

Type

I/O

O

I

I/O

I

Analog

I/O

I/O
I/O

O

CMOS

I/O
I/O
I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

PORTC is a bidirectional I/O port.

ST

—

ST

ST

ST

ST
ST

ST
ST
ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Digital I/O
Timer1 oscillator output
Timer1/Timer3 external clock input

Digital I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2 output

Digital I/O
Capture 1 input/Compare 1 output
Enhanced CCP1 PWM output

Digital I/O
Synchronous serial clock input/output for SPI mode
Synchronous serial clock input/output for I

Digital I/O
SPI data in

2

C™ data I/O

I

Digital I/O
SPI data out

Digital I/O
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)

Digital I/O
EUSART asynchronous receive
EUSART synchronous data (see related TX/CK)

/VPP/RE3 pin

Description

2

C™ mode

 2010 Microchip Technology Inc. DS41303G-page 19

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS

Pin Name

/VPP/RE3

MCLR

MCLR
VPP
RE3

OSC1/CLKIN/RA7

OSC1

CLKIN

RA7

OSC2/CLKOUT/RA6

OSC2

CLKOUT

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

11818

13 32 30

14 33 31

Pin

Type

I

P

I

I

I

I/O

O

O

I/O

Buffer

Type

ST

ST

ST

CMOS

TTL

—

—

TTL

Description

Master Clear (input) or programming voltage (input)

Active-low Master Clear (device Reset) input
Programming voltage input
Digital input

Oscillator crystal or external clock input

Oscillator crystal input or external clock source input
ST buffer when configured in RC mode;
analog otherwise
External clock source input. Always associated with
pin function OSC1 (See related OSC1/CLKIN,
OSC2/CLKOUT pins)
General purpose I/O pin

Oscillator crystal or clock output

Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate
General purpose I/O pin

DS41303G-page 20  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0/C12IN0-

RA0
AN0
C12IN0-

RA1/AN1/C12IN0-

RA1
AN1
C12IN0-

RA2/AN2/V
C2IN+

RA3/AN3/V
C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS
C2OUT

RA6 See the OSC2/CLKOUT/RA6 pin

RA7 See the OSC1/CLKIN/RA7 pin

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

REF-/CVREF/

RA2
AN2

REF-

V

REF

CV
C2IN+

REF+/

RA3
AN3
VREF+
C1IN+

RA4
T0CKI
C1OUT

/HLVDIN/

RA5
AN4
SS
HLVDIN
C2OUT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

21919

32020

42121

52222

62323

72424

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

O

I

I/O

I
I
I

I/O

I

O

I/O

I
I
I

O

Buffer

Type

TTL
Analog
Analog

TTL
Analog
Analog

TTL
Analog
Analog
Analog
Analog

TTL
Analog
Analog
Analog

ST
ST

CMOS

TTL
Analog

TTL
Analog
CMOS

Description

PORTA is a bidirectional I/O port.

Digital I/O
Analog input 0, ADC channel 0
Comparator C1 and C2 inverting input

Digital I/O
Analog input 1, ADC channel 1
Comparator C1 and C2 inverting input

Digital I/O
Analog input 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input

Digital I/O
Analog input 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input

Digital I/O
Timer0 external clock input
Comparator C1 output

Digital I/O
Analog input 4, ADC channel 4
SPI slave select input
High/Low-Voltage Detect input
Comparator C2 output

 2010 Microchip Technology Inc. DS41303G-page 21

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0/AN12

RB0
INT0
FLT0
AN12

RB1/INT1/AN10/
C12IN3-

RB1
INT1
AN10
C12IN3-

RB2/INT2/AN8

RB2
INT2
AN8

RB3/AN9/C12IN2-/
CCP2

RB3
AN9
C12IN23-

(2)

CCP2

RB4/KBI0/AN11

RB4
KBI0
AN11

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Type

I/O

I
I
I

I/O

I
I
I

I/O

I
I

I/O

I
I

I/O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

Buffer

Type

TTL

ST
ST

Analog

TTL

ST
Analog
Analog

TTL

ST
Analog

TTL
Analog
Analog

ST

TTL

TTL
Analog

TTL

TTL

ST

TTL

TTL

ST

TTL

TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on
each input.

Digital I/O
External interrupt 0
PWM Fault input for Enhanced CCP1
Analog input 12, ADC channel 12

Digital I/O
External interrupt 1
Analog input 10, ADC channel 10
Comparator C1 and C2 inverting input

Digital I/O
External interrupt 2
Analog input 8, ADC channel 8

Digital I/O
Analog input 9, ADC channel 9
Comparator C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2 output

Digital I/O
Interrupt-on-change pin
Analog input 11, ADC channel 11

Digital I/O
Interrupt-on-change pin
Low-Voltage ICSP™ Programming enable pin

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming
clock pin

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming
data pin

DS41303G-page 22  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(1)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK

SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

15 34 32

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Buffer

Type

I/O

O

I

I/O

I

CMOS

I/O

I/O
I/O

O

I/O
I/O

I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

Type

PORTC is a bidirectional I/O port.

ST

—

ST

ST

ST

ST
ST

—

ST
ST

ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Digital I/O
Timer1 oscillator output
Timer1/Timer3 external clock input

Digital I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2 output

Digital I/O
Capture 1 input/Compare 1 output/PWM 1 output
Enhanced CCP1 output

Digital I/O
Synchronous serial clock input/output for
SPI mode
Synchronous serial clock input/output for I

Digital I/O
SPI data in

2

C™ data I/O

I

Digital I/O
SPI data out

Digital I/O
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)

Digital I/O
EUSART asynchronous receive
EUSART synchronous data (see related TX/CK)

Description

2

C™ mode

 2010 Microchip Technology Inc. DS41303G-page 23

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/PSP0

RD0
PSP0

RD1/PSP1

RD1
PSP1

RD2/PSP2

RD2
PSP2

RD3/PSP3

RD3
PSP3

RD4/PSP4

RD4
PSP4

RD5/PSP5/P1B

RD5
PSP5
P1B

RD6/PSP6/P1C

RD6
PSP6
P1C

RD7/PSP7/P1D

RD7
PSP7
P1D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Buffer

Type

Type

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/O

TTL

O

I/O
I/O

TTL

O

I/O
I/O

TTL

O

Description

PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

ST

—

ST

—

ST

—

Digital I/O
Parallel Slave Port data
Enhanced CCP1 output

Digital I/O
Parallel Slave Port data
Enhanced CCP1 output

Digital I/O
Parallel Slave Port data
Enhanced CCP1 output

DS41303G-page 24  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/RD

RE1/WR/AN6

RE2/CS/AN7

RE3 — — — — — See MCLR

VSS 12, 31 6, 30, 316, 29 P — Ground reference for logic and I/O pins

/AN5
RE0
RD

AN5

RE1
WR

AN6

RE2
CS

AN7

Pin Number

PDIP QFN TQFP

82525

92626

10 27 27

Pin

Type

I/O

I

I

I/O

I

I

I/O

I

I

Buffer

Type

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

Description

PORTE is a bidirectional I/O port

Digital I/O
Read control for Parallel Slave Port
(see related WR
Analog input 5, ADC channel 5

Digital I/O
Write control for Parallel Slave Port
(see related CS
Analog input 6, ADC channel 6

Digital I/O
Chip Select control for Parallel Slave Port
(see related RD
Analog input 7, ADC channel 7

/VPP/RE3 pin

and CS pins)

and RD pins)

and WR)

V

DD 11, 32 7, 8,

28, 29

NC — 13 12, 13,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

7, 28 P — Positive supply for logic and I/O pins

— — No connect

33, 34

 2010 Microchip Technology Inc. DS41303G-page 25

PIC18F2XK20/4XK20

NOTES:

DS41303G-page 26  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

4 x PLL

FOSC<3:0>

Secondary Oscillator

T1OSCEN
Enable
Oscillator

T1OSO

T1OSI

Clock Source Option
for other Modules

OSC1

OSC2

Sleep

HSPLL, HFINTOSC/PLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

Postscaler

MUX

MUX

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

250 kHz

500 kHz

OSCCON<6:4>

111
110
101
100

011
010
001
000

31 kHz

31 kHz
Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

16 MHz

Internal Oscillator

(HFINTOSC)

Clock

Control

OSCCON<1:0>

Source

16 MHz

31 kHz (LFINTOSC)

OSCTUNE<6>

(1)

0

1

OSCTUNE<7>

and Two-Speed Start-up

Primary Oscillator

PIC18F2XK20/4XK20

Sleep

Sleep

Main

FOSC<3:0> O SCCON<1:0>

Note 1: Operates only when HFINTOSC is the primary oscillator.

2.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

2.1 Overview

The O scillator m odule has a wide va riety o f cl ock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor­mance and minimizing power consumption. Figure 2-1
illustrates a block diagram of the Oscillator module.

Clock sources ca n be con figured from external
oscillators, quartz crystal resonators, ceramic resonators
and R esistor-Capacitor (R C) c ircuits. In a ddition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable via
software. Additional clock features include:

• Selectable system clock source between external

or internal via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and
code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.

The Oscillator module can be configured in one of ten
primary clock modes.

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator
with PLL enabled

5. RC External Resistor/Capacitor with

OSC/4 output on RA6

F

6. RCIO External Resistor/Capacitor with I/O
on RA6

7. INTOSC Internal Oscillator with F

OSC/4

output on RA6 and I/O on RA7

8. INTOSCIO Internal Oscillator with I/O on RA6
and RA7

9. EC External Clock with F

OSC/4 output

10. ECIO External Clock with I/O on RA6

Primary Clock modes are selected by the FOSC<3:0>
bits of t he CONFIG1H C onfiguration R egister. T he
HFINTOSC and LFINTOSC are factory calibrated high­frequency and low-frequency oscillators, respectively,
which are used as the internal clock sources.

FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

 2010 Microchip Technology Inc. DS41303G-page 27

PIC18F2XK20/4XK20

2.2 Oscillator Control

The OSCCON register (Register 2-1) controls several
aspects o f the dev ice c lock’s op eration, bo th in ful l
power operation and in power-managed modes.

• Main System Clock Selection (SCS)

• Internal Frequency selection bits (IRCF)

• Clock Status bits (OSTS, IOFS)

• Power management selection (IDLEN)

2.2.1 MAIN SYSTEM CLOCK SELECTION

The Sy stem Cloc k Se lect b its, SCS<1 :0>, s elect th e
main clock source. The available clock sources are

• Primary clock defined by the FOSC<3:0> bits of
CONFIG1H. The primary clock can be the primary
oscillator, an external clock, or the internal oscilla­tor block.

• Secondary clock (Timer1 oscillator)

• Internal oscillator block (HFINTOSC and
LFINTOSC).

The c lock s ource cha nges i mmediately af ter one or
more of the bits is written to, following a brief clock tran­sition interval. The SCS bits are cl eared to sel ect the
primary clock on all forms of Reset.

2.2.4 CLOCK STATUS

The OSTS and IOFS bits of the OSCCON register, and
the T1RUN bit of the T1CON register, indicate which
clock source is currently providing the main clock. The
OSTS b it i ndicates th at th e O scillator S tart-up T imer
has timed out and the primary clock is p roviding the
device clock. The IOFS bit indicates when the internal
oscillator b lock has stabilized a nd is p roviding th e
device cl ock i n H FINTOSC C lock m odes. The IO FS
and O STS S tatus bit s w ill bo th b e s et w hen
SCS<1:0> = 00 and HFINTOSC is the primary clock.
The T1RUN bit indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes.
When SCS<1:0>  00, only one of these three bits will
be set at any time. If none of the se bits are set, th e
LFINTOSC is providing the clock or the H FINTOSC
has just started and is not yet stable.

2.2.5 POWER MANAGEMENT

The IDLEN bit of the OSCCON register determines if
the d evice go es into Sle ep mode o r on e of the Idl e
modes when the SLEEP instruction is executed.

The use of the flag and control bits in the OSCCON

register i s di scussed in m ore d etail in Section 3.0
“Power-Managed Modes”.

2.2.2 INTERNAL FREQUENCY

SELECTION

The Int ernal Os cillator Frequency Se lect bit s
(IRCF<2:0>) select the frequency output of the internal
oscillator block. The choices are the LFINTOSC source
(31 kHz), the HFINTOSC so urce (16 MHz) or one of
the freq uencies de rived from the H FINTOSC pos t­scaler (31 .25 kHz to 8 MHz). If the internal oscillator
block is supplying the main clock, changing the states
of th ese b its w ill ha ve an i mmediate c hange on th e
internal oscillator’s output. On device Resets, the out­put f requency of the in ternal oscillator is s et t o th e
default frequency of 1 MHz.

2.2.3 LOW FREQUENCY SELECTION

When a nominal output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose which internal
oscillator ac ts as th e s ource. Thi s i s done w ith th e
INTSRC bit of the OSCTUNE register. Setting this bit
selects the HFINTOSC as a 31.25 kHz clock source by
enabling the di vide-by-512 ou tput of the H FINTOSC
postscaler. Clearing INTSRC selects LFINTOSC (nom­inally 31 kHz) as the clock source.

This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while maintain­ing power savings with a very low clock speed. Regard­less of t he se tting of I NTSRC, LFINTOSC a lways
remains th e c lock source fo r fea tures s uch a s th e
Watchdog Timer and the Fail-Safe Clock Monitor.

Note 1: The Timer1 oscillator must be enabled to

select the secondary c lock so urce. Th e
Timer1 oscillator is enabled by setting the
T1OSCEN b it of the T1 CON re gister. If
the Timer1 oscillator is not enabled, then
the m ain osc illator w ill c ontinue to ru n
from the previously selected source. The
source will then switch to the secondary
oscillator after the T1OSCEN bit is set.

2: It i s rec ommended tha t the Timer1

oscillator be operating and stable before
selecting the secondary clock source or a
very lo ng delay ma y o ccur while th e
Timer1 oscillator starts.

DS41303G-page 28  2010 Microchip Technology Inc.

PIC18F2XK20/4XK20

REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0

IDLEN IRCF2 IRCF1 IRCF0 OSTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

111 = 16 MHz (HFINTOSC drives clock directly)
110 = 8 MHz
101 = 4 MHz
100 = 2 MHz
011 = 1 MHz
010 = 500 kHz
001 = 250 kHz
000 = 31 kHz (from either HFINTOSC/512 or LFINTOSC directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

bit 2 IOFS: HFINTOSC Frequency Stable bit

1 = HFINTOSC frequency is stable
0 = HFINTOSC frequency is not stable

bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block
01 = Secondary (Timer1) oscillator
00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]).

(3)

(1)

(1)

IOFS SCS1 SCS0

(2)

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit of the OSCTUNE register, see text.
3: Default output frequency of HFINTOSC on Reset.

 2010 Microchip Technology Inc. DS41303G-page 29

PIC18F2XK20/4XK20

OSC1/CLKIN

OSC2/CLKOUT

(1)

I/O

Clock from
Ext. System

PIC

®

MCU

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2.3 Clock Source Modes

Clock Source modes can be classified as external or
internal.

• External Clock modes rely on external circuitry for
the clock source. Examples are: Clock modules
(EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resistor­Capacitor (RC mode) circuits.

• Internal clock sources are contained internally
within the Oscillator block. The Oscillator block
has two internal oscillators: the 16 MHz High­Frequency Internal Oscillator (HFINTOSC) and
the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).

The system clock can be selected between external or
internal cl ock sources vi a the S ystem Cl ock S elect
(SCS<1:0>) b its o f the OSCCO N register. Se e

Section 2.9 “Clock Switching” for additional informa-

tion.

2.4 External Clock Modes

2.4.1 OSCILLATOR START-UP TIMER (OST)

When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from O SC1. Thi s occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is prov iding a stable system clo ck to the Oscillator
module. W hen swi tching be tween cl ock s ources, a
delay i s required to al low the new cl ock to s tabilize.
These oscillator delays are shown in Table 2-1.

In order to minimize latency between external oscillator
start-up a nd c ode ex ecution, the T wo-Speed C lock

Start-up mo de can be se lected (see Section 2.10

“Two-Speed Clock Start-up Mode”).

TABLE 2-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR

Sleep/POR EC, RC DC – 64 MHz 2 instruction cycles

LFINTOSC (31 kHz) EC, RC DC – 64 MHz 1 cycle of each

Sleep/POR LP, XT, HS 32 kHz to 40 MHz 1024 Clock Cycles (OST)

Sleep/POR HSPLL 32 MHz to 64 MHz 1024 Clock Cycles (OST) + 2 ms

LFINTOSC (31 kHz) HFINTOSC 250 kHz to 16 MHz 1 s (approx.)

LFINTOSC

HFINTOSC

31 kHz

250 kHz to 16 MHz

Oscillator Warm-Up Delay (T

WARM)

2.4.2 EC MODE

The Ext ernal C lock ( EC) mode al lows an ext ernally
generated logic level as the system clock source. When
operating in this mode , a n ext ernal clock sour ce is
connected to the OSC1 input and the OSC2 is available
for ge neral p urpose I /O. Fig ure 2-2 s hows th e pi n
connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation af ter a Power-on R eset (POR) or wake-up
from Sleep. B ecause t he PIC
static, sto pping t he external clock input w ill have the
effect of halting the device while leaving all data intact.
Upon res tarting the external cl ock, th e dev ice w ill
resume operation as if no time had elapsed.

DS41303G-page 30  2010 Microchip Technology Inc.

®

MCU de sign is fully

FIGURE 2-2: EXTERNAL CLOCK (EC)

MODE OPERATION