Datasheet PIC18F23K20, PIC18F24K20, PIC18F25K20, PIC18F26K20, PIC18F43K20 Datasheet

PIC18F2XK20/4XK20

28/40/44-Pin Flash Microcontrollers

with XLP Technology

High-Performance RISC CPU

• C Compiler Optimized Architecture:

- Optional extended in struct ion set designed to
optimize re-entrant code

• Up to 1024 bytes Data EEPROM

• Up to 64 Kbytes Linear Program Memory
Addressing

• Up to 3936 bytes Lin ear Data Mem ory Addressin g

• Up to 16 MIPS Operation

• 16-bit Wide Instructions, 8-bit Wide Data Path

• Priority Levels for Interrupts

• 31-Level, Software Accessible Hardware Stack

• 8 x 8 Single-Cycle Hardware Multiplier

Flexible Oscillator Struc ture

• Precision 16 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%

- Software selectable frequencies range of

31 kHz to 16 MHz

- 64 MHz performance available using PLL –

no external components required

• Four Crystal Modes up to 64 MHz

• Two External Clock Modes up to 64 MHz

• 4X Phase Lock Loop (PLL)

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown, if peripheral clock

stops

- Two-Speed Oscillator Start-up

Special Microcontroller Features

• Operating Voltage Range: 1.8V to 3.6V

• Self-Programmable under Software Control

• Programmable 16-Level High/Low-Voltage
Detection (HLVD) module:

- Interrupt on High/Low-Voltage Detection

• Programmable Brown-out Reset (BOR):

- With software enable option

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single-Supply 3V In-Circuit Serial
Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

Extreme Low-Power Management with XLP

• Sleep Mode: < 100 nA @ 1.8V

• Watchdog Timer: < 800 nA @ 1.8V

• Timer1 Oscillator: < 800 nA @ 32 kHz and 1.8V

Analog Features

• Analog-to-Digital Converter (ADC) Module:

- 10-bit resolution, 13 External Channels

- Auto-acquisition capability

- Conversion available during Sleep

- 1.2V Fixed Voltage Reference (FVR) channel

- Independent input multiplexing

• Analog Comparator Module:

- Two rail-to-rail analog comparators

- Independent input multiplexing

• Volt a ge Refere nc e (CV

- Programmable (% VDD), 16 steps

- Two 16-level voltage ranges using V

REF) Module

REF pins

Peripheral Highlight s

• Up to 35 I/O Pins plus 1 Input-only Pin:

- High-Current Sink/Source 25 mA/25 mA

- Three programmable external interrupts

- Four pr ogrammable interrupt-on-change

- Eight programmable weak pull-ups

- Programmable slew rate

• Capture/Compare/PWM (CCP) Module

• Enhanced CCP (ECCP) module:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Master Synchronous Serial Port (MSSP) Module

- 3-wire SPI (supports all four modes)

2

-I

C™ Master and Slave modes with address

mask

• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) Module:

- Supports RS-485, RS-232 and LIN

- RS-232 operation using internal oscillator

- Auto-Wake-up on Break

- Auto-Baud Detect

 2010-2015 Microchip Technology Inc. DS40001303H-page 1

PIC18F2XK20/4XK20

-

PIC18F2XK20/4XK20 Family Types

Program Memory Data Memory

Device

PIC18F23K20 8K 4096 512 256 25 11 1/1 Y Y 1 2 1/3
PIC18F24K20 16K 8192 768 256 25 11 1/1 Y Y 1 2 1/3
PIC18F25K20 32K 16384 1536 256 25 11 1/1 Y Y 1 2 1/3
PIC18F26K20 64k 32768 3936 1024 25 11 1/1 Y Y 1 2 1/3
PIC18F43K20 8K 4096 512 256 36 14 1/1 Y Y 1 2 1/3
PIC18F44K20 16K 8192 768 256 36 14 1/1 Y Y 1 2 1/3
PIC18F45K20 32K 16384 1536 256 36 14 1/1 Y Y 1 2 1/3
PIC18F46K20 64k 32768 3936 1024 36 14 1/1 Y Y 1 2 1/3

Note 1: One pin is input-only.

2: Channel count includes internal Fixed Voltage Reference channel.

Flash

(bytes)

# Single-Word

Instructions

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-bit

(1)

A/D

(ch)

CCP/

ECCP

(2)

(PWM)

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

SPI

MSSP

Master

2

I

C™

Comp.

EUSART

Timers

8/16-bit

DS40001303H-page 2  2010-2015 Microchip Technology Inc.

Pin Diagrams

10
11

2
3
4
5
6

1

8

7

9

12
13
14

15

16

17

18

19

20

23

24

25

26

27

28

22
21

MCLR/VPP/RE3
AN0/C12IN0-/RA0
AN1/C12IN1-/RA1

AN2/V

REF-/CVREF/C2IN+/RA2

AN3/V

REF+/C1IN+/RA3

T0CKI/C1OUT/RA4

AN4/SS

/HLVDIN/C2OUT/RA5

V

SS

OSC1/CLKIN/RA7

OSC2/CLKOUT/RA6
T1OSO/T13CKI/RC0

T1OSI/CCP2

(1)

/RC1

CCP1/P1A/RC2

SCK/SCL/RC3

RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11/P1D
RB3/AN9/C12IN2-/CCP2

(1)

RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

PIC18F23K20

PIC18F24K20

PIC18F25K20

PIC18F26K20

Note: See Table1 for pin allocation table.

1011

2
3

6

1

18

19

20

21

22

121314

15

8

7

16

17

232425262728

9

T1OSO/T13CKI/RC0

5

4

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11/P1D

RB3/AN9/C12IN2-/CCP2

(1)

RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
V

DD

VSS
RC7/RX/DT

TX/CK/RC6

SDO/RC5

SDI/SDA/RC4

RE3/

MCLR/VPP

RA0/AN0/C12IN0-

RA1/AN1/C12IN1-

AN2/VREF-/CVREF/C2IN+/RA2

AN3/V

REF+/C1IN+/RA3

T0CKI/C1OUT/RA4

AN4/SS

/HLVDIN/C2OUT/RA5

V

SS

OSC1/CLKIN/RA7

OSC2/CLKOUT/RA6

T1OSI/CCP2

(1)

/RC1

CCP1/P1A/RC2

SCK/SCL/RC3

PIC18F23K20
PIC18F24K20
PIC18F25K20
PIC18F26K20

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: UQFN package availability applies only to PIC18F23K20.
3: See Table 1 for pin allocation table.
4: The exposed pad should be connected to V

SS.

FIGURE 1: 28-PIN SPDIP, SOIC, SSOP

FIGURE 2: 28-PIN QFN/UQFN

PIC18F2XK20/4XK20

 2010-2015 Microchip Technology Inc. DS40001303H-page 3

PIC18F2XK20/4XK20

RB7/KBI3/PGD
RB6/KBI2/PGC

RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/C12IN2-/CCP2

(1)

RB2/INT2/AN8
RB1/INT1/AN10/C12IN3-

RB0/INT0/FLT0/AN12
V

DD

VSS
RD7/PSP7/P1D
RD6/PSP6/P1C

RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2

MCLR/VPP/RE3

AN0/C12IN0-/RA0
AN1/C12IN1-/RA1

AN2/V

REF-/CVREF/C2IN+/RA2

AN3/V

REF+/C1IN+/RA3

T0CKI/C1OUT/RA4

AN4/SS

/HLVDIN/C2OUT/RA5

R

D/AN5/RE0

W

R/AN6/RE1

C

S/AN7/RE2

V

DD

VSS

OSC1/CLKIN/RA7

OSC2/CLKOUT/RA6

T1OSO/T13CKI/RC0

T1OSI/CCP2

(1)

/RC1

CCP1/P1A/RC2

SCK/SCL/RC3

PSP0/RD0
PSP1/RD1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

PIC18F43K20

PIC18F44K20

PIC18F45K20

PIC18F46K20

Note: See Table 2 for pin allocation table.

10

11

2
3

4
5
6

1

18 19 20

21

22

12 13 14 15

38

8

7

40 39

16 17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

AN1/C12/IN1-/RA1

AN0/C12IN0-/RA0

M

CLR/VPP/RE3

AN9/C12IN2-/CCP/RB3

KBI3/PGD/RB7

KBI2/PGC/RB6

KBI1/PGM/RB5

KBI0/AN11/RB4

RC6/TX/Ck

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
V

SS

VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD

/AN5

RA5/AN4/SS

/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RX/DT/RC7

RD4/PSP4/RD4

PSP5/P1B/RD5

RD6/PSP6/P1C/RD6

PSP7/P1D/RD7

V

SS

VDD

INT0/FLT0/AN12/RB0

INT1/AN10/C12IN3-/RB1

INT2/AN8/RB2

AN3/VREF+/C1IN+/RA3

AN2/V

REF-/CVREF/C2IN+/RA2

PIC18F4XK20

Note 1: See Table 2 for location of all peripheral functions.

2: It is recommended that the exposed bottom pad be connected to V

SS.

FIGURE 3: 40-PIN PDIP

FIGURE 4: 40-PIN UQFN

DS40001303H-page 4  2010-2015 Microchip Technology Inc.

FIGURE 5: 44-PIN QFN

10
11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

AN3/V

REF+/C1IN+/RA3

AN2/V

REF-/CVREF/C2IN+/RA2

AN1/C12IN1-/RA1

AN0/C12IN0-/RA0

MCLR

/VPP/RE3

AN9/C12IN2-/CCP2

(1)

/RB3

KBI3/PGD/RB7

KBI2/PGC/RB6

KBI1/PGM/RB5

KBI0/AN11/RB4

NC

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

(1)

RC0/T1OSO/T13CKI

RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
V

SS

VSS
VDD
VDD
RE2/CS/AN7
RE1/WR

/AN6

RE0/RD

/AN5

RA5/AN4/SS

/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RX/DT/RC7

RD4/PSP4/RD4

PSP5/P1B/RD5
PSP6/P1C/RD6
PSP7/P1D/RD7

V

SS

VDD
VDD

INT0/FLT0/AN12/RB0

INT1/AN10/C12IN3-/RB1

INT2/AN8/RB2

PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: The exposed pad should be connected to V

SS.

3: See Table 2 for pin allocation table.

10
11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

AN3/VREF+/C1IN+/RA3

AN2/V

REF-/CVREF/C2IN+/RA2

AN1/C12IN1-/RA1

AN0/C12IN0-/RA0

MCLR

/VPP/RE3

NC

KBI3/PGD/RB7

KBI2/PGC/RB6

KBI1/PGM/RB5

KBI0/AN11/RB4

NC

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

(1)

NC

NC
RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
V

SS

VDD
RE2/CS/AN7
RE1/WR

/AN6

RE0/RD

/AN5

RA5/AN4/SS

/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RX/DT/RC7

PSP4/RD4

PSP6/P1C/RD6
PSP7/P1D/RD7

V

SS

VDD

INT0/FLT0/AN12/RB0

INT1/AN10/C12IN3-/RB1

INT2/AN8/RB2

AN9/C12IN2-/CCP2

(1)

/RB3

PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: See Table 2 for pin allocation table.

PSP5/P1B/RD5

PIC18F2XK20/4XK20

FIGURE 6: 44-PIN TQFP

 2010-2015 Microchip Technology Inc. DS40001303H-page 5

PIC18F2XK20/4XK20

Pin Allocation Tables

TABLE 1: 28-PIN ALLOCATION TABLE (PIC18F2XK20)

I/O

28-Pin SPDIP, SOIC, SSOP

RA0 2 27 AN0 C12IN0- — — — — — — — — —
RA1 3 28 AN1 C12IN1- — — — — — — — — —
RA2 4 1 AN2 C2IN+ V

RA3 5 2 AN3 C1IN+ VREF+ — — — — — — — —
RA4 6 3 — C1OUT — — — — T0CKI — — — —

RA5 7 4 AN4 C2OUT HLVDIN
RA6 10 7 — — — — — — — — — — OSC2/

RA7 9 6 — — — — — — — — — — OSC1/

RB0 21 18 AN12 — — FLT0 — — — — INT0 Yes —
RB1 22 19 AN10 C12IN3- — P1C — — — — INT1 Yes —
RB2 23 20 AN8 — — P1B — — — — INT2 Yes —
RB3 24 21 AN9 C12IN2- CCP2
RB4 25 22 AN11 — — P1D — — — — KBI0 Yes —
RB5 26 23 — — — — — — — — KBI1 Yes PGM
RB6 27 24 — — — — — — — — KBI2 Yes PGC
RB7 28 25 — — — — — — — — KBI3 Yes PGD
RC0 11 8 — — — — — — T1OSO/

RC1 12 9 — — — CCP2
RC2 13 10 — — — CCP1/

RC3 14 11 — — — — — SCK/

RC4 15 12 — — — — — SDI/

RC5 16 13 — — — — — SDO — — — — —
RC6 17 14 — — — — TX/CK — — — — — —
RC7 18 15 — — — — RX/DT — — — — — —

(3)

RE3

Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0

126

8 5 — — — — — — — — — — VSS
19 16 — — — — — — — — — — V SS
20 17 — — — — — — — — — — VDD

2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only

Analog

Comparator

28-Pin QFN/UQFN

—— ————————

CV

Reference

REF-/

REF

ECCP

——— ———— —

— —

(1)

(2)

P1A

EUSART

— — — — — Yes —

— — T1OSI — — — —
—— — ——— —

SS

SCL

SDA

MSSP

Timers

— — — — —

T13CKI

— — — — —

———— —

Slave

Interrupts

——— —

Pull-up

CLKOUT

CLKIN

MCLR

V

Basic

/

PP

DS40001303H-page 6  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18F4XK20)

I/O

40-Pin PDIP

RA0 2 17 19 19 AN0 C12IN0-— — — — — — — — —

RA1 3 18 20 20 AN1 C12IN1-———————— —

RA2 4 19 21 21 AN2 C2IN+ VREF-/

RA3 5 20 22 22 AN3 C1IN+ V
RA4 6 21 23 23 — C1OUT — — — — T0CKI — — — —

RA5 7 22 24 24 AN4 C2OUT HLVDIN
RA6 14 29 31 33 — — — — — — — — — — OSC2/

RA7 13 28 30 32 — — — — — — — — — — OSC1/

RB0 33 8 8 9 AN12 — — FLT0 — — — — INT0 Yes —
RB1 34 9 9 10 AN10 C12IN3-——————INT1Yes —

RB2 35 10 10 11 AN8 — — — — — — — INT2 Yes —
RB3 36 11 11 12 AN9 C12IN2-— CCP2

RB4 37 12 14 14 AN11 — — — — — — — KBI0 Yes —
RB5 38 13 15 15 — — — — — — — — KBI1 Yes PGM
RB6 39 14 16 16 — — — — — — — — KBI2 Yes PGC
RB7 40 15 17 17 — — — — — — — — KBI3 Yes PGD
RC0 15 30 32 34 — — — — — — T1OSO/

RC1 16 31 35 35 — — — CCP 2
RC2 17 32 36 36 — — — CCP1/

RC3 18 33 37 37 — — — — — SCK/

RC4 23 38 42 42 — — — — — SDI/

RC5 24 39 43 43 — — — — — SDO — — — — —
RC6 25 40 44 44 — — — — TX/CK— — — — — —

40-Pin UQFN

44-Pin TQFP

Analog

44-Pin QFN

Comp.

Reference

CV

REF

REF+— — — — — — — —

ECCP

— — — — — — — —

——

(1)

—— — — —Yes —

(2)

——T1OSI— — — —
— — — — — — —

P1A

EUSART

SS

SCL

SDA

MSSP

Timers

———— —

T13CKI

———— —

— — — — —

Slave

— — — —

Pull-up

Interrupts

CLKOUT

CLKIN

Basic

RC7 26 1 1 1 — — — — RX/DT————— —

RD0 19 34 38 38 — — — — — — — PSP0 — — —
RD1 20 35 39 39 — — — — — — — PSP1 — — —
RD2 21 36 40 40 — — — — — — — PSP2 — — —
RD3 22 37 41 41 — — — — — — — PSP3 — — —
RD4 27 2 2 2 — — — — — — — PSP4 — — —
RD5 28 3 3 3 — — — P1B — — — PSP5 — — —
RD6 29 4 4 4 — — — P1C — — — PSP6 — — —

Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0

2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only.

 2010-2015 Microchip Technology Inc. DS40001303H-page 7

PIC18F2XK20/4XK20

TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18F4XK20) (CONTINUED)

I/O

40-Pin PDIP

RD7 30 5 5 5 — — — P1D — — — PSP7 — — —
RE0 8 23 25 25 AN5

RE1 9 24 26 26 AN6
RE2 10 25 27 27 AN7

(3)

RE3

Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0

1161818

— 11 7 7 7 — — — — — — — — — — VDD
—32262828 — — — — — — — — — — VDD
— 12 6 6 6 — — — — — — — — — — VSS
—31272930 — — — — — — — — — — VSS
— – — NC 8 — — — — — — — — — — VDD
—–—NC29— — — — — — — — — — VDD
— –- — NC 31 — — — — — — — — — — VSS

2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only.

40-Pin UQFN

44-Pin TQFP

Analog

44-Pin QFN

——————————

Comp.

— — — — — —
——————
— — — — — —

Reference

ECCP

EUSART

MSSP

Timers

RD
WR

CS

Slave

— — —
—— —
— — —

Pull-up

Interrupts

MCLR

Basic

/VPP

DS40001303H-page 8  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

Table of Contents

1.0 Device Overview .............................................................................................................................. .. .............. ............. .. .......... 11

2.0 Oscillator Module (With Fail-Safe Clock Monitor)...................................................................................................................... 26

3.0 Power-Managed Modes............................................................................................................................................................ 41

4.0 Reset......................................................................................................................................................................................... 48

5.0 Memory Organization . ............................................................................................................................................................... 61

6.0 Flash Program Memory......... ....................................................... ............... ......................... ..................................................... 84

7.0 Data EEPROM Memory ............................. ............................ .............. ............................ ........................ ............. .. .............. .... 93

8.0 8 x 8 Hardware Multiplier............................................................................................................... ............. ............. .. .............. .. 98

9.0 Interrupts................................................................................................................................................................................. 100

10.0 I/O Ports.................. ........................... ........................... ............... ........................................................................................... 113

11.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................ 134

12.0 Timer0 Module ................................................................................................................................. .. .............. .. ............. ........ 145

13.0 Timer1 Module ................................................................................................................................. .. .............. .. ............. ........ 148

14.0 Timer2 Module ................................................................................................................................. .. .............. .. ............. ........ 155

15.0 Timer3 Module ................................................................................................................................. .. .............. .. ............. ........ 157

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................... .. .......... 161

17.0 Master Synchronous Serial Port (MSSP) Module ................................................................................................................... 179

18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART).............................................................. 222

19.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 249

20.0 Comparator Module................................................................................................................................................................. 262

21.0 Voltage References.................................................................. .. .. .... .. .. ....... .... .. .... .. .. ............................. .. ............. .............. .. .. 27 2

22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................ 276

23.0 Special Features of the CPU......................... ...................................................... ............... ..................................................... 281

24.0 Instruction Set Summary......................................................................................................................................................... 296

25.0 Development Support............................................................................................................................. .. ............. .. .............. .. 34 6

26.0 Electrical Characteristics.......................................................................................................................... .. ............. .. .............. 35 0

27.0 DC and AC Characteristics Graphs and Tables...................................................................................................................... 387

28.0 Packaging Information. ............... ...................................................... ............... ........................................................................ 410

Appendix A: Revision History............................................................................................................................................................ 435

Appendix B: Device Differences ............................................................................................................. .. ............. .. ............. .. .......... 436

The Microchip Web Site.............. ............... ........................... ............................ ................................................................................ 437

Customer Change Notification Service ..................................................................................................... . .............. ............. .. .......... 437

Customer Support............................................................................................................................................................................. 437

Product Identification System........................................................................................................................................................... 438

 2010-2015 Microchip Technology Inc. DS40001303H-page 9

PIC18F2XK20/4XK20

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents r egarding t his publication, p lease c ontact the M arket ing Communications Department via
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS40001303H-page 10  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

1.0 DEVICE OVERVIEW

This document co nta i ns dev ic e spec if i c in for m at ion fo r
the following devices:

• PIC18F23K20 • PIC18F43K20

• PIC18F24K20 • PIC18F44K20

• PIC18F25K20 • PIC18F45K20

• PIC18F26K20 • PIC18F46K20

This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-endurance, Flash program memory. On top of
these features, the PIC18F2XK20/4XK20 family
introduces design enhancements that make these
microcontrollers a logical choice for many
high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 XLP TECHNOLOGY

All of the devices in the PIC18F2XK20/4XK20 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these st ates, powe r consumpt ion can be
reduced even further, to as little as 4% of normal
operation requirements.

• On-the-fly Mode Switching: The power­managed modes a re invo ked b y user code durin g
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.

• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See

Section 26.0 “Electrical Specifications”

for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2XK20/4XK20 family
offer ten different oscillator options, allowing users a
wide range of choices in developing application
hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same

pin options as the External Clock modes

• An internal oscillator block which contains a

16 MHz HFINTOSC oscillator and a 31 kHz
LFINTOSC oscillator which together provide 8
user selectable clock frequencies, from 31 kHz to
16 MHz. This option frees the two oscillator pins
for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and inter­nal oscillator m odes, which a llows clo ck speeds o f
up to 64 MHz. Used with t he internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 64 MHz – all without using
an external crystal or clock circuit.

Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re ference source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a
reference signal provided by the LFINTOSC. If a
clock failure occurs, the controller is switched to
the internal oscillato r block, al lowing f or continue d
operation or a safe application shutdown.

• T wo-S pe ed S tart-up: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

 2010-2015 Microchip Technology Inc. DS40001303H-page 11

PIC18F2XK20/4XK20

1.2 Other Special Features

• Memory Endurance: The Flash cells for both
program memory and data EEPROM are rated to
last for many thousands of erase/write cycles – up to
10K for program memory and 100K for EEPROM.
Data retention without refresh is conservatively
estimated to be greater than 40 years.

• Self-programmability: These devices can write
to their own program mem ory spaces under
internal software control. By using a bootloader
routine located in the protected Boot Block at the
top of program memory, it becomes possible to
create an application that can update itself in the
field.

• Extended Instruction Set: The PIC18F2XK20/
4XK20 family introduces an optional extension to
the PIC18 instruction set, which adds eight new
instructions and an Indexed Addressing mode.
This extension, en abled as a de vi ce conf igurati on
option, has been specifi cally des igned to opt imize
re-entrant applica tion cod e origina lly deve loped in
high-level languages, such as C.

• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include:

- Auto-Shutdown, for disabling PWM outputs

on interrupt or other select conditions

- Auto-Restart, to reactivate outputs once the

condition has cleared

- Output steering to selectively enable one or

more of four outputs to provide the PWM
signal.

• Enhanced Addressable EUSART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolu tion. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).

• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated withou t wai ting for a sampling perio d an d
thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit
postscaler, allowing an extended time-out range
that is stable across operati ng vol t age and
temperature. See Section 26.0 “Electrical

Specifications” for time-out periods.

1.3 Details on Individual Family Members

Devices in the PIC18F2XK20/4XK20 family are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.

The devices are differentiated from each other in five
ways:

1. Flash program memory (8 Kbytes for

PIC18F23K20/43K20 devices, 16 Kbytes for
PIC18F24K20/44K20 devices, 32 Kbytes for
PIC18F25K20/45K20 AND 64Kbytes for
PIC18F26K20/46K20).

2. A/D channels (11 for 28-pin devices, 14 for

40/44-pin devices).

3. I/O ports (three bidirectional ports on 28-pin

devices, five bidirectional ports on 40/44-pin
devices).

4. Parallel Slave Port (present only on 40/44-pin

devices).

All other features fo r device s in this family are identi cal.
These are summarized in Table 1-1.

The pinouts for al l devices are lis ted in the pin summar y
tables: Table and Table , and I/O description tables:

Table 1-2 and Table 1-3.

DS40001303H-page 12  2010-2015 Microchip Technology Inc.

 2010-2015 Microchip Technology Inc. DS40001303H-page 13

TABLE 1-1: DEVICE FEATURES

Features PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20

Operating Frequency
Program Memory (Bytes) 8192 16384 32768 65536 8192 16384 32768 65536
Program Memory

(Instructions)
Data Memory (Bytes) 512 768 1536 3936 512 768 1536 3936
Data EEPROM Memory

(Bytes)
Interrupt Sources 19 19 19 19 20 20 20 20
I/O Ports A, B, C, (E)
Timers 4 4 44 44 44
Capture/Compare/PWM

Modules
Enhanced Capture/

Compare/PWM Modules
Serial Communications MSSP, Enhanced

Parallel Communica­tions (PSP)

10-bit Analog-to-Digital
Module

Resets (and Delays) POR, BOR, RESET

Programmable High/
Low-Voltage Detect

Programmable Brown­out Reset

Instruction Set 75 Instructions; 83

Packages 28-pin PDIP

Note 1: PORTE contains the single RE3 read-only bit. The LATE and TRISE registers are not implemented.

2: Frequency range shown applies to industrial range devices only. Maximum frequency for extended range devices is 48 MHz.

(2)

DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz

EUSART

1 internal plus 10

Input Channels

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

MCLR

with Extended

Instruction Set

28-pin SOIC

28-pin QFN
28-pin SSOP
28-pin UQFN

4096 8192 16384 32768 4096 8192 16384 32768

256 256 256 1024 256 256 256 1024

(1)

11111111

1 1 11 11 11

No No No No Yes Yes Yes Yes

(optional),

WDT

Yes Yes Yes Yes Yes Yes Yes Yes

Yes Yes Yes Yes Yes Yes Yes Yes

enabled

A, B, C, (E)

MSSP, Enhanced

1 internal plus 10

Input Channels

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

(PWRT, OST), MCLR

(optional), WDT

75 Instructions; 83

with Extended

Instruction Set

28-pin PDIP

28-pin SOIC

28-pin QFN

28-pin SSOP

EUSART

enabled

(1)

MSSP, Enhanced

1 internal plus 10

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

75 Instructions; 83

A, B, C, (E)

EUSART

Input Channels

(PWRT, OST),

(optional),

MCLR

WDT

with Extended

Instruction Set

enabled

28-pin PDIP
28-pin SOIC

28-pin QFN

28-pin SSOP

(1)

MSSP, Enhanced

1 internal plus 10

POR, BOR, RESET

Instruction, Stack
Full, Stack Underflow
(PWRT, OST), MCLR

(optional), WDT

75 Instructions; 83

A, B, C, (E)

Input Channels

with Extended
Instruction Set

28-pin PDIP

28-pin SOIC

28-pin QFN

28-pin SSOP

(1)

EUSART

enabled

A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E

MSSP, Enhanced

EUSART

1 internal plus 13

Input Channels

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions; 83

with Extended
Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

40-pin UQFN

MSSP, Enhanced

EUSART

1 internal plus 13

Input Channels

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions; 83

with Extended
Instruction Set

enabled

40-pin PDIP

44-pin QFN
44-pin TQFP
40-pin UQFN

MSSP, Enhanced

EUSART

1 internal plus 13

Input Channels

POR, BOR, RESET

Instruction, Stack

Full, Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions; 83

with Extended
Instruction Set

enabled

40-pin PDIP

44-pin QFN
44-pin TQFP
40-pin UQFN

POR, BOR, RESET

MSSP, Enhanced

EUSART

1 internal plus 13

Input Channels

Instruction, Stack

Full, Stack

Underflow (PWRT,

OST), MCLR

(optional), WDT

75 Instructions; 83

with Extended
Instruction Set

enabled

40-pin PDIP

44-pin QFN
44-pin TQFP
40-pin UQFN

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20

Instruction

Decode and

Control

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT
RA5/AN4/SS

/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

(1)

RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10/C12IN3-

Data Latch

Data Memory

Address Latch

Data Address< 12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

20

8

8

T able Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

ROM Latch

RB2/INT2/AN8
RB3/AN9/CCP2

(1)

/C12IN2-

PCLATU

PCU

OSC2/CLKOUT

(3)

/RA6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

functionality is disabled.

3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Module (With Fail- Safe Clock Mo nitor )” for additional information.

RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

EUSARTComparator

MSSP

10-bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR

Data

EEPROM

W

Instruction Bus <16>

STKPTR

Bank

8

State machine
control signals

Decode

8

8

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

V

SS

MCLR

(2)

Block

LFINTOSC

Oscillator

16 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

T1OSO

OSC1/CLKIN

(3)

/RA7

T1OSI

PORTE

MCLR/VPP/RE3

(2)

FVR

FVR

FVR

CVREF

Address Latch

Program Memory

(8/16/32/64 Kbytes)

Data Latch

FIGURE 1-1: PIC18F2XK20 (28-PIN) BLOCK DIAGRAM

DS40001303H-page 14  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

Instruction

Decode and

Control

Data Latch

Data Memory

Address Latc h

Data Address< 12>

12

Access

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

4

12

4

PCH PCL

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP

8

8

ALU<8>

Address Latch

Program Memory

(8/16/32/ 64Kbytes)

Data Latch

20

8

8

T able Pointer<21>

inc/dec logic

21

Data Bus<8>

Table Latch

8

IR

12

3

ROM Latch

PORTD

RD0/PSP0

PCU

PORTE

MCLR/VPP/RE3

(2)

RE2/CS/AN7

RE0/RD/AN5
RE1/WR/AN6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

functionality is disabled.

3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.

EUSARTComparator

MSSP

10-bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR

Data

EEPROM

W

Instruction Bus <16>

STKPTR

Bank

8

State machine
control signals

Decode

8

8

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

V

SS

MCLR

(2)

Block

LFINTOSC

Oscillator

16 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

T1OSI

T1OSO

RD1/PSP1
RD2/PSP2
RD3/PSP3

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT
RA5/AN4/SS

/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A
RC3/SCK/SCL

RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10/C12IN3­RB2/INT2/AN8
RB3/AN9/CCP2

(1)

/C12IN2-

OSC2/CLKOUT

(3)

/RA6

RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

OSC1/CLKIN

(3)

/RA7

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

FVR

FVR

PSP

FVR

CVREF

PCLATH

8

8

PCLATU

FIGURE 1-2: PIC18F4XK20 (40/44-PIN) BLOCK DIAGRAM

 2010-2015 Microchip Technology Inc. DS40001303H-page 15

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

MCLR

/VPP/RE3
MCLR
VPP
RE3

OSC1/CLKIN/RA7

OSC1
CLKIN

RA7

OSC2/CLKOUT/RA6

OSC2
CLKOUT
RA6

Legend: TTL= TTL compatible input CMOS = C MOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assi gnment for CCP2 when Configur ation bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,
SOIC

126

96

10 7

QFN

Pin

Type

I

P

I

I
I

I/O

O
O

I/O

Buffer

Type

ST
ST

ST

CMOS

TTL

—
—

TTL

Description

Master Clear (input) or programming voltage (input)

Active-low Master Clear (device Reset) input
Programmin g voltage input
Digital input

Oscillator crystal or external clock input

Oscillator crystal input or external clock source input
ST buffer when configured in RC mode; CMOS otherwise
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT
pins)
General purpose I/O pin

Oscillator crystal or clock output

Oscillator crystal output. Connects to crystal or
resonator i n Crystal Oscillat or mode
In RC mode, OSC2 pin out put s CLKOUT which h as 1/4 th e
frequency of OSC1 and denotes the instruction cycle rate
General purpose I/O pin

DS40001303H-page 16  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0/C12IN0-

RA0
AN0
C12IN0-

RA1/AN1/C12IN1-

RA1
AN1
C12IN1-

RA2/AN2/V
C2IN+

RA2
AN2
V
CV
C2IN+

RA3/AN3/V

RA3
AN3
V
C1IN+

RA4/T0CKI/C1OUT

RA4
T0CKI
C1OUT

RA5/AN4/SS
C2OUT

RA5
AN4
SS
HLVDIN

C2OUT
RA6 See the OSC2/CLKOUT/RA6 pin
RA7 See the OSC1/CLKIN/RA7 pin

Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

REF-/CVREF/

REF-

REF

REF+/C1IN+

REF+

/HLVDIN/

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,

QFN

SOIC

227

328

41

52

63

74

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

O

I

I/O

I
I
I

I/O

I

O

I/O

I
I
I

O

Buffer

Type

TTL
Analog
Analog

TTL
Analog
Analog

TTL
Analog
Analog
Analog
Analog

TTL
Analog
Analog
Analog

ST
ST

CMOS

TTL
Analog

TTL
Analog
CMOS

Description

PORTA is a bidirectional I/O port.

Digital I/O
Analog input 0, ADC channel 0
Comparators C1 and C2 inverting input

Digital I/O
ADC input 1, ADC channel 1
Comparators C1 and C2 inverting input

Digital I/O
Analog input 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input

Digital I/O
Analog input 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input

Digital I/O
Timer0 external clock input
Comparator C1 output

Digital I/O
Analog input 4, ADC channel 4
SPI slave select input
High/Low-Voltage Detect inpu t
Comparator C2 output

 2010-2015 Microchip Technology Inc. DS40001303H-page 17

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/INT0/FLT0/AN12

RB0
INT0
FLT0
AN12

RB1/INT1/AN10/C12IN3­/P1C

RB1
INT1
AN10
C12IN3­P1C

RB2/INT2/AN8/P1B

RB2
INT2
AN8
P1B

RB3/AN9/C12IN2-/CCP2

RB3
AN9
C12IN2-

(2)

CCP2

RB4/KBI0/AN11/P1D

RB4
KBI0
AN11
P1D

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL= TTL compatible input CMOS = C MOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assi gnment for CCP2 when Configur ation bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,
SOIC

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Pin

Type

I/O

I
I
I

I/O

I
I
I

O

I/O

I
I

O

I/O

I
I

I/O

I/O

I
I

O

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

Buffer

Type

TTL

ST
ST

Analog

TTL

ST
Analog
Analog

CMOS

TTL

ST
Analog

CMOS

TTL
Analog
Analog

ST

TTL

TTL
Analog

CMOS

TTL

TTL

ST

TTL

TTL

ST

TTL

TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on each input.

Digital I/O
External interrupt 0
PWM Fault input for CCP1
Analog input 12, ADC channel 12

Digital I/O
External interrupt 1
Analog input 10, ADC channel 10
Comparators C1 and C2 inverting input
Enhanced CCP1 PWM output

Digital I/O
External interrupt 2
Analog input 8, ADC channel 8
Enhanced CCP1 PWM output

Digital I/O
Analog input 9, ADC channel 9
Comparators C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2 output

Digital I/O
Interrupt-on-change pin
Analog input 11, ADC channel 11
Enhanced CCP1 PWM output

Digital I/O
Interrupt-on-change pin
Low-Voltage ICSP™ Programming enable pin

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming clock pin

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming data pin

DS40001303H-page 18  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(1)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX

DT
RE3 — — — — See MCLR
V

SS 8, 19 5, 16 P — Ground reference for logic and I/O pins
DD 20 17 P — Positive supply for logic and I/O pins

V
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP,
SOIC

11 8

12 9

13 10

14 11

15 12

16 13

17 14

18 15

QFN

Pin

Buffer

Type

I/O

O

I

I/O

I

Analog

I/O

I/O
I/O

O

CMOS

I/O
I/O
I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

Type

PORTC is a bidirectional I/O port.

ST

—

ST

ST
ST

ST
ST

ST
ST
ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Digital I/O
Timer1 oscillator output
Timer1/Timer3 external clock input

Digital I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2 output

Digital I/O
Capture 1 input/Compare 1 outpu t
Enhanced CCP1 PWM output

Digital I/O
Synchronous serial clock input/output for SPI mode
Synchronous serial clock input/output for I

Digital I/O
SPI data in

2

C™ data I/O

I

Digital I/O
SPI data out

Digital I/O
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)

Digital I/O
EUSART asynchronous receive
EUSART synchronous data (see related TX/CK)

/VPP/RE3 pin

Description

2

C™ mode

 2010-2015 Microchip Technology Inc. DS40001303H-page 19

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS

Pin Name

/VPP/RE3

MCLR

MCLR
VPP
RE3

OSC1/CLKIN/RA7

OSC1

CLKIN

RA7

OSC2/CLKOUT/
RA6

OSC2
CLKOUT

RA6

Legend: TTL= TTL compatible input CMOS = C MOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assi gnment for CCP2 when Configur ation bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP QFN TQFP UQFN

Pin Number

1181816

13 32 30 28

14 33 31 29

Pin

Type

I

P

I

I

I

I/O

O
O

I/O

Buffer

Type

ST
ST

ST

CMOS

TTL

—
—

TTL

Description

Master Clear (input) or programming voltage
(input)

Active-low Master Clear (device Reset) input
Programming voltage input
Digital input

Oscillator crystal or external clock input

Oscillator crystal input or external clock source
input
ST buffer when configured in RC mode;
analog otherwise
External clock source input. Always associated

with

pin function OSC1 (See related OSC1/CLKIN,
OSC2/CLKOUT pins)
General purpose I/O p i n

Oscillator crystal or clock output

Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate
General purpose I/O p i n

DS40001303H-page 20  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0/C12IN0-

RA0

AN0

C12IN0­RA1/AN1/C12IN0-

RA1

AN1

C12IN0­RA2/AN2/V

REF/C2IN+

CV

RA3/AN3/V
C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS
DIN/C2OUT

RA6 See the OSC2/CLKOUT/RA6 pin
RA7 See the OSC1/CLKIN/RA7 pin

Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

REF-/

RA2

AN2

REF-

V

REF

CV

C2IN+

REF+/

RA3

AN3

VREF+

C1IN+

RA4

T0CKI

C1OUT

/HLV-

RA5

AN4

SS

HLVDIN

C2OUT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP QFN TQFP UQFN

Pin Number

21919

32020

42121

52222

62323

72424

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

O

I

I/O

I
I
I

I/O

I

O

I/O

I
I
I

O

Buffer

Type

TTL
Analog
Analog

TTL
Analog
Analog

TTL
Analog
Analog
Analog
Analog

TTL
Analog
Analog
Analog

ST
ST

CMOS

TTL
Analog

TTL
Analog
CMOS

Description

PORTA is a bidirectional I/O port.

Digital I/O
Analog input 0, ADC channel 0
Comparator C1 and C2 inverting input

Digital I/O
Analog input 1, ADC channel 1
Comparator C1 and C2 inverting input

Digital I/O
Analog input 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input

Digital I/O
Analog input 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input

Digital I/O
Timer0 external clock input
Comparator C1 output

Digital I/O
Analog input 4, ADC channel 4
SPI slave select input
High/Low-Voltage Detect input
Comparator C2 output

 2010-2015 Microchip Technology Inc. DS40001303H-page 21

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0/
AN12

RB0
INT0
FLT0
AN12

RB1/INT1/AN10/
C12IN3-

RB1
INT1
AN10
C12IN3-

RB2/INT2/AN8

RB2
INT2
AN8

RB3/AN9/C12IN2-/
CCP2

RB3
AN9
C12IN23-

(2)

CCP2

RB4/KBI0/AN11

RB4
KBI0
AN11

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL= TTL compatible input CMOS = C MOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assi gnment for CCP2 when Configur ation bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP QFN TQFP UQFN

Pin Number

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Type

I/O

I
I
I

I/O

I
I
I

I/O

I
I

I/O

I
I

I/O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

Buffer

Type

TTL

ST
ST

Analog

TTL

ST
Analog
Analog

TTL

ST
Analog

TTL
Analog
Analog

ST

TTL

TTL
Analog

TTL

TTL

ST

TTL

TTL

ST

TTL

TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can
be software programmed for internal weak
pull-up on each input.

Digital I/O
External interrupt 0
PWM Fault input for Enhanced CCP1
Analog input 12, ADC channel 12

Digital I/O
External interrupt 1
Analog input 10, ADC channel 10
Comparator C1 and C2 inverting input

Digital I/O
External interrupt 2
Analog input 8, ADC channel 8

Digital I/O
Analog input 9, ADC channel 9
Comparator C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2
output

Digital I/O
Interrupt-on-change pin
Analog input 11, ADC channel 11

Digital I/O
Interrupt-on-change pin
Low-Volt age ICSP™ Programming enabl e p in

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™
programming clock pin

Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™

programming data pin

DS40001303H-page 22  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/
T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(1)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK

SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP QFN TQFP UQFN

Pin Number

15 34 32

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Buffer

Type

I/O

O

I

I/O

I

CMOS

I/O

I/O
I/O

O

I/O
I/O

I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

Type

PORTC is a bidirectional I/O port.

ST

—

ST

ST
ST

ST
ST

—

ST
ST

ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Digital I/O
Timer1 oscilla tor output
Timer1/Timer3 external clock input

Digital I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2
output

Digital I/O
Capture 1 input/Compare 1 output/PWM 1
output
Enhanced CCP1 output

Digital I/O
Synchronous serial clock input/output for
SPI mode
Synchronous serial clock input/output for I

mode

Digital I/O
SPI data in

2

C™ data I/O

I

Digital I/O
SPI data out

Digital I/O
EUSART asynchronous transm it
EUSART sync hronous clock (see related RX/
DT)

Digital I/O
EUSART asynchronous receive
EUSART synchronous data (see related TX/

CK)

Description

2

C™

 2010-2015 Microchip Technology Inc. DS40001303H-page 23

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/PSP0

RD0
PSP0

RD1/PSP1

RD1
PSP1

RD2/PSP2

RD2
PSP2

RD3/PSP3

RD3
PSP3

RD4/PSP4

RD4
PSP4

RD5/PSP5/P1B

RD5
PSP5
P1B

RD6/PSP6/P1C

RD6
PSP6
P1C

RD7/PSP7/P1D

RD7
PSP7
P1D

Legend: TTL= TTL compatible input CMOS = C MOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assi gnment for CCP2 when Configur ation bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP QFN TQFP UQFN

Pin Number

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Buffer

Type

Type

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/O

O

I/O
I/O

O

I/O
I/O

O

Description

PORTD is a bidirectional I/O port or a Parallel
Slave Port (PSP) for interfacing to a
microprocessor port. Th es e p ins ha ve TTL input
buffers when PSP module is enabled.

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

Digital I/O
Parallel Slave Port data

ST

TTL

—

ST

TTL

—

ST

TTL

—

Digital I/O
Parallel Slave Port data
Enhanced CCP1 output

Digital I/O
Parallel Slave Port data
Enhanced CCP1 output

Digital I/O
Parallel Slave Port data
Enhanced CCP1 output

DS40001303H-page 24  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/RD

RE1/WR/AN6

RE2/CS/AN7

RE3 — — — — — See MCLR
VSS 12, 31 6, 30, 316, 29 P — Ground reference for logic and I/O pins

/AN5
RE0
RD

AN5

RE1
WR

AN6

RE2
CS

AN7

PDIP QFN TQFP UQFN

Pin Number

82525

92626

10 27 27

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

Buffer

Type

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

Description

PORTE is a bidirectional I/O port

Digital I/O
Read control for Parallel Slave Port
(see related WR
Analog input 5, ADC channel 5

Digital I/O
Write control for Parallel Slave Port
(see related CS
Analog input 6, ADC channel 6

Digital I/O
Chip Select control for Parallel Slave Port
(see related RD
Analog input 7, ADC channel 7

/VPP/RE3 pin

and CS pins)

and RD pins)

and WR)

V

DD 11, 32 7, 8,

28, 29

NC — 13 12, 13,

Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

7, 28 P — Positive supply for logic and I/O pins

— — No connect

33, 34

 2010-2015 Microchip Technology Inc. DS40001303H-page 25

PIC18F2XK20/4XK20

4 x PLL

FOSC<3:0>

Secondary Oscillator

T1OSCEN
Enable
Oscillator

T1OSO

T1OSI

Clock Source Option
for other Modules

OSC1

OSC2

Sleep

HSPLL, HFINTOSC/PLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

Postscaler

MUX

MUX

16 MHz

8 MHz
4 MHz
2 MHz
1 MHz

250 kHz

500 kHz

OSCCON<6:4>

111
110
101
100

011
010
001
000

31 kHz

31 kHz
Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

16 MHz

Internal Oscillator

(HFINTOSC)

Clock

Control

OSCCON<1:0>

Source

16 MHz

31 kHz (LFINTOSC)

OSCTUNE<6>

(1)

0

1

OSCTUNE<7>

and Two-Speed Start-up

Primary Oscillator

PIC18F2XK20/4XK20

Sleep

Sleep

Main

FOSC<3:0> OSCCON<1:0>

Note 1: Operates only when HFINTOSC is the primary oscillator.

2.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

2.1 Overview

The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing
performance and minimizing power consumption.

Figure 2-1 illustrates a block diagram of the oscillator

module.
Clock sources can be configured from external

oscillators, quar tz cryst al resonator s, cerami c resonato rs
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds select able via
software. Additional clo ck feat ures inc lud e:

• Selectable system clock source between external

or intern al via software.

• Tw o-Speed Start-up mode, which min im iz es

latency between external oscillator start-up and
code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.

The oscillator module can be configured in one of ten
primary clock modes.

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator
with PLL enabled

5. RC External Resistor/Capacitor with

OSC/4 output on RA6

F

6. RCIO External Resistor/Cap acitor with I/O
on RA6

7. INTOSC Internal Oscillator with F

OSC/4

output on RA6 and I/O on RA7

8. INTOSCIO Internal Oscillator with I/O on RA6
and RA7

9. EC External Clock with F

OSC/4 output

10. ECIO External Clock with I/O on RA6

Primary Clock modes are selected by the FOSC<3:0>
bits of the CONFIG1H Configuration Register. The
HFINTOSC and LFINTOSC are factory calibrated
high-frequency and low-frequency oscillators,
respectively, which are used as the internal clock
sources.

FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS40001303H-page 26  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

2.2 Oscillator Control

The OSCCON register (Register 2-1) controls several
aspects of the device clock’s operation, both in full
power operation and in power-ma nag ed mo des .

• Main System Clock Selection (SCS)

• Internal Frequency selection bits (IRCF)

• Clock Status bits (OSTS, IOFS)

• Power management selection (IDLEN)

2.2.1 MAIN SYSTEM CLOCK SELECTION

The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are

• Primary clock defined by the FOSC<3:0> bits of
CONFIG1H. The primary clock can be the primary
oscillator, an external clock, or the internal
oscillator block.

• Secondary clock (Timer1 oscillator)

• Internal oscillator block (HFINTOSC and
LFINTOSC).

The clock source changes immediately after one or
more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared to select
the primary clock on all forms of Reset.

2.2.4 CLOCK STATUS

The OSTS and IOFS bits of the OSCCON reg ister , an d
the T1RUN bit of the T1CON register, indicate which
clock source is c urr e ntl y pr ov id in g the ma i n clo ck. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device cloc k. T he I OFS b it i ndi cat es wh en t he in ter nal
oscillator block has stabilized and is providing the
device clock in HFINTOSC Clock modes. The IOFS
and OSTS Status bits will both be set when
SCS<1:0> = 00 and HFINTOSC is the primary clock.
The T1RUN bi t indi cat es w hen t he Timer1 o sci llat or is
providing the device clock in secondary clock modes.
When SCS<1:0>  00, only one of these three bits will
be set at any time. If none of these bits are set, the
LFINTOSC is provid ing the clock or the HFINTO SC has
just started and is not yet stable.

2.2.5 POWER MANAGEMENT

The IDLEN bit of the OSCCON register determines if
the device goes into Sleep mode or one of the Idle
modes when the SLEEP instruction is executed.

The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0

“Power-Managed Modes”.

2.2.2 INTERNAL FREQUENCY

SELECTION

The Internal Oscillator Frequency Select bits
(IRCF<2:0>) select the fr equenc y output of th e interna l
oscillator block. The choices are th e LFINTOSC source
(31 kHz), the HFINTOSC source (16 MHz) or one of
the frequencies derived from the HFINTOSC
postscaler (31.25 kHz to 8 MHz). If the internal
oscillator block is supplying the main clock, changing
the states of these bits will have an immediate change
on the internal oscillator’s output. On device Resets,
the output frequency of the internal oscillator is set to
the default frequency of 1 MHz.

2.2.3 LOW FREQUENCY SELECTION

When a nominal ou tput frequenc y of 31 kHz is selected
(IRCF<2:0> = 000), users may choo se which inte rnal
oscillator acts as the source. This is done with the
INTSRC bit of the OSCTUNE register. Setting this bit
selects the HFINTOSC as a 31.25 kHz clock source by
enabling the divide-by-512 output of the HFINTOSC
postscaler. Clearing INTSRC selects LFINTOSC
(nominally 31 kHz) as the clock source.

This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while
maintaining p ower savings w ith a very lo w clock spee d.
Regardless of the setting of INTSRC, LFINTOSC
always remains the clock source for features such as
the Watchdog Timer and the Fail-Safe Clock Monitor.

Note 1: The Timer1 os ci ll ator must be enabled to

select the s econdary clock source. The
Timer1 os cillator is enabled by s etting the
T1OSCEN bit of the T1CON register. If
the Timer1 oscillator is not enabled, then
the main oscillator will continue to run
from the previ o us ly sel e ct ed so ur c e. The
source will then switch to the secondary
oscillator after the T1OSCEN bit is set.

2: It is recommended that the Timer1

oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.

 2010-2015 Microchip Technology Inc. DS40001303H-page 27

PIC18F2XK20/4XK20

REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Slee p mode on SLEEP instruction

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

111 = 16 MHz (HFINTOSC drives clock directly)
110 = 8 MHz
101 = 4 MHz
100 = 2 MHz
011 = 1 MHz
010 = 500 kHz
001 = 250 kHz
000 = 31 kHz (from either HFINTOSC/512 or LFINTOSC directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

bit 2 IOFS: HFINTOSC Frequency Stable bit

1 = HFINTOSC frequency is stable
0 = HFINTOSC frequency is not stable

bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block
01 = Secondary (Timer1) oscillator
00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]).

(3)

(1)

(1)

IOFS SCS1 SCS0

(2)

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit of the OSCTUNE register, see text.
3: Default output frequency of HFINTOSC on Reset.

DS40001303H-page 28  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20

OSC1/CLKIN

OSC2/CLKOUT

(1)

I/O

Clock from
Ext. System

PIC

®

MCU

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2.3 Clock Source Modes

Clock Source modes can be classified as external or
internal.

• External Clock mod es re ly on external circ uitry for
the clock source. Examples are: Clock modules
(EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resistor­Capacitor (RC mode) circuits.

• Internal clock sources are contained internally
within the Oscillator block. The Oscillator block
has two internal oscillators: the 16 MHz
High-Frequency Internal Oscillator (HFINTOSC)
and the 31 kHz Low-Frequency Internal Os cillator
(LFINTOSC).

The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS<1:0>) bits of the OSCCON register. See

Section 2.9 “Clock Switching” for additional

information.

2.4 External Clock Modes

2.4.1 OSCILLATOR START-UP TIMER (OST)

When the oscil lat or modu le i s conf igu red f or LP, XT or
HS modes, th e Osc illa tor Start-up Timer (O ST) c oun ts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator o r ce ramic res onator, has started and
is providing a stable system clock to the oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 2-1.

In order to minimize laten cy between externa l oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 2.10

“Two-Speed Clock Start-up Mode”).

TABLE 2-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR
Sleep/POR EC, RC DC – 64 MHz 2 instructi on cycles

LFINTOSC (31 kHz) EC, RC DC – 64 MHz 1 cycle of each

Sleep/POR LP, XT, HS 32 kHz to 40 MHz 1024 Clock Cycles (OST)
Sleep/POR HSPLL 32 MHz to 64 MHz 1024 Clock Cycles (OST) + 2 ms

LFINTOSC (31 kHz) HFINTOSC 250 kHz to 16 MHz 1 s (approx.)

LFINTOSC

HFINTOSC

31 kHz

250 kHz to 16 MHz

Oscillator Warm-Up Delay (T

WARM)

2.4.2 EC MODE

The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 2-2 shows the pin
connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

 2010-2015 Microchip Technology Inc. DS40001303H-page 29

FIGURE 2-2: EXTERNAL CLOCK (EC)

MODE OPERATION

®

MCU design is fully

PIC18F2XK20/4XK20

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

C1

C2

Quartz

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (R

P)

may be required for proper ceramic resonator
operation.

C1

C2

Ceramic

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

RP

(3)

Resonator

OSC2/CLKOUT

2.4.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 2-3). The mode selects a low ,
medium or high gain setting of the internal inverter­amplifier to support v arious resonato r types and spee d.

LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consum ption
is the least of the three modes. This mode is best suited
to drive resonators with a l ow drive level specification , for
example, tuning fork type crystals.

XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medi um of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.

HS Oscillator mode select s the highest gain setting of the
internal inverter-amplifie r. H S mode current consum ption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.

Figure 2-3 and Figure 2-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 2-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR
HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and
manufacturer. The u ser should consult th e
manufacturer data sh eets for specif ica tions
and recommended appl ication .

2: Always verify oscillator perform ance ov er

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

®

and PIC®

Devices” (DS00826)

®

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

®

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”
(DS00949)

FIGURE 2-4: CERAMIC RESONATOR

OPERATION
(XT OR HS MODE)

DS40001303H-page 30  2010-2015 Microchip Technology Inc.