Datasheet PIC18F2423, PIC18F2523, PIC18F4423, PIC18F4523 Datasheet
PIC18F2423/2523/4423/4523
Data Sheet
28/40/44-Pin, Enhanced Flash
Microcontrollers with 12-Bit A/D
and nanoWatt Technology
© 2009 Microchip Technology Inc. DS39755C
Note the following details of the code protection feature on Microchip devices:
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intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC
32
logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS39755C-page 2 © 2009 Microchip Technology Inc.
PIC18F2423/2523/4423/4523
28/40/44-Pin, Enhanced Flash Microcontrollers with
12-Bit A/D and nanoWatt Technology
Power Management Features:
• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
• Ultra Low 50 nA Input Leakage
• Run mode Currents Down to 11 μA Typical
• Idle mode Currents Down to 2.5 μA Typical
• Sleep mode Current Down to 100 μA Typical
• Timer1 Oscillator: 900 nA, 32 kHz, 2V
• Watchdog Timer: 1.4 μA, 2V Typical
• Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
• Four Crystal modes, up to 40 MHz
• 4x Phase Lock Loop (PLL) – Available for Crystal
and Internal Oscillators
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Internal Oscillator Block:
- Fast wake from Sleep and Idle, 1 μs typical
- 8 user-selectable frequencies, from 31 kHz to 8 MHz
- Provides a complete range of clock speeds,
from 31 kHz to 32 MHz, when used with PLL
- User-tunable to Compensate for Frequency Drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock stops
Peripheral Highlights:
• 12-Bit, Up to 13-Channel Analog-to-Digital Converter
module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep mode
• Dual Analog Comparators with Input Multiplexing
• High-Current Sink/Source 25 mA/25 mA
• Three Programmable External Interrupts
• Four Input Change Interrupts
• Up to Two Capture/Compare/PWM (CCP)
modules, One with Auto-Shutdown (28-pin devices)
• Enhanced Capture/Compare/PWM (ECCP) module
(40/44-pin devices only):
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
Peripheral Highlights (Continued):
• Master Synchronous Serial Port (MSSP) module
Supporting 3-Wire SPI (all four modes) and I
Master and Slave modes
• Enhanced USART module:
- Support for RS-485, RS-232 and LIN/J2602
- RS-232 operation using internal oscillator
block (no external crystal required)
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
2
C™
Special Microcontroller Features:
• C Compiler Optimized Architecture: Optional
Extended Instruction Set Designed to Optimize
Re-Entrant Code
• 100,000 Erase/Write Cycle, Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle, Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: 100 Years Typical
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): Programmable
Period, from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Operating Voltage Range: 2.0V to 5.5V
• Programmable, 16-Level High/Low-Voltage
Detection (HLVD) module: Supports Interrupt on
High/Low-Voltage Detection
• Programmable Brown-out Reset (BOR): With
Software-Enable Option
Note: This document is supplemented by the
“PIC18F2420/2520/4420/4520 Data Sheet”
(DS39631). See Section 1.0 “Device
Overview”.
Program Memory Data Memory
Device
PIC18F2423 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3
PIC18F2523 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3
PIC18F4423 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3
PIC18F4523 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3
© 2009 Microchip Technology Inc. DS39755C-page 3
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
I/O
12-Bit
A/D (ch)
CCP/
ECCP
(PWM)
SPI
MSSP
Master
2
C™
I
Comp.
EUSART
Timers
8/16-Bit
PIC18F2423/2523/4423/4523
PIC18F2523
10
11
2
3
4
5
6
1
8
7
9
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/V
REF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
/HLVDIN/C2OUT
V
SS
OSC1/CLKI
(3)
/RA7
OSC2/CLKO
(3)
/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(2)
RC2/CCP1
RC3/SCK/SCL
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2
(2)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
28-Pin PDIP, SOIC
PIC18F2423
Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.
2: RB3 is the alternate pin for CCP2 multiplexing.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not
being used as digital I/O. For additional information, see Section 2.0 “Oscillator Configurations” of the
“PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
PIC18F2423
RC0/T1OSO/T13CKI
5
4
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4KBI0/AN11
RB3/AN9/CCP2
(2)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
MCLR
/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
/HLVDIN/C2OUT
V
SS
OSC1/CLKI
(3)
/RA7
OSC2/CLKO
(3)
/RA6
RC1/T1OSI/CCP2
(2)
RC2/CCP1
RC3/SCK/SCL
PIC18F2523
28-Pin QFN
(1)
Pin Diagrams
DS39755C-page 4 © 2009 Microchip Technology Inc.
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2
(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V
DD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/V
REF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
/HLVDIN/C2OUT
RE0/RD
/AN5
RE1/WR
/AN6
RE2/CS
/AN7
V
DD
VSS
OSC1/CLKI
(2)
/RA7
OSC2/CLKO
(2)
/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4523
40-Pin PDIP
PIC18F4423
10
11
2
3
4
5
6
1
1819202122
121314
15
38
8
7
4443424140
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
PIC18F4423
37
RA3/AN3/VREF+
RA2/AN2/V
REF-/CVREF
RA1/AN1
RA0/AN0
MCLR
/VPP/RE3
NC
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2
(1)
NC
NC
RC0/T1OSO/T13CKI
OSC2/CLKO
(2)
/RA6
OSC1/CLKI
(2)
/RA7
V
SS
VDD
RE2/CS/AN7
RE1/WR
/AN6
RE0/RD
/AN5
RA5/AN4/SS
/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
V
SS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
44-Pin TQFP
PIC18F4523
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not
being used as digital I/O. For additional information, see Section 2.0 “Oscillator Configurations” of the
“PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).
PIC18F2423/2523/4423/4523
Pin Diagrams (Continued)
© 2009 Microchip Technology Inc. DS39755C-page 5
PIC18F2423/2523/4423/4523
10
11
2
3
4
5
6
1
1819202122
121314
15
38
8
7
4443424140
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
PIC18F4423
37
RA3/AN3/V
REF+
RA2/AN2/V
REF-/CVREF
RA1/AN1
RA0/AN0
MCLR
/VPP/RE3
RB3/AN9/CCP2
(2)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2
(2)
RC0/T1OSO/T13CKI
OSC2/CLKO
(3)
/RA6
OSC1/CLKI
(3)
/RA7
V
SS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR
/AN6
RE0/RD
/AN5
RA5/AN4/SS
/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
V
SS
VDD
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
44-Pin QFN
(1)
PIC18F4523
Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.
2: RB3 is the alternate pin for CCP2 multiplexing.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not
being used as digital I/O. For additional information, see Section 2.0 “Oscillator Configurations” of the
“PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).
Pin Diagrams (Continued)
DS39755C-page 6 © 2009 Microchip Technology Inc.
PIC18F2423/2523/4423/4523
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 25
3.0 Special Features of the CPU...................................................................................................................................................... 35
4.0 Electrical Characteristics............................................................................................................................................................ 37
5.0 Packaging Information................................................................................................................................................................ 43
Appendix A: Revision History............................................................................................................................................................... 45
Appendix B: Device Differences .......................................................................................................................................................... 45
Appendix C: Conversion Considerations ............................................................................................................................................. 46
Appendix D: Migration from Baseline to Enhanced Devices................................................................................................................ 46
Appendix E: Migration from Mid-Range to Enhanced Devices ............................................................................................................ 47
Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................... 47
Index ................................................................................................................................................................................................... 49
The Microchip Web Site....................................................................................................................................................................... 51
Customer Change Notification Service ................................................................................................................................................ 51
Customer Support ................................................................................................................................................................................ 51
Reader Response ................................................................................................................................................................................ 52
Product Identification System .............................................................................................................................................................. 53
© 2009 Microchip Technology Inc. DS39755C-page 7
PIC18F2423/2523/4423/4523
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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DS39755C-page 8 © 2009 Microchip Technology Inc.
PIC18F2423/2523/4423/4523
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F2423 • PIC18LF2423
• PIC18F2523 • PIC18LF2523
• PIC18F4423 • PIC18LF4423
• PIC18F4523 • PIC18LF4523
Note: This data sheet documents only the devices’
features and specifications that are in addition
to, or different from, the features and specifications of the PIC18F2420/2520/4420/4520
devices. For information on the features and
specifications shared by the PIC18F2423/
2523/4423/4523 and PIC18F2420/2520/
4420/4520 devices, see the “PIC18F2420/
2520/4420/4520 Data Sheet” (DS39631).
This family offers the advantages of all PIC18
microcontrollers – namely, high computational performance at an economical price – with the addition of
high-endurance, Enhanced Flash program memory.
On top of these features, the PIC18F2423/2523/4423/
4523 family introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power-sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F2423/2523/4423/4523
family incorporate a range of features that can significantly reduce power consumption during operation.
Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller also can run
with its CPU core disabled and the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-Fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• Low Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer are minimized. See Section 4.0 “Electrical
Characteristics” for values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F2423/2523/4423/4523
family offer ten different oscillator options, allowing
users a wide range of choices in developing application
hardware. These include:
• Four Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).
• Two External RC Oscillator modes with the same
pin options as the External Clock modes.
• An internal oscillator block that offers eight clock
frequencies: an 8 MHz clock and an INTRC source
(approximately 31 kHz), as well as a range of six
user-selectable clock frequencies, between
125 kHz to 4 MHz. This option frees the two
oscillator pins for use as additional general
purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the High-Speed Crystal and
Internal Oscillator modes, allowing clock speeds
of up to 40 MHz from the HS clock source. Used
with the internal oscillator, the PLL gives users a
complete selection of clock speeds, from 31 kHz
to 32 MHz, all without using an external crystal or
clock circuit.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: Constantly monitors
the main clock source against a reference signal
provided by the internal oscillator. If a clock failure
occurs, the controller is switched to the internal
oscillator block, allowing for continued operation
or a safe application shutdown.
• Two-Speed Start-up: Allows the internal oscillator
to serve as the clock source from Power-on Reset,
or wake-up from Sleep mode, until the primary clock
source is available.
© 2009 Microchip Technology Inc. DS39755C-page 9
PIC18F2423/2523/4423/4523
1.2 Other Special Features
• 12-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period,
thereby reducing code overhead.
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
• Self-Programmability: These devices can write
to their own program memory spaces under internal software control. By using a bootloader routine
located in the protected Boot Block at the top of
program memory, it is possible to create an
application that can update itself in the field.
• Extended Instruction Set: The PIC18F2423/
2523/4423/4523 family introduces an optional
extension to the PIC18 instruction set that adds
eight new instructions and an Indexed Addressing
mode. This extension, enabled as a device configuration option, has been specifically designed
to optimize re-entrant application code originally
developed in high-level languages, such as C.
• Enhanced CCP module: In PWM mode, this
module provides one, two or four modulated
outputs for controlling half-bridge and full-bridge
drivers. Other features include auto-shutdown, for
disabling PWM outputs on interrupt or other select
conditions, and auto-restart, to reactivate outputs
once the condition has cleared.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the
LIN/J2602 bus protocol. Other enhancements
include automatic baud rate detection and a 16-bit
Baud Rate Generator for improved resolution.
When the microcontroller is using the internal
oscillator block, the EUSART provides stable
operation for applications that talk to the outside
world without using an external crystal (or its
accompanying power requirement).
• Extended Watchdog Timer (WDT): This
Enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 4.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family Members
Devices in the PIC18F2423/2523/4423/4523 family are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in these
ways:
• Flash Program Memory:
- PIC18F2423/4423 devices – 16 Kbytes
- PIC18F2523/4523 devices – 32 Kbytes
• A/D Channels:
- PIC18F2423/2523 devices – 10
- PIC18F4423/4523 devices – 13
• I/O Ports:
- PIC18F2423/2523 devices – Three bidirectional
ports
- PIC18F4423/4523 devices – Five bidirectional
ports
• CCP and Enhanced CCP Implementation:
- PIC18F2423/2523 devices – Two standard
CCP modules
- PIC18F4423/4523 devices – One standard
CCP module and one ECCP module
• Parallel Slave Port – Present only on
PIC18F4423/4523 devices
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Members of the PIC18F2423/2523/4423/4523 family
are available only as low-voltage devices, designated
by “LF” (such as PIC18LF2423), and function over an
extended V
DD range of 2.0V to 5.5V.
DS39755C-page 10 © 2009 Microchip Technology Inc.
PIC18F2423/2523/4423/4523
TABLE 1-1: DEVICE FEATURES
Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 16,384 32,768 16,384 32,768
Program Memory (Instructions) 8,192 16,384 8,192 16,384
Data Memory (Bytes) 768 1,536 768 1,536
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced
Capture/Compare/PWM Modules
Serial Communications MSSP,
Parallel Communications (PSP) No No Yes Yes
12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR,
Underflow (PWRT, OST),
MCLR
Programmable
High/Low-Voltage Detect
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions;
Instruction Set enabled
Packages 28-Pin PDIP
0011
Enhanced USART
RESET Instruction,
Stack Full, Stack
(optional), WDT
Ye s Ye s Ye s Ye s
83 with Extended
28-Pin SOIC
28-Pin QFN
MSSP,
Enhanced USART
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
75 Instructions;
83 with Extended
Instruction Set enabled
28-Pin PDIP
28-Pin SOIC
28-Pin QFN
MSSP,
Enhanced USART
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
75 Instructions;
83 with Extended
Instruction Set enabled
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
MSSP,
Enhanced USART
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
75 Instructions;
83 with Extended
Instruction Set enabled
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
© 2009 Microchip Technology Inc. DS39755C-page 11
PIC18F2423/2523/4423/4523
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS
/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
Data Latch
Data Memory
( 3.9 Kbytes )
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
PCLATU
PCU
OSC2/CLKO
(3)
/RA6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR
functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSARTComparator
MSSP
12-Bit
ADC
Timer2Timer1 Tim er3Timer0
CCP2
HLVD
CCP1
BOR
Data
EEPROM
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1
(3)
OSC2
(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
V
SS
MCLR
(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSO
OSC1/CLKI
(3)
/RA7
T1OSI
PORTE
MCLR/VPP/RE3
(2)
FIGURE 1-1: PIC18F2423/2523 (28-PIN) BLOCK DIAGRAM
DS39755C-page 12 © 2009 Microchip Technology Inc.
PIC18F2423/2523/4423/4523
Instruction
Decode and
Control
Data Latch
Data Memory
( 3.9 Kbytes )
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD0/PSP0
PCLATU
PCU
PORTE
MCLR/VPP/RE3
(2)
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR
functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).
:RD4/PSP4
EUSARTComparator
MSSP
12-Bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
HLVD
ECCP1
BOR
Data
EEPROM
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1
(3)
OSC2
(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
V
SS
MCLR
(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS
/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
OSC2/CLKO
(3)
/RA6
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
OSC1/CLKI
(3)
/RA7
FIGURE 1-2: PIC18F4423/4523 (40/44-PIN) BLOCK DIAGRAM
© 2009 Microchip Technology Inc. DS39755C-page 13
PIC18F2423/2523/4423/4523
TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
/VPP/RE3
MCLR
MCLR
VPP
RE3
OSC1/CLKI/RA7
OSC1
CLKI
RA7
OSC2/CLKO/RA6
OSC2
CLKO
RA6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
2
C=I2C™/SMBus
I
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PDIP,
SOIC
QFN
126
96
10 7
Pin
Typ e
I
P
I
I
I
I/O
O
O
I/O
Buffer
Type
ST
ST
ST
CMOS
TTL
—
—
TTL
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated with pin
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
General purpose I/O pin.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
DS39755C-page 14 © 2009 Microchip Technology Inc.
PIC18F2423/2523/4423/4523
TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
REF
CV
RA3/AN3/V
RA3
AN3
V
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
RA5/AN4/SS
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
REF+
REF+
/HLVDIN/
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
2
C=I2C™/SMBus
I
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PDIP,
SOIC
227
328
41
52
63
74
QFN
Pin
Buffer
Typ e
Type
I/OITTL
Analog
I/OITTL
Analog
I/O
TTL
I
Analog
I
Analog
O
Analog
I/O
TTL
I
Analog
I
Analog
I/O
I
O
I/O
TTL
I
Analog
I
TTL
I
Analog
O
PORTA is a bidirectional I/O port.
Digital I/O.
Analog Input 0.
Digital I/O.
Analog Input 1.
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
ST
ST
—
—
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
Digital I/O.
Analog Input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
Description
© 2009 Microchip Technology Inc. DS39755C-page 15
PIC18F2423/2523/4423/4523
TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
RB1/INT1/AN10
RB1
INT1
AN10
RB2/INT2/AN8
RB2
INT2
AN8
RB3/AN9/CCP2
RB3
AN9
(1)
CCP2
RB4/KBI0/AN11
RB4
KBI0
AN11
RB5/KBI1/PGM
RB5
KBI1
PGM
RB6/KBI2/PGC
RB6
KBI2
PGC
RB7/KBI3/PGD
RB7
KBI3
PGD
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
2
C=I2C™/SMBus
I
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PDIP,
SOIC
21 18
22 19
23 20
24 21
25 22
26 23
27 24
28 25
QFN
Pin
Typ e
I/O
I
I
I
I/O
I
I
I/O
I
I
I/O
I
I/O
I/O
I
I
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
Buffer
Type
TTL
ST
ST
Analog
TTL
ST
Analog
TTL
ST
Analog
TTL
Analog
ST
TTL
TTL
Analog
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
Digital I/O.
External Interrupt 0.
PWM Fault input for CCP1.
Analog Input 12.
Digital I/O.
External Interrupt 1.
Analog Input 10.
Digital I/O.
External Interrupt 2.
Analog Input 8.
Digital I/O.
Analog Input 9.
Capture 2 input/Compare 2 output/PWM2 output.
Digital I/O.
Interrupt-on-change pin.
Analog Input 11.
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
DS39755C-page 16 © 2009 Microchip Technology Inc.
PIC18F2423/2523/4423/4523
TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
T1OSI
(2)
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
RE3 — — — — See MCLR
SS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
V
V
DD 20 17 P — Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
2
C=I2C™/SMBus
I
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PDIP,
SOIC
11 8
12 9
13 10
14 11
15 12
16 13
17 14
18 15
QFN
Pin
Buffer
Typ e
Type
I/O
O
I
I/O
I
Analog
I/O
I/O
I/OSTST
I/O
I/O
I/O
I/O
I
I/O
I/OOST
I/O
O
I/O
I/O
I
I/O
PORTC is a bidirectional I/O port.
ST
—
ST
ST
ST
ST
ST
I
ST
ST
I
—
ST
—
ST
ST
ST
ST
2
2
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Digital I/O.
Synchronous serial clock input/output for SPI mode.
C
C
Synchronous serial clock input/output for I2C™ mode.
Digital I/O.
SPI data in.
I2C data I/O.
Digital I/O.
SPI data out.
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
/VPP/RE3 pin.
Description
© 2009 Microchip Technology Inc. DS39755C-page 17
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