Datasheet PIC18F2331, PIC18F2431, PIC18F4331, PIC18F4431 Datasheet

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PIC18F2331/2431/4331/4431

Data Sheet

28/40/44-Pin Enhanced Flash

Microcontrollers with nanoWatt Technology,

High-Performance PWM and A/D

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

PIC18F2331/2431/4331/4431

28/40/44-Pin Enhanced Flash Microcontrollers with

nanoWatt Technology, High-Performance PWM and A/D

14-Bit Power Control PWM Module:

• Up to 4 Channels with Complementary Outputs

• Edge or Center-Aligned Operation

• Flexible Dead-Band Generator

• Hardware Fault Protection Inputs

• Simultaneous Update of Duty Cycle and Period:

- Flexible Special Event Trigger output

Motion Feedback Module:

• Three Independent Input Capture Channels:

- Flexible operating modes for period and pulse-width measurement

- Special Hall sensor interface module

- Special Event Trigger output to other modules

• Quadrature Encoder Interface:

- 2-phase inputs and one index input from encoder

- High and low position tracking with direction status and change of direction interrupt

- Velocity measurement

High-Speed, 200 ksps 10-Bit A/D Converter:

• Up to 9 Channels

• Simultaneous, Two-Channel Sampling

• Sequential Sampling: 1, 2 or 4 Selected Channels

• Auto-Conversion Capability

• 4-Word FIFO with Selectable Interrupt Frequency

• Selectable External Conversion Triggers

• Programmable Acquisition Time

Flexible Oscillator Structure:

• Four Crystal modes up to 40 MHz

• Two External Clock modes up to 40 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies: 31 kHz to 8 MHz

- OSCTUNE can compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown of device if clock fails

Program Memory Data Memory

Device

PIC18F2331 8192 4096 768 256 24 5 2 Y Y Y Y 6 1/3

PIC18F2431 16384 8192 768 256 24 5 2 Y Y Y Y 6 1/3

PIC18F4331 8192 4096 768 256 36 9 2 Y Y Y Y 8 1/3

PIC18F4431 16384 8192 768 256 36 9 2 Y Y Y Y 8 1/3

Flash

(bytes)

# Single-Word

Instructions

SRAM (bytes)

EEPROM

(bytes)

I/O

Power-Managed Modes:

• Run: CPU on, Peripherals on

• Idle: CPU off, Peripherals on

• Sleep: CPU off, Peripherals off

• Idle mode Currents Down to 5.8 μA, Typical

• Sleep Current Down to 0.1 μA, Typical

• Timer1 Oscillator, 1.8 μA, Typical, 32 kHz, 2V

• Watchdog Timer (WDT), 2.1 μA, typical

• Oscillator Two-Speed Start-up

Peripheral Highlights:

• High-Current Sink/Source 25 mA/25 mA

• Three External Interrupts

• Two Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 6.25 ns (T

- Compare is 16-bit, max. resolution 100 ns (T

- PWM output: PWM resolution is 1 to 10 bits

• Enhanced USART module:

- Supports RS-485, RS-232 and LIN 1.2

- Auto-wake-up on Start bit

- Auto-Baud Detect

• RS-232 Operation using Internal Oscillator Block (no external crystal required)

Special Microcontroller Features:

• 100,000 Erase/Write Cycle Enhanced Flash Program Memory, Typical

• 1,000,000 Erase/Write Cycle Data EEPROM Memory, Typical

• Flash/Data EEPROM Retention: 100 Years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins:

- Drives PWM outputs safely when debugging

SSP

10-Bit

A/D (ch)

CCP

SPI

Slave

C™

EUSART

Encoder

Quadrature

14-Bit

PWM

(ch)

Timers

8/16-Bit

CY/16)

CY)

PIC18F2331/2431/4331/4431

Pin Diagrams

28-Pin SPDIP, SOIC

MCLR/VPP/RE3

RA2/AN2/V

RA3/AN3/V

REF-/CAP1/INDX

REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI/T5CKI/INT0

RA0/AN0

RA1/AN1

AVSS

7 8

Note 1: Low-Voltage Programming must be enabled.

28-Pin QFN

22 21

PIC18F2331/2431

(1)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM

RB4/KBI0/PWM5

RB3/PWM3

RB2/PWM2

RB1/PWM1

RB0/PWM0

VSS

RC7/RX/DT/SDO

RC6/TX/CK/SS

RC5/INT2/SCK/SCL

RC4/INT1/SDI/SDA

(1)

RA0/AN0

RA1/AN1

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM

RA2/AN2/VREF-/CAP1/INDX

RA3/AN3/V

Note 1: Low-Voltage Programming must be enabled.

REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

V VSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

MCLR/VPP/RE3

28 1 2 3 4 5 6 7

RC0/T1OSO/T1CKI

PIC18F2331

PIC18F2431

1011121314

RC2/CCP1/FLTB

RC1/T1OSI/CCP2/FLTA

RC4/INT1/SDI/SDA

RC3/T0CKI/T5CKI/INT0

RC5/INT2/SCK/SCL

RB4/KBI0/PWM5

21 20 19 18 17 16 15

RC6/TX/CK/SS

RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 V

VSS RC7/RX/DT/SDO

Pin Diagrams (Continued)

40-Pin PDIP

PIC18F2331/2431/4331/4431

MCLR/VPP/RE3

RA2/AN2/V RA3/AN3/V

REF-/CAP1/INDX REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

RA5/AN5/LVDIN

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI

(1)

/T5CKI

RD0/T0CKI/T5CKI

RA0/AN0 RA1/AN1

RE0/AN6 RE1/AN7 RE2/AN8

AVSS

(1)

/INT0

RD1/SDO

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29

PIC18F4331/4431

28 27 26 25 24 23 22 21

RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2

RB1/PWM1 RB0/PWM0

V VSS RD7/PWM7 RD6/PWM6

RD5/PWM4 RD4/FLTA

(4)

(3)

RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK

RC4/INT1/SDI

(1)

/SDA

/SCL

RD3/SCK/SCL RD2/SDI/SDA

(2)

(1)

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-Voltage Programming must be enabled.

3: RD4 is the alternate pin for FLTA

4: RD5 is the alternate pin for PWM4.

PIC18F2331/2431/4331/4431

Pin Diagrams (Continued)

44-Pin TQFP

RC7/RX/DT/SDO

RD4/FLTA

RD5/PWM4

RD6/PWM6 RD7/PWM7

VDD RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3

(1)

/SCL

/SDA

(1)

RC6/TX/CK/SS

RC5/INT2/SCK

RC4/INT1/SDI

RD3/SCK/SCL

4443424140

(3) (4)

1 2 3 4 5 6 7 8 9 10 11

121314

PIC18F4331 PIC18F4431

(2)

(1)

RD2/SDI/SDA

RD1/SDO

RD0/T0CKI/T5CKI

1819202122

/VPP/RE3

/INT0

/T5CKI

RC3/T0CKI

RA0/AN0

RC2/CCP1/FLTB

363435

RA1/AN1

RC1/T1OSI/CCP2/FLTA

33 32 31 30 29 28 27 26 25 24

NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7

AV AVDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB

RB7/KBI3/PGD

RB6/KBI2/PGC

MCLR

RB4/KBI0/PWM5

RB5/KBI1/PWM4/PGM

REF-/CAP1/INDX

RA2/AN2/V

RA3/AN3/VREF+/CAP2/QEA

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-Voltage Programming must be enabled.

3: RD4 is the alternate pin for FLTA

4: RD5 is the alternate pin for PWM4.

Pin Diagrams (Continued)

44-Pin QFN

PIC18F2331/2431/4331/4431

RC7/RX/DT/SDO

RD4/FLTA

RD5/PWM4

RD6/PWM6 RD7/PWM7

V VDD

AVDD RB0/PWM0 RB1/PWM1 RB2/PWM2

RD2/SDI/SDA

RB6/KBI2/PGC

RD1/SDO

RB7/KBI3/PGD

/INT0

(1)

/T5CKI

(1)

RD0/T0CKI/T5CKI

RC3/T0CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

363435

1819202122

RA1/AN1

RA0/AN0

/VPP/RE3

MCLR

REF-/CAP1/INDX

RC0/T1OSO/T1CKI

33 32 31 30 29 28 27 26 25 24 23

OSC2/CLKO/RA6 OSC1/CLKI/RA7

V AVSS

AVDD VDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB

(1)

/SCL

/SDA

(1)

RC6/TX/CK/SS

RC5/INT2/SCK

RC4/INT1/SDI

RD3/SCK/SCL

4443424140

(3) (4)

1 2 3 4 5

PIC18F4331

PIC18F4431

7 8 9 10 11

121314

RB3/PWM3

(2)

RB4/KBI0/PWM5

RB5/KBI1/PWM4/PGM

RA2/AN2/V

RA3/AN3/VREF+/CAP2/QEA

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-Voltage Programming must be enabled.

3: RD4 is the alternate pin for FLTA

4: RD5 is the alternate pin for PWM4.

PIC18F2331/2431/4331/4431

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 33

4.0 Reset .......................................................................................................................................................................................... 47

5.0 Memory Organization ................................................................................................................................................................. 59

6.0 Flash Program Memory.............................................................................................................................................................. 77

7.0 Data EEPROM Memory ............................................................................................................................................................. 87

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 91

9.0 Interrupts .................................................................................................................................................................................... 93

10.0 I/O Ports ................................................................................................................................................................................... 109

11.0 Timer0 Module ......................................................................................................................................................................... 135

12.0 Timer1 Module ......................................................................................................................................................................... 139

13.0 Timer2 Module ......................................................................................................................................................................... 145

14.0 Timer5 Module ......................................................................................................................................................................... 147

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 153

16.0 Motion Feedback Module ......................................................................................................................................................... 159

17.0 Power Control PWM Module .................................................................................................................................................... 181

18.0 Synchronous Serial Port (SSP) Module ................................................................................................................................... 213

19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 223

20.0 10-Bit High-Speed Analog-to-Digital Converter (A/D) Module ................................................................................................. 245

21.0 Low-Voltage Detect .................................................................................................................................................................. 263

22.0 Special Features of the CPU.................................................................................................................................................... 269

23.0 Instruction Set Summary .......................................................................................................................................................... 289

24.0 Development Support............................................................................................................................................................... 331

25.0 Electrical Characteristics .......................................................................................................................................................... 335

26.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 371

27.0 Packaging Information.............................................................................................................................................................. 373

Appendix A: Revision History............................................................................................................................................................. 381

Appendix B: Device Differences......................................................................................................................................................... 381

Appendix C: Conversion Considerations ........................................................................................................................................... 382

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 382

Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 383

Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 383

Index .................................................................................................................................................................................................. 385

The Microchip Web Site..................................................................................................................................................................... 395

Customer Change Notification Service .............................................................................................................................................. 395

Customer Support .............................................................................................................................................................................. 395

Reader Response .............................................................................................................................................................................. 396

Product Identification System............................................................................................................................................................. 397

PIC18F2331/2431/4331/4431

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

PIC18F2331/2431/4331/4431

NOTES:

PIC18F2331/2431/4331/4431

1.0 DEVICE OVERVIEW

This document contains device specific information for the following devices:

• PIC18F2331 • PIC18F4331

• PIC18F2431 • PIC18F4431

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price, with the addition of high endurance enhanced Flash program memory and a high-speed 10-bit A/D Converter. On top of these features, the PIC18F2331/2431/4331/4431 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power control and motor control applications. These special peripherals include:

• 14-Bit Resolution Power Control PWM module (PCPWM) with Programmable Dead-time Insertion

• Motion Feedback Module (MFM), including a 3-Channel Input Capture (IC) module and Quadrature Encoder Interface (QEI)

• High-Speed 10-Bit A/D Converter (HSADC)

The PCPWM can generate up to eight complementary PWM outputs with dead-band time insertion. Overdrive current is detected by off-chip analog comparators or the digital Fault inputs (FLTA

The MFM Quadrature Encoder Interface provides precise rotor position feedback and/or velocity measurement. The MFM 3x input capture or external interrupts can be used to detect the rotor state for electrically commutated motor applications using Hall sensor feedback, such as BLDC motor drives.

PIC18F2331/2431/4331/4431 devices also feature Flash program memory and an internal RC oscillator with built-in LP modes.

1.1 New Core Features

1.1.1 nanoWatt Technology

All of the devices in the PIC18F2331/2431/4331/4431 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled, but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements.

, FLTB).

• On-the-Fly Mode Switching: The power- managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 μA, respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2331/2431/4331/4431 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include:

• Four Crystal modes, using crystals or ceramic resonators.

• Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).

• Two External RC Oscillator modes, with the same pin options as the External Clock modes.

• An internal oscillator block, which provides an 8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and V as well as a range of 6 user-selectable clock frequencies (from 125 kHz to 4 MHz) for a total of 8 clock frequencies.

Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. This allows for code execution during what would otherwise be the clock start-up interval, and can even allow an application to perform routine background activities and return to Sleep without returning to full power operation.

DD),

PIC18F2331/2431/4331/4431

1.2 Other Special Features

• Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years.

• Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.

• Power Control PWM Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown on Fault detection and auto-restart to reactivate outputs once the condition has cleared.

• Enhanced USART: This serial communication module is capable of standard RS-232 operation using the internal oscillator block, removing the need for an external crystal (and its accompanying power requirement) in applications that talk to the outside world. This module also includes Auto-Baud Detect and LIN capability.

• High-Speed 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead.

• Motion Feedback Module (MFM): This module features a Quadrature Encoder Interface (QEI) and an Input Capture (IC) module. The QEI accepts two phase inputs (QEA, QEB) and one index input (INDX) from an incremental encoder. The QEI supports high and low precision position tracking, direction status and change of direction interrupt and velocity measurement. The input capture features 3 channels of independent input capture with Timer5 as the time base, a Special Event Trigger to other modules and an adjustable noise filter on each IC input.

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes, that is stable across operating voltage and temperature.

PIC18F2331/2431/4331/4431

1.3 Details on Individual Family Members

Devices in the PIC18F2331/2431/4331/4431 family are available in 28-pin (PIC18F2331/2431) and 40/44-pin (PIC18F4331/4431) packages. The block diagram for the two groups is shown in Figure 1-1.

The devices are differentiated from each other in three ways:

1. Flash program memory (8 Kbytes for PIC18F2331/4331 devices, 16 Kbytes for PIC18F2431/4431).

2. A/D channels (5 for PIC18F2331/2431 devices, 9 for PIC18F4331/4431 devices).

3. I/O ports (3 bidirectional ports on PIC18F2331/ 2431 devices, 5 bidirectional ports on PIC18F4331/4431 devices).

All other features for devices in this family are identical. These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and Table 1-3.

TABLE 1-1: DEVICE FEATURES

Features PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 8192 16384 8192 16384

Program Memory (Instructions) 4096 8192 4096 8192

Data Memory (Bytes) 768 768 768 768

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 22 22 34 34

I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM modules 2 2 2 2

14-Bit Power Control PWM (6 Channels) (6 Channels) (8 Channels) (8 Channels)

Motion Feedback Module (Input Capture/Quadrature Encoder Interface)

Serial Communications SSP,

10-Bit High-Speed Analog-to-Digital Converter module

Resets (and Delays) POR, BOR,

Programmable Low-Voltage Detect Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions

Packages 28-pin SPDIP

1 QEI

3x IC

Enhanced USART

5 Input Channels 5 Input Channels 9 Input Channels 9 Input Channels

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SOIC

28-pin QFN

1 QEI

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SPDIP

28-pin SOIC

28-pin QFN

1 QEI

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

1 QEI

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

PIC18F2331/2431/4331/4431

FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM

Data Bus<8>

Address Latch

Program

Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

T1OSI

T1OSO

/VPP

MCLR

Table Pointer<21>

Table Latch

Instruction

Decode &

Control

Timing

Generation

4X PLL

Precision Band Gap Reference

inc/dec logic

PCLATH

PCLATU

PCU

PCH PCL

Program Counter

31 Level Stack

ROM Latch

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

Power-Managed

Mode Logic

Decode

BITOP

BSR

Data Latch

Data RAM

(768 bytes)

Address Latch

Address<12>

FSR0 FSR1 FSR2

inc/dec

Bank 0, F

logic

PRODLPRODH

8 x 8 Multiply

ALU<8>

PORTA

RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7

PORTB

PORTC

PORTE

RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO

INTRC

VDD, VSS

Timer0 Timer1 Timer2

Data EE

CCP1 CCP2

OSC

Synchronous

Serial Port

Timer5

EUSART

HS 10-Bit

ADC

PCPWM

MCLR/VPP/RE3

(1,2)

AVDD, AVSS

MFM

Note 1: RE3 input pin is only enabled when MCLRE fuse is programmed to ‘0’.

2: RE3 is available only when MCLR is disabled.

PIC18F2331/2431/4331/4431

FIGURE 1-2: PIC18F4331/4431 BLOCK DIAGRAM

Address Latch

Program Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

T1OSI

T1OSO

/VPP

MCLR

VDD, VSS

Table Pointer<21>

inc/dec logic

Table Latch

Instruction

Decode &

Control

Timing

Generation

4X PLL

Precision

Band Gap

Reference

PCLATH

PCLATU

PCH PCL

PCU Program Counter

31 Level Stack

ROM Latch

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Power-Managed

Mode Logic

INTRC

OSC

Decode

BITOP

BSR

Data Latch

Data RAM

(768 bytes)

Address Latch

Address<12>

12 4

FSR0 FSR1 FSR2

inc/dec

logic

8 x 8 Multiply

ALU<8>

Data Bus<8>

Bank 0, F

PRODLPRODH

PORTA

PORTB

PORTC

PORTD

PORTE

RA0/AN0 RA1/AN1

RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7

RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO

RD0/IT0CKI/T5CKI RD1/SDO RD2/SDI/SDA RD3/SCK/SCL RD4/FLTA

RD5/PWM4 RD6/PWM6 RD7/PWM7

RE0/AN6

RE1/AN7

RE2/AN8

MCLR/VPP/RE3

(2)

(4)

(3)

(1)

Timer0 Timer1 Timer2

Data EE

CCP1

CCP2

Synchronous

Serial Port

Timer5

EUSART

HS 10-Bit

ADC

PCPWM

AVDD, AVSS

MFM

Note 1: RE3 is available only when MCLR is disabled.

2: RD4 is the alternate pin for FLTA

3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively. 4: RD5 is the alternate pin for PWM4.

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

SPDIP,

SOIC

QFN

Typ e

Buffer

Type

Description

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA2 AN2 V CAP1 INDX

RA3/AN3/V

RA3 AN3 V CAP2 QEA

RA4/AN4/CAP3/QEB

RA4 AN4 CAP3 QEB

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF-/CAP1/INDX

REF-

REF+/CAP2/QEA

REF+

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

126

10 7

227

328

CMOS

I/O

TTL

I/O

TTL

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

Analog

Analog I I

I/O

TTL

Analog I

Analog I I

I/O

TTL

Analog I I

DD)

Master Clear (input) or programming voltage (input).

—

ST ST

Master Clear (Reset) input. This pin is an active-low Reset to the device. High-voltage ICSP™ programming enable pin. Digital input. Available only when MCLR

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input. Input capture pin 1. Quadrature Encoder Interface index input pin.

Digital I/O. Analog input 3. A/D reference voltage (high) input. Input capture pin 2. Quadrature Encoder Interface channel A input pin.

Digital I/O. Analog input 4. Input capture pin 3. Quadrature Encoder Interface channel B input pin.

is disabled.

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/PWM0

RB0 PWM0

RB1/PWM1

RB1 PWM1

RB2/PWM2

RB2 PWM2

RB3/PWM3

RB3 PWM3

RB4/KBI0/PWM5

RB4 KBI0 PWM5

RB5/KBI1/PWM4/PGM

RB5 KBI1 PWM4 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

SPDIP,

SOIC

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Buffer

Typ e

Type

I/OOTTL

I/O

DD)

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O.

TTL

TTL TTL TTL

TTL TTL

PWM output 0.

Digital I/O. PWM output 1.

Digital I/O. PWM output 2.

Digital I/O. PWM output 3.

Digital I/O. Interrupt-on-change pin. PWM output 5.

Digital I/O. Interrupt-on-change pin. PWM output 4. Low-Voltage ICSP™ Programming entry pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T1CKI

RC0 T1OSO T1CKI

RC1/T1OSI/CCP2/FLTA

RC1 T1OSI CCP2 FLTA

RC2/CCP1/FLTB

RC2 CCP1 FLTB

RC3/T0CKI/T5CKI/INT0

RC3 T0CKI T5CKI INT0

RC4/INT1/SDI/SDA

RC4 INT1 SDI SDA

RC5/INT2/SCK/SCL

RC5 INT2 SCK SCL

RC6/TX/CK/SS

RC6 TX CK SS

RC7/RX/DT/SDO

RC7 RX DT SDO

SS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

DD 7, 20 4, 17 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

SPDIP,

SOIC

11 8

12 9

13 10

14 11

15 12

16 13

17 14

18 15

QFN

Typ e

I/O

I/O I/O

I/O

I I I

I/O

I I

I/O

I/O I/O

I/O

DD)

Buffer

Type

—

CMOS

ST ST

ST ST ST

ST ST ST ST

—

TTL

ST ST ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O. Timer1 oscillator output. Timer1 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM2 output. Fault interrupt input pin.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Fault interrupt input pin.

Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External interrupt 0.

Digital I/O. External interrupt 1. SPI data in.

C™ data I/O.

Digital I/O. External interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). SPI slave select input.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). SPI data out.

C mode.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS

Pin Name

MCLR

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

11818

13 30 32

14 31 33

Type

I/O

DD)

Buffer

Type

Master Clear (input) or programming voltage (input).

CMOS

TTL

—

TTL

Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Available only when MCLR

Oscillator crystal or external clock input.

Oscillator crystal or clock output.

Description

is disabled.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V INDX

RA3/AN3/V CAP2/QEA

RA4/AN4/CAP3/QEB

RA5/AN5/LVDIN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

REF-/CAP1/

RA2 AN2 V

REF-

CAP1 INDX

REF+/

RA3 AN3 V

REF+

CAP2 QEA

RA4 AN4 CAP3 QEB

RA5 AN5 LVD IN

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

21919

32020

42121

52222

62323

72424

Type

I/OITTL

I/O

I I I I

I/O

I I I I

I/O

I I I

I/O

I I

DD)

Buffer

Type

Analog

TTL Analog Analog

ST ST

TTL Analog Analog

ST ST

TTL Analog

ST ST

TTL Analog Analog

Description

PORTA is a bidirectional I/O port.

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input. Input capture pin 1. Quadrature Encoder Interface index input pin.

Digital I/O. Analog input 3. A/D reference voltage (high) input. Input capture pin 2. Quadrature Encoder Interface channel A input pin.

Digital I/O. Analog input 4. Input capture pin 3. Quadrature Encoder Interface channel B input pin.

Digital I/O. Analog input 5. Low-Voltage Detect input.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/PWM0

RB0 PWM0

RB1/PWM1

RB1 PWM1

RB2/PWM2

RB2 PWM2

RB3/PWM3

RB3 PWM3

RB4/KBI0/PWM5

RB4 KBI0 PWM5

RB5/KBI1/PWM4/ PGM

RB5 KBI1 PWM4 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

33 8 9

34 9 10

35 10 11

36 11 12

37 14 14

38 15 15

39 16 16

40 17 17

Buffer

Type

I/OOTTL

I/O

DD)

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O.

TTL

TTL TTL TTL

TTL TTL

PWM output 0.

Digital I/O. PWM output 1.

Digital I/O. PWM output 2.

Digital I/O. PWM output 3.

Digital I/O. Interrupt-on-change pin. PWM output 5.

Digital I/O. Interrupt-on-change pin. PWM output 4. Low-Voltage ICSP™ Programming entry pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

Pin Number

PDIP TQFP QFN

15 32 34 RC0 T1OSO T1CKI

RC1/T1OSI/CCP2/

16 35 35

FLTA

RC1 T1OSI CCP2 FLTA

RC2/CCP1/FLTB

17 36 36 RC2 CCP1 FLTB

RC3/T0CKI/T5CKI/

18 37 37

INT0

RC3

(1)

T0CKI

(1)

T5CKI INT0

RC4/INT1/SDI/SDA

23 42 42 RC4 INT1

(1)

SDI

(1)

SDA

RC5/INT2/SCK/SCL

24 43 43 RC5 INT2

(1)

SCK

(1)

SCL

RC6/TX/CK/SS

25 44 44 RC6 TX CK SS

RC7/RX/DT/SDO

26 1 1 RC7 RX DT SDO

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4.

Type

I/O

I/O I/O

I/O

I I I

I/O

I I

I/O

I I/O I/O

I/O

I I/O

DD)

Buffer

Type

—

CMOS

ST ST

ST ST ST

ST ST ST ST

— ST ST

ST ST ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O. Timer1 oscillator output. Timer1 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM2 output. Fault interrupt input pin.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Fault interrupt input pin.

Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External interrupt 0.

Digital I/O. External interrupt 1. SPI data in.

C™ data I/O.

Digital I/O. External interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). SPI slave select input.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). SPI data out.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/T0CKI/T5CKI

RD0 T0CKI T5CKI

RD1/SDO

RD1 SDO

RD2/SDI/SDA

RD2 SDI SDA

RD3/SCK/SCL

RD3 SCK SCL

RD4/FLTA

RD4

(2)

FLTA

RD5/PWM4

RD5

(3)

PWM4

RD6/PWM6

RD6 PWM6

RD7/PWM7

RD7 PWM7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Type

I/O

I I

I/OOST

I/O

I/O I/O I/O

I/OIST

I/OOST

DD)

Buffer

Type

ST ST ST

—

ST ST ST

TTL

Description

PORTD is a bidirectional I/O port.

Digital I/O. Timer0 external clock input. Timer5 input clock.

Digital I/O. SPI data out.

Digital I/O. SPI data in.

C™ data I/O.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. Fault interrupt input pin.

Digital I/O. PWM output 4.

Digital I/O. PWM output 6.

Digital I/O. PWM output 7.

C mode.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN6

RE0 AN6

RE1/AN7

RE1 AN7

RE2/AN8

RE2 AN8

VSS 12, 316, 29 6, 30, 31P — Ground reference for logic and I/O pins.

DD 11 ,

NC — 12, 13,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

82525

92626

10 27 27

7, 28 7, 8,

28, 29

33, 34

Buffer

Type

PORTE is a bidirectional I/O port.

I/OIST

Analog

I/OIST

Analog

I/OIST

Analog

P — Positive supply for logic and I/O pins.

13 NC NC No connect.

DD)

Digital I/O. Analog input 6.

Digital I/O. Analog input 7.

Digital I/O. Analog input 8.

Description

PIC18F2331/2431/4331/4431

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the Configuration bits FOSC3:FOSC0 in Configuration Register 1H to select one of these 10 modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL Enabled

5. RC External Resistor/Capacitor with

OSC/4 Output on RA6

6. RCIO External Resistor/Capacitor with

I/O on RA6

7. INTIO1 Internal Oscillator with F

Output on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections.

The oscillator design requires the use of a parallel cut crystal.

Note: Use of a series cut crystal may give a

frequency out of the crystal manufacturers’ specifications.

OSC/4

OSC/4 Output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)

(1)

Note 1: See Table 2-1 and Table 2-2 for initial values of

C1 and C2.

2: A series resistor (R

strip cut crystals.

3: R

OSC1

Internal

XTAL

(2)

OSC2

F varies with the oscillator mode chosen.

(3)

PIC18FXXXX

S) may be required for AT

Logic

Sleep

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

Capacitor values are for design guidance only.

These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized.

Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected

DD and temperature range for the application.

See the notes following Table 2-2 for additional information.

Resonators Used:

56 pF 47 pF 33 pF

27 pF 22 pF

56 pF 47 pF 33 pF

27 pF 22 pF

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

PIC18F2331/2431/4331/4431

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc Type

Crystal

Freq

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected

DD and temperature range for the application.

See the notes following this table for additional information.

Crystals Used:

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher capacitance increases the

stability of oscillator, but also increases the start-up time.

2: When operating below 3V V

using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

Typical Capacitor Values

Tested:

C1 C2

DD, or when

An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC CONFIGURATION)

Clock from Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 HSPLL

A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals.

The HSPLL mode makes use of the HS Oscillator mode for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz.

The PLL is enabled only when the oscillator Configuration bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled.

FIGURE 2-3: PLL BLOCK DIAGRAM

HS Osc Enable

PLL Enable

(from Configuration Register 1H)

OSC2

OSC1

HS Mode

Crystal

Osc

FOUT

÷4

Phase

Comparator

Loop Filter

VCO

SYSCLK

MUX

PIC18F2331/2431/4331/4431

2.4 External Clock Input

The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT

OPERATION (EC CONFIGURATION)

Clock from Ext. System

OSC/4

The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT

Clock from Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

OPERATION (ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

2.5 RC Oscillator

For timing insensitive applications, the RC and RCIO device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low

EXT values. The user also needs to take into account

C variation due to tolerance of external R and C components used. Figure 2-6 shows how the R/C combination is connected.

In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic.

FIGURE 2-6: RC OSCILLATOR MODE

REXT

CEXT

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

The RCIO Oscillator mode (Figure 2-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).

EXT) and capacitor (CEXT) values and the

VDD

OSC1

PIC18FXXXX

OSC2/CLKO

OSC/4

EXT > 20 pF

Internal

Clock

FIGURE 2-7: RCIO OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

RA6

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

I/O (OSC2)

EXT > 20 pF

Internal

Clock

PIC18FXXXX

PIC18F2331/2431/4331/4431

2.6 Internal Oscillator Block

The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator (INTRC), which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in Section 22.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 2-2).

2.6.2 INTRC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency.

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at the factory, but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range.

When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8*32μs = 256 μs). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency.

2.6.1 INTIO MODES

Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F while OSC1 functions as RA7 for digital input and output.

• In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.

OSC/4,

PIC18F2331/2431/4331/4431

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TUN5:TUN0: Frequency Tuning bits

011111 = Maximum frequency

• •

000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111

• •

• • 100000 = Minimum frequency

PIC18F2331/2431/4331/4431

2.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the PIC18F2331/2431/ 4331/4431 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2331/ 2431/4331/4431 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes.

Essentially, there are three clock sources for these devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter.

The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode.

PIC18F2331/2431/4331/4431 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC).

Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in Section 12.2 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2331/2431/4331/4431 devices are shown in Figure 2-8. See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 22.1 “Configuration Bits” for Configuration register details.

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several aspects of the system clock’s operation, both in full power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in power-managed modes. The available clock sources are the primary clock (defined in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a power-managed mode of operation. The SCS bits are cleared on all forms of Reset.

The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator’s output.

The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out, and the primary clock is providing the system clock in

primary clock modes. The IOFS bit indicates when the

internal oscillator block has stabilized, and is providing the system clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is

providing the system clock in secondary clock modes. In

power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable.

The IDLEN bit controls the selective shutdown of the controller’s CPU in power-managed modes. The use of these bits is discussed in more detail in Section 3.0

“Power-Managed Modes”

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before executing the SLEEP instruction, or a very long delay may occur while the Timer1 oscillator starts.

PIC18F2331/2431/4331/4431

FIGURE 2-8: PIC18F2331/2431/4331/4431 CLOCK DIAGRAM

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

Secondary Oscillator

T1OSCEN Enable Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

INTRC Source

PIC18F2331/2431/4331/4431

8 MHz

4 MHz

2 MHz

1 MHz

8 MHz

(INTOSC)

Postscaler

500 kHz

250 kHz

125 kHz

31 kHz

4 x PLL

OSCCON<6:4>

111

110

101

100

MUX

011

010

001

000

CONFIG1H <3:0>

HSPLL

LP, XT, HS, RC, EC

T1OSC

Clock Source Option for other Modules

Internal Oscillator

Clock

Control

MUX

OSCCON<1:0>

Peripherals

CPU

IDLEN

WDT, FSCM

PIC18F2331/2431/4331/4431

REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Idle mode enabled; CPU core is not clocked in power-managed modes 0 = Run mode enabled; CPU core is clocked in power-managed modes

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz (default) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (INTRC source drives clock directly)

bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block (RC modes) 01 = Timer1 oscillator (Secondary modes) 00 = Primary oscillator (Sleep and PRI_IDLE modes)

(1)

R-0 R/W-0 R/W-0

(1)

Note 1: Depends on the state of the IESO bit in Configuration Register 1H.

PIC18F2331/2431/4331/4431

2.7.2 OSCILLATOR TRANSITIONS

The PIC18F2331/2431/4331/4431 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

2.8 Effects of Power-Managed Modes on the Various Clock Sources

When the device executes a SLEEP instruction, the system is switched to one of the power-managed modes, depending on the state of the IDLEN and SCS1:SCS0 bits of the OSCCON register. See Section 3.0 “Power-Managed Modes” for details.

When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1.

In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the system clock source. The INTRC output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 22.2 “Watchdog

Timer (WDT)” through Section 22.4 “Fail-Safe Clock Monitor”). The INTOSC output at 8 MHz may be used

directly to clock the system, or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents).

Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a RealTime Clock. Other features may be operating that do not require a system clock source (i.e., SSP slave, INTx pins, A/D conversions and others).

2.9 Power-up Delays

Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances, and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.1 “Power-on Reset (POR)” through Section 4.5 “Brown-out Reset (BOR)”.

The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 25-8), if enabled, in Configuration Register 2L. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency.

There is a delay of 5 to 10 μs following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source.

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode OSC1 Pin OSC2 Pin

RC, INTIO1 Floating, external resistor

should pull high

RCIO, INTIO2 Floating, external resistor

should pull high

ECIO Floating, pulled by external clock Configured as PORTA, bit 6

EC Floating, pulled by external clock At logic low (clock/4 output)

LP, XT and HS Feedback inverter disabled at

quiescent voltage level

Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR

At logic low (clock/4 output)

Configured as PORTA, bit 6

Feedback inverter disabled at quiescent voltage level

Reset.

PIC18F2331/2431/4331/4431

NOTES:

PIC18F2331/2431/4331/4431

3.0 POWER-MANAGED MODES

The PIC18F2331/2431/4331/4431 devices offer a total of six operating modes for more efficient power management (see Table 3-1). These operating modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).

There are three categories of power-managed modes:

• Sleep mode

• Idle modes

• Run modes

These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or INTOSC multiplexer); the Sleep mode does not use a clock source.

The clock switching feature offered in other PIC18 devices (i.e., using the Timer1 oscillator in place of the primary oscillator), and the Sleep mode offered by all

devices (where all system clocks are stopped), are

PIC both offered in the PIC18F2331/2431/4331/4431 devices (SEC_RUN and Sleep modes, respectively). However, additional power-managed modes are available that allow the user greater flexibility in determining what portions of the device are operating. The power-managed modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these operating modes.

For PIC18F2331/2431/4331/4431 devices, the powermanaged modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset or a WDT timeout (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power-managed Run modes may also exit to Sleep mode or their corresponding Idle mode.

3.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires deciding if the CPU is to be clocked or not, and selecting a clock source. The IDLEN bit controls CPU clocking, while the SCS1:SCS0 bits select a clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1.

3.1.1 CLOCK SOURCES

The clock source is selected by setting the SCS bits of the OSCCON register. Three clock sources are available for use in power-managed Idle modes: the primary clock (as configured in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The secondary and internal oscillator block sources are available for the power-managed modes (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source).

TABLE 3-1: POWER-MANAGED MODES

Mode

Sleep 000Off Off None – All clocks are disabled

PRI_RUN 000Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC

SEC_RUN 001Clocked Clocked Secondary – Timer1 Oscillator

RC_RUN 01xClocked Clocked Internal Oscillator Block

PRI_IDLE 100Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC

SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator

RC_IDLE 11xOff Clocked Internal Oscillator Block

Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

OSCCON<7,1:0> Module Clocking

Available Clock and Oscillator Source

IDLEN SCS1:SCS0 CPU Peripherals

This is the normal full power execution mode.

(1)

PIC18F2331/2431/4331/4431

3.1.2 ENTERING POWER-MANAGED MODES

In general, entry, exit and switching between powermanaged clock sources requires clock source switching. In each case, the sequence of events is the same.

Any change in the power-managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power-managed clock sources; the primary clock (as defined in Configuration Register 1H), the secondary clock (the Timer1 oscillator) and the internal oscillator block (used in RC modes). Modifying the SCS bits will have no effect until a SLEEP instruction is executed. Entry to the power-managed mode is triggered by the execution of a SLEEP instruction.

Figure 3-5 shows how the system is clocked while switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. Eight clock cycles from the new clock source are counted to synchronize with the new clock source. After eight clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. The actual length of the pause is between eight and nine clock periods from the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources.

Three bits indicate the current clock source: OSTS and IOFS in the OSCCON register, and T1RUN in the T1CON register. Only one of these bits will be set while in a power-managed mode other than PRI_RUN. When the OSTS bit is set, the primary clock is providing the system clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source and is providing the system clock. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If none of these bits are set, then either the INTRC clock source is clocking the system, or the INTOSC source is not yet stable.

If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering a power-managed RC mode (same frequency) would clear the OSTS bit.

Note 1: Caution should be used when modifying

a single IRCF bit. If V is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep mode. Executing a SLEEP instruction is simply a trigger to place the controller into a power-managed mode selected by the OSCCON register, one of which is Sleep mode.

DD is less than 3V, it

3.1.3 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the SLEEP instruction is determined by the settings of the IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by these same bits at that time. If the bits have changed, the device will enter the new power-managed mode specified by the new bit settings.

3.1.4 COMPARISONS BETWEEN RUN AND IDLE MODES

Clock source selection for the Run modes is identical to the corresponding Idle modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register are used to switch to a different clock source. As a result, if there is a change of clock source at the time a SLEEP instruction is executed, a clock switch will occur.

In Idle modes, the CPU is not clocked and is not running. In Run modes, the CPU is clocked and executing code. This difference modifies the operation of the WDT when it times out. In Idle modes, a WDT time-out results in a wake from power-managed modes. In Run modes, a WDT time-out results in a WDT Reset (see Table 3-2).

During a wake-up from an Idle mode, the CPU starts executing code by entering the corresponding Run mode until the primary clock becomes ready. When the primary clock becomes ready, the clock source is automatically switched to the primary clock. The IDLEN and SCS bits are unchanged during and after the wake-up.

Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode).

PIC18F2331/2431/4331/4431

TABLE 3-2: COMPARISON BETWEEN POWER-MANAGED MODES

Power-Managed

Mode

Sleep Not clocked (not running) Wake-up Not clocked None or INTOSC multiplexer if

Any Idle mode Not clocked (not running) Wake-up Primary, secondary or

Any Run mode Secondary or INTOSC

CPU is Clocked by ...

multiplexer

WDT Time-out

Causes a ...

Reset Secondary or INTOSC

Peripherals are

Clocked by ...

INTOSC multiplexer

multiplexer

Clock During Wake-up

(while primary clock source

becomes ready)

Two-Speed Start-up or Fail-Safe Clock Monitor are enabled.

Unchanged from Idle mode (CPU operates as in corresponding Run mode).

Unchanged from Run mode.

3.2 Sleep Mode

The power-managed Sleep mode in the PIC18F2331/ 2431/4331/4431 devices is identical to that offered in all other PIC the IDLEN and SCS1:SCS0 bits (this is the Reset state) and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1).

When a wake event occurs in Sleep mode (by interrupt, Reset, or WDT time-out), the system will not be clocked until the primary clock source becomes ready (see Figure 3-2), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 22.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock provides the system clocks. The IDLEN and SCS bits are not affected by the wake-up.

microcontrollers. It is entered by clearing

3.3 Idle Modes

The IDLEN bit allows the controller’s CPU to be selectively shut down while the peripherals continue to operate. Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-2). The peripherals continue to be clocked regardless of the setting of the IDLEN bit.

There is one exception to how the IDLEN bit functions. When all the low-power OSCCON bits are cleared (IDLEN:SCS1:SCS0 = 000), the device enters Sleep mode upon execution of the SLEEP instruction. This is both the Reset state of the OSCCON register and the setting that selects Sleep mode. This maintains compatibility with other PIC devices that do not offer power-managed modes.

If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset.

When a wake event occurs, CPU execution is delayed approximately 10 μs while it becomes ready to execute code. When the CPU begins executing code, it is clocked by the same clock source as was selected in the power-managed mode (i.e., when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals until the primary clock source becomes ready – this is essentially RC_RUN mode). This continues until the primary clock source becomes ready. When the primary clock becomes ready, the OSTS bit is set and the system clock source is switched to the primary clock (see Figure 3-4). The IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to full power operation.

PIC18F2331/2431/4331/4431

FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE

Q4Q3Q2

Q1Q1

OSC1

CPU

Clock

Peripheral

Clock

Sleep

Program

Counter

FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

PC + 2PC

Q3 Q4 Q1 Q2

PC + 4

PC + 6

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Wake Event

TOST

Q1 Q2 Q3 Q4 Q1 Q2

(1)

TPLL

OSTS bit Set

PC + 2

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

Q3 Q4

Q1 Q2 Q3 Q4

PC + 8

PIC18F2331/2431/4331/4431

3.3.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle modes, in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another

When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 μs is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-4).

oscillator.

PRI_IDLE mode is entered by setting the IDLEN bit, clearing the SCS bits and executing a SLEEP instruction. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H. The OSTS bit remains set in PRI_IDLE mode (see Figure 3-3).

FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

PC PC + 2

FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

CPU Start-up Delay

Wake Event

PC + 2

PIC18F2331/2431/4331/4431

3.3.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the Idle bit, modifying SCS1:SCS0 = 01 and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set.

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 μs delay following the wake event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.

If the T1OSCEN bit is not set when the

SLEEP instruction is executed, a forced NOP will be executed instead and entry to

SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result.

FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE

Q4Q3Q2

12345678

Clock Transition

PC + 2PC

T1OSI

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

FIGURE 3-6: TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)

Q3 Q4

T1OSI

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

PC PC + 2

TOST

(1)

TPLL

(1)

12345678

Clock Transition

PC + 4

PC + 6

Wake from Interrupt Event

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

OSTS bit Set

PIC18F2331/2431/4331/4431

3.3.3 RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods.

This mode is entered by setting the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer (see Figure 3-7), the primary oscillator is shut down and the OSTS bit is cleared.

If the IRCF bits are set to a non-zero value (thus enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable, in about 1 ms. Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were

instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source.

When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a 10 μs delay following the wake event, the CPU begins executing code, being clocked by the INTOSC multiplexer. The microcontroller operates in RC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.

previously at a non-zero value before the SLEEP

FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE

Q4Q3Q2

12345678

Clock Transition

PC + 2PC

INTRC

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

FIGURE 3-8: TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)

Q3 Q4

INTOSC

Multiplexer

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

PC PC + 2

Wake from Interrupt Event

TOST

(1)

TPLL

OSTS bit Set

(1)

12345678

Clock Transition

PC + 4

PC + 6

PIC18F2331/2431/4331/4431

3.4 Run Modes

If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source. RC_RUN mode also offers the possibility of executing code at a frequency greater than the primary clock.

Wake-up from a power-managed Run mode can be triggered by an interrupt, or any Reset, to return to full power operation. As the CPU is executing code in Run modes, several additional exits from Run modes are possible. They include exit to Sleep mode, exit to a corresponding Idle mode and exit by executing a RESET instruction. While the device is in any of the power-managed Run modes, a WDT time-out will result in a WDT Reset.

3.4.1 PRI_RUN MODE

The PRI_RUN mode is the normal full power execution mode. If the SLEEP instruction is never executed, the microcontroller operates in this mode (a SLEEP instruction is executed to enter all other power-managed modes). All other power-managed modes exit to PRI_RUN mode when an interrupt or WDT time-out occur.

There is no entry to PRI_RUN mode. The OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 “Oscillator Control Register”).

3.4.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source.

SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01 and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the

SLEEP instruction is executed, a forced NOP will be executed instead and entry to

SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, system clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.

When a wake event occurs, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.

Firmware can force an exit from SEC_RUN mode. By clearing the T1OSCEN bit (T1CON<3>), an exit from SEC_RUN back to normal full power operation is triggered. The Timer1 oscillator will continue to run and provide the system clock even though the T1OSCEN bit is cleared. The primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the primary clock provides the system clock. The IDLEN and SCS bits are not affected by the wake-up.

FIGURE 3-9: TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE

Q4Q3Q2

T1OSI

OSC1

CPU

Clock

Peripheral

Clock

Program Counter

12345678

Clock Transition

PC + 2PC

Q4Q3

PC + 2

PIC18F2331/2431/4331/4431

3.4.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. This mode works well for user applications that are not highly timing sensitive, or do not require high-speed clocks at all times.

If the primary clock source is the internal oscillator block (either of the INTIO1 or INTIO2 oscillators), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to, and exit from, RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended.

This mode is entered by clearing the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The IRCF bits may select the clock frequency before the SLEEP instruction is executed. When the clock source is switched to the INTOSC multiplexer (see Figure 3-10), the primary oscillator is shut down and the OSTS bit is cleared.

The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a SLEEP instruction is not required to select a new clock frequency from the INTOSC multiplexer.

Note: Caution should be used when modifying a

single IRCF bit. If V

DD is less than 3V, it is

possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated.

If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the system clocks.

If the IRCF bits are changed from all clear (thus enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the system continue while the INTOSC source stabilizes in approximately 1 ms.

If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set.

When a wake event occurs, the system continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock provides the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 3-10: TIMING TRANSITION TO RC_RUN MODE

Q3Q2Q1

12345678

Clock Transition

PC + 2

INTRC

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

Q3Q2Q1 Q4 Q2Q1 Q3

PC + 4

PIC18F2331/2431/4331/4431

3.4.4 EXIT TO IDLE MODE

An exit from a power-managed Run mode to its corresponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source.

3.4.5 EXIT TO SLEEP MODE

An exit from a power-managed Run mode to Sleep mode is executed by clearing the IDLEN and SCS1:SCS0 bits and executing a SLEEP instruction. The code is no different than the method used to invoke Sleep mode from the normal operating (full power) mode.

The primary clock and internal oscillator block are disabled. The INTRC will continue to operate if the WDT is enabled. The Timer1 oscillator will continue to run, if enabled, in the T1CON register. All clock source status bits are cleared (OSTS, IOFS and T1RUN).

3.5 Wake From Power-Managed

Modes

An exit from any of the power-managed modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Sections 3.2 through 3.4).

Note: If application code is timing sensitive, it

should wait for the OSTS bit to become set before continuing. Use the interval during the Low-Power mode exit sequence (before OSTS is set) to perform timing insensitive “housekeeping” tasks.

Device behavior during Low-Power mode exits is summarized in Table 3-3.

3.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the device to exit a power-managed mode and resume full power operation. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Low-Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”).

PIC18F2331/2431/4331/4431

TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE

Clock in

Power- Managed

Mode

(BY CLOCK SOURCES)

Primary System

Clock

Power- Managed

Mode Exit Delay

Clock Ready

Status bit

(OSCCON)

Activity During Wake from

Power-Managed Mode

Exit by Interrupt Exit by Reset

Primary System Clock (PRI_IDLE mode)

T1OSC or

(1)

INTRC

INTOSC

(2)

Sleep mode

LP, XT, HS

HSPLL

EC, RC, INTRC

INTOSC

(2)

(1)

5-10 μs

(5)

LP, XT, HS OST

HSPLL OST + 2 ms

EC, RC, INTRC

INTOSC

(2)

(1)

5-10 μs

1ms

(5)

(4)

LP, XT, HS OST

HSPLL OST + 2 ms

EC, RC, INTRC

INTOSC

(2)

(1)

(5)

5-10 μs

None IOFS

LP, XT, HS OST

HSPLL OST + 2 ms

EC, RC, INTRC

INTOSC

(2)

(1)

5-10 μs

1ms

(5)

(4)

OSTS

—

IOFS

OSTS

—

IOFS

OSTS

—

OSTS

—

IOFS

CPU and peripherals clocked by primary clock and executing instructions.

CPU and peripherals clocked by selected power-managed mode clock and executing instructions until primary clock source becomes ready.

Not clocked or Two-Speed Start-up (if enabled) until primary clock source becomes

(3)

ready

Not clocked or Two-Speed Start-up (if enabled).

Note 1: In this instance, refers specifically to the INTRC clock source.

2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies. 3: Two-Speed Start-up is covered in greater detail in Section 22.3 “Two-Speed Start-up”. 4: Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other

required delays (see Section 3.3 “Idle Modes”).

(3)

PIC18F2331/2431/4331/4431

3.5.2 EXIT BY RESET

Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code.

Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 22.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 22.4 “Fail-Safe Clock Monitor”) are enabled in Configuration Register 1H, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Since the OSCCON register is cleared following all Resets, the INTRC clock source is selected. A higher speed clock may be selected by modifying the IRCF bits in the OSCCON register. Execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down.

3.5.3 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs.

If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in a wake from the power-managed mode (see Section 3.2 “Sleep Mode” through Section 3.4 “Run Modes”).

If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 22.2 “Watchdog Timer (WDT)”).

The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the system clock source.

3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DE LAY

Certain exits from power-managed modes do not invoke the OST at all. These are:

• PRI_IDLE mode where the primary clock source

is not stopped; and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes).

However, a fixed delay (approximately 10 μs) following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.

3.6 INTOSC Frequency Drift

The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways.

It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has the side effect that the INTRC clock source frequency is also affected. However, the features that use the INTRC source often do not require an exact frequency. These features include the Fail-Safe Clock Monitor, the Watchdog Timer and the RC_RUN/RC_IDLE modes when the INTRC clock source is selected.

Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made, and in some cases, how large a change is needed. Three examples follow, but other techniques may be used.

PIC18F2331/2431/4331/4431

3.6.1 EXAMPLE – EUSART

An adjustment may be indicated when the EUSART begins to generate framing errors, or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high – try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low – increment OSCTUNE.

3.6.2 EXAMPLE – TIMERS

This technique compares system clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator.

Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE.

3.6.3 EXAMPLE – CCP IN CAPTURE MODE

A CCP module can use free-running Timer1, clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated.

If the measured time is much greater than the calculated time, the internal oscillator block is running too fast – decrement OSCTUNE. If the measured time is much less than the calculated time, the internal oscillator block is running too slow – increment OSCTUNE.

PIC18F2331/2431/4331/4431

NOTES:

PIC18F2331/2431/4331/4431

4.0 RESET

Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal

The PIC18F2331/2431/4331/4431 devices differentiate between various kinds of Reset:

a) Power-on Reset (POR) b) MCLR

Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during

execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset

Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.

operation. Status bits from the RCON register, RI

, POR and BOR, are set or cleared differently in

PD different Reset situations, as indicated in Table 4-2. These bits are used in software to determine the nature of the Reset. See Table 4-3 for a full description of the Reset states of all registers.

A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1.

The enhanced MCU devices have a MCLR in the MCLR

Reset path. The filter will detect and

ignore small pulses.

The MCLR

pin is not driven low by any internal Resets,

including the WDT.

The MCLR

input provided by the MCLR pin can be disabled with the MCLRE bit in Configuration Register 3H (CONFIG3H<7>). See Section 22.1 “Configuration

Bits” for more information.

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

, TO,

noise filter

MCLR

VDD

OSC1

( )_IDLE

Sleep

WDT

Time-out

DD Rise

Detect

Brown-out

Reset

OST/PWRT

32 μs

(1)

INTRC

External Reset

MCLRE

POR Pulse

BOREN

OST

PWRT

1024 Cycles

10-Bit Ripple Counter

65.5 ms

11-Bit Ripple Counter

Chip_Reset

Enable PWRT

Enable OST

(2)

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

2: See Table 4-1 for time-out situations.

PIC18F2331/2431/4331/4431

4.1 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

DD rise is detected. To take advantage of the POR

V circuitry, just tie the MCLR 10 kΩ) to V

DD. This will eliminate external RC compo-

nents usually needed to create a Power-on Reset delay. A minimum rise rate for V (parameter D004). For a slow rise time, see Figure 4-2.

When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.

Note: The following decoupling method is

recommended:

1. A 1 μF capacitor should be connected

across AV

2. A similar capacitor should be connected across V

FIGURE 4-2: EXTERNAL POWER-ON

VDD

pin through a resistor (1k to

DD is specified

DD and AVSS.

DD and VSS.

RESET CIRCUIT (FOR SLOW V

DD POW E R-U P)

MCLR

PIC18FXXXX

4.2 Power-up Timer (PWRT)

The Power-up Timer (PWRT) of the PIC18F2331/2431/ 4331/4431 devices is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 x 32 μs = 65.6 ms. While the PWRT is counting, the device is held in Reset.

The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter 33 for details.

The PWRT is enabled by clearing Configuration bit PWRTEN

4.3 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP, HS and HSPLL modes, and only on Power-on Reset or on exit from most power-managed modes.

4.4 PLL Lock Time-out

With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (T 2 ms and follows the oscillator start-up time-out.

PLL) is typically

Note 1: External Power-on Reset circuit is

required only if the V

DD power-up slope

is too slow. The diode D helps discharge the capacitor quickly when V

DD powers

down.

2: R < 40 kΩ is recommended to make

sure that the voltage drop across R does not violate the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing

into MCLR the event of MCLR

from external capacitor C, in

/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

4.5 Brown-out Reset (BOR)

A Configuration bit, BOREN, can disable (if clear/ programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (parameter D005A through D005K) for greater than T the brown-out situation will reset the chip. A Reset may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until V above V invoked after V

BOR. If the Power-up Timer is enabled, it will be

DD rises above VBOR; it then will keep

the chip in Reset for an additional time delay T (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V

DD rises above VBOR, the Power-up

Timer will execute the additional time delay. Enabling the Brown-out Reset does not automatically enable the PWRT.

BOR (parameter 35),

DD rises

PWRT

PIC18F2331/2431/4331/4431

4.6 Time-out Sequence

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bring-

On power-up, the time-out sequence is as follows: First, after the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figures 4-3 through 4-7 depict time-out sequences on power-up.

ing MCLR (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel.

Table 4-2 shows the Reset conditions for some Special Function Registers, while Table 4-3 shows the Reset conditions for all the registers.

TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Configuration

HSPLL 66 ms

HS, XT, LP 66 ms

EC, ECIO 66 ms

RC, RCIO 66 ms

INTIO1, INTIO2 66 ms

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the 4x PLL to lock.

PWRTEN

(1)

+ 1024 TOSC + 2 ms

Power-up

= 0 PWRTEN = 1

(1)

+ 1024 TOSC 1024 TOSC 1024 TOSC

(1)

(2)

and Brown-out

(2)

1024 TOSC + 2 ms

REGISTER 4-1: RCON REGISTER BITS AND POSITIONS

R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN

bit 7 bit 0

Note: Refer to Section 5.14 “RCON Register” for bit definitions.

— —RITO PD POR BOR

high will begin execution immediately

Exit From

Power-Managed Mode

(2)

——

1024 TOSC + 2 ms

(2)

TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Condition

Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0

RESET Instruction 0000h 0--0 uuuu 0 u u u u u u

Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u

Reset during power-managed

MCLR Run modes

MCLR

Reset during power-managed Idle

and Sleep modes

WDT Time-out during full power or power-managed Run modes

MCLR

Reset during full power execution

Stack Full Reset (STVREN = 1) 1u

Stack Underflow Reset (STVREN = 1) u1

Stack Underflow Error (not an actual Reset, STVREN = 0)

WDT time-out during power-managed Idle or Sleep modes

Interrupt exit from power-managed modes PC + 2

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’. Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0x000008h or 0x000018h).

Program

Counter

0000h 0--u 1uuu u 1 u u u u u

0000h 0--u 10uu u 1 0 u u u u

0000h 0--u 0uuu u 0 u u u u u

0000h 0--u uuuu u u u u u

0000h u--u uuuu u u u u u u 1

PC + 2 u--u 00uu u 0 0 u u u u

RCON

(1)

u--u u0uu u u 0 u u u u

TO PD POR BOR STKFUL STKUNF

PIC18F2331/2431/4331/4431

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Resets

MCLR

Power-on Reset,

Brown-out Reset

TOSU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---0 uuuu

TOSH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

TOSL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

STKPTR 2331 2431 4331 4431 00-0 0000 uu-0 0000 uu-u uuuu

PCLATU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu

PCLATH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PCL 2331 2431 4331 4431 0000 0000 0000 0000 PC + 2

TBLPTRU 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

TBLPTRH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

TBLPTRL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

TABLAT 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PRODH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON 2331 2431 4331 4431 0000 000x 0000 000u uuuu uuuu

INTCON2 2331 2431 4331 4431 1111 -1-1 1111 -1-1 uuuu -u-u

INTCON3 2331 2431 4331 4431 11-0 0-00 11-0 0-00 uu-u u-uu

INDF0 2331 2431 4331 4431 N/A N/A N/A

POSTINC0 2331 2431 4331 4431 N/A N/A N/A

POSTDEC0 2331 2431 4331 4431 N/A N/A N/A

PREINC0 2331 2431 4331 4431 N/A N/A N/A

PLUSW0 2331 2431 4331 4431 N/A N/A N/A

FSR0H 2331 2431 4331 4431 ---- xxxx ---- uuuu ---- uuuu

FSR0L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

WREG 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 2331 2431 4331 4431 N/A N/A N/A

POSTINC1 2331 2431 4331 4431 N/A N/A N/A

POSTDEC1 2331 2431 4331 4431 N/A N/A N/A

PREINC1 2331 2431 4331 4431 N/A N/A N/A

PLUSW1 2331 2431 4331 4431 N/A N/A N/A

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE

pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR disabled.

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

(3)

(2)

(1)

PIC18F2331/2431/4331/4431

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

FSR1H 2331 2431 4331 4431 ---- 0000 ---- uuuu ---- uuuu

FSR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

BSR 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu

INDF2 2331 2431 4331 4431 N/A N/A N/A

POSTINC2 2331 2431 4331 4431 N/A N/A N/A

POSTDEC2 2331 2431 4331 4431 N/A N/A N/A

PREINC2 2331 2431 4331 4431 N/A N/A N/A

PLUSW2 2331 2431 4331 4431 N/A N/A N/A

FSR2H 2331 2431 4331 4431 ---- 0000 ---- uuuu ---- uuuu

FSR2L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS 2331 2431 4331 4431 ---x xxxx ---u uuuu ---u uuuu

TMR0H 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

TMR0L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

OSCCON 2331 2431 4331 4431 0000 q000 0000 q000 uuuu uuuu

LVDCON 2331 2431 4331 4431 --00 0101 --00 0101 --uu uuuu

WDTCON 2331 2431 4331 4431 0--- ---0 0--- ---0 u--- ---u

(4)

RCON

TMR1H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 2331 2431 4331 4431 0000 0000 u0uu uuuu uuuu uuuu

TMR2 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PR2 2331 2431 4331 4431 1111 1111 1111 1111 1111 1111

T2CON 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu

SSPBUF 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

SSPCON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

6: Bit 3 of PORTE and LATE are enabled if MCLR

2331 2431 4331 4431 0--1 11q0 0--q qquu u--u qquu

Shaded cells indicate conditions do not apply for the designated device.

interrupt vector (0008h or 0018h).

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

not enabled as PORTA pins, they are disabled and read ‘0’.

pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR disabled.

Power-on Reset,

Brown-out Reset

functionality is disabled. When not enabled as the PORTE

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

PIC18F2331/2431/4331/4431

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

ADRESH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

ADCON1 2331 2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu

ADCON2 2331

ADCON3 2331

ADCHS 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

CCPR1H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 2331 2431

CCPR2H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

ANSEL1 2331

ANSEL0 2331

T5CON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

QEICON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

SPBRGH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

SPBRG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

RCREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

TXREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

TXSTA 2331 2431 4331 4431 0000 -010 0000 -010 uuuu -uuu

RCSTA 2331 2431 4331 4431 0000 000x 0000 000x uuuu uuuu

BAUDCTL 2331 2431 4331 4431 -1-1 0-00 -1-1 0-00 -u-u u-uu

EEADR 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

EEDATA 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

EECON2 2331 2431 4331 4431 0000 0000 0000 0000 0000 0000

EECON1 2331 2431 4331 4431 xx-0 x000 uu-0 u000 uu-0 u000

IPR3 2331 2431 4331 4431 ---1 1111 ---1 1111 ---u uuuu

PIE3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu

PIR3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: Bit 3 of PORTE and LATE are enabled if MCLR

pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR disabled.

2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu

4331 4431 --00 0000 --00 0000 --uu uuuu

2431 4331 4431 ---- ---1 ---- ---1 ---- ---u

2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

Power-on Reset,

Brown-out Reset

functionality is disabled. When not enabled as the PORTE

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

PIC18F2331/2431/4331/4431

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Power-on Reset,

Brown-out Reset

IPR2 2331 2431 4331 4431 1--1 -1-1 1--1 -1-1 u--u -u-u

PIR2 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u

PIE2 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u

IPR1 2331 2431 4331 4431 -111 1111 -111 1111 -uuu uuuu

PIR1

2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu

PIE1 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu

OSCTUNE 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

TRISE

TRISD

(6)

2331 2431 4331 4431 ---- -111 ---- -111 ---- -uuu

2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

TRISC 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

TRISB 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

TRISA

(5)

2331 2431 4331 4431 1111 1111

(5)

PR5H 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

PR5L 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

LATE

(6)

2331 2431 4331 4431 ---- -xxx ---- -uuu ---- -uuu

LATD 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

LATC 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

LATB 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

LATA

(5)

2331 2431 4331 4431 xxxx xxxx

(5)

TMR5H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

TMR5L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

PORTE

PORTD

(6)

2331 2431 4331 4431 ---- xxxx ---- xxxx ---- uuuu

2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

PORTB 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA

(5)

2331 2431 4331 4431 xx0x 0000

(5)

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: Bit 3 of PORTE and LATE are enabled if MCLR

functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR disabled.

WDT Reset

RESET Instruction

Stack Resets

1111 1111

uuuu uuuu

uu0u 0000

(5)

Wake-up via WDT

or Interrupt

uuuu uuuu

(1)

(5)

PIC18F2331/2431/4331/4431

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

PTCON0 2331 2431 4331 4431 0000 0000 uuuu uuuu uuuu uuuu

PTCON1 2331 2431 4331 4431 00-- ---- 00-- ---- uu-- ----

PTMRL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PTMRH 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu

PTPERL 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

PTPERH 2331 2431 4331 4431 ---- 1111 ---- 1111 ---- uuuu

PDC0L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PDC0H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

PDC1L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PDC1H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

PDC2L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PDC2H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

PDC3L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

PDC3H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu

SEVTCMPL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

SEVTCMPH 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu

PWMCON0 2331 2431 4331 4431 -111 0000 -111 0000 -uuu uuuu

PWMCON1 2331 2431 4331 4431 0000 0-00 0000 0-00 uuuu u-uu

DTCON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

FLTCONFIG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

OVDCOND 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu

OVDCONS 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu

CAP1BUFH/ VELRH

CAP1BUFL/ VELRL

CAP2BUFH/ POSCNTH

CAP2BUFL/ POSCNTL

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

6: Bit 3 of PORTE and LATE are enabled if MCLR

2331 2431 4331 4431

Shaded cells indicate conditions do not apply for the designated device.

interrupt vector (0008h or 0018h).

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

not enabled as PORTA pins, they are disabled and read ‘0’.

pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR disabled.

Power-on Reset,

Brown-out Reset

xxxx xxxx uuuu uuuu

functionality is disabled. When not enabled as the PORTE

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

uuuu uuuu

PIC18F2331/2431/4331/4431

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

CAP3BUFH/ MAXCNTH

CAP3BUFL/ MAXCNTL

CAP1CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu

CAP2CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu

CAP3CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu

DFLTCON 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

6: Bit 3 of PORTE and LATE are enabled if MCLR

2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu

Shaded cells indicate conditions do not apply for the designated device.

interrupt vector (0008h or 0018h).

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

not enabled as PORTA pins, they are disabled and read ‘0’.

functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR disabled.

PIC18F2331/2431/4331/4431

FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TOST

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

NOT TIED TO VDD): CASE 1

TOST

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

NOT TIED TO VDD): CASE 2

TOST

PIC18F2331/2431/4331/4431

FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

VDD

MCLR

INTERNAL POR

PWRT

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TOST

FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

PLL TIME-OUT

TOST

TPLL

TIED TO VDD)

INTERNAL RESET

Note: TOST = 1024 clock cycles.

PLL ≈ 2 ms max. First three stages of the PWRT timer.

PIC18F2331/2431/4331/4431

NOTES:

PIC18F2331/2431/4331/4431

5.0 MEMORY ORGANIZATION

There are three memory types in enhanced MCU devices. These memory types are:

• Program Memory

• Data RAM

• Data EEPROM

Data and program memory use separate busses, which allows for concurrent access of these types.

Additional detailed information for Flash program memory and data EEPROM is provided in Section 6.0

“Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively.

FIGURE 5-1: PROGRAM MEMORY MAP

AND STACK FOR PIC18F2331/4331

PC<20:0>

CALL,RCALL,RETURN RETFIE,RETLW

Stack Level 1

Stack Level 31

Reset Vector LSb

High-Priority Interrupt Vector LSb

Low-Priority Interrupt Vector LSb

On-Chip Flash

Program Memory

•

000000h

000008h

000018h

001FFFh 002000h

5.1 Program Memory Organization

A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP instruction).

The PIC18F2331/4331 devices each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions.

The PIC18F2431/4431 devices each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions.

The Reset vector address is at 000000h and the interrupt vector addresses are at 000008h and 000018h.

The program memory maps for PIC18F2331/4331 and PIC18F2431/4431 devices are shown in Figure 5-1 and Figure 5-2, respectively.

FIGURE 5-2: PROGRAM MEMORY MAP

AND STACK FOR PIC18F2431/4431

CALL,RCALL,RETURN RETFIE,RETLW

Stack Level 1

Stack Level 31

Reset Vector LSb

High-Priority Interrupt Vector LSb

Low-Priority Interrupt Vector LSb

On-Chip Flash

Program Memory

PC<20:0>

•

000000h

000008h

000018h

003FFFh

Space

User Memory

Unused

Read ‘0’s

1FFFFFh

Space

User Memory

Unused

Read ‘0’s

004000h

1FFFFFh

PIC18F2331/2431/4331/4431

5.2 Return Address Stack

The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, with the Stack Pointer initialized to 00000b after all Resets. There is no RAM associated with Stack Pointer 00000b. This is only a Reset value. During a CALL type instruction, causing a push onto the stack, the Stack Pointer is first incremented and the RAM location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented.

The stack space is not part of either program or data space. The Stack Pointer is readable and writable, and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special Function Registers. Data can also be pushed to, or popped from, the stack using the Top-of-Stack SFRs. Status bits indicate if the stack is full, has overflowed or underflowed.

5.2.1 TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return.

The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.

5.2.2 RETURN STACK POINTER (STKPTR)

The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. At Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance.

After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR.

The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 22.1 “Configuration Bits” for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31.

When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset as the contents of the SFRs are not affected.

FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack

11111 11110

TOSLTOSHTOSU

34h1Ah00h

Top-of-Stack

001A34h

000D58h

11101

00011 00010 00001 00000

STKPTR<4:0>

00010

PIC18F2331/2431/4331/4431

REGISTER 5-1: STKPTR: STACK POINTER REGISTER

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL

bit 7 bit 0

Legend: C = Clearable-only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

STKUNF

(1)

— SP4 SP3 SP2 SP1 SP0

bit 7 STKFUL: Stack Full Flag bit

1 = Stack became full or overflowed 0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit

1 = Stack underflow occurred 0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

5.2.3 PUSH AND POP INSTRUCTIONS

Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack.

The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value.

(1)

5.2.4 STACK FULL/UNDERFLOW RESETS

These Resets are enabled by programming the STVREN bit in Configuration Register 4L. When the STVREN bit is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. When the STVREN bit is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset.

PIC18F2331/2431/4331/4431

5.3 Fast Register Stack

A “fast return” option is available for interrupts. A Fast Register Stack is provided for the STATUS, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt.

All interrupt sources will push values into the Stack registers. If both low and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. Users must save the key registers in software during a low-priority interrupt.

If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt.

If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack.

Example 5-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return.

5.4 PCL, PCLATH and PCLATU

The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register.

The contents of PCLATH and PCLATU will be transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.8.1 “Computed GOTO”).

The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

CALL SUB1, FAST ;STATUS, WREG, BSR

•

SUB1 •

•

RETURN FAST ;RESTORE VALUES SAVED

;SAVED IN FAST REGISTER ;STACK

;IN FAST REGISTER STACK

PIC18F2331/2431/4331/4431

5.5 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the Instruction Register (IR) in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-4.

FIGURE 5-4: CLOCK/ INSTRUCTION CYCLE

OSC1

OSC2/CLKO

(RC mode)

Q2 Q3 Q4

Execute INST (PC – 2)

Fetch INST (PC)

Q2 Q3 Q4

Execute INST (PC)

Fetch INST (PC + 2)

5.6 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-2).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Internal Phase Clock

PC + 2

PC + 4

Execute INST (PC + 2)

Fetch INST (PC + 4)

EXAMPLE 5-2: INSTRUCTION PIPELINE FLOW

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush (NOP)

Fetch SUB_1 Execute SUB_1

PIC18F2331/2431/4331/4431

5.7 Instructions in Program Memory

The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 5.4 “PCL, PCLATH and PCLATU”).

The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory.

5.7.1 TWO-WORD INSTRUCTIONS

PIC18F2331/2431/4331/4431 devices have four twoword instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip operation. A program example that demonstrates this concept is shown in Example 5-3. Refer to Section 23.0 “Instruction Set Summary” for further details of the instruction set.

Instruction 2 in Figure 5-5 shows how the instruction ‘GOTO 000006h’ is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 23.0 “Instruction Set Summary” provides further details of the instruction set.

FIGURE 5-5: INSTRUCTIONS IN PROGRAM MEMORY

LSB = 1 LSB = 0 ↓

0Fh 55h 000008h

EFh 03h 00000Ah

F0h 00h 00000Ch

C1h 23h 00000Eh

F4h 56h 000010h

Instruction 1: Instruction 2:

Instruction 3:

Program Memory Byte Locations

MOVLW 055h

GOTO 000006h

MOVFF 123h, 456h

→

Word Address

000000h 000002h 000004h 000006h

000012h 000014h

EXAMPLE 5-3: TWO-WORD INSTRUCTIONS

CASE 1: Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2: Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F2331/2431/4331/4431

5.8 Look-up Tables

Look-up tables are implemented two ways:

• Computed GOTO

• Table Reads

5.8.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-4.

A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, which returns the value 0xnn to the calling function.

The offset value (in WREG) specifies the number of bytes that the program counter should advance, and should be multiples of 2 (LSB = 0).

In this method, only one data byte may be stored in each instruction location and room on the return address stack is required.

EXAMPLE 5-4: COMPUTED GOTO USING

AN OFFSET VALUE

MOVFW OFFSET

CALL TABLE ORG 0xnn00 TABLE ADDWF PCL

RETLW 0xnn

. . .

5.8.2 TABLE READS/TABLE WRITES

A better method of storing data in program memory allows two bytes of data to be stored in each instruction location.

Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) specifies the byte address and the Table Latch (TABLAT) contains the data that is read from, or written to, program memory. Data is transferred to/from program memory, one byte at a time.

The table read/table write operation is discussed further in Section 6.1 “Table Reads and Table

Writes”.

5.9 Data Memory Organization

The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 5-6 shows the data memory organization for the PIC18F2331/2431/4331/4431 devices.

The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented.

The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. The SFRs start at the last location of Bank 15 (FFFh) and extend to F60h. Any remaining space beyond the SFRs in the bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as ‘0’s.

The entire data memory may be accessed directly or indirectly. Direct Addressing mode may require the use of the BSR register. Indirect Addressing mode requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit address value that can be used to access any location in the data memory map without banking. See Section 5.12 “Indirect Addressing, INDF and FSR Registers” for Indirect Addressing details.

The instruction set and architecture allow operations across all banks. This may be accomplished by Indirect Addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another.

To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 5.10 “Access Bank” provides a detailed description of the Access RAM.

5.9.1 GENERAL PURPOSE REGISTER FILE

Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets.

Data RAM is available for use as GPR registers by all instructions. The second half of Bank 15 (F60h to FFFh) contains SFRs. All other banks of data memory contain GPRs, starting with Bank 0.

PIC18F2331/2431/4331/4431

FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2331/2431/4331/4431 DEVICES

BSR<3:0>

= 0000

= 0001

= 0010

= 0011

= 1110

Bank 0

Bank 1

Bank 2

Bank 3

Bank 14

Data Memory Map

00h

Access RAM

FFh

00h

FFh

00h

FFh

00h

Unused

Read ‘00h’

GPR

000h 05Fh 060h 0FFh 100h

1FFh 200h

2FFh 300h

Access Bank

Access RAM Low

Access RAM High

(SFRs)

00h

5Fh 60h

FFh

= 1111

Bank 15

00h

FFh

Unused

SFR

EFFh F00h F5Fh

F60h FFFh

When a = 0:

The BSR is ignored and the Access Bank is used.

The first 96 bytes are General Purpose RAM (from Bank 0).

The second 160 bytes are Special Function Registers (from Bank 15).

When a = 1:

The BSR specifies the bank used by the instruction.

PIC18F2331/2431/4331/4431

5.9.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets; those asso-

“core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature.

The SFRs are typically distributed among the peripherals whose functions they control.

The unused SFR locations will be unimplemented and read as ‘0’s.

ciated with the “core” function and those related to the peripheral functions. Those registers related to the

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES

Address Name Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2 FBFh CCPR1H F9Fh IPR1 F7Fh PTCON0

FFEh TOSH FDEh POSTINC2 FBEh CCPR1L F9Eh PIR1 F7Eh PTCON1

FFDh TOSL FDDh POSTDEC2 FBDh CCP1CON F9Dh PIE1 F7Dh PTMRL

FFCh STKPTR FDCh PREINC2 FBCh CCPR2H F9Ch

FFBh PCLATU FDBh PLUSW2 FBBh CCPR2L F9Bh OSCTUNE F7Bh PTPERL

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah ADCON3 F7Ah PTPERH

FF9h PCL FD9h FSR2L FB9h ANSEL1 F99h ADCHS F 79h PDC0L

FF8h TBLPTRU FD8h STATUS FB8h ANSEL0 F98h

FF7h TBLPTRH FD7h TMR0H FB7h T5CON F97h — F77h PDC1L

FF6h TBLPTRL FD6h TMR0L FB6h QEICON F96h TRISE F76h PDC1H

FF5h TABLAT FD5h T0CON FB5h

FF4h PRODH FD4h

FF3h PRODL FD3h OSCCON FB3h — F93h TRISB F73h PDC3L

FF2h INTCON FD2h LVDCON FB2h

FF1h INTCON2 FD1h WDTCON FB1h — F91h PR5H F71h SEVTCMPL

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h PR5L F70h SEVTCMPH

FEFh INDF0 FCFh TMR1H FAFh SPBRG F8Fh

FEEh POSTINC0 FCEh TMR1L FAEh RCREG F8Eh

FEDh POSTDEC0 FCDh T1CON FADh TXREG F8Dh LATE F6Dh DTCON

FECh PREINC0 FCCh TMR2 FACh TXSTA F8Ch LATD F6Ch FLTCONFIG

FEBh PLUSW0 FCBh PR2 FABh RCSTA F8Bh LATC F6Bh OVDCOND

FEAh FSR0H FCAh T2CON FAAh BAUDCTL F8Ah LATB F6Ah OVDCONS

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA F69h CAP1BUFH

FE8h WREG FC8h SSPADD FA8h EEDATA F88h TMR5H F68h CAP1BUFL

FE7h INDF1 FC7h SSPSTAT FA7h EECON2 F87h TMR5L F67h CAP2BUFH

FE6h POSTINC1 FC6h SSPCON FA6h EECON1 F86h

FE5h POSTDEC1 FC5h —FA5hIPR3F85h— F65h CAP3BUFH

FE4h PREINC1 FC4h ADRESH FA4h PIR3 F84h PORTE F64h CAP3BUFL

FE3h PLUSW1 FC3h ADRESL FA3h PIE3 F83h PORTD F63h CAP1CON

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h CAP2CON

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h CAP3CON

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h DFLTCON

—FB4h— F94h TRISC F74h PDC2H

—

— F92h TRISA F72h PDC3H

F95h TRISD F75h PDC2L

—F7ChPTMRH

— F78h PDC0H

—F6FhPWMCON0

—F6EhPWMCON1

— F66h CAP2BUFL

PIC18F2331/2431/4331/4431

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TOSU

TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 50, 60

TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 50, 60

STKPTR STKFUL STKUNF

PCLATU

PCLATH Holding Register for PC<15:8> 0000 0000 50, 62

PCL PC Low Byte (PC<7:0>) 0000 0000 50, 62

TBLPTRU

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 50, 80

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 50, 80

TABLAT Program Memory Table Latch 0000 0000 50, 80

PRODH Product Register High Byte xxxx xxxx 50, 91

PRODL Product Register Low Byte xxxx xxxx 50, 91

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 50, 95

INTCON2 RBPU

INTCON3 INT2IP INT1IP

INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 50, 73

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 50, 73

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 50, 73

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 50, 73

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) N/A 50, 73

FSR0H

FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 50, 73

WREG Working Register xxxx xxxx 50

INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 50, 73

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 50, 73

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 50, 73

PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 50, 73

PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) N/A 50, 73

FSR1H

FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 51, 73

BSR

INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 51, 73

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 51, 73

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 51, 73

PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 51, 73

PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) N/A 51, 73

FSR2H

FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 51, 73

STATUS

TMR0H Timer0 Register High Byte 0000 0000 51, 137

TMR0L Timer0 Register Low Byte xxxx xxxx 51, 137

T0CON TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 51, 135

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented. Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read

2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes. 3: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 4: If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as

5: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only.

— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 50, 60

— SP4 SP3 SP2 SP1 SP0 00-0 0000 50, 61

— —bit 21

INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 50, 96

— — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 50, 73

— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 51, 73

— — — — Bank Select Register ---- 0000 51, 72

— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 51, 73

— — —NOVZDCC---x xxxx 51, 75

‘0’ in all other oscillator modes.

analog inputs and read ‘0’ following a Reset.

(3)

Holding Register for PC<20:16> ---0 0000 50, 62

(3)

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 50, 80

— INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 50, 97

Valu e o n

POR, BOR

Details on

page:

PIC18F2331/2431/4331/4431

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 30, 51

LVDCON

WDTCON WDTW

RCON IPEN

TMR1H Timer1 Register High Byte xxxx xxxx 51, 143

TMR1L Timer1 Register Low Byte xxxx xxxx 51, 143

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR2 Timer2 Register 0000 0000 51, 145

PR2 Timer2 Period Register 1111 1111 51, 145

T2CON

SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 51, 222

SSPADD SSP Address Register in I

SSPSTAT SMP CKE D/A

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 51, 215

ADRESH A/D Result Register High Byte xxxx xxxx 52, 261

ADRESL A/D Result Register Low Byte xxxx xxxx 52, 261

ADCON0

ADCON1 VCFG1 VCFG0

ADCON2 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 52, 248

ADCON3 ADRS1 ADRS0

ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000 52, 250

CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 52, 153

CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 52, 153

CCP1CON

CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 52, 153

CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 52, 153

CCP2CON

ANSEL1

ANSEL0 ANS7

T5CON T5SEN RESEN

QEICON VELM

SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 52, 227

SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 52, 227

RCREG EUSART Receive Register 0000 0000 52, 235,

TXREG EUSART Transmit Register 0000 0000 52, 232,

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 52, 224

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 52, 225

BAUDCTL

— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 51, 265

— — — — — —SWDTEN0--- ---0 51, 281

— —RITO PD POR BOR 0--1 11q0 49, 76, 107

TMR1CS TMR1ON 0000 0000 51, 139

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 51, 145

C™ Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 51, 222

PSR/WUA BF 0000 0000 51, 214

— — ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON --00 0000 52, 246

— FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 00-0 0000 52, 247

— SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000 52. 249

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 52, 156,

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 52, 156

— — — — — — —ANS8

(5)

— RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 52, 226

‘0’ in all other oscillator modes.

analog inputs and read ‘0’ following a Reset.

(5)

ANS6

(5)

QERR UP/DOWN QEIM2 QEIM1 QEIM0 PDEC1 PDEC0 0000 0000 52, 170

(5)

ANS5

T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON 0000 0000 52, 147

ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 52, 251

Valu e o n

POR, BOR

(5)

---- ---1 52, 251

Details on

page:

149

234

PIC18F2331/2431/4331/4431

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Valu e o n

POR, BOR

EEADR EEPROM Address Register 0000 0000 52, 87

EEDATA EEPROM Data Register 0000 0000 52, 90

EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 52, 78, 87

EECON1 EEPGD CFGS

IPR3

PIR3

PIE3

IPR2 OSCFIP

PIR2 OSCFIF

PIE2 OSCFIE

IPR1

PIR1

PIE1

OSCTUNE

— — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 52, 106

— — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 52, 100

— — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 52, 103

— —EEIP—LVDIP— CCP2IP 1--1 -1-1 53, 105

— — EEIF —LVDIF—CCP2IF0--0 -0-0 53, 99

— —EEIE—LVDIE— CCP2IE 0--0 -0-0 53, 102

— ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 53, 104

— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 53, 98

— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 53, 101

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 27, 53

ADCON3 ADRS1 ADRS0

— FREE WRERR WREN WR RD xx-0 x000 52, 79, 88

— SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000 52

ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000 52

TRISE

TRISD

(5)

— — — — — PORTE Data Direction Register

PORTD Data Direction Register 1111 1111 53, 130

(5)

---- -111 53, 133

TRISC PORTC Data Direction Register 1111 1111 53, 125

TRISB PORTB Data Direction Register 1111 1111 53, 119

TRISA TRISA7

(2)

TRISA6

(1)

PORTA Data Direction Register 1111 1111 53, 113

PR5H Timer5 Period Register High Byte 1111 1111 52

PR5L Timer5 Period Register Low Byte 1111 1111 52

(5)

LATE

LATD

(5)

— — — — — LATE Data Output Register ---- -xxx 53, 133

LATD Data Output Register xxxx xxxx 53, 130

LATC LATC Data Output Register xxxx xxxx 53, 125

LATB LATB Data Output Register xxxx xxxx 53, 119

LATA LATA7

(2)

LATA6

(1)

LATA Data Output Register xxxx xxxx 53, 113

TMR5H Timer5 Register High Byte xxxx xxxx 148

TMR5L Timer5 Register Low Byte xxxx xxxx 148

PORTE

PORTD

(5)

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 53, 130

— — — —RE3

(6)

RE2

(5)

RE1

(5)

RE0

(5)

---- xxxx 53, 133

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 53, 125

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 53, 119

PORTA RA7

(2)

RA6

(1)

RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 53, 113

PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 54, 186

PTCON1 PTEN PTDIR

— — — — — — 00-- ---- 54, 186

PTMRL PWM Time Base Register (lower 8 bits) 0000 0000 184

PTMRH

UNUSED PWM Time Base Register (upper 4 bits) ---- 0000 184

PTPERL PWM Time Base Period Register (lower 8 bits) 1111 1111 184

PTPERH

UNUSED PWM Time Base Period Register (upper 4 bits) ---- 1111 184

‘0’ in all other oscillator modes.

analog inputs and read ‘0’ following a Reset.

Details on

page:

PIC18F2331/2431/4331/4431

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PDC0L PWM Duty Cycle #0L Register (lower 8 bits) 0000 0000 184

PDC0H

PDC1L PWM Duty Cycle #1L Register (lower 8 bits) 0000 0000 184

PDC1H

PDC2L PWM Duty Cycle #2L Register (lower 8 bits) 0000 0000 184

PDC2H

(5)

PDC3L

(5)

PDC3H

SEVTCMPL PWM Special Event Compare Register (lower 8 bits) 0000 0000 N/A

SEVTCMPH

PWMCON0

PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR

DTCON DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 0000 0000 54, 200

FLTCONFIG BRFEN FLTBS

OVDCOND POVD7

OVDCONS POUT7

CAP1BUFH/ VELRH

CAP1BUFL/ VELRL

CAP2BUFH/ POSCNTH

CAP2BUFL/ POSCNTL

CAP3BUFH/ MAXCNTH

CAP3BUFL/ MAXCNTL

CAP1CON

CAP2CON

CAP3CON

DFLTCON

‘0’ in all other oscillator modes.

analog inputs and read ‘0’ following a Reset.

UNUSED PWM Duty Cycle #0H Register (upper 6 bits) --00 0000 184

UNUSED PWM Duty Cycle #1H Register (upper 6 bits) --00 0000 184

UNUSED PWM Duty Cycle #2H Register (upper 6 bits) --00 0000 184

PWM Duty Cycle #3L Register (lower 8 bits) 0000 0000 184

UNUSED PWM Duty Cycle #3H Register (upper 6 bits) --00 0000 184

UNUSED PWM Special Event Compare Register (upper 4 bits) ---- 0000 N/A

— PWMEN2 PWMEN1 PWMEN0 PMOD3 PMOD2 PMOD1 PMOD0 -111 0000 54, 187

— UDIS OSYNC 0000 0-00 54, 188

(5)

POVD6

(5)

POUT6

Capture 1 Register High Byte/Velocity Register High Byte xxxx xxxx 54

Capture 1 Register Low Byte/Velocity Register Low Byte xxxx xxxx 54

Capture 2 Register High Byte/QEI Position Counter Register High Byte xxxx xxxx 54

Capture 2 Register Low Byte/QEI Position Counter Register Low Byte xxxx xxxx 54

Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte xxxx xxxx 55

Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte xxxx xxxx 55

— CAP1REN — — CAP1M3 CAP1M2 CAP1M1 CAP1M0 -0-- 0000 55, 163

— CAP2REN — — CAP2M3 CAP2M2 CAP2M1 CAP2M0 -0-- 0000 55, 163

— CAP3REN — — CAP3M3 CAP3M2 CAP3M1 CAP3M0 -0-- 0000 55, 163

— FLT4 EN F LT3 EN F LT2E N F LT1 EN F LTC K2 FLT CK1 FLTC K0 -000 0000 55, 177

FLTBMOD

(5)

POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 1111 1111 54, 204

POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0000 0000 54, 204

FLTBEN

(5)

FLTCON FLTAS FLTAMOD FLTAEN 0000 0000 54, 209

Valu e o n

POR, BOR

Details on

page:

PIC18F2331/2431/4331/4431

5.10 Access Bank

The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly.

This data memory region can be used for:

• Intermediate computational values

• Local variables of subroutines

• Faster context saving/switching of variables

• Common variables

• Faster evaluation/control of SFRs (no banking)

The Access Bank is comprised of the last 128 bytes in Bank 15 (SFRs) and the first 128 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 5-6 indicates the Access RAM areas.

A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank. This bit is denoted as the ‘a’ bit (for access bit).

When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function Registers, so these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits.

5.11 Bank Select Register (BSR)

The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using Direct Addressing, the BSR should be configured for the desired bank.

BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read ‘0’s and writes will have no effect (see Figure 5-7).

A MOVLB instruction has been provided in the instruction set to assist in selecting banks.

If the currently selected bank is not implemented, any read will return all ‘0’s and all writes are ignored. The STATUS register bits will be set/cleared as appropriate for the instruction performed.

Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM.

A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word.

Section 5.12 “Indirect Addressing, INDF and FSR Registers” provides a description of Indirect Address-

ing, which allows linear addressing of the entire RAM space.

FIGURE 5-7: DIRECT ADDRESSING

Direct Addressing

BSR<7:4>

BSR<3:0> 7

0000

Bank Select

Note 1: For register file map detail, see Table 5-1.

(2)

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Location Select

From Opcode

Data Memory

(3)

(1)

(3)

00h 01h 0Eh 0Fh

000h

0FFh

100h

1FFh

E00h

EFFh

F00h

FFFh

Bank 0 Bank 1 Bank 14 Bank 15

PIC18F2331/2431/4331/4431

5.12 Indirect Addressing, INDF and FSR Registers

Indirect Addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 5-8 shows how the fetched instruction is modified prior to being executed.

Indirect Addressing is possible by using one of the INDFn registers. Any instruction using the INDFn register actually accesses the register pointed to by the File Select Register, FSRn. Reading the INDFn register itself, indirectly (FSRn = 0), will read 00h. Writing to the INDFn register, indirectly, results in a no operation. The FSRn register contains a 12-bit address, which is shown in Figure 5-9.

The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is Indirect Addressing.

Example 5-5 shows a simple use of Indirect Addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions.

EXAMPLE 5-5: HOW TO CLEAR RAM

(BANK 1) USING INDIRECT ADDRESSING

LFSR FSR0, 0x100 ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then ; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

GOTO NEXT ; NO, clear next

CONTINUE ; YES, continue

There are three Indirect Addressing registers. To address the entire data memory space (4096 bytes), these registers are 12 bits wide. To store the 12 bits of addressing information, two 8-bit registers are required:

1. FSR0: composed of FSR0H:FSR0L.

2. FSR1: composed of FSR1H:FSR1L.

3. FSR2: composed of FSR2H:FSR2L.

In addition, there are registers, INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates Indirect Addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used.

If INDF0, INDF1 or INDF2 are read indirectly via a FSRn, all ‘0’s are read (Zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected.

5.12.1 INDIRECT ADDRESSING OPERATION

Each FSRn register has an INDFn register associated with it, plus four additional register addresses. Performing an operation using one of these five registers determines how the FSRn will be modified during Indirect Addressing.

When data access is performed using one of the five INDFn locations, the address selected will configure the FSRn register to:

• Do nothing to FSRn after an indirect access (no

change) – INDFn

• Auto-decrement FSRn after an indirect access

(post-decrement) – POSTDECn

• Auto-increment FSRn after an indirect access

(post-increment) – POSTINCn

• Auto-increment FSRn before an indirect access

(pre-increment) – PREINCn

• Use the value in the WREG register as an offset

to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) – PLUSWn

When using the auto-increment or auto-decrement features, the effect on the FSRn is not reflected in the STATUS register. For example, if Indirect Addressing causes the FSRn to equal ‘0’, the Z bit will not be set.

Auto-incrementing or auto-decrementing a FSRn affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically.

Adding these features allows the FSRn to be used as a Stack Pointer in addition to its uses for table operations in data memory.

Each FSRn has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSRn to form the address before an indirect access. The FSRn value is not changed. The WREG offset range is -128 to +127.

If an FSRn register contains a value that points to one of the INDFn, an indirect read will read 00h (Zero bit is set), while an indirect write will be equivalent to a NOP (Status bits are not affected).

If an Indirect Addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSRn register, but no pre- or post-increment/decrement is performed.

PIC18F2331/2431/4331/4431

FIGURE 5-8: INDIRECT ADDRESSING OPERATION

RAM

Instruction Executed

Opcode

Address

File Address = access of an Indirect Addressing register

FFFh

BSR<3:0>

Instruction Fetched

Opcode

File

FIGURE 5-9: INDIRECT ADDRESSING

Indirect Addressing

FSRnH:FSRnL

11 0

Location Select

FSRn

Data Memory

0000h

(1)

0FFFh

Note 1: For register file map detail, see Table 5-1.

PIC18F2331/2431/4331/4431

5.13 STATUS Register

The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions not affecting any Status bits, see Table 23-2.

Note: The C and DC bits operate as a borrow

and digit borrow bit respectively, in subtraction.

REGISTER 5-2: STATUS REGISTER

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

(2)

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1).

1 = Result was negative 0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

(1)

bit

bit 1 DC: Digit carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow,

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.

2: For borrow,

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.

the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

bit

(2)

PIC18F2331/2431/4331/4431

5.14 RCON Register

The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO BOR

and RI bits. This register is readable and writable.

, PD, POR,

Note 1: If the BOREN Configuration bit is set

(Brown-out Reset enabled), the BOR is ‘1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset.

2: It is recommended that the POR

after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected.

bit be set

REGISTER 5-3: RCON: RESET CONTROL REGISTER

R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

bit 6-5 Unimplemented: Read as ‘0’

bit 4 RI

bit 3 TO

bit 2 PD

bit 1 POR

bit 0 BOR

— —RITO PD POR BOR

1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a

Brown-out Reset occurs)

: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-Down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction

: Power-on Reset Status bit

1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

bit

PIC18F2331/2431/4331/4431

6.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and erasable during normal operation over the entire V range.

A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code.

While writing or erasing program memory, instruction fetches cease until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases.

A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP.

6.1 Table Reads and Table Writes

In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT).

Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM.

Table write operations store data from TABLAT in the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 “Writing to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data RAM.

Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned, (TBLPTRL<0> = 0).

The EEPROM on-chip timer controls the write and erase times. The write and erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations.

FIGURE 6-1: TABLE READ OPERATION

Table Pointer

TBLPTRU

Note 1: Table Pointer points to a byte in program memory.

TBLPTRH TBLPTRL

(1)

Program Memory (TBLPTR)

Instruction: TBLRD*

Program Memory

Table Latch (8-bit)

TAB LAT

PIC18F2331/2431/4331/4431

FIGURE 6-2: TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Table Pointer

TBLPTRU

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by

TBLPTRH TBLPTRL

TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in

Section 6.5 “Writing to Flash Program Memory”.

(1)

Program Memory (TBLPTR)

Holding Registers

Table Latch (8-bit)

TAB LAT

6.2 Control Registers

Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1 EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences.

Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed.

Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory.

The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled.

The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled – the WR bit cannot be set while the WREN bit is clear. This process helps to prevent accidental writes to memory due to errant (unexpected) code execution.

Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress.

The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It will be necessary to reload the data and address registers (EEDATA and EEADR) as these registers have cleared as a result of the Reset.

Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation.

The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.3 “Reading the

Flash Program Memory” regarding table reads.

Note: Interrupt flag bit, EEIF in the PIR2 register,

is set when the write is complete. It must be cleared in software.

PIC18F2331/2431/4331/4431

REGISTER 6-1: EECON1: FLASH PROGRAM/DATA EEPROM CONTROL REGISTER 1

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS

bit 7 bit 0

Legend: S = Settable only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access program Flash memory 0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers 0 = Access program Flash or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by

completion of erase operation – TBLPTR<5:0> are ignored)

0 = Perform write only

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any Reset during self-timed programming) 0 = The write operation completed normally

bit 2 WREN: Write Enable bit

1 = Allows erase or write cycles 0 = Inhibits erase or write cycles

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.)

0 = Write cycle completed

bit 0 RD: Read Control bit

1 = Initiates a memory read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Read completed

— FREE WRERR

(1)

WREN WR RD

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

PIC18F2331/2431/4331/4431

6.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM.

6.2.3 TBLPTR – TABLE POINTER REGISTER

The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. Setting the 22nd bit allows access to the Device ID, the User ID and the Configuration bits.

The TBLPTR is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits.

6.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the Flash program memory.

When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT.

When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer, TBLPTR (TBLPTR<21:3>), will determine which program memory block of 8 bytes is written to (TBLPTR<2:0> are ignored). For more detail, see Section 6.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations.

TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Example Operation on Table Pointer

TBLRD* TBLWT*

TBLRD*+ TBLWT*+

TBLRD*TBLWT*-

TBLRD+* TBLWT+*

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLPTR is not modified

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

TBLPTRU

ERASE – TBLPTR<21:6>

LONG WRITE – TBLPTR<21:3>

TBLPTRH

READ or WRITE – TBLPTR<21:0>

87 0

TBLPTRL

PIC18F2331/2431/4331/4431

6.3 Reading the Flash Program Memory

The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table

The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT.

reads from program memory are performed one byte at a time.

TBLPTR points to a byte address in program space. Executing a TBLRD instruction places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation.

FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY

Program Memory

Odd (High) Byte

Even (Low) Byte

TBLPTR LSB = 1

Instruction Register

(IR)

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment TBLPTR MOVFW TABLAT ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment TBLPTR MOVFW TABLAT ; get data MOVWF WORD_ODD

TBLPTR LSB = 0

TAB LAT

Read Register

PIC18F2331/2431/4331/4431

6.4 Erasing Flash Program Memory

The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported.

When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The CFGS bit must be clear to access program Flash and data EEPROM memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The WR bit is set as part of the required instruction sequence (as shown in Example 6-2), and starts the actual erase operation. It is not necessary to load the TABLAT register with any data, as it is ignored.

For protection, the write initiate sequence using EECON2 must be used.

A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.

6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE

The sequence of events for erasing a block of internal program memory location is:

1. Load Table Pointer with address of row being

erased.

2. Set the EECON1 register for the erase

operation:

- set EEPGD bit to point to program memory;

- clear the CFGS bit to access program memory;

- set WREN bit to enable writes;

- set FREE bit to enable the erase.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the row erase cycle.

7. The CPU will stall for duration of the erase (about 2 ms using internal timer).

8. Execute a NOP.

9. Re-enable interrupts.

EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL

ERASE_ROW

Required MOVLW 0AAh Sequence MOVWF EECON2 ; write 0AAH

BSF EECON1, EEPGD ; point to Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55H

BSF EECON2, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts

PIC18F2331/2431/4331/4431

6.5 Writing to Flash Program Memory

The programming block size is 4 words or 8 bytes. Word or byte programming is not supported.

Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming.

Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write.

The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.

FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY

TABL AT

Write Register

8 8 8

TBLPTR = xxxxx2

Holding Register

TBLPTR = xxxxx0

Holding Register

TBLPTR = xxxxx1

Holding Register

TBLPTR = xxxxx7

Holding Register

6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE

The sequence of events for programming an internal program memory location should be:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer with address being erased.

4. Do the row erase procedure (see Section 6.4.1

“Flash Program Memory Erase Sequence”).

5. Load Table Pointer with address of first byte

being written.

6. Write the first 8 bytes into the holding registers

with auto-increment.

7. Set the EECON1 register for the write operation:

- set EEPGD bit to point to program memory;

- clear the CFGS bit to access program memory;

- set WREN bit to enable byte writes.

Program Memory

8. Disable interrupts.

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about 2 ms using internal timer).

13. Execute a NOP.

14. Re-enable interrupts.

15. Repeat steps 6-14 seven times, to write 64 bytes.

16. Verify the memory (table read).

This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3.

PIC18F2331/2431/4331/4431

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D'64 ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; 6 LSB = 0 MOVWF TBLPTRL

READ_BLOCK

MODIFY_WORD

ERASE_BLOCK

WRITE_BUFFER_BACK

PROGRAM_LOOP

WRITE_WORD_TO_HREGS

TBLRD*+ ; read into TABLAT, and inc MOVFW TABLAT ; get data MOVWF POSTINC0 ; store data and increment FSR0 DECFSZ COUNTER ; done? GOTO READ_BLOCK ; repeat

MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word and increment FSR0 MOVWF POSTINC0 MOVLW NEW_DATA_HIGH ; update buffer word MOVWF INDF0

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; 6 LSB = 0 MOVWF TBLPTRL BCF EECON1, CFGS ; point to PROG/EEPROM memory BSF EECON1, EEPGD ; point to Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h ; Required sequence MOVWF EECON2 ; write 55H MOVLW 0AAh MOVWF EECON2 ; write 0AAH BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts

MOVLW 8 ; number of write buffer groups of 8 bytes MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L

MOVLW 8 ; number of bytes in holding register MOVWF COUNTER

MOVFW POSTINC0 ; get low byte of buffer data and increment FSR0 MOVWF TABLAT ; present data to table latch TBLWT+* ; short write

; to internal TBLWT holding register, increment

; TBLPTR DECFSZ COUNTER ; loop until buffers are full GOTO WRITE_WORD_TO_HREGS

PIC18F2331/2431/4331/4431

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BCF INTCON, GIE ; disable interrupts MOVLW 55h ; required sequence MOVWF EECON2 ; write 55H MOVLW 0AAh MOVWF EECON2 ; write 0AAH BSF EECON1, WR ; start program (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done GOTO PROGRAM_LOOP BCF EECON1, WREN ; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive

reprogrammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location.

writes can stress bits near the specification limit.

6.6 Flash Program Operation During

6.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION

If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and

See Section 22.5 “Program Verification and Code Protection” for details on code protection of Flash program memory.

TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TBLPTRU

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 0000 0000

TABLAT Program Memory Table Latch 0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL

EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 0000 0000

EECON1 EEPGD CFGS

IPR2 OSCFIP

PIR2 OSCFIF

PIE2 OSCFIE

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.

— —bit 21

— —EEIP —LVDIP— CCP2IP 1--1 -1-1 1--1 -1-1

— — EEIF —LVDIF— CCP2IF 0--0 -0-0 0--0 -0-0

— —EEIE —LVDIE — CCP2IE 0--0 -0-0 0--0 -0-0

(1)

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

— FREE WRERR WREN WR RD xx-0 x000 uu-0 u000

Code Protection

Value on:

POR, BOR

Value on all other

Resets

PIC18F2331/2431/4331/4431

NOTES:

PIC18F2331/2431/4331/4431

7.0 DATA EEPROM MEMORY

The data EEPROM is readable and writable during normal operation over the entire V memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR).

There are four SFRs used to read and write the program and data EEPROM memory. These registers are:

• EECON1

• EECON2

• EEDATA

• EEADR

The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 00h to FFh.

The EEPROM data memory is rated for high erase/ write cycle endurance. A byte write automatically erases the location and writes the new data (erasebefore-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to parameter D122 (Table 25-1 in Section 25.0

“Electrical Characteristics”) for exact limits.

7.1 EEADR

The address register can address 256 bytes of data EEPROM.

7.2 EECON1 and EECON2 Registers

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences.

DD range. The data

Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed.

The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled; the WR bit cannot be set while the WREN bit is clear. This mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution.

The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), as these registers have cleared as a result of the Reset.

Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation.

The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 “Table Reads

and Table Writes” regarding table reads.

Note: Interrupt flag bit, EEIF in the PIR2 register,

is set when write is complete. It must be cleared in software.

PIC18F2331/2431/4331/4431

REGISTER 7-1: EECON1: FLASH PROGRAM/DATA EEPROM CONTROL REGISTER 1

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS

bit 7 bit 0

Legend: S = Settable only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access program Flash memory 0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers 0 = Access program Flash or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by

completion of erase operation)

0 = Perform write only

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (MCLR or WDT Reset during self-timed erase or

program operation)

0 = The write operation completed normally

bit 2 WREN: Erase/Write Enable bit

1 = Allows erase/write cycles 0 = Inhibits erase/write cycles

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.)

0 = Write cycle completed

bit 0 RD: Read Control bit

1 = Initiates a memory read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Read completed

— FREE WRERR

(1)

WREN WR RD

Note 1: When a WRERR occurs, the EEPGD and FREE bits are not cleared. This allows tracing of the error

condition.

PIC18F2331/2431/4331/4431

7.3 Reading the Data EEPROM

Memory

To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).

7.4 Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle.

The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction.

At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software.

7.5 Write Verify

7.6 Protection Against Spurious Write

There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write.

The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction.

EXAMPLE 7-1: DATA EEPROM READ

MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ;

Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts

SLEEP ; Wait for interrupt to signal write complete BCF EECON1, WREN ; Disable writes

PIC18F2331/2431/4331/4431

7.7 Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 22.0 “Special Features of the CPU” for additional information.

7.8 Using the Data EEPROM

The data EEPROM is a high-endurance, byteaddressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124 or D124A. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.

A simple data EEPROM refresh routine is shown in Example 7-3.

Note: If data EEPROM is only used to store con-

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes

LOOP ; Loop to refresh array

BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA Loop ; Not zero, do it again

stants and/or data that changes rarely, an array refresh is likely not required. See specification D124 or D124A.

BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts

TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL

EEADR EEPROM Address Register 0000 0000 0000 0000

EEDATA EEPROM Data Register 0000 0000 0000 0000

EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 0000 0000

EECON1 EEPGD CFGS

IPR2 OSCFIP

PIR2 OSCFIF

PIE2 OSCFIE

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

— —EEIP—LVDIP— CCP2IP 1--1 -1-1 1--1 -1-1

— —EEIF—LVDIF— CCP2IF 0--0 -0-0 0--0 -0-0

— —EEIE—LVDIE— CCP2IE 0--0 -0-0 0--0 -0-0

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

— FREE WRERR WREN WR RD xx-0 x000 uu-0 u000

Value on:

POR, BOR

Value on all other

Resets

PIC18F2331/2431/4331/4431

8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

An 8 x 8 hardware multiplier is included in the ALU of the PIC18F2331/2431/4331/4431 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit Product register pair (PRODH:PRODL). The multiplier does not affect any flags in the STATUS register.

Making the 8 x 8 multiplier execute in a single cycle gives the following advantages:

• Higher computational throughput

• Reduces code size requirements for multiply

algorithms

The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors.

Table 8-1 shows a performance comparison between enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply.

8.2 Operation

Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done.

EXAMPLE 8-1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF ARG1, W MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH

; - ARG1 MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

TABLE 8-1: PERFORMANCE COMPARISON

Program

Routine Multiply Method

8 x 8 Unsigned

8 x 8 Signed

16 x 16 Unsigned

16 x 16 Signed

Without Hardware Multiply 13 69 6.9 μs 27.6 μs 69 μs

Hardware Multiply 1 1 100 ns 400 ns 1 μs

Without Hardware Multiply 33 91 9.1 μs 36.4 μs 91 μs

Hardware Multiply 6 6 600 ns 2.4 μs6 μs

Without Hardware Multiply 21 242 24.2 μs 96.8 μs242 μs

Hardware Multiply 24 24 2.4 μs9.6 μs 24 μs

Without Hardware Multiply 52 254 25.4 μs102.6 μs254 μs

Hardware Multiply 36 36 3.6 μs 14.4 μs 36 μs

Memory (Words)

Cycles

(Max)

Time

@ 40 MHz @ 10 MHz @ 4 MHz

PIC18F2331/2431/4331/4431

Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2 (ARG1L • ARG2H • 2 (ARG1L • ARG2L)

) +

EXAMPLE 8-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L ->

MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H ->

MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H ->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

;

MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L ->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pair’s Most Significant bit (MSb) is tested and the appropriate subtractions are done.

; PRODH:PRODL

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION ALGORITHM

RES3:RES0

= ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 2 (ARG1L • ARG2H ² 2

) +

(ARG1L • ARG2L)+ (-1 • ARG2H<7> • ARG1H:ARG1L • 2 (-1 • ARG1H<7> • ARG2H:ARG2L • 2

EXAMPLE 8-4: 16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L ->

MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H ->

MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ;

;

MOVF ARG1L,W MULWF ARG2H ; ARG1L * ARG2H ->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

;

MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L ->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; MOVF ARG1H, W ;

SUBWFB RES3 ; SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3 ; CONT_CODE

; PRODH:PRODL

) +

)

PIC18F2331/2431/4331/4431

9.0 INTERRUPTS

The PIC18F2331/2431/4331/4431 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high-priority level or a low-priority level. The highpriority interrupt vector is at 000008h and the low-priority interrupt vector is at 000018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.

There are thirteen registers which are used to control interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files supplied with MPLAB names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register.

In general, each interrupt source has three bits to control its operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event occurred

• Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set

• Priority bit to select high priority or low priority (most interrupt sources have priority bits)

The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.

IDE be used for the symbolic bit

When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC bility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode.

When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a lowpriority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress.

The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INTx pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the Interrupt Control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.

mid-range devices. In Compati-

PIC18F2331/2431/4331/4431

FIGURE 9-1: INTERRUPT LOGIC

TMR0IF TMR0IE TMR0IP

RBIF RBIE RBIP

INT0IF INT0IE

INT1IF

INT1IE TXIF TXIE TXIP

ADIF

ADIE

ADIP

RCIF RCIE RCIP

High-Priority Interrupt Generation

Low-Priority Interrupt Generation

IPEN

Additional Peripheral Interrupts

INT1IP

INT2IF

INT2IE

INT2IP

IPEN

PEIE/GIEL

IPEN

Wake-up i f in Power-Managed Mode

Interrupt to CPU Vector to Location 0008h

GIE/GIEH

ADIF ADIE ADIP

RCIF RCIE RCIP

TXIF TXIE TXIP

Additional Peripheral Interrupts

TMR0IF TMR0IE

TMR0IP

RBIF RBIE

RBIP

INT0IF INT0IE

INT1IF INT1IE

INT1IP INT2IF

INT2IE INT2IP

PEIE/GIEL

Interrupt to CPU Vector to Location 0018h

PIC18F2331/2431/4331/4431

9.1 INTCON Registers

The INTCON registers are readable and writable registers which contain various enable, priority and flag bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.

REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN =

1 = Enables all unmasked interrupts 0 = Disables all interrupts

When IPEN =

1 = Enables all high-priority interrupts 0 = Disables all high-priority interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN =

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

When IPEN =

1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt for RB7:RB4 pins 0 = Disables the RB port change interrupt for RB7:RB4 pins

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

(1)

Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and

allow the bit to be cleared.

PIC18F2331/2431/4331/4431

REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1

RBPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP

bit 7 RBPU

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

bit 3 Unimplemented: Read as ‘0’

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

bit 1 Unimplemented: Read as ‘0’

bit 0 RBIP: RB Port Change Interrupt Priority bit

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.

: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge 0 = Interrupt on falling edge

1 =High priority 0 = Low priority

PIC18F2331/2431/4331/4431

REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

INT2IP INT1IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 =High priority 0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 =High priority 0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur

—

INT2IE INT1IE

—

INT2IF INT1IF

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F2331/2431/4331/4431

9.2 PIR Registers

The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) Registers (PIR1, PIR2 and PIR3).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.

REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIF: A/D Converter Interrupt Flag bit

bit 5 RCIF: EUSART Receive Interrupt Flag bit

bit 4 TXIF: EUSART Transmit Interrupt Flag bit

bit 3 SSPIF: Synchronous Serial Port Interrupt Flag bit

bit 2 CCP1IF: CCP1 Interrupt Flag bit

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete

1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty

1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full

1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM mode: Unused in this mode.

1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred

1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow

Datasheet PIC18F2331, PIC18F2431, PIC18F4331, PIC18F4431 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

14-Bit Power Control PWM Module:

Motion Feedback Module:

High-Speed, 200 ksps 10-Bit A/D Converter:

Flexible Oscillator Structure:

Power-Managed Modes:

Peripheral Highlights:

Special Microcontroller Features:

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 New Core Features

1.1.1 nanoWatt Technology

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES

FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM

FIGURE 1-2: PIC18F4331/4431 BLOCK DIAGRAM

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

2.2 Crystal Oscillator/Ceramic Resonators

2.3 HSPLL

FIGURE 2-3: PLL BLOCK DIAGRAM

2.4 External Clock Input

2.5 RC Oscillator

FIGURE 2-6: RC OSCILLATOR MODE

FIGURE 2-7: RCIO OSCILLATOR MODE

2.6 Internal Oscillator Block

2.6.2 INTRC OUTPUT FREQUENCY

2.6.3 OSCTUNE REGISTER

2.6.1 INTIO MODES

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

2.7.1 OSCILLATOR CONTROL REGISTER

FIGURE 2-8: PIC18F2331/2431/4331/4431 CLOCK DIAGRAM

REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER

2.7.2 OSCILLATOR TRANSITIONS

2.8 Effects of Power-Managed Modes on the Various Clock Sources

2.9 Power-up Delays

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

3.0 POWER-MANAGED MODES

3.1 Selecting Power-Managed Modes

3.1.1 CLOCK SOURCES

TABLE 3-1: POWER-MANAGED MODES

3.1.2 ENTERING POWER-MANAGED MODES

3.1.3 MULTIPLE SLEEP COMMANDS

3.1.4 COMPARISONS BETWEEN RUN AND IDLE MODES

TABLE 3-2: COMPARISON BETWEEN POWER-MANAGED MODES

3.2 Sleep Mode

3.3 Idle Modes

FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE

FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

3.3.1 PRI_IDLE MODE

FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE

FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE

3.3.2 SEC_IDLE MODE

FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE

FIGURE 3-6: TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)

3.3.3 RC_IDLE MODE

FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE

FIGURE 3-8: TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)

3.4 Run Modes

3.4.1 PRI_RUN MODE

3.4.2 SEC_RUN MODE

FIGURE 3-9: TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE

3.4.3 RC_RUN MODE

FIGURE 3-10: TIMING TRANSITION TO RC_RUN MODE

3.4.4 EXIT TO IDLE MODE

3.4.5 EXIT TO SLEEP MODE

3.5.1 EXIT BY INTERRUPT