Datasheet PIC18F2423, PIC18F2523, PIC18F4423, PIC18F4523 Datasheet

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PIC18F2423/2523/4423/4523

Data Sheet

28/40/44-Pin, Enhanced Flash

Microcontrollers with 12-Bit A/D

and nanoWatt Technology

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

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The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC

logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

PIC18F2423/2523/4423/4523

28/40/44-Pin, Enhanced Flash Microcontrollers with

12-Bit A/D and nanoWatt Technology

Power Management Features:

• Run: CPU on, Peripherals on

• Idle: CPU off, Peripherals on

• Sleep: CPU off, Peripherals off

• Ultra Low 50 nA Input Leakage

• Run mode Currents Down to 11 μA Typical

• Idle mode Currents Down to 2.5 μA Typical

• Sleep mode Current Down to 100 μA Typical

• Timer1 Oscillator: 900 nA, 32 kHz, 2V

• Watchdog Timer: 1.4 μA, 2V Typical

• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

• Four Crystal modes, up to 40 MHz

• 4x Phase Lock Loop (PLL) – Available for Crystal and Internal Oscillators

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal Oscillator Block:

- Fast wake from Sleep and Idle, 1 μs typical

- 8 user-selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds,

from 31 kHz to 32 MHz, when used with PLL

- User-tunable to Compensate for Frequency Drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock stops

Peripheral Highlights:

• 12-Bit, Up to 13-Channel Analog-to-Digital Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep mode

• Dual Analog Comparators with Input Multiplexing

• High-Current Sink/Source 25 mA/25 mA

• Three Programmable External Interrupts

• Four Input Change Interrupts

• Up to Two Capture/Compare/PWM (CCP) modules, One with Auto-Shutdown (28-pin devices)

• Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only):

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

Peripheral Highlights (Continued):

• Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all four modes) and I Master and Slave modes

• Enhanced USART module:

- Support for RS-485, RS-232 and LIN/J2602

- RS-232 operation using internal oscillator

block (no external crystal required)

- Auto-wake-up on Start bit

- Auto-Baud Detect (ABD)

C™

Special Microcontroller Features:

• C Compiler Optimized Architecture: Optional Extended Instruction Set Designed to Optimize Re-Entrant Code

• 100,000 Erase/Write Cycle, Enhanced Flash Program Memory Typical

• 1,000,000 Erase/Write Cycle, Data EEPROM Memory Typical

• Flash/Data EEPROM Retention: 100 Years Typical

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT): Programmable Period, from 4 ms to 131s

• Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Operating Voltage Range: 2.0V to 5.5V

• Programmable, 16-Level High/Low-Voltage Detection (HLVD) module: Supports Interrupt on High/Low-Voltage Detection

• Programmable Brown-out Reset (BOR): With Software-Enable Option

Note: This document is supplemented by the

“PIC18F2420/2520/4420/4520 Data Sheet”

(DS39631). See Section 1.0 “Device Overview”.

Program Memory Data Memory

Device

PIC18F2423 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3 PIC18F2523 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3 PIC18F4423 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3 PIC18F4523 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3

Flash

(bytes)

# Single-Word

Instructions

SRAM (bytes)

EEPROM

(bytes)

I/O

12-Bit

A/D (ch)

CCP/

ECCP

(PWM)

SPI

MSSP

Master

C™

Comp.

EUSART

Timers

8/16-Bit

PIC18F2423/2523/4423/4523

PIC18F2523

10 11

2 3 4 5 6

12 13 14

22 21

MCLR/VPP/RE3

RA0/AN0 RA1/AN1

RA2/AN2/V

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS

/HLVDIN/C2OUT

OSC1/CLKI

(3)

/RA7

OSC2/CLKO

(3)

/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

(2)

RC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2

(2)

RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 V

VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

28-Pin PDIP, SOIC

PIC18F2423

Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.

2: RB3 is the alternate pin for CCP2 multiplexing. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. For additional information, see Section 2.0 “Oscillator Configurations” of the

“PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).

10 11

2 3

12 13 14

232425262728

PIC18F2423

RC0/T1OSO/T13CKI

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4KBI0/AN11

RB3/AN9/CCP2

(2)

RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 V

VSS RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

MCLR

/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS

/HLVDIN/C2OUT

OSC1/CLKI

(3)

/RA7

OSC2/CLKO

(3)

/RA6

RC1/T1OSI/CCP2

(2)

RC2/CCP1

RC3/SCK/SCL

PIC18F2523

28-Pin QFN

(1)

Pin Diagrams

RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2

(1)

RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 V

VSS RD7/PSP7/P1D RD6/PSP6/P1C

RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

RD3/PSP3 RD2/PSP2

MCLR/VPP/RE3

RA0/AN0 RA1/AN1

RA2/AN2/V

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS

/HLVDIN/C2OUT

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS

/AN7

VSS

OSC1/CLKI

(2)

/RA7

OSC2/CLKO

(2)

/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0 RD1/PSP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

PIC18F4523

40-Pin PDIP

PIC18F4423

10 11

2 3 4 5 6

1819202122

121314

4443424140

363435

PIC18F4423

RA3/AN3/VREF+

RA2/AN2/V

REF-/CVREF

RA1/AN1

RA0/AN0

MCLR

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

(1)

NC RC0/T1OSO/T13CKI OSC2/CLKO

(2)

/RA6

OSC1/CLKI

(2)

/RA7

VDD RE2/CS/AN7 RE1/WR

/AN6

RE0/RD

/AN5

RA5/AN4/SS

/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D

VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2

(1)

44-Pin TQFP

PIC18F4523

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. For additional information, see Section 2.0 “Oscillator Configurations” of the

“PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).

PIC18F2423/2523/4423/4523

Pin Diagrams (Continued)

PIC18F2423/2523/4423/4523

10 11

2 3 4 5 6

1819202122

121314

4443424140

363435

PIC18F4423

RA3/AN3/V

REF+

RA2/AN2/V

REF-/CVREF

RA1/AN1

RA0/AN0

MCLR

/VPP/RE3

RB3/AN9/CCP2

(2)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

(2)

RC0/T1OSO/T13CKI

OSC2/CLKO

(3)

/RA6

OSC1/CLKI

(3)

/RA7

VSS VDD VDD RE2/CS/AN7 RE1/WR

/AN6

RE0/RD

/AN5

RA5/AN4/SS

/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D

VDD VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

44-Pin QFN

(1)

PIC18F4523

Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.

2: RB3 is the alternate pin for CCP2 multiplexing. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. For additional information, see Section 2.0 “Oscillator Configurations” of the

“PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).

Pin Diagrams (Continued)

PIC18F2423/2523/4423/4523

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 25

3.0 Special Features of the CPU...................................................................................................................................................... 35

4.0 Electrical Characteristics............................................................................................................................................................ 37

5.0 Packaging Information................................................................................................................................................................ 43

Appendix A: Revision History............................................................................................................................................................... 45

Appendix B: Device Differences .......................................................................................................................................................... 45

Appendix C: Conversion Considerations ............................................................................................................................................. 46

Appendix D: Migration from Baseline to Enhanced Devices................................................................................................................ 46

Appendix E: Migration from Mid-Range to Enhanced Devices ............................................................................................................ 47

Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................... 47

Index ................................................................................................................................................................................................... 49

The Microchip Web Site....................................................................................................................................................................... 51

Customer Change Notification Service ................................................................................................................................................ 51

Customer Support ................................................................................................................................................................................ 51

Reader Response ................................................................................................................................................................................ 52

Product Identification System .............................................................................................................................................................. 53

PIC18F2423/2523/4423/4523

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

PIC18F2423/2523/4423/4523

1.0 DEVICE OVERVIEW

This document contains device-specific information for the following devices:

• PIC18F2423 • PIC18LF2423

• PIC18F2523 • PIC18LF2523

• PIC18F4423 • PIC18LF4423

• PIC18F4523 • PIC18LF4523

Note: This data sheet documents only the devices’

features and specifications that are in addition to, or different from, the features and specifications of the PIC18F2420/2520/4420/4520 devices. For information on the features and specifications shared by the PIC18F2423/ 2523/4423/4523 and PIC18F2420/2520/ 4420/4520 devices, see the “PIC18F2420/ 2520/4420/4520 Data Sheet” (DS39631).

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory. On top of these features, the PIC18F2423/2523/4423/ 4523 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power-sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2423/2523/4423/4523 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller also can run with its CPU core disabled and the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements.

• On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 4.0 “Electrical Characteristics” for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2423/2523/4423/4523 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).

• Two External RC Oscillator modes with the same

pin options as the External Clock modes.

• An internal oscillator block that offers eight clock

frequencies: an 8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of six user-selectable clock frequencies, between 125 kHz to 4 MHz. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and Internal Oscillator modes, allowing clock speeds of up to 40 MHz from the HS clock source. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz, all without using an external crystal or clock circuit.

Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: Constantly monitors

the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown.

• Two-Speed Start-up: Allows the internal oscillator

to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

PIC18F2423/2523/4423/4523

1.2 Other Special Features

• 12-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, thereby reducing code overhead.

• Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

• Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it is possible to create an application that can update itself in the field.

• Extended Instruction Set: The PIC18F2423/ 2523/4423/4523 family introduces an optional extension to the PIC18 instruction set that adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C.

• Enhanced CCP module: In PWM mode, this module provides one, two or four modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select conditions, and auto-restart, to reactivate outputs once the condition has cleared.

• Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN/J2602 bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement).

• Extended Watchdog Timer (WDT): This Enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 4.0 “Electrical Characteristics” for time-out periods.

1.3 Details on Individual Family Members

Devices in the PIC18F2423/2523/4423/4523 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in these ways:

• Flash Program Memory:

- PIC18F2423/4423 devices – 16 Kbytes

- PIC18F2523/4523 devices – 32 Kbytes

• A/D Channels:

- PIC18F2423/2523 devices – 10

- PIC18F4423/4523 devices – 13

• I/O Ports:

- PIC18F2423/2523 devices – Three bidirectional ports

- PIC18F4423/4523 devices – Five bidirectional ports

• CCP and Enhanced CCP Implementation:

- PIC18F2423/2523 devices – Two standard CCP modules

- PIC18F4423/4523 devices – One standard CCP module and one ECCP module

• Parallel Slave Port – Present only on PIC18F4423/4523 devices

All other features for devices in this family are identical. These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and Table 1-3.

Members of the PIC18F2423/2523/4423/4523 family are available only as low-voltage devices, designated by “LF” (such as PIC18LF2423), and function over an extended V

DD range of 2.0V to 5.5V.

PIC18F2423/2523/4423/4523

TABLE 1-1: DEVICE FEATURES

Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 16,384 32,768 16,384 32,768

Program Memory (Instructions) 8,192 16,384 8,192 16,384

Data Memory (Bytes) 768 1,536 768 1,536

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 2 2 1 1

Enhanced Capture/Compare/PWM Modules

Serial Communications MSSP,

Parallel Communications (PSP) No No Yes Yes

12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

Resets (and Delays) POR, BOR,

Underflow (PWRT, OST),

MCLR

Programmable High/Low-Voltage Detect

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;

Instruction Set enabled

Packages 28-Pin PDIP

0011

Enhanced USART

RESET Instruction,

Stack Full, Stack

(optional), WDT

Ye s Ye s Ye s Ye s

83 with Extended

28-Pin SOIC

28-Pin QFN

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT, OST),

MCLR (optional), WDT

75 Instructions;

83 with Extended

Instruction Set enabled

28-Pin PDIP 28-Pin SOIC

28-Pin QFN

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT, OST),

MCLR (optional), WDT

75 Instructions;

83 with Extended

Instruction Set enabled

40-Pin PDIP

44-Pin QFN

44-Pin TQFP

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT, OST),

MCLR (optional), WDT

75 Instructions;

83 with Extended

Instruction Set enabled

40-Pin PDIP

44-Pin QFN

44-Pin TQFP

PIC18F2423/2523/4423/4523

Instruction

Decode and

Control

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT RA5/AN4/SS

/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI RC1/T1OSI/CCP2

(1)

RC2/CCP1 RC3/SCK/SCL

RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10

Data Latch

Data Memory

( 3.9 Kbytes )

Address Latch

Data Address<12>

Access

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP

ALU<8>

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

RB2/INT2/AN8 RB3/AN9/CCP2

(1)

PCLATU

PCU

OSC2/CLKO

(3)

/RA6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).

RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD

EUSARTComparator

MSSP

12-Bit

ADC

Timer2Timer1 Tim er3Timer0

CCP2

HLVD

CCP1

BOR

Data

EEPROM

Instruction Bus <16>

STKPTR

Bank

State Machine Control Signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

MCLR

(2)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply Programming

In-Circuit

Debugger

T1OSO

OSC1/CLKI

(3)

/RA7

T1OSI

PORTE

MCLR/VPP/RE3

(2)

FIGURE 1-1: PIC18F2423/2523 (28-PIN) BLOCK DIAGRAM

PIC18F2423/2523/4423/4523

Instruction

Decode and

Control

Data Latch

Data Memory

( 3.9 Kbytes )

Address Latch

Data Address<12>

Access

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP

ALU<8>

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PORTD

RD0/PSP0

PCLATU

PCU

PORTE

MCLR/VPP/RE3

(2)

RE2/CS/AN7

RE0/RD/AN5 RE1/WR/AN6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).

:RD4/PSP4

EUSARTComparator

MSSP

12-Bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR

Data

EEPROM

Instruction Bus <16>

STKPTR

Bank

State Machine Control Signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(3)

OSC2

(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

MCLR

(2)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT RA5/AN4/SS

/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2

(1)

OSC2/CLKO

(3)

/RA6

RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD

OSC1/CLKI

(3)

/RA7

FIGURE 1-2: PIC18F4423/4523 (40/44-PIN) BLOCK DIAGRAM

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

C=I2C™/SMBus

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PDIP, SOIC

QFN

126

10 7

Typ e

I/O

Buffer

Type

CMOS

TTL

—

TTL

Description

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/VREF-/CVREF

RA2 AN2 VREF-

REF

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI/C1OUT

RA4 T0CKI C1OUT

RA5/AN4/SS C2OUT

RA5 AN4 SS HLVDIN C2OUT

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

REF+

/HLVDIN/

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

C=I2C™/SMBus

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PDIP, SOIC

227

328

QFN

Buffer

Typ e

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

Analog

I/O

TTL

Analog

I/O

TTL

Analog

TTL

Analog

PORTA is a bidirectional I/O port.

Digital I/O. Analog Input 0.

Digital I/O. Analog Input 1.

Digital I/O. Analog Input 2. A/D reference voltage (low) input. Comparator reference voltage output.

Digital I/O. Analog Input 3. A/D reference voltage (high) input.

ST ST

—

Digital I/O. Timer0 external clock input. Comparator 1 output.

Digital I/O. Analog Input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output.

Description

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/INT0/FLT0/AN12

RB0 INT0 FLT0 AN12

RB1/INT1/AN10

RB1 INT1 AN10

RB2/INT2/AN8

RB2 INT2 AN8

RB3/AN9/CCP2

RB3 AN9

(1)

CCP2

RB4/KBI0/AN11

RB4 KBI0 AN11

RB5/KBI1/PGM

RB5 KBI1 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

C=I2C™/SMBus

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PDIP, SOIC

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Typ e

I/O

I I I

I/O

I I

I/O

I I

I/O

I I

I/O

Buffer

Type

TTL

ST ST

Analog

TTL

Analog

TTL

Analog

TTL

Analog

TTL TTL

Analog

TTL TTL

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External Interrupt 0. PWM Fault input for CCP1. Analog Input 12.

Digital I/O. External Interrupt 1. Analog Input 10.

Digital I/O. External Interrupt 2. Analog Input 8.

Digital I/O. Analog Input 9. Capture 2 input/Compare 2 output/PWM2 output.

Digital I/O. Interrupt-on-change pin. Analog Input 11.

Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/CCP2

RC1 T1OSI

(2)

CCP2

RC2/CCP1

RC2 CCP1

RC3/SCK/SCL

RC3 SCK SCL

RC4/SDI/SDA

RC4 SDI SDA

RC5/SDO

RC5 SDO

RC6/TX/CK

RC6 TX CK

RC7/RX/DT

RC7 RX DT

RE3 — — — — See MCLR

SS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

DD 20 17 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

C=I2C™/SMBus

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PDIP, SOIC

11 8

12 9

13 10

14 11

15 12

16 13

17 14

18 15

QFN

Buffer

Typ e

Type

I/O

Analog

I/O

I/O I/OSTST

I/O I/O I/O

I/O

I/OOST

I/O

PORTC is a bidirectional I/O port.

—

ST ST

—

ST ST ST

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output.

Digital I/O. Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C™ mode.

Digital I/O. SPI data in. I2C data I/O.

Digital I/O. SPI data out.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT).

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK).

/VPP/RE3 pin.

Description

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS

Pin Name

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

C=I2C™/SMBus

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Pin Number

PDIP QFN TQFP

11818

13 32 30

14 33 31

Type

I/O

Buffer

Typ e

CMOS

TTL

—

TTL

Description

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/C1OUT

RA5/AN4/SS C2OUT

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

REF-/CVREF

RA2 AN2 VREF-

REF

REF+

RA3 AN3

REF+

RA4 T0CKI C1OUT

/HLVDIN/

RA5 AN4 SS HLVDIN C2OUT

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

C=I2C™/SMBus

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Pin Number

PDIP QFN TQFP

21919

32020

42121

52222

62323

72424

Buffer

Type

Typ e

I/OITTL

Analog

I/OITTL

Analog

I/O

Analog

I/O

Analog

I/O

Analog I I

Analog

PORTA is a bidirectional I/O port.

Digital I/O. Analog Input 0.

Digital I/O. Analog Input 1.

TTL

ST ST

—

TTL

—

Digital I/O. Analog Input 2. A/D reference voltage (low) input. Comparator reference voltage output.

Digital I/O. Analog Input 3. A/D reference voltage (high) input.

Digital I/O. Timer0 external clock input. Comparator 1 output.

Digital I/O. Analog Input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output.

Description

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0/AN12

RB0 INT0 FLT0 AN12

RB1/INT1/AN10

RB1 INT1 AN10

RB2/INT2/AN8

RB2 INT2 AN8

RB3/AN9/CCP2

RB3 AN9

(1)

CCP2

RB4/KBI0/AN11

RB4 KBI0 AN11

RB5/KBI1/PGM

RB5 KBI1 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

C=I2C™/SMBus

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Pin Number

PDIP QFN TQFP

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Type

I/O

I I I

I/O

I I

I/O

I I

I/O

I I

I/O

Buffer

Typ e

TTL

ST ST

Analog

TTL

Analog

TTL

Analog

TTL

Analog

TTL TTL

Analog

TTL TTL

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External Interrupt 0. PWM Fault input for Enhanced CCP1. Analog Input 12.

Digital I/O. External Interrupt 1. Analog Input 10.

Digital I/O. External Interrupt 2. Analog Input 8.

Digital I/O. Analog Input 9. Capture 2 input/Compare 2 output/PWM2 output.

Digital I/O. Interrupt-on-change pin. Analog Input 11.

Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/CCP2

RC1 T1OSI

(2)

CCP2

RC2/CCP1/P1A

RC2 CCP1 P1A

RC3/SCK/SCL

RC3 SCK

SCL

RC4/SDI/SDA

RC4 SDI SDA

RC5/SDO

RC5 SDO

RC6/TX/CK

RC6 TX CK

RC7/RX/DT

RC7 RX DT

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

C=I2C™/SMBus

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Pin Number

PDIP QFN TQFP

15 34 32

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Buffer

Type

I/O

CMOS

I/O

I/O I/O

I/O

I/OOST

I/O

Typ e

PORTC is a bidirectional I/O port.

ST ST

ST ST ST

—

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Enhanced CCP1 output.

Digital I/O. Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C™ mode.

Digital I/O. SPI data in.

C data I/O.

Digital I/O. SPI data out.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT).

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK).

Description

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/PSP0

RD0 PSP0

RD1/PSP1

RD1 PSP1

RD2/PSP2

RD2 PSP2

RD3/PSP3

RD3 PSP3

RD4/PSP4

RD4 PSP4

RD5/PSP5/P1B

RD5 PSP5 P1B

RD6/PSP6/P1C

RD6 PSP6 P1C

RD7/PSP7/P1D

RD7 PSP7 P1D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

C=I2C™/SMBus

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Pin Number

PDIP QFN TQFP

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Buffer

Type

Typ e

I/O I/OSTTTL

I/O I/O

TTL

I/O I/O

TTL

I/O I/O

TTL

Description

PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled.

Digital I/O. Parallel Slave Port data.

—

Digital I/O. Parallel Slave Port data. Enhanced CCP1 output.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/RD

RE1/WR/AN6

RE2/CS

RE3 — — — — — See MCLR

NC — 13 12, 13,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

/AN5 RE0 RD

AN5

RE1 WR

AN6

/AN7 RE2 CS

AN7

SS 12, 31 6, 30,

DD 11, 32 7, 8,

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

C=I2C™/SMBus

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Pin Number

PDIP QFN TQFP

82525

92626

10 27 27

6, 29 P — Ground reference for logic and I/O pins.

7, 28 P — Positive supply for logic and I/O pins.

28, 29

33, 34

Buffer

Type

Typ e

PORTE is a bidirectional I/O port.

I/O

— — No connect.

TTL

Analog

TTL

Analog

TTL

Analog

Digital I/O. Read control for Parallel Slave Port (see also WR Analog Input 5.

Digital I/O. Write control for Parallel Slave Port (see CS Analog Input 6.

Digital I/O. Chip select control for Parallel Slave Port (see related RD Analog Input 7.

Description

and CS pins).

and RD pins).

and WR).

/VPP/RE3 pin.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

2.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) Converter module has 10 inputs for the PIC18F2423/2523 devices and 13 for the PIC18F4423/4523 devices. This module allows conversion of an analog input signal to a corresponding 12-bit digital number.

The module has five registers:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

Of the ADCONx registers:

• ADCON0 (shown in Register 2-1) – Controls the module’s operation

• ADCON1 (Register 2-2) – Configures the functions of the port pins

• ADCON2 (Register 2-3) – Configures the A/D clock source, programmed acquisition time and justification

REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12 1101 = Unimplemented 1110 = Unimplemented 1111 = Unimplemented

bit 1 GO/DONE

When ADON =

1 = A/D conversion in progress 0 = A/D Idle

bit 0 ADON: A/D On bit

1 = A/D Converter module is enabled 0 = A/D Converter module is disabled

: A/D Conversion Status bit

(2)

(1,2)

Note 1: These channels are not implemented on PIC18F2423/2523 devices.

2: Performing a conversion on unimplemented channels will return a floating input measurement.

PIC18F2423/2523/4423/4523

A = Analog input D = Digital I/O

PCFG<3:0>

AN12

AN11

AN10

AN9

AN8

AN7

(2)

AN6

(2)

AN5

(2)

AN4

AN3

AN2

AN1

AN0

0000

(1)

A A AAAAAAAAAAA

0001 AA A AAAAAAAAAA 0010 AA A AAAAAAAAAA 0011 D A AAAAAAAAAAA 0100 DDAAAAAAAAAAA 0101 DDDAAAAAAAAAA 0110 DDDDAAAAAAAAA

0111

(1)

DDDDDAAAAAAAA

1000 D D DDDDAAAAAAA 1001 D D DDDDDAAAAAA 1010 D D DDDDDDAAAAA 1011 D D DDDDDDDAAAA 1100 D D DDDDDDDDAAA 1101 D D DDDDDDDDDAA 1110 D D DDDDDDDDDDA 1111 D D DDDDDDDDDDD

REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1

U-0 U-0 R/W-0 R/W-0 R/W-0

(1)

— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 VCFG1: Voltage Reference Configuration bit (V

1 = V

REF- (AN2)

0 = V

REF- source)

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)

REF+ (AN3)

1 = V

0 = V

bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits:

R/W

(1)

R/W

(1)

R/W

(1)

Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When

PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.

2: AN5 through AN7 are only available on PIC18F4423/4523 devices.

PIC18F2423/2523/4423/4523

REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified 0 = Left justified

bit 6 Unimplemented: Read as ‘0’

bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits

111 = 20 T 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD

bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits

111 = FRC (clock derived from A/D RC oscillator) 110 = F 101 = F 100 = F 011 = F 010 = F 001 = F 000 = F

(1)

OSC/64 OSC/16 OSC/4 RC (clock derived from A/D RC oscillator) OSC/32 OSC/8 OSC/2

(1)

Note 1: If the A/D F

RC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D

clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

PIC18F2423/2523/4423/4523

(Input Voltage)

AIN

VREF+

Reference

Voltage

(2)

VCFG<1:0>

CHS<3:0>

AN7

(1)

AN6

(1)

AN5

(1)

AN4

AN3

AN2

AN1

AN0

0111

0110

0101

0100

0011

0010

0001

0000

12-Bit

A/D

VREF-

VSS

(2)

Converter

AN12

AN11

AN10

AN9

AN8

1100

1011

1010

1001

1000

Note 1: Channels, AN5 through AN7, are not available on PIC18F2423/2523 devices.

2: I/O pins have diode protection to VDD and VSS.

The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/

REF+ and RA2/AN2/VREF-/CVREF pins.

The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the converter, which generates the result via successive approximation.

FIGURE 2-1: A/D BLOCK DIAGRAM

A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted.

Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE

bit (ADCON0<1>) is cleared

and A/D Interrupt Flag bit, ADIF, is set.

The block diagram of the A/D module is shown in Figure 2-1.

PIC18F2423/2523/4423/4523

Digital Code Output

FFEh

003h

002h

001h

000h

0.5 LSB

1 LSB

1.5 LSB

2 LSB

2.5 LSB 4094 LSB

4094.5 LSB

3 LSB

Analog Input Voltage

FFFh

4095 LSB

4095.5 LSB

VAIN

CPIN

ANx

5 pF

T = 0.6V

LEAKAGE

RIC ≤ 1k

Sampling

Switch

CHOLD = 25 pF

VDD

±100 nA

Legend: CPIN

VT ILEAKAGE

RIC SS C

HOLD

= Input Capacitance

= Threshold Voltage = Leakage Current at the pin due to

= Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance (from DAC)

various junctions

= Sampling Switch ResistanceRSS

VDD

Sampling Switch

5V 4V 3V 2V

1234

(kΩ)

The value in the ADRESH:ADRESL registers is unknown following POR and BOR Resets and is not affected by any other Reset.

After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 2.1 “A/D Acquisition Requirements”.

After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion.

The following steps should be followed to perform an A/D conversion:

1. Configure the A/D module:

• Configure analog pins, voltage reference and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCON2)

• Turn on the A/D module (ADCON0)

2. Configure the A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion by setting the GO/DONE

bit

(ADCON0<1>).

5. Wait for the A/D conversion to complete by either:

• Polling for the GO/DONE

bit to be cleared

• Waiting for the A/D interrupt

6. Read the A/D Result registers (ADRESH:ADRESL) and clear the ADIF bit, if required.

7. For the next conversion, go to step 1 or step 2, as required.

The A/D conversion time per bit is defined as

AD. A minimum wait of 2 TAD is required before

T the next acquisition starts.

FIGURE 2-2: A/D TRANSFER FUNCTION

FIGURE 2-3: ANALOG INPUT MODEL

PIC18F2423/2523/4423/4523

2.1 A/D Acquisition Requirements

For the A/D Converter to meet its specified accuracy, the charge holding capacitor (C to fully charge to the input channel voltage level. The analog input model is shown in Figure 2-3.

The source impedance (R switch (R

SS) impedance directly affect the time

required to charge the capacitor, C switch (R (V

SS) impedance varies over the device voltage

DD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog sources is 2.5 kΩ.

After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion.

HOLD) must be allowed

S) and the internal sampling

HOLD. The sampling

To calculate the minimum acquisition time, Equation 2-1 may be used. This equation assumes that 1/2 LSb error is used (4,096 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.

Example 2-3 shows the calculation of the minimum required acquisition time, T based on the application system assumptions shown in Table 2-1:

TABLE 2-1: TACQ ASSUMPTIONS

CHOLD = 25 pF

Rs = 2.5 kΩ

Conversion Error ≤ 1/2 LSb

DD =3V → Rss = 4 kΩ

Temperature = 85°C (system maximum)

Note: When the conversion is started, the

holding capacitor is disconnected from the input pin.

EQUATION 2-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

AMP + TC + TCOFF

ACQ. This calculation is

EQUATION 2-2: A/D MINIMUM CHARGING TIME

VHOLD = (VREF – (VREF/4096)) • (1 – e or

C = -(CHOLD)(RIC + RSS + RS) ln(1/4096)

(-TC/CHOLD(RIC + RSS + RS))

)

EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

ACQ =TAMP + TC + TCOFF

TAMP =0.2 μs

COFF = (Temp – 25°C)(0.02 μs/°C)

(85°C – 25°C)(0.02 μs/°C)

1.2 μs

Temperature coefficient is only required for temperatures > 25°C. Below 25°C, T

C = -(CHOLD)(RIC + RSS + RS) ln(1/4095) μs

-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0004883) μs

1.56 μs

ACQ =0.2 μs + 1.56 μs + 1.2 μs

2.96 μs

COFF = 0 ms.

PIC18F2423/2523/4423/4523

2.2 Selecting and Configuring Acquisition Time

The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option of having an automatically determined acquisition time.

Acquisition time may be set with the ACQT<2:0> bits (ADCON2<5:3>), which provide a range of 2 to 20 T When the GO/DONE

bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE

bit.

Manual acquisition time is selected when ACQT<2:0> = 000. When the GO/DONE

bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE

bit. This option is also the default Reset state of the ACQT<2:0> bits and is compatible with devices that do not offer programmable acquisition times.

In either case, when the conversion is completed, the GO/DONE

bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun.

AD.

2.3 Selecting the A/D Conversion Clock

The A/D conversion time per bit is defined as TAD. The A/D conversion requires 13 T The source of the A/D conversion clock is software selectable.

There are seven possible options for T

•2 TOSC • 32 TOSC

•4 TOSC • 64 TOSC

•8 TOSC • Internal RC Oscillator

OSC

•16 T

For correct A/D conversions, the A/D conversion clock (T

AD) must be as short as possible, but greater than the

minimum T

AD. (For more information, see parameter 130

on page 41.)

Table 2-2 shows the resultant T the device operating frequencies and the A/D clock source selected.

AD per 12-bit conversion.

AD:

AD times derived from

TABLE 2-2: TAD vs. DEVICE OPERATING FREQUENCIES

A/D Clock Source (TAD)

Operation ADCS<2:0> Maximum F

2 TOSC 000 2.50 MHz

4 TOSC 100 5.00 MHz

OSC 001 10.00 MHz

8 T

16 TOSC 101 20.00 MHz

32 T

OSC 010 40.00 MHz

OSC 110 40.00 MHz

64 T

(2)

x11 1.00 MHz

Note 1: The RC source has a typical TAD time of 2.5 μs.

2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a F

divider should be used instead; otherwise, the A/D accuracy specification may not be met.

Assumes T

AD Min. = 0.8 μs

OSC

(1)

OSC

PIC18F2423/2523/4423/4523

2.4 Operation in Power-Managed Modes

The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in a power-managed mode, the ADCS<2:0> bits in ADCON2 should be updated in accordance with the clock source to be used. The ACQT<2:0> bits do not need to be adjusted as the ADCS<2:0> bits adjust the

AD time for the new clock speed. After entering the

T mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed.

If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D RC clock source should be selected.

Operation in Sleep mode requires the A/D F be selected. If bits, ACQT<2:0>, are set to ‘000’ and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion.

RC clock to

2.5 Configuring Analog Port Pins

The ADCON1, TRISA, TRISB and TRISE registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (V

The A/D operation is independent of the state of the CHS<3:0> bits and the TRIS bits.

Note 1: When reading the PORT register, all pins

OH or VOL) will be converted.

configured as analog input channels will read as cleared (a low level). Analog conversion on pins configured as digital pins can be performed. The voltage on the pin will be accurately converted.

2: Analog levels on any pin defined as a

digital input may cause the digital input buffer to consume current out of the device’s specification limits.

3: The PBADEN bit in Configuration

Register 3H configures PORTB pins to reset as analog or digital pins by controlling how the PCFG<3:0> bits in ADCON1 are reset.

PIC18F2423/2523/4423/4523

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10TCY – TAD

ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

b11

b10

On the following cycle:

Discharge

TAD13TAD12

b0b1

TAD1

(typically 200 ns)

3 4

6 7

8 13

Set GO/DONE bit

(Holding capacitor is disconnected)

Conversion starts

(Holding capacitor continues acquiring input)

ACQT Cycles

TAD Cycles

Automatic

Acquisition

Time

b0b11

b7 b6

b10

ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.

On the following cycle:

TAD1

Discharge

(typically 200 ns)

Points to end of T

ACQT period (current black arrow)

2.6 A/D Conversions

Figure 2-4 shows the operation of the A/D Converter after the GO/DONE ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.

Figure 2-5 shows the operation of the A/D Converter after the GO/DONE bits have been set to ‘010’ and a 4 T has been selected before the conversion starts.

Clearing the GO/DONE the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers).

bit has been set and the

bit has been set, the ACQT<2:0>

AD acquisition time

bit during a conversion will abort

After the A/D conversion is completed or aborted, a

CY wait is required before the next acquisition can

2T be started. After this wait, acquisition on the selected channel is automatically started.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D. Code should wait at least 3 TAD after enabling the A/D before beginning an acquisition and conversion cycle.

2.7 Discharge

The discharge phase is used to initialize the value of the holding capacitor. The array is discharged before every sample. This feature helps to optimize the unitygain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values.

FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 2-5: A/D CONVERSION T

AD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

PIC18F2423/2523/4423/4523

2.8 Use of the CCP2 Trigger

An A/D conversion can be started by the Special Event Trigger of the CCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead

bit

The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user or an appropriate TACQ time is selected before the Special Event Trigger sets the GO/DONE

bit (starts

a conversion).

If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter.

(moving ADRESH:ADRESL to the desired location).

TABLE 2-3: REGISTERS ASSOCIATED WITH A/D OPERATION

Reset

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL

PIR1

PIE1 PSPIE

IPR1

PSPIF

PSPIP

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF (Note 4)

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE (Note 4)

(1)

ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP (Note 4)

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF (Note 4)

PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF (Note 4)

PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE (Note 4)

IPR2

OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP (Note 4)

ADRESH A/D Result Register High Byte (Note 4)

ADRESL A/D Result Register Low Byte (Note 4)

ADCON0

ADCON1

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON (Note 4)

— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 (Note 4)

ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 (Note 4)

PORTA RA7

TRISA TRISA7

(2)

RA6

TRISA6

(2)

RA5 RA4 RA3 RA2 RA1 RA0 (Note 4)

(2)

PORTA Data Direction Control Register (Note 4)

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Note 4)

TRISB PORTB Data Direction Control Register (Note 4)

LATB PORTB Data Latch Register (Read and Write to Data Latch) (Note 4)

PORTE

TRISE

(1)

LATE

(1)

— — — —RE3

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 (Note 4)

— — — — — PORTE Data Latch Register (Note 4)

(3)

RE2 RE1 RE0 (Note 4)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers and/or bits are not implemented on PIC18F2423/2523 devices and are read as ‘0’.

2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: For these Reset values, see Section 4.0 “Reset” of the “PIC18F2420/2520/4420/4520 Data Sheet”

(DS39631).

Values on

page

PIC18F2423/2523/4423/4523

3.0 SPECIAL FEATURES OF THE CPU

Note: For additional details on the Configuration

bits, refer to Section 23.1 “Configuration Bits” in the “PIC18F2420/2520/4420/4520

3.1 Device ID Registers

The Device ID registers are read-only registers. They identify the device type and revision for device programmers and can be read by firmware using table reads.

Data Sheet” (DS39631). Device ID information presented in this section is for the PIC18F2423/2523/4423/4523 devices only.

TABLE 3-1: DEVICE IDs

Default/

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(1)

3FFFFEh DEVID1

3FFFFFh DEVID2

Legend: x = unknown, u = unchanged, — = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: DEVID registers are read-only and cannot be programmed by the user.

2: See Register 3-1 and Register 3-2 for DEVID1 and DEVID2 values.

DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0 xxxx xxxx

(1)

DEV11 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 xxxx xxxx

Unprogrammed

Value

REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2423/2523/4423/4523

RRRRRRRR

DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0

bit 7 bit 0

(2)

Legend:

R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 DEV<3:0>: Device ID bits

1101 = PIC18F4423 1001 = PIC18F4523 0101 = PIC18F2423 0001 = PIC18F2523

bit 3-0 REV<3:0>: Revision ID bits

These bits are used to indicate the device revision.

PIC18F2423/2523/4423/4523

REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2423/2523/4423/4523

RRRRRRRR

(1)

DEV11

bit 7 bit 0

Legend:

R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

DEV10

(1)

DEV9

(1)

DEV8

(1)

DEV7

(1)

DEV6

(1)

DEV5

(1)

DEV4

(1)

bit 7-0 DEV<11:4>: Device ID bits

(1)

These bits are used with the DEV<3:0> bits in Device ID Register 1 to identify the part number.

0001 0001 = PIC18F2423/2523 devices 0001 0000 = PIC18F4423/4523 devices

Note 1: These values for DEV<11:4> may be shared with other devices. The specific device is always identified by

using the entire DEV<11:0> bit sequence.

PIC18F2423/2523/4423/4523

4.0 ELECTRICAL CHARACTERISTICS

Note: Other than some basic data, this section documents only the PIC18F2423/2523/4423/4523 devices’ specifi-

cations that differ from those of the PIC18F2420/2520/4420/4520 devices. For detailed information on the electrical specifications shared by the PIC18F2423/2523/4423/4523 and PIC18F2420/2520/4420/4520 devices, see the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to V

Voltage on V

Voltage on MCLR

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of V

Maximum current into V

Input clamp current, I

Output clamp current, I

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports ..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

DD with respect to VSS ......................................................................................................... -0.3V to +7.5V

with respect to VSS (Note 2)......................................................................................... 0V to +13.25V

SS pin ...........................................................................................................................300 mA

DD pin ..............................................................................................................................250 mA

IK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA

OK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA

Pdis = V

2: Voltage spikes below V

latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR RE3 pin, rather than pulling this pin directly to V

DD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

(†)

SS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)

SS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause

/VPP/

SS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

PIC18F2423/2523/4423/4523

Frequency

Volta ge

6.0V

5.5V

4.5V

4.0V

2.0V

40 MHz

5.0V

3.5V

3.0V

2.5V

4.2V

PIC18F2423/2523/4423/4523

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

25 MHz

5.0V

3.5V

3.0V

2.5V

4.2V

PIC18F2423/2523/4423/4523

FIGURE 4-1: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

FIGURE 4-2: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (EXTENDED)

PIC18F2423/2523/4423/4523

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

40 MHz

5.0V

3.5V

3.0V

2.5V

FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz

Note: V

DDAPPMIN is the minimum voltage of the PIC

device in the application.

4 MHz

4.2V

PIC18LF2423/2523/4423/4523

FIGURE 4-3: PIC18LF2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

PIC18F2423/2523/4423/4523

TABLE 4-1: A/D CONVERTER CHARACTERISTICS: PIC18F2423/2523/4423/4523 (INDUSTRIAL)

PIC18LF2423/2523/4423/4523 (INDUSTRIAL)

Param

A01 N

A03 E

A04 E

A06 E

A07 E

A10 — Monotonicity Guaranteed

A20 ΔVREF Reference Voltage Range

A21 V

A22 V

A25 V

A30 Z

A50 I

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

Sym Characteristic Min Typ Max Units Conditions

No.

R Resolution — — 12 bit ΔVREF ≥ 3.0V

IL Integral Linearity Error — <±1 ±2.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V

——±2.0LSBV

DL Differential Linearity Error — <±1 +1.5/-1.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V

——+1.5/-1.0LSBV

OFF Offset Error — <±1 ±5 LSB VDD = 3.0V ΔVREF ≥ 3.0V

——±3LSBV

GN Gain Error — <±1 ±1.25 LSB VDD = 3.0V ΔVREF ≥ 3.0V

——±2.00LSBV

(1)

REFH – VREFL)

3—V

REFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V For 12-bit resolution.

REFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V For 12-bit resolution.

AIN Analog Input Voltage VREFL —VREFH V

AIN Recommended

——2.5kΩ

DD – VSS V For 12-bit resolution.

DD = 5.0V

—VSS ≤ VAIN ≤ VREF

Impedance of Analog Voltage Source

REF VREF Input Current

(2)

— —

150

μA μA

During VAIN acquisition. During A/D conversion cycle.

REFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from

2: V

the RA2/AN2/V

REF-/CVREF pin or VSS, whichever is selected as the VREFL source.

PIC18F2423/2523/4423/4523

131

130

132

BSF ADCON0, GO

A/D CLK

(1)

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

11 10 9 3 2 1

Note 1: If the A/D clock source is selected as RC, a time of T

CY is added before the A/D clock starts. This allows the SLEEP instruction

to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . .

TCY

FIGURE 4-4: A/D CONVERSION TIMING

TABLE 4-2: A/D CONVERSION REQUIREMENTS

Param

130 T

131 T

132 TACQ Acquisition Time

135 T

137 TDIS Discharge Time 0.2 — μs

Note 1: The time of the A/D clock period is dependent on the device frequency and the T

Symbol Characteristic Min Max Units Conditions

No.

AD A/D Clock Period PIC18FXXXX 0.8 12.5

PIC18LFXXXX 1.4 25.0

(1)

μsTOSC based, VREF ≥ 3.0V

(1)

μsVDD = 3.0V;

PIC18FXXXX — 1 μs A/D RC mode

PIC18LFXXXX — 3 μsVDD = 3.0V; A/D RC mode

CNV Conversion Time

(not including acquisition time)

(3)

SWC Switching Time from Convert → Sample — (Note 4)

(2)

13 14 TAD

1.4 — μs

2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (V

4: On the following cycle of the device clock.

DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

OSC based, VREF full range

AD clock divider.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

5.0 PACKAGING INFORMATION

For packaging information, see Section 28.0 “Packaging Information” in the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631).

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

APPENDIX A: REVISION HISTORY

APPENDIX B: DEVICE

DIFFERENCES

Revision A (June 2006)

Original data sheet for PIC18F2423/2523/4423/4523 devices.

Revision B (January 2007)

This revision includes updates to the packaging diagrams.

Revision C (September 2009)

Electrical specifications updated. Preliminary condition status removed. Converted document to the “mini data sheet” format.

TABLE B-1: DEVICE DIFFERENCES

Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523

Program Memory (Bytes) 16384 32768 16384 32768

Program Memory (Instructions) 8192 16384 8192 16384

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Capture/Compare/PWM Modules 2 2 1 1

Enhanced Capture/Compare/PWM Modules

Parallel Communications (PSP) No No Yes Yes

12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

Packages 28-Pin PDIP

00 1 1

28-Pin SOIC

28-Pin QFN

The differences between the devices listed in this data sheet are shown in Table B-1.

28-Pin PDIP 28-Pin SOIC

28-Pin QFN

40-Pin PDIP

44-Pin TQFP

44-Pin QFN

40-Pin PDIP

44-Pin TQFP

44-Pin QFN

PIC18F2423/2523/4423/4523

APPENDIX C: CONVERSION

CONSIDERATIONS

This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B.

Not Applicable

APPENDIX D: MIGRATION FROM

BASELINE TO ENHANCED DEVICES

This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX).

The following are the list of modifications over the PIC16C5X microcontroller family:

Not Currently Available

PIC18F2423/2523/4423/4523

APPENDIX E: MIGRATION FROM

MID-RANGE TO ENHANCED DEVICES

A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in

AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device

specific, are generally applicable to all mid-range to enhanced device migrations.

This Application Note is available as Literature Number DS00716.

APPENDIX F: MIGRATION FROM

HIGH-END TO ENHANCED DEVICES

A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration”. This Application Note is available as Literature Number DS00726.

PIC18F2423/2523/4423/4523

NOTES:

INDEX

A/D ......................................................................................25

A/D Converter Interrupt, Configuring .......................... 29

Acquisition Requirements ...........................................30

ADCON0 Register....................................................... 25

ADCON1 Register....................................................... 25

ADCON2 Register....................................................... 25

ADRESH Register................................................. 25, 28

ADRESL Register .......................................................25

Analog Port Pins, Configuring.....................................32

Associated Registers ..................................................34

Configuring the Module............................................... 29

Conversion Clock (T Conversion Status (GO/DONE

Conversions................................................................33

Converter Characteristics ...........................................40

Discharge....................................................................33

Operation in Power-Managed Modes ......................... 32

Selecting and Configuring Acquisition Time ............... 31

Special Event Trigger (CCP).......................................34

Use of the CCP2 Trigger.............................................34

Absolute Maximum Ratings ................................................37

ADCON0 Register...............................................................25

GO/DONE

ADCON1 Register...............................................................25

ADCON2 Register...............................................................25

ADRESH Register...............................................................25

ADRESL Register .........................................................25, 28

Analog-to-Digital Converter. See A/D.

Bit.............................................................. 28

AD) ..............................................31

Bit) .............................28

Block Diagrams

A/D ..............................................................................28

Analog Input Model ..................................................... 29

PIC18F2423/2523 (28-Pin) .........................................12

PIC18F4423/4523 (40/44-Pin) ....................................13

Compare (CCP Module)

Special Event Trigger..................................................34

Conversion Considerations ................................................. 46

Customer Change Notification Service ............................... 51

Customer Notification Service.............................................51

Customer Support ............................................................... 51

Device Differences.............................................................. 45

Device Overview...................................................................9

Details on Individual Family Members ........................ 10

Features (table)...........................................................11

New Core Features.......................................................9

Other Special Features ............................................... 10

Documentation

Related Data Sheet.......................................................9

Electrical Characteristics.....................................................37

Equations

A/D Acquisition Time................................................... 30

A/D Minimum Charging Time......................................30

Calculating the Minimum Required

Errata ....................................................................................8

Acquisition Time..................................................30

Internet Address ................................................................. 51

Interrupt Sources

A/D Conversion Complete .......................................... 29

Microchip Internet Web Site................................................ 51

Migration from Baseline to Enhanced Devices ................... 46

Migration from High-End to Enhanced Devices .................. 47

Migration from Mid-Range to Enhanced Devices ............... 47

Packaging Information ........................................................ 43

Pin Functions

Pinout I/O Descriptions

Power-Managed Modes

/VPP/RE3 .................................................... 14, 18

MCLR

OSC1/CLKI/RA7................................................... 14, 18

OSC2/CLKO/RA6 ................................................. 14, 18

RA0/AN0 ............................................................... 15, 19

RA1/AN1 ............................................................... 15, 19

RA2/AN2/V RA3/AN3/V

RA4/T0CKI/C1OUT .............................................. 15, 19

RA5/AN4/SS

RB0/INT0/FLT0/AN12........................................... 16, 20

RB1/INT1/AN10.................................................... 16, 20

RB2/INT2/AN8...................................................... 16, 20

RB3/AN9/CCP2 .................................................... 16, 20

RB4/KBI0/AN11.................................................... 16, 20

RB5/KBI1/PGM..................................................... 16, 20

RB6/KBI2/PGC ..................................................... 16, 20

RB7/KBI3/PGD ..................................................... 16, 20

RC0/T1OSO/T13CKI ............................................ 17, 21

RC1/T1OSI/CCP2................................................. 17, 21

RC2/CCP1.................................................................. 17

RC2/CCP1/P1A .......................................................... 21

RC3/SCK/SCL ...................................................... 17, 21

RC4/SDI/SDA ....................................................... 17, 21

RC5/SDO .............................................................. 17, 21

RC6/TX/CK........................................................... 17, 21

RC7/RX/DT........................................................... 17, 21

RD0/PSP0 .................................................................. 22

RD1/PSP1 .................................................................. 22

RD2/PSP2 .................................................................. 22

RD3/PSP3 .................................................................. 22

RD4/PSP4 .................................................................. 22

RD5/PSP5/P1B .......................................................... 22

RD6/PSP6/P1C .......................................................... 22

RD7/PSP7/P1D .......................................................... 22

RE0/RD RE1/WR RE2/CS V

DD ....................................................................... 17, 23

SS ....................................................................... 17, 23

PIC18F2423/2523 ...................................................... 14

PIC18F4423/4523 ...................................................... 18

and A/D Operation...................................................... 32

REF-/CVREF......................................... 15, 19

REF+ ................................................... 15, 19

/HLVDIN/C2OUT.............................. 15, 19

/AN5............................................................... 23

/AN6.............................................................. 23

/AN7............................................................... 23

PIC18F2423/2523/4423/4523

Reader Response ...............................................................52

Registers

ADCON0 (A/D Control 0)............................................25

ADCON1 (A/D Control 1)............................................26

ADCON2 (A/D Control 2)............................................27

DEVID1 (Device ID 1) .................................................35

DEVID2

(Device ID 2)....................................................... 36

Revision History ..................................................................45

Special Features of the CPU............................................... 35

Timing Diagrams

A/D Conversion........................................................... 41

Timing Diagrams and Specifications

A/D Conversion Requirements ................................... 41

Voltage-Frequency Graphics

PIC18F2423/2523/4423/4523 (Extended) .................. 38

PIC18F2423/2523/4423/4523 (Industrial)................... 38

PIC18LF2423/2523/4423/4523 (Industrial)................. 39

WWW Address ................................................................... 51

WWW, On-Line Support ....................................................... 8

PIC18F2423/2523/4423/4523

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing

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CUSTOMER CHANGE NOTIFICATION SERVICE

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

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• Technical Support

• Development Systems Information Line

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://support.microchip.com

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.

To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.

PIC18F2423/2523/4423/4523

To :

Technical Publications Manager

RE: Reader Response

Total Pages Sent ________

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS39755CPIC18F2423/2523/4423/4523

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

PIC18F2423/2523/4423/4523

PART NO. X /XX XXX

PatternPackageTemperature

Range

Device

Device PIC18F2423

(1)

, PIC18F2523

(1)

, PIC18F4423T

(2)

PIC18F4523T

(2)

;

DD range 4.2V to 5.5V

PIC18F2423

(1)

, PIC18F2523

(1)

, PIC18F4423T

(2)

PIC18F4523T

(2)

;

DD range 2.0V to 5.5V

Temperature Range I = -40°C to +85°C (Industrial)

E= -40°C to +125°C (Extended)

Package PT = TQFP (Thin Quad Flat pack)

ML = QFN SO = SOIC SP = Skinny Plastic DIP P=PDIP

Pattern QTP, SQTP, Code or Special Requirements

(blank otherwise)

Examples:

a) PIC18F4523-I/P 301 = Industrial temp., PDIP

package, Extended VDD limits, QTP pattern #301.

b) PIC18F4523-I/PT = Industrial temp., TQFP

package, Extended V

DD limits.

c) PIC18F4523-E/P = Extended temp., PDIP

package, normal V

DD limits.

Note 1: F = Standard Voltage Range

LF = Wide Voltage Range

2: T = In tape and reel PLCC, and TQFP

packages only.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com

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Boston

Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088

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Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431

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Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100 Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511 Fax: 86-28-8665-7889

China - Hong Kong SAR

Tel: 852-2401-1200 Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460 Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355 Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533 Fax: 86-21-5407-5066

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Tel: 86-24-2334-2829 Fax: 86-24-2334-2393

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Tel: 86-755-8203-2660 Fax: 86-755-8203-1760

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Tel: 86-29-8833-7252 Fax: 86-29-8833-7256

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Tel: 86-756-3210040 Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

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Tel: 91-11-4160-8631 Fax: 91-11-4160-8632

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Tel: 886-2-2500-6610 Fax: 886-2-2508-0102

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EUROPE

Austria - Wels

Tel: 43-7242-2244-39 Fax: 43-7242-2244-393

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Tel: 45-4450-2828 Fax: 45-4485-2829

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Tel: 34-91-708-08-90 Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869 Fax: 44-118-921-5820

03/26/09

Datasheet PIC18F2423, PIC18F2523, PIC18F4423, PIC18F4523 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Power Management Features:

Flexible Oscillator Structure:

Peripheral Highlights:

Peripheral Highlights (Continued):

Special Microcontroller Features:

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES

FIGURE 1-1: PIC18F2423/2523 (28-PIN) BLOCK DIAGRAM

FIGURE 1-2: PIC18F4423/4523 (40/44-PIN) BLOCK DIAGRAM

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS

2.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0

REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1

REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2

FIGURE 2-1: A/D BLOCK DIAGRAM

FIGURE 2-2: A/D TRANSFER FUNCTION

FIGURE 2-3: ANALOG INPUT MODEL

2.1 A/D Acquisition Requirements

TABLE 2-1: TACQ ASSUMPTIONS

EQUATION 2-1: ACQUISITION TIME

EQUATION 2-2: A/D MINIMUM CHARGING TIME

EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

2.2 Selecting and Configuring Acquisition Time

2.3 Selecting the A/D Conversion Clock

TABLE 2-2: TAD vs. DEVICE OPERATING FREQUENCIES

2.4 Operation in Power-Managed Modes

2.5 Configuring Analog Port Pins

2.6 A/D Conversions

2.7 Discharge

FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

2.8 Use of the CCP2 Trigger

TABLE 2-3: REGISTERS ASSOCIATED WITH A/D OPERATION

3.0 SPECIAL FEATURES OF THE CPU

3.1 Device ID Registers

TABLE 3-1: DEVICE IDs

REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2423/2523/4423/4523

REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2423/2523/4423/4523

4.0 ELECTRICAL CHARACTERISTICS

FIGURE 4-1: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

FIGURE 4-2: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (EXTENDED)

FIGURE 4-3: PIC18LF2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

FIGURE 4-4: A/D CONVERSION TIMING

TABLE 4-2: A/D CONVERSION REQUIREMENTS

5.0 PACKAGING INFORMATION

APPENDIX A: REVISION HISTORY

Revision A (June 2006)

Original data sheet for PIC18F2423/2523/4423/4523 devices.

TABLE B-1: DEVICE DIFFERENCES

INDEX

THE MICROCHIP WEB SITE

CUSTOMER CHANGE NOTIFICATION SERVICE

CUSTOMER SUPPORT

READER RESPONSE

PRODUCT IDENTIFICATION SYSTEM

WORLDWIDE SALES AND SERVICE