Datasheet PIC18F2331, PIC18F2431, PIC18F4331, PIC18F4431 Datasheet

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PIC18F2331/2431/4331/4431

Data Sheet

28/40/44-Pin Enhanced Flash

Microcontrollers with nanoWatt Technology,

High-Performance PWM and A/D

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

PIC18F2331/2431/4331/4431

28/40/44-Pin Enhanced Flash Microcontrollers with

nanoWatt Technology, High-Performance PWM and A/D

14-Bit Power Control PWM Module:

• Up to 4 Channels with Complementary Outputs

• Edge or Center-Aligned Operation

• Flexible Dead-Band Generator

• Hardware Fault Protection Inputs

• Simultaneous Update of Duty Cycle and Period:

- Flexible Special Event Trigger output

Motion Feedback Module:

• Three Independent Input Capture Channels:

- Flexible operating modes for period and pulse-width measurement

- Special Hall sensor interface module

- Special Event Trigger output to other modules

• Quadrature Encoder Interface:

- 2-phase inputs and one index input from encoder

- High and low position tracking with direction status and change of direction interrupt

- Velocity measurement

High-Speed, 200 ksps 10-Bit A/D Converter:

• Up to 9 Channels

• Simultaneous, Two-Channel Sampling

• Sequential Sampling: 1, 2 or 4 Selected Channels

• Auto-Conversion Capability

• 4-Word FIFO with Selectable Interrupt Frequency

• Selectable External Conversion Triggers

• Programmable Acquisition Time

Flexible Oscillator Structure:

• Four Crystal modes up to 40 MHz

• Two External Clock modes up to 40 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies: 31 kHz to 8 MHz

- OSCTUNE can compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown of device if clock fails

Program Memory Data Memory

Device

PIC18F2331 8192 4096 768 256 24 5 2 Y Y Y Y 6 1/3

PIC18F2431 16384 8192 768 256 24 5 2 Y Y Y Y 6 1/3

PIC18F4331 8192 4096 768 256 36 9 2 Y Y Y Y 8 1/3

PIC18F4431 16384 8192 768 256 36 9 2 Y Y Y Y 8 1/3

Flash

(bytes)

# Single-Word

Instructions

SRAM (bytes)

EEPROM

(bytes)

I/O

Power-Managed Modes:

• Run: CPU on, Peripherals on

• Idle: CPU off, Peripherals on

• Sleep: CPU off, Peripherals off

• Idle mode Currents Down to 5.8 μA, Typical

• Sleep Current Down to 0.1 μA, Typical

• Timer1 Oscillator, 1.8 μA, Typical, 32 kHz, 2V

• Watchdog Timer (WDT), 2.1 μA, typical

• Oscillator Two-Speed Start-up

Peripheral Highlights:

• High-Current Sink/Source 25 mA/25 mA

• Three External Interrupts

• Two Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 6.25 ns (T

- Compare is 16-bit, max. resolution 100 ns (T

- PWM output: PWM resolution is 1 to 10 bits

• Enhanced USART module:

- Supports RS-485, RS-232 and LIN 1.2

- Auto-wake-up on Start bit

- Auto-Baud Detect

• RS-232 Operation using Internal Oscillator Block (no external crystal required)

Special Microcontroller Features:

• 100,000 Erase/Write Cycle Enhanced Flash Program Memory, Typical

• 1,000,000 Erase/Write Cycle Data EEPROM Memory, Typical

• Flash/Data EEPROM Retention: 100 Years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins:

- Drives PWM outputs safely when debugging

SSP

10-Bit

A/D (ch)

CCP

SPI

Slave

C™

EUSART

Encoder

Quadrature

14-Bit

PWM

(ch)

Timers

8/16-Bit

CY/16)

CY)

PIC18F2331/2431/4331/4431

Pin Diagrams

28-Pin SPDIP, SOIC

MCLR/VPP/RE3

RA2/AN2/V

RA3/AN3/V

REF-/CAP1/INDX

REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI/T5CKI/INT0

RA0/AN0

RA1/AN1

AVSS

7 8

Note 1: Low-Voltage Programming must be enabled.

28-Pin QFN

22 21

PIC18F2331/2431

(1)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM

RB4/KBI0/PWM5

RB3/PWM3

RB2/PWM2

RB1/PWM1

RB0/PWM0

VSS

RC7/RX/DT/SDO

RC6/TX/CK/SS

RC5/INT2/SCK/SCL

RC4/INT1/SDI/SDA

(1)

RA0/AN0

RA1/AN1

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM

RA2/AN2/VREF-/CAP1/INDX

RA3/AN3/V

Note 1: Low-Voltage Programming must be enabled.

REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

V VSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

MCLR/VPP/RE3

28 1 2 3 4 5 6 7

RC0/T1OSO/T1CKI

PIC18F2331

PIC18F2431

1011121314

RC2/CCP1/FLTB

RC1/T1OSI/CCP2/FLTA

RC4/INT1/SDI/SDA

RC3/T0CKI/T5CKI/INT0

RC5/INT2/SCK/SCL

RB4/KBI0/PWM5

21 20 19 18 17 16 15

RC6/TX/CK/SS

RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 V

VSS RC7/RX/DT/SDO

Pin Diagrams (Continued)

40-Pin PDIP

PIC18F2331/2431/4331/4431

MCLR/VPP/RE3

RA2/AN2/V RA3/AN3/V

REF-/CAP1/INDX REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

RA5/AN5/LVDIN

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI

(1)

/T5CKI

RD0/T0CKI/T5CKI

RA0/AN0 RA1/AN1

RE0/AN6 RE1/AN7 RE2/AN8

AVSS

(1)

/INT0

RD1/SDO

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29

PIC18F4331/4431

28 27 26 25 24 23 22 21

RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2

RB1/PWM1 RB0/PWM0

V VSS RD7/PWM7 RD6/PWM6

RD5/PWM4 RD4/FLTA

(4)

(3)

RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK

RC4/INT1/SDI

(1)

/SDA

/SCL

RD3/SCK/SCL RD2/SDI/SDA

(2)

(1)

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-Voltage Programming must be enabled.

3: RD4 is the alternate pin for FLTA

4: RD5 is the alternate pin for PWM4.

PIC18F2331/2431/4331/4431

Pin Diagrams (Continued)

44-Pin TQFP

RC7/RX/DT/SDO

RD4/FLTA

RD5/PWM4

RD6/PWM6 RD7/PWM7

VDD RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3

(1)

/SCL

/SDA

(1)

RC6/TX/CK/SS

RC5/INT2/SCK

RC4/INT1/SDI

RD3/SCK/SCL

4443424140

(3) (4)

1 2 3 4 5 6 7 8 9 10 11

121314

PIC18F4331 PIC18F4431

(2)

(1)

RD2/SDI/SDA

RD1/SDO

RD0/T0CKI/T5CKI

1819202122

/VPP/RE3

/INT0

/T5CKI

RC3/T0CKI

RA0/AN0

RC2/CCP1/FLTB

363435

RA1/AN1

RC1/T1OSI/CCP2/FLTA

33 32 31 30 29 28 27 26 25 24

NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7

AV AVDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB

RB7/KBI3/PGD

RB6/KBI2/PGC

MCLR

RB4/KBI0/PWM5

RB5/KBI1/PWM4/PGM

REF-/CAP1/INDX

RA2/AN2/V

RA3/AN3/VREF+/CAP2/QEA

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-Voltage Programming must be enabled.

3: RD4 is the alternate pin for FLTA

4: RD5 is the alternate pin for PWM4.

Pin Diagrams (Continued)

44-Pin QFN

PIC18F2331/2431/4331/4431

RC7/RX/DT/SDO

RD4/FLTA

RD5/PWM4

RD6/PWM6 RD7/PWM7

V VDD

AVDD RB0/PWM0 RB1/PWM1 RB2/PWM2

RD2/SDI/SDA

RB6/KBI2/PGC

RD1/SDO

RB7/KBI3/PGD

/INT0

(1)

/T5CKI

(1)

RD0/T0CKI/T5CKI

RC3/T0CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

363435

1819202122

RA1/AN1

RA0/AN0

/VPP/RE3

MCLR

REF-/CAP1/INDX

RC0/T1OSO/T1CKI

33 32 31 30 29 28 27 26 25 24 23

OSC2/CLKO/RA6 OSC1/CLKI/RA7

V AVSS

AVDD VDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB

(1)

/SCL

/SDA

(1)

RC6/TX/CK/SS

RC5/INT2/SCK

RC4/INT1/SDI

RD3/SCK/SCL

4443424140

(3) (4)

1 2 3 4 5

PIC18F4331

PIC18F4431

7 8 9 10 11

121314

RB3/PWM3

(2)

RB4/KBI0/PWM5

RB5/KBI1/PWM4/PGM

RA2/AN2/V

RA3/AN3/VREF+/CAP2/QEA

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-Voltage Programming must be enabled.

3: RD4 is the alternate pin for FLTA

4: RD5 is the alternate pin for PWM4.

PIC18F2331/2431/4331/4431

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 33

4.0 Reset .......................................................................................................................................................................................... 47

5.0 Memory Organization ................................................................................................................................................................. 59

6.0 Flash Program Memory.............................................................................................................................................................. 77

7.0 Data EEPROM Memory ............................................................................................................................................................. 87

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 91

9.0 Interrupts .................................................................................................................................................................................... 93

10.0 I/O Ports ................................................................................................................................................................................... 109

11.0 Timer0 Module ......................................................................................................................................................................... 135

12.0 Timer1 Module ......................................................................................................................................................................... 139

13.0 Timer2 Module ......................................................................................................................................................................... 145

14.0 Timer5 Module ......................................................................................................................................................................... 147

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 153

16.0 Motion Feedback Module ......................................................................................................................................................... 159

17.0 Power Control PWM Module .................................................................................................................................................... 181

18.0 Synchronous Serial Port (SSP) Module ................................................................................................................................... 213

19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 223

20.0 10-Bit High-Speed Analog-to-Digital Converter (A/D) Module ................................................................................................. 245

21.0 Low-Voltage Detect .................................................................................................................................................................. 263

22.0 Special Features of the CPU.................................................................................................................................................... 269

23.0 Instruction Set Summary .......................................................................................................................................................... 289

24.0 Development Support............................................................................................................................................................... 331

25.0 Electrical Characteristics .......................................................................................................................................................... 335

26.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 371

27.0 Packaging Information.............................................................................................................................................................. 373

Appendix A: Revision History............................................................................................................................................................. 381

Appendix B: Device Differences......................................................................................................................................................... 381

Appendix C: Conversion Considerations ........................................................................................................................................... 382

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 382

Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 383

Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 383

Index .................................................................................................................................................................................................. 385

The Microchip Web Site..................................................................................................................................................................... 395

Customer Change Notification Service .............................................................................................................................................. 395

Customer Support .............................................................................................................................................................................. 395

Reader Response .............................................................................................................................................................................. 396

Product Identification System............................................................................................................................................................. 397

PIC18F2331/2431/4331/4431

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

PIC18F2331/2431/4331/4431

NOTES:

PIC18F2331/2431/4331/4431

1.0 DEVICE OVERVIEW

This document contains device specific information for the following devices:

• PIC18F2331 • PIC18F4331

• PIC18F2431 • PIC18F4431

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price, with the addition of high endurance enhanced Flash program memory and a high-speed 10-bit A/D Converter. On top of these features, the PIC18F2331/2431/4331/4431 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power control and motor control applications. These special peripherals include:

• 14-Bit Resolution Power Control PWM module (PCPWM) with Programmable Dead-time Insertion

• Motion Feedback Module (MFM), including a 3-Channel Input Capture (IC) module and Quadrature Encoder Interface (QEI)

• High-Speed 10-Bit A/D Converter (HSADC)

The PCPWM can generate up to eight complementary PWM outputs with dead-band time insertion. Overdrive current is detected by off-chip analog comparators or the digital Fault inputs (FLTA

The MFM Quadrature Encoder Interface provides precise rotor position feedback and/or velocity measurement. The MFM 3x input capture or external interrupts can be used to detect the rotor state for electrically commutated motor applications using Hall sensor feedback, such as BLDC motor drives.

PIC18F2331/2431/4331/4431 devices also feature Flash program memory and an internal RC oscillator with built-in LP modes.

1.1 New Core Features

1.1.1 nanoWatt Technology

All of the devices in the PIC18F2331/2431/4331/4431 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled, but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements.

, FLTB).

• On-the-Fly Mode Switching: The power- managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 μA, respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2331/2431/4331/4431 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include:

• Four Crystal modes, using crystals or ceramic resonators.

• Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).

• Two External RC Oscillator modes, with the same pin options as the External Clock modes.

• An internal oscillator block, which provides an 8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and V as well as a range of 6 user-selectable clock frequencies (from 125 kHz to 4 MHz) for a total of 8 clock frequencies.

Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. This allows for code execution during what would otherwise be the clock start-up interval, and can even allow an application to perform routine background activities and return to Sleep without returning to full power operation.

DD),

PIC18F2331/2431/4331/4431

1.2 Other Special Features

• Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years.

• Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.

• Power Control PWM Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown on Fault detection and auto-restart to reactivate outputs once the condition has cleared.

• Enhanced USART: This serial communication module is capable of standard RS-232 operation using the internal oscillator block, removing the need for an external crystal (and its accompanying power requirement) in applications that talk to the outside world. This module also includes Auto-Baud Detect and LIN capability.

• High-Speed 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead.

• Motion Feedback Module (MFM): This module features a Quadrature Encoder Interface (QEI) and an Input Capture (IC) module. The QEI accepts two phase inputs (QEA, QEB) and one index input (INDX) from an incremental encoder. The QEI supports high and low precision position tracking, direction status and change of direction interrupt and velocity measurement. The input capture features 3 channels of independent input capture with Timer5 as the time base, a Special Event Trigger to other modules and an adjustable noise filter on each IC input.

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes, that is stable across operating voltage and temperature.

PIC18F2331/2431/4331/4431

1.3 Details on Individual Family Members

Devices in the PIC18F2331/2431/4331/4431 family are available in 28-pin (PIC18F2331/2431) and 40/44-pin (PIC18F4331/4431) packages. The block diagram for the two groups is shown in Figure 1-1.

The devices are differentiated from each other in three ways:

1. Flash program memory (8 Kbytes for PIC18F2331/4331 devices, 16 Kbytes for PIC18F2431/4431).

2. A/D channels (5 for PIC18F2331/2431 devices, 9 for PIC18F4331/4431 devices).

3. I/O ports (3 bidirectional ports on PIC18F2331/ 2431 devices, 5 bidirectional ports on PIC18F4331/4431 devices).

All other features for devices in this family are identical. These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and Table 1-3.

TABLE 1-1: DEVICE FEATURES

Features PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 8192 16384 8192 16384

Program Memory (Instructions) 4096 8192 4096 8192

Data Memory (Bytes) 768 768 768 768

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 22 22 34 34

I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM modules 2 2 2 2

14-Bit Power Control PWM (6 Channels) (6 Channels) (8 Channels) (8 Channels)

Motion Feedback Module (Input Capture/Quadrature Encoder Interface)

Serial Communications SSP,

10-Bit High-Speed Analog-to-Digital Converter module

Resets (and Delays) POR, BOR,

Programmable Low-Voltage Detect Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions

Packages 28-pin SPDIP

1 QEI

3x IC

Enhanced USART

5 Input Channels 5 Input Channels 9 Input Channels 9 Input Channels

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SOIC

28-pin QFN

1 QEI

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SPDIP

28-pin SOIC

28-pin QFN

1 QEI

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

1 QEI

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

PIC18F2331/2431/4331/4431

FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM

Data Bus<8>

Address Latch

Program

Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

T1OSI

T1OSO

/VPP

MCLR

Table Pointer<21>

Table Latch

Instruction

Decode &

Control

Timing

Generation

4X PLL

Precision Band Gap Reference

inc/dec logic

PCLATH

PCLATU

PCU

PCH PCL

Program Counter

31 Level Stack

ROM Latch

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

Power-Managed

Mode Logic

Decode

BITOP

BSR

Data Latch

Data RAM

(768 bytes)

Address Latch

Address<12>

FSR0 FSR1 FSR2

inc/dec

Bank 0, F

logic

PRODLPRODH

8 x 8 Multiply

ALU<8>

PORTA

RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7

PORTB

PORTC

PORTE

RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO

INTRC

VDD, VSS

Timer0 Timer1 Timer2

Data EE

CCP1 CCP2

OSC

Synchronous

Serial Port

Timer5

EUSART

HS 10-Bit

ADC

PCPWM

MCLR/VPP/RE3

(1,2)

AVDD, AVSS

MFM

Note 1: RE3 input pin is only enabled when MCLRE fuse is programmed to ‘0’.

2: RE3 is available only when MCLR is disabled.

PIC18F2331/2431/4331/4431

FIGURE 1-2: PIC18F4331/4431 BLOCK DIAGRAM

Address Latch

Program Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

T1OSI

T1OSO

/VPP

MCLR

VDD, VSS

Table Pointer<21>

inc/dec logic

Table Latch

Instruction

Decode &

Control

Timing

Generation

4X PLL

Precision

Band Gap

Reference

PCLATH

PCLATU

PCH PCL

PCU Program Counter

31 Level Stack

ROM Latch

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Power-Managed

Mode Logic

INTRC

OSC

Decode

BITOP

BSR

Data Latch

Data RAM

(768 bytes)

Address Latch

Address<12>

12 4

FSR0 FSR1 FSR2

inc/dec

logic

8 x 8 Multiply

ALU<8>

Data Bus<8>

Bank 0, F

PRODLPRODH

PORTA

PORTB

PORTC

PORTD

PORTE

RA0/AN0 RA1/AN1

RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7

RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO

RD0/IT0CKI/T5CKI RD1/SDO RD2/SDI/SDA RD3/SCK/SCL RD4/FLTA

RD5/PWM4 RD6/PWM6 RD7/PWM7

RE0/AN6

RE1/AN7

RE2/AN8

MCLR/VPP/RE3

(2)

(4)

(3)

(1)

Timer0 Timer1 Timer2

Data EE

CCP1

CCP2

Synchronous

Serial Port

Timer5

EUSART

HS 10-Bit

ADC

PCPWM

AVDD, AVSS

MFM

Note 1: RE3 is available only when MCLR is disabled.

2: RD4 is the alternate pin for FLTA

3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively. 4: RD5 is the alternate pin for PWM4.

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

SPDIP,

SOIC

QFN

Typ e

Buffer

Type

Description

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA2 AN2 V CAP1 INDX

RA3/AN3/V

RA3 AN3 V CAP2 QEA

RA4/AN4/CAP3/QEB

RA4 AN4 CAP3 QEB

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF-/CAP1/INDX

REF-

REF+/CAP2/QEA

REF+

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

126

10 7

227

328

CMOS

I/O

TTL

I/O

TTL

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

Analog

Analog I I

I/O

TTL

Analog I

Analog I I

I/O

TTL

Analog I I

DD)

Master Clear (input) or programming voltage (input).

—

ST ST

Master Clear (Reset) input. This pin is an active-low Reset to the device. High-voltage ICSP™ programming enable pin. Digital input. Available only when MCLR

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input. Input capture pin 1. Quadrature Encoder Interface index input pin.

Digital I/O. Analog input 3. A/D reference voltage (high) input. Input capture pin 2. Quadrature Encoder Interface channel A input pin.

Digital I/O. Analog input 4. Input capture pin 3. Quadrature Encoder Interface channel B input pin.

is disabled.

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/PWM0

RB0 PWM0

RB1/PWM1

RB1 PWM1

RB2/PWM2

RB2 PWM2

RB3/PWM3

RB3 PWM3

RB4/KBI0/PWM5

RB4 KBI0 PWM5

RB5/KBI1/PWM4/PGM

RB5 KBI1 PWM4 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

SPDIP,

SOIC

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Buffer

Typ e

Type

I/OOTTL

I/O

DD)

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O.

TTL

TTL TTL TTL

TTL TTL

PWM output 0.

Digital I/O. PWM output 1.

Digital I/O. PWM output 2.

Digital I/O. PWM output 3.

Digital I/O. Interrupt-on-change pin. PWM output 5.

Digital I/O. Interrupt-on-change pin. PWM output 4. Low-Voltage ICSP™ Programming entry pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T1CKI

RC0 T1OSO T1CKI

RC1/T1OSI/CCP2/FLTA

RC1 T1OSI CCP2 FLTA

RC2/CCP1/FLTB

RC2 CCP1 FLTB

RC3/T0CKI/T5CKI/INT0

RC3 T0CKI T5CKI INT0

RC4/INT1/SDI/SDA

RC4 INT1 SDI SDA

RC5/INT2/SCK/SCL

RC5 INT2 SCK SCL

RC6/TX/CK/SS

RC6 TX CK SS

RC7/RX/DT/SDO

RC7 RX DT SDO

SS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

DD 7, 20 4, 17 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

SPDIP,

SOIC

11 8

12 9

13 10

14 11

15 12

16 13

17 14

18 15

QFN

Typ e

I/O

I/O I/O

I/O

I I I

I/O

I I

I/O

I/O I/O

I/O

DD)

Buffer

Type

—

CMOS

ST ST

ST ST ST

ST ST ST ST

—

TTL

ST ST ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O. Timer1 oscillator output. Timer1 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM2 output. Fault interrupt input pin.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Fault interrupt input pin.

Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External interrupt 0.

Digital I/O. External interrupt 1. SPI data in.

C™ data I/O.

Digital I/O. External interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). SPI slave select input.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). SPI data out.

C mode.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS

Pin Name

MCLR

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

11818

13 30 32

14 31 33

Type

I/O

DD)

Buffer

Type

Master Clear (input) or programming voltage (input).

CMOS

TTL

—

TTL

Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Available only when MCLR

Oscillator crystal or external clock input.

Oscillator crystal or clock output.

Description

is disabled.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V INDX

RA3/AN3/V CAP2/QEA

RA4/AN4/CAP3/QEB

RA5/AN5/LVDIN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

REF-/CAP1/

RA2 AN2 V

REF-

CAP1 INDX

REF+/

RA3 AN3 V

REF+

CAP2 QEA

RA4 AN4 CAP3 QEB

RA5 AN5 LVD IN

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

21919

32020

42121

52222

62323

72424

Type

I/OITTL

I/O

I I I I

I/O

I I I I

I/O

I I I

I/O

I I

DD)

Buffer

Type

Analog

TTL Analog Analog

ST ST

TTL Analog Analog

ST ST

TTL Analog

ST ST

TTL Analog Analog

Description

PORTA is a bidirectional I/O port.

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input. Input capture pin 1. Quadrature Encoder Interface index input pin.

Digital I/O. Analog input 3. A/D reference voltage (high) input. Input capture pin 2. Quadrature Encoder Interface channel A input pin.

Digital I/O. Analog input 4. Input capture pin 3. Quadrature Encoder Interface channel B input pin.

Digital I/O. Analog input 5. Low-Voltage Detect input.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/PWM0

RB0 PWM0

RB1/PWM1

RB1 PWM1

RB2/PWM2

RB2 PWM2

RB3/PWM3

RB3 PWM3

RB4/KBI0/PWM5

RB4 KBI0 PWM5

RB5/KBI1/PWM4/ PGM

RB5 KBI1 PWM4 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

33 8 9

34 9 10

35 10 11

36 11 12

37 14 14

38 15 15

39 16 16

40 17 17

Buffer

Type

I/OOTTL

I/O

DD)

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O.

TTL

TTL TTL TTL

TTL TTL

PWM output 0.

Digital I/O. PWM output 1.

Digital I/O. PWM output 2.

Digital I/O. PWM output 3.

Digital I/O. Interrupt-on-change pin. PWM output 5.

Digital I/O. Interrupt-on-change pin. PWM output 4. Low-Voltage ICSP™ Programming entry pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

Pin Number

PDIP TQFP QFN

15 32 34 RC0 T1OSO T1CKI

RC1/T1OSI/CCP2/

16 35 35

FLTA

RC1 T1OSI CCP2 FLTA

RC2/CCP1/FLTB

17 36 36 RC2 CCP1 FLTB

RC3/T0CKI/T5CKI/

18 37 37

INT0

RC3

(1)

T0CKI

(1)

T5CKI INT0

RC4/INT1/SDI/SDA

23 42 42 RC4 INT1

(1)

SDI

(1)

SDA

RC5/INT2/SCK/SCL

24 43 43 RC5 INT2

(1)

SCK

(1)

SCL

RC6/TX/CK/SS

25 44 44 RC6 TX CK SS

RC7/RX/DT/SDO

26 1 1 RC7 RX DT SDO

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4.

Type

I/O

I/O I/O

I/O

I I I

I/O

I I

I/O

I I/O I/O

I/O

I I/O

DD)

Buffer

Type

—

CMOS

ST ST

ST ST ST

ST ST ST ST

— ST ST

ST ST ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O. Timer1 oscillator output. Timer1 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM2 output. Fault interrupt input pin.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Fault interrupt input pin.

Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External interrupt 0.

Digital I/O. External interrupt 1. SPI data in.

C™ data I/O.

Digital I/O. External interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). SPI slave select input.

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). SPI data out.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/T0CKI/T5CKI

RD0 T0CKI T5CKI

RD1/SDO

RD1 SDO

RD2/SDI/SDA

RD2 SDI SDA

RD3/SCK/SCL

RD3 SCK SCL

RD4/FLTA

RD4

(2)

FLTA

RD5/PWM4

RD5

(3)

PWM4

RD6/PWM6

RD6 PWM6

RD7/PWM7

RD7 PWM7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Type

I/O

I I

I/OOST

I/O

I/O I/O I/O

I/OIST

I/OOST

DD)

Buffer

Type

ST ST ST

—

ST ST ST

TTL

Description

PORTD is a bidirectional I/O port.

Digital I/O. Timer0 external clock input. Timer5 input clock.

Digital I/O. SPI data out.

Digital I/O. SPI data in.

C™ data I/O.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. Fault interrupt input pin.

Digital I/O. PWM output 4.

Digital I/O. PWM output 6.

Digital I/O. PWM output 7.

C mode.

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN6

RE0 AN6

RE1/AN7

RE1 AN7

RE2/AN8

RE2 AN8

VSS 12, 316, 29 6, 30, 31P — Ground reference for logic and I/O pins.

DD 11 ,

NC — 12, 13,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: RD4 is the alternate pin for FLTA 3: RD5 is the alternate pin for PWM4.

Pin Number

PDIP TQFP QFN

82525

92626

10 27 27

7, 28 7, 8,

28, 29

33, 34

Buffer

Type

PORTE is a bidirectional I/O port.

I/OIST

Analog

I/OIST

Analog

I/OIST

Analog

P — Positive supply for logic and I/O pins.

13 NC NC No connect.

DD)

Digital I/O. Analog input 6.

Digital I/O. Analog input 7.

Digital I/O. Analog input 8.

Description

PIC18F2331/2431/4331/4431

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the Configuration bits FOSC3:FOSC0 in Configuration Register 1H to select one of these 10 modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL Enabled

5. RC External Resistor/Capacitor with

OSC/4 Output on RA6

6. RCIO External Resistor/Capacitor with

I/O on RA6

7. INTIO1 Internal Oscillator with F

Output on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections.

The oscillator design requires the use of a parallel cut crystal.

Note: Use of a series cut crystal may give a

frequency out of the crystal manufacturers’ specifications.

OSC/4

OSC/4 Output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)

(1)

Note 1: See Table 2-1 and Table 2-2 for initial values of

C1 and C2.

2: A series resistor (R

strip cut crystals.

3: R

OSC1

Internal

XTAL

(2)

OSC2

F varies with the oscillator mode chosen.

(3)

PIC18FXXXX

S) may be required for AT

Logic

Sleep

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

Capacitor values are for design guidance only.

These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized.

Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected

DD and temperature range for the application.

See the notes following Table 2-2 for additional information.

Resonators Used:

56 pF 47 pF 33 pF

27 pF 22 pF

56 pF 47 pF 33 pF

27 pF 22 pF

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

PIC18F2331/2431/4331/4431

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc Type

Crystal

Freq

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected

DD and temperature range for the application.

See the notes following this table for additional information.

Crystals Used:

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher capacitance increases the

stability of oscillator, but also increases the start-up time.

2: When operating below 3V V

using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

Typical Capacitor Values

Tested:

C1 C2

DD, or when

An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC CONFIGURATION)

Clock from Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 HSPLL

A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals.

The HSPLL mode makes use of the HS Oscillator mode for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz.

The PLL is enabled only when the oscillator Configuration bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled.

FIGURE 2-3: PLL BLOCK DIAGRAM

HS Osc Enable

PLL Enable

(from Configuration Register 1H)

OSC2

OSC1

HS Mode

Crystal

Osc

FOUT

÷4

Phase

Comparator

Loop Filter

VCO

SYSCLK

MUX

PIC18F2331/2431/4331/4431

2.4 External Clock Input

The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT

OPERATION (EC CONFIGURATION)

Clock from Ext. System

OSC/4

The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT

Clock from Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

OPERATION (ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

2.5 RC Oscillator

For timing insensitive applications, the RC and RCIO device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low

EXT values. The user also needs to take into account

C variation due to tolerance of external R and C components used. Figure 2-6 shows how the R/C combination is connected.

In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic.

FIGURE 2-6: RC OSCILLATOR MODE

REXT

CEXT

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

The RCIO Oscillator mode (Figure 2-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).

EXT) and capacitor (CEXT) values and the

VDD

OSC1

PIC18FXXXX

OSC2/CLKO

OSC/4

EXT > 20 pF

Internal

Clock

FIGURE 2-7: RCIO OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

RA6

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

I/O (OSC2)

EXT > 20 pF

Internal

Clock

PIC18FXXXX

PIC18F2331/2431/4331/4431

2.6 Internal Oscillator Block

The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator (INTRC), which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in Section 22.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 2-2).

2.6.2 INTRC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency.

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at the factory, but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range.

When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8*32μs = 256 μs). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency.

2.6.1 INTIO MODES

Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F while OSC1 functions as RA7 for digital input and output.

• In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.

OSC/4,

PIC18F2331/2431/4331/4431

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TUN5:TUN0: Frequency Tuning bits

011111 = Maximum frequency

• •

000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111

• •

• • 100000 = Minimum frequency

PIC18F2331/2431/4331/4431

2.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the PIC18F2331/2431/ 4331/4431 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2331/ 2431/4331/4431 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes.

Essentially, there are three clock sources for these devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter.

The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode.

PIC18F2331/2431/4331/4431 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC).

Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in Section 12.2 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2331/2431/4331/4431 devices are shown in Figure 2-8. See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 22.1 “Configuration Bits” for Configuration register details.

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several aspects of the system clock’s operation, both in full power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in power-managed modes. The available clock sources are the primary clock (defined in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a power-managed mode of operation. The SCS bits are cleared on all forms of Reset.

The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator’s output.

The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out, and the primary clock is providing the system clock in

primary clock modes. The IOFS bit indicates when the

internal oscillator block has stabilized, and is providing the system clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is

providing the system clock in secondary clock modes. In

power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable.

The IDLEN bit controls the selective shutdown of the controller’s CPU in power-managed modes. The use of these bits is discussed in more detail in Section 3.0

“Power-Managed Modes”

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before executing the SLEEP instruction, or a very long delay may occur while the Timer1 oscillator starts.

+ 370 hidden pages

Datasheet PIC18F2331, PIC18F2431, PIC18F4331, PIC18F4431 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

14-Bit Power Control PWM Module:

Motion Feedback Module:

High-Speed, 200 ksps 10-Bit A/D Converter:

Flexible Oscillator Structure:

Power-Managed Modes:

Peripheral Highlights:

Special Microcontroller Features:

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 New Core Features

1.1.1 nanoWatt Technology

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES

FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM

FIGURE 1-2: PIC18F4331/4431 BLOCK DIAGRAM

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

2.2 Crystal Oscillator/Ceramic Resonators

2.3 HSPLL

FIGURE 2-3: PLL BLOCK DIAGRAM

2.4 External Clock Input

2.5 RC Oscillator

FIGURE 2-6: RC OSCILLATOR MODE

FIGURE 2-7: RCIO OSCILLATOR MODE

2.6 Internal Oscillator Block

2.6.2 INTRC OUTPUT FREQUENCY

2.6.3 OSCTUNE REGISTER

2.6.1 INTIO MODES

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

2.7.1 OSCILLATOR CONTROL REGISTER