Datasheet PIC18F13K50, PIC18F14K50 Datasheet

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PIC18F13K50/14K50

Data Sheet

20-Pin USB Flash Microcontrollers

with nanoWatt XLP™ Technology

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, Sm artShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programmin g , IC SP, ICEPIC, Mindi, MiW i , MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail , PIC

logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

PIC18F1XK50/PIC18LF1XK50

20-Pin USB Flash Microcontrollers with nanoWatt XLP™ Technology

Universal Serial Bus Features:

• USB V2.0 Compliant SIE

• Full Speed (12 Mb/s) and Low Speed (1.5 Mb/s)

• Supports Control, Interrupt, Isochronous and Bulk Transfers

• Supports up to 16 Endpoints (8 bidirectional)

• 256-byte Dual Access RAM for USB

• Input-change interrupt on D+/D- for detecting physical connection to USB host

High Performance RISC CPU:

• C Compiler Optimized Architecture:

- Optional extended in struct ion set designed to

optimize re-entrant code

- 256 bytes, data EEPROM

- Up to 16 Kbytes linear program memory

addressing

- Up to 768 bytes linear data memory

addressing

• Priority levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

Flexible Oscillator Struc ture:

• CPU divider to run the core slower than the USB peripheral

• 16 MHz Internal Oscillator Block:

- Software selectable frequencies, 31 kHz to

16 MHz

- Provides a complete range of clock speeds

from 31 kHz to 32 MHz when used with PLL

- User tunable to compensate for frequency

drift

• Four Crystal modes, up to 48 MHz

• External Clock modes, up to 48 MHz

• 4X Phase Lock Loop (PLL)

• Secondary oscillator using Timer1 at 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if primary or second-

ary oscillator stops

• Two-speed Oscillator Start-up

Special Microcontroller Featues:

• Full 5.5V Operation – PIC18F1XK50

• 1.8V-3.6V Operation – PIC18LF1XK50

• Self-programmable under Software Control

• Programmable Brown-out Reset (BOR)

- With software enable option

• Extended Watchdog Timer (WDT)

- Programmable period from 4ms to 131s

• Single-supply 3V In-Circuit Serial Programming™ (ICSP™) via two pins

Extreme Low-Power Management PIC18LF1XK50 with nanoWatt XLP™:

• Sleep Mode: 24nA

• Watchdog Timer: 450nA

• Timer1 Oscillator: 790nA @ 32 kHz

Analog Features:

• Analog-to-Digital Converter (ADC) module :

- 10-bit resolution, 9 external channels

- Auto a cquisition capability

- Conversion available during Sleep

- Internal 1.024V Fixed Voltage Reference (FVR) channel

- Independent input multiplexing

• Dual Analog Comparators

- Rail-to-rail operation

- Independent input multiplexing

• Volt age Reference module:

- Programmable (% of V

- Two 16-level voltage ranges using V

- Programmable Fixed Voltage Reference (FVR), 3 levels

• On-chip 3.2V LDO Regulator – (PIC18F1XK50)

DD), 16 steps

REF pins

Peripheral Highlight s:

• 14 I/O Pins plus 1 Input-only pin:

- High-current sink/source 25mA/25 mA

- 7 Programmable weak pull-ups

- 7 Programmable Interrupt-on-change pins

- 3 programmable external interrupts

- Programmable slew rate

• Enhanced Capture/Compare/PWM (ECCP) module:

- One, two, three, or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and Auto-restart

• Master Synchronous Serial Port (MSSP) module:

- 3-wire SPI (supports all 4 modes)

C™ Master and Slave modes (Slave mode

-I

address masking)

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module:

- Supports RS-485, RS-232 and LIN 2.0

- RS-232 operation using internal oscillator

- Auto-Baud Detect

- Auto- Wake-up on Break

• SR Latch mode

PIC18F1XK50/PIC18LF1XK50

20-pin PDIP, SSOP, SOIC (300 MIL)

2 3 4 5 6

18 17

VDD

RA5/OSC1/CLKIN

RA4/AN3/OSC2/CLKOUT

RA3/MCLR

/VPP

RC5/CCP1/P1A/T0CKI

RC4/P1B/C12OUT/SRQ

RC3/AN7/P1C/C12IN3-/PGM

RC6/AN8/SS

/T13CKI/T1OSCI

RC7/AN9/SDO/T1OSCO

RB7/TX/CK

RA0/D+/PGD RA1/D-/PGC VUSB RC0/AN4/C12IN+/INT0/V

REF+

RC1/AN5/C12IN1-/INT1/V

REF-

RC2/AN6/P1D/C12IN2-/CV

REF/INT2

RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL

PIC18F1XK50/

PIC18LF1XK50

Device

PIC18F13K50/

Program Memor y Data Memor y

Flash

# Single-Word

(bytes)

Instructions

8K 4096 512

SRAM (bytes)

(3)

EEPROM

(bytes)

256 15 11 1 Y Y 1 2 1/3 Y

I/O

10-bit

(1)

(ch)

A/D

ECCP

(PWM)

(2)

PIC18LF13K50

(3)

PIC18F14K50/

16K 8192 768

256 15 11 1 Y Y 1 2 1/3 Y

PIC18LF14K50

Note 1: One pin is input only.

2: Channel count includes internal Fixed Voltage Reference (FVR) and Programmable Voltage Reference (CV 3: Includes the dual port RAM used by the USB module which is shared with the data memory.

Pin Diagrams

SPI

MSSP

Master

C™

EUSART

Comp.

Timers

8/16-bit

REF) channels.

USB

TABLE 1: PIC18F1XK50/PIC18LF1XK50 PIN SUMMARY

I/O

19 RA0 IOC D+ PGD 18 RA1 IOC D- PGC

4 RA3 3RA4 AN3 IOC Y 2 RA5 IOC Y

13 RB4 AN10 SDI/SDA IOC Y 12 RB5 AN11 RX/DT IOC Y 11 RB6 SCL/SCK IOC Y 10 RB7 TX/CK IOC Y 16 RC0 AN4 C12IN+ VREF+INT0 15 RC1 AN5 C12IN1- VREF- INT1 14 RC2 AN6 C12IN2- CVREF P1D INT2

7 RC3 AN7 C12IN3- P1C PGM 6 RC4 C12OUT P1B SRQ 5 RC5 CCP1/P1A T0CKI 8 RC6 AN8 SS T13CKI/T1OSCI 9 RC7 AN9 SDO T1OSCO

17 VUSB

1 VDD

20 VSS

Note 1: Input only

(1)

Analog

Comparator

Reference

ECCP

EUSART

MSSP

Timers

Interrupts

IOC Y

USB

Pull-up

Basic

MCLR/VPP

OSC2/CLKOUT

OSC1/CLKIN

PIC18F1XK50/PIC18LF1XK50

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................11

3.0 Memory Organization.................................................................................................................................................................25

4.0 Flash Progr a m Mem o ry......... .............................................................................. ....................................................................... 47

5.0 Data EEPROM Memory............. .......................................................................................... ...................................................... 57

6.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 61

7.0 Interrupts.................................................................................................................................................................................... 63

8.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 77

9.0 I/O Ports...................................................................................................... ............. .................................................................. 79

10.0 Timer0 Module ........................................................................................................................................................................... 97

11.0 Timer1 Module ......................................................................................................................................................................... 101

12.0 Timer2 Module ......................................................................................................................................................................... 107

13.0 Timer3 Module ......................................................................................................................................................................... 109

14.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 113

15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 135

16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 177

17.0 Analog-to-Digital Converter (ADC) Module ..............................................................................................................................205

18.0 Comparator Module.................................................................................................................................................................. 219

19.0 Power-Managed Modes ................................................................................ .. .... .. .... ....... .... .................................................... 231

20.0 SR Latch................................................................................................................................................................................... 239

21.0 Voltage References.................................................................... .. .... .. ....... .... .. .. .... .. .. ............................................................... 241

22.0 Universal Serial Bus (USB)...................................................................................................................................................... 245

23.0 Reset........................................................................................................................................................................................ 271

24.0 Special Features of the CPU........................................................................... .........................................................................285

25.0 Instruction Set Summary .......................................................................................................................................................... 303

26.0 Development Support............................................................................................................................................................... 353

27.0 Electrical Specifications............................................................................................................................................................ 357

28.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................391

29.0 Packaging Information. ................................................................. .................................... ........................................................ 393

Appendix A: Revision History............................................................................................................................................................. 397

Appendix B: Device Differences ........................................................................................................................................................ 397

Index .................................................................................................................................................................................................. 399

The Microchip Web Site.............. ....................................................................................................................................................... 409

Customer Change Notification Service .............................................................................................................................................. 409

Customer Support..............................................................................................................................................................................409

Reader Response.............................................................................................................................................................................. 410

Product Identification System............................................................................................................................................................ 411

PIC18F1XK50/PIC18LF1XK50

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents r egarding t his publication, p lease c ontact the M arket ing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Notification System

PIC18F1XK50/PIC18LF1XK50

1.0 DEVICE OVERVIEW

This document co nta i ns dev ic e spec if i c in for m at ion fo r the following devices:

• PIC18F13K50 • PIC18F14K50

• PIC18LF13K50 • PIC18LF14K50

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Flash program memory. On top of these features, the PIC18F1XK50/PIC18LF1XK50 family introduces design enhancements that make these microcontrollers a logical choice for many highperformance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt XLP™ TECHNOLOGY

All of the devices in the PIC 18F1 XK50/PIC18L F1XK50 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these st ates, powe r consumpt ion can be reduced even further, to as little as 4% of normal operation requirements.

• On-the-fly Mode Switching: The powermanaged modes a re invo ked b y user code durin g operation, allowing the user to incorporate powersaving ideas into their application’s software design.

• Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 27.0 “Electrical Specifications” for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in th e PIC18F1X K50/P IC18LF1XK5 0 family offer ten different oscillator options, allowing users a wide range o f choices i n develo ping applica tion hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators

• External Clock mode s, offe ring the option of us ing

two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O)

• External RC Oscillator modes with the same pin

options as the External Clock modes

• An internal oscillator block which contains a

16 MHz HFINTOSC oscillator and a 31 kHz LFINTOSC oscillator which together provide 8 user selectable clock frequencies, from 31 kHz to 16 MHz. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and internal oscillator m odes, which a llows clo ck speeds o f up to 48 MHz. Used with the internal osci llator , th e PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz – all without using an external crystal or clock circuit.

Besides its ava ilability as a cloc k source, the intern al oscillator block pro vid es a s t ab le re ference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference signal provid ed by the LFINTOSC. If a c lo ck failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown.

• T wo-Speed Start-up: This option allows the

internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

PIC18F1XK50/PIC18LF1XK50

1.2 Other Special Features

• Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 1K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

• Self-programmability: These devices can write to their own program memory spaces under internal software control. Using a bootloader routine located in the code protected Boot Block, it is possible to create an application that can update itself in the field.

• Extended Instruction Set: The PIC18F1XK50/ PIC18LF1XK50 family introduces an optional extension to the PIC18 ins truction set, whic h adds 8 new instructions and an Indexed Addressing mode. This extension has been specifically designed to optimize re-entrant application code originally deve loped in high -level la nguages, such as C.

• Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include:

- Auto-Shutdown, for disabling PWM outputs

on interrupt or other select conditions

- Auto-Restart, to reactivate outputs once the

condition has cleared

- Output steering to selectively enable one or

more of 4 outputs to provide the PWM signal.

• Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation an d provides support for th e LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution.

• 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated withou t wai ting for a sampling perio d and thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit postscaler, allowing an extended time-out range that is stable across operati ng vol t age and temperature. See Section 27.0 “Electrical

Specifications” for time-out periods.

1.3 Details on Individual Family Members

Devices in the PIC18F1XK50/PIC18LF1XK50 family are available in 20-pin packages. Block diagrams for the two groups are shown in Figure 1-1.

The devices are differentiated from each other in the following ways:

1. Flash program memory:

• 8 Kbytes for PIC18F13K50/PIC18LF13K50

• 16 Kbyt es for PIC18F14K50/PIC18LF14K50

2. On-chip 3.2V LDO regulator for PIC18F13K50

and PIC18F14K50.

All other features fo r device s in this family are identi cal. These are summarized in Table1-1.

The pinouts for all devices are listed in Table 1 and I/O description are in Table 1-2.

PIC18F1XK50/PIC18LF1XK50

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F1XK50/PIC18LF1XK50 (20-PIN DEVICES)

Features PIC18F13K50 PIC18LF13K50 PIC18F14K50 PIC18LF14K50

LDO Regulator Y es No Yes No Program Memory (Bytes) 8K 16K Program Memory (Instructions) 4096 8192 Data Memory (Bytes) 512 768 Operating Frequency DC – 48 MHz Interrupt Sources 30 I/O Ports Ports A, B, C Timers 4 Enhanced Capture/ Compare/PWM Modules 1 Serial Communications MSSP, Enhanced USART, USB 10-Bit Analog-to-Digital Module 9 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow , MCLR

(PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 20-Pin PDIP , SSOP, SOIC (300 mil)

, WDT

PIC18F1XK50/PIC18LF1XK50

Instruction

Decode and

Control

PORTA

PORTB

PORTC

RA1

RA0

Data Latch

Data Memory

Address Latc h

Data Address< 12>

Access

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

PCH PCL

PCLATH

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP

ALU<8>

T able Pointer<21>

inc/dec logic

Data Bus<8>

Table Lat ch

ROM Latch

PCLATU

PCU

Note 1: RA3 is only available when MCLR functionality is disabled.

2: OSC1/CLKIN and OSC2/CLKOU T are only avai lable i n sele ct osci llator mo des and whe n these pins are not bei ng u sed

as digital I/O. Refer to Section 2.0 “Oscillator Module” for additional information.

3: PIC18F13K50/PIC 18F14K50 onl y.

EUSARTComparator

MSSP

10-bit

ADC

Timer2Timer1 Timer3Timer0

ECCP1

BOR

Data

EEPROM

Instruction Bus <16>

STKPTR

Bank

State machine control signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

(2)

OSC2

(2)

VDD,

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

MCLR

(1)

Block

LFINTOSC

Oscillator

16 MHz

Oscillator

Single-Supply Programming

T1OSO

T1OSI

FVR

CVREF

Address Latch

Program Memory

Data Latch

CVREF

RA3 RA4 RA5

RB4 RB5 RB6

RB7

RC0 RC1

RC2

RC3 RC4 RC5 RC6 RC7

(512/768 bytes)

VUSB

USB

Module

USB

LDO

(3)

Regulator

FIGURE 1-1: PIC18F1XK50/PIC18LF1XK50 BLOCK D IA G RA M

PIC18F1XK50/PIC18LF1XK50

TABLE 1-2: PIC18F1XK50/PIC18LF1XK50 PINOUT I/O DESCRIPTIONS

Pin Name

RA0/D+/PGD

RA0 D+ PGD

RA1/D-/PGC

RA1 DPGC

RA3/MCLR

RA4/AN3/OSC2/CLKOUT

RA5/OSC1/CLKIN

RB4/AN10/SDI/SDA

RB5/AN11/RX/DT

RB6/SCK/SCI

RB7/TX/CK

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

/VPP RA3 MCLR VPP

RA4 AN3 OSC2

CLKOUT

RA5 OSC1

CLKIN

RB4 AN10 SDI SDA

RB5 AN11 RX DT

RB6 SCK SCI

RB7 TX CK

ST = Schmitt Trigger input I = Input O = Output P = Power XTAL= Crystal Oscillator XCVR = USB Differential Transceiver

Number

Buffer

Type

I/O I/O

I/O

I/O I/O I/O

I/O

Type

TTL

XCVR

TTL

XCVR

—

TTL

Analog

XTAL

CMOS

TTL

XTAL

CMOS

TTL

Analog

ST ST

TLL

Analog

ST ST

TLL

ST ST

TLL

CMOS

Digital input USB differential plus line (input/output) ICSP™ programming data pin

Digital input USB differential minus line (input/output) ICSP™ programming clock pin

Master Clear (input) or programming voltage (input)

Digital input Active-low Master Clear with internal pull-up High voltage programming input

Digital I/O ADC channel 3 Oscillator crystal output. Connect to crystal or resonator in Crystal Oscillator mode In RC mode, OSC2 pin outputs CL KOUT whi ch has 1/4 the frequency of OSC1 and den otes the instruction cycle rate

Digital I/O Oscillator crystal input or external clock input ST buffer when configured in RC mode; analog other wise External clock source input. Always associated with the pin function OSC1 (See related OSC1/CLKIN, OSC2, CLKOUT pins

Digital I/O ADC channel 10 SPI data in

C™ data I/O

Digital I/O ADC channel 11 EUSART asynchronous receive EUSART synchronous data (see related RX/TX)

Digital I/O Synchronous serial clock input/output for SPI mode Synchronous serial clock input/output for I

Digital I/O EUSART asynchronous transmit EUSART synchronous clock (see related RX/DT)

Description

C™ mode

PIC18F1XK50/PIC18LF1XK50

TABLE 1-2: PIC18F1XK50/PIC18LF1XK50 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/AN4/C12IN+/INT0/V

RC0 AN4 C12IN+ INT0

REF+

RC1/AN5/C12IN-/INT1/V

RC1 AN5 C12ININT1

REF-

RC2/AN6/P1D/C12IN2-/CV

RC2 AN6 P1D C12IN2-

REF

CV INT2

RC3/AN7/P1C/C12IN3-/PGM

RC3 AN7 P1C C12IN3PGM

RC4/P1B/C12OUT/SRQ

RC4 P1B C12OUT SRQ

RC5/CCP1/P1A/T0CKI

RC5 CCP1 P1A T0CKI

RC6/AN8/SS

RC6 AN8 SS T13CKI T1OSCI

RC7/AN9/SDO/T1OSCO

RC7 AN9 SDO

T1OSCO VSS 20 P — Ground reference for logic and I/O pins VDD 1 P — Positive supply for logic and I/O pins

USB 17 P — Positive supply for USB transceiver

V Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

/T13CKI/T1OSCI

ST = Schmitt Trigger input I = Input O = Output P = Power XTAL= Crystal Oscillator XCVR = USB Differential Transceiver

REF+

REF-

REF/INT2

Number

Buffer

Type

I/O

I/O I/O

I/O

Analog

CMOS

Analog

CMOS

Analog

CMOS

ST ST

CMOS

Analog

TTL

XTAL

Analog

CMOS

XTAL

Digital I/O ADC channel 4 Comparator C1 and C2 non-inverting input External interrupt 0 Comparator reference voltage (high) input

Digital I/O ADC channel 5 Comparator C1 and C2 non-inverting input External interrupt 0 Comparator reference voltage (low) input

Digital I/O ADC channel 6 Enhanced CCP1 PWM output Comparator C1 and C2 inverting input Comparator reference voltage output External interrupt 0

Digital I/O ADC channel 7 Enhanced CCP1 PWM output Comparator C1 and C2 inverting input Low-Voltage ICSP Programming enable pin

Digital I/O Enhanced CCP1 PWM output Comparator C1 and C2 output SR Latch output

Digital I/O Capture 1 input/Compare 1 output/PWM 1 output Enhanced CCP1 PWM output Timer0 external clock input

Digital I/O ADC channel 8 SPI slave select input Timer0 and Timer3 external clock input Timer1 oscillator input

Digital I/O ADC channel 9 SPI data out Timer1 oscillator output

Description

PIC18F1XK50/PIC18LF1XK50

2.0 OSCILLATOR MODULE

2.1 Overview

The oscillator module has a variety of clock sources and features that allow it to be used in a wide range of applications, maximizing performance and minimizing power consumption. Figure 2-1 illustrates a block diagram of the oscillator module .

Key features of the oscillator module include:

• System Clock Selection

- Primary External Oscillator

- Secondary External Oscillator

- Internal Oscillator

• Oscillator Start-up Timer

• System Clock Selection

• Clock Switching

• 4x Phase Lock Loop Frequency Multiplier

• CPU Clock Divider

• USB Operation

- Low Speed

- Full Speed

• Two-Speed Start-up Mode

• Fail-Safe Clock Monitoring

2.2 System Clock Selection

The SCS bits of the OSCCON register select between the following clock sources:

• Primary External Oscillator

• Secondary External Oscillator

• Internal Oscilla tor Note: The frequency of the system clock will be

referred to as F document.

TABLE 2-1: SYSTEM CLOCK SELECTION

Configuration Selection

SCS <1:0> System Clock 1x Internal Oscillator 01 Secondary External Oscillator 00

(Default after Reset)

The default state of the SCS bits sets th e sy s tem cl oc k to be the oscillator defined by the FOSC bits of the CONFIG1H Configuration register. The system clock will always be defined by the FOSC bits until the SCS bits are modified in software.

When the Internal Oscillator is selected as the system clock, the IRCF bits of the OSCCON register and the INTSRC bit of the OSCTUNE register will select either the LFINTOSC or the HFINTOSC. The LFINTOSC is selected when the IRCF<2:0> = 000 and the INTSRC bit is clear. All other combinations of the IRCF bits and the INTSRC bit will select the HFINTOSC as the system clock.

Oscillator defined by FOSC<3:0>

OSC throughout this

2.3 Primary External Oscillator

The Primary External Oscillator’s mode of operation is selected by setting the FOSC<3:0> bits of the CONFIG1H Co nfiguration regi ster. The oscill ator can be set to the following modes:

• LP: Low-Power Crystal

• XT: Crystal/Ceramic Resonator

• HS: High-Speed Crystal Resonator

• RC: External RC Oscillator

• EC: External Clock

Additionally, the Primary External Oscillator may be shut-down under firmware control to save power.

PIC18F1XK50/PIC18LF1XK50

4 x PLL

FOSC<3:0>

OSC2

OSC1

Sleep

CPU

Peripherals

IDLEN

Postscaler

MUX

16 MHz

8 MHz 4 MHz 2 MHz 1 MHz

250 kHz

500 kHz

IRCF<2:0>

111 110 101 100

011 010 001 000

31 kHz

LFINTOSC

Internal

Oscillator

Block

Clock

Control

SCS<1:0>

HFINTOSC

16 MHz

INTSRC

Primary

PIC18F1XK50/PIC18LF1XK50

Sleep

System

Secondary

T1OSCEN Enable Oscillator

T1OSI

T1OSO

PCLKEN PRI_SD

÷ 2

CPU

Divider

1 0

USBDIV

FOSC<3:0>

Low Speed USB

High Speed USB

PLLEN

SPLLEN

Oscillator

Watchdog

Timer

Oscillator

Fail-Safe

Clock

Two-Speed

Start-up

Clock

FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

PIC18F1XK50/PIC18LF1XK50

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

Quartz

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

Crystal

OSC2/CLKOUT

2.3.1 PRIMARY EXTERNAL OSCILLATOR SHUT-DOWN

The Primary External Oscillator can be enabled or disabled via software. To enable software control of the Primary External Oscillator, the PCLKEN bit of the CONFIG1H Configuration register must be set. With the PCLKEN bit set, the Primary External Oscillator is controlled by the PRI_SD b it of the OSCCON2 register. The Primary External Oscillator will be enabled when the PRI_SD bit is set, and disabled when the PRI_SD bit is clear.

Note: The Primary External Oscillator cannot be

shut down when it is selected as the System Clock. To shut down the oscillator, the system clock source must be either the Secondary Oscillator or the Internal Oscillator.

2.3.2 LP, XT AND HS OSCILLATOR MODES

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figu re 2-2). The mode selects a low , medium or high gain setting of the internal inverteramplifier to support v arious resonato r types and spee d.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals.

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medi um of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode select s the highest gain setting of the internal inverter-amplifie r. H S mode current consum ption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 2-2 and Figure 2-3 show typical circuits for quartz crystal and ceramic resonators, respectively.

FIGURE 2-2: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

Note 1: Quartz crystal charac teristics vary a ccording

to type, package and manufacturer. The user should consult the manu facturer data sheets for sp ecifi catio ns an d reco mmen ded application.

2: Always verify oscillator per form anc e ov er

DD and temperature range that is

the V expected for the application.

3: For oscillat or design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC Devices” (DS00826)

• AN849, “Basic PIC (DS00849)

• AN943, “Practical PIC Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

and PIC®

Oscillator Design”

Oscillator

PIC18F1XK50/PIC18LF1XK50

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 MΩ to 1 0 MΩ).

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

Ceramic

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

(3)

Resonator

OSC2/CLKOUT

(1)

CEXT

REXT

PIC® MCU

OSC1/CLKIN

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ

EXT > 20 pF

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2: Output depends upon RC or RCIO clock mod e.

I/O

(2)

FIGURE 2-3: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

2.3.3 EXTERNAL RC

The External Res istor-Capacitor (RC) mode supports the use of an external RC circuit. This allows the designer maximum flexibility i n frequency choice while keeping costs to a minimum when clock accuracy is not required. In RC mode, the RC circuit connects to OSC1, allowing OSC2 to be configured as an IO or as CLKOUT. The CLKOUT function is selected by the FOSC bits of the CONFIG1H Configuration register. When OSC2 is configured as C LKOUT, the frequency at the pin is the frequency of the RC oscillator divided by

4. Figure 2-4 shows the external RC mode connections.

FIGURE 2-4: EXTERNAL RC MODES

The RC oscillator frequency is a function of the supply voltage, the r esistor REXT, the capacitor CEXT and th e operating temperature. Other factors affecting the oscillator frequency are:

• Input threshold voltage variation

• Component tolerances

• Variation in capacitance due to packaging

2.3.4 EXTERNAL CLOCK

The External Clock (EC) mode allows an externally generated logic level clock to be used as the system’s clock source. When operating in this mode, the external clock source is connected to the OSC1 allowing OSC2 to be configured as an I/O or as CLKOUT. The CLKOUT function is selected by the FOSC bits of the CONFIG1H Configuration register. When OSC2 is configured as CLKOUT, the frequency at the pin is the frequency of the EC oscillator divided by 4.

Three different power settings are available for EC mode. The power s ettings allow fo r a reduced I

DD of the

device, if the EC clock is known to be in a specific range. If there is an expected range of frequencies for the EC clock, select the power mode for the highest frequency.

EC Low power 0 – 250 kHz EC Medium power 250 kHz – 4 MHz EC High power 4 – 48 MHz

2.4 Secondary External Oscillator

The Secondary External Oscillator is designed to drive an external 32.768 kHz crystal. This oscillator is enabled or disabled by the T1OSC EN bit of the T1C ON register. See Section 11.0 “Timer1 Module” for more information.

PIC18F1XK50/PIC18LF1XK50

2.5 Internal Oscillator

The internal oscillator module contains two inde pendent oscillators which are:

• LFINTOSC: Low-Frequency Internal Oscillator

• HFINTOSC: High-Frequency Internal Oscillator When operating with either oscillator, OSC1 will be an

I/O and OSC2 will be either an I/O or CLKOUT. The CLKOUT function is selected by the FOSC bits of the CONFIG1H Configuration register. When OSC2 is configured as CLKOUT, the frequency at the pin is the frequency of the Internal Oscillator divided by 4.

2.5.1 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is a 31 kHz internal clock source. The LFINTOSC oscillator is the clock source for:

• Power-up Timer

• Watchdog Timer

• Fail-Safe Clock Monitor The LFINTOSC is enabled when any of the following

conditions are true:

• Power-up Timer is enabled (PWRTEN= 0)

• Watchdog Timer is enabled (WDTEN = 1)

• Watchdog Timer is enabled by software (WDTEN = 0 and SWDTEN = 1)

• Fail-Safe Clock Monitor is enabled (FCMEM= 1)

•SCS1=1 and IRCF<2:0> = 000 and INTSRC = 0

• FOSC<3:0> selects the internal oscillator as the primary clock and IRCF<2:0> = 000 and INTSRC = 0

• IESO = 1 (Two-Speed Start-up) and IRCF<2:0> = 000 and INTSRC = 0

The HFIOFS bit of the OSCCON register indicates whether the HFINTOSC is stable.

Note 1: Selecting 31 kHz from the HFINTOSC

oscillator requires IRCF<2:0> = 000 and the INTSRC bit of the OSCTUNE regist er to be set. If the INTSRC bit is clear, the system clock will come from the LFINTOSC.

2: Additional adjustments to the frequency

of the HFINTOSC can made via the OSCTUNE registers. See Register 2-3 for more details

The HFINTOSC is enabled if any of the following conditions are true:

• SCS1 = 1 and IRCF<2:0> ≠ 000

• SCS1 = 1 and IRCF<2:0> = 000 and INTSRC = 1

• FOSC<3:0> selects the internal oscillator as the primary clock and

- IRCF<2:0> ≠ 000 or

- IRCF<2:0> = 000 and INTSRC = 1

• IESO = 1 (Two-Speed Start-up) and

- IRCF<2:0> ≠ 000 or

- IRCF<2:0> = 000 and INTSRC = 1

•FCMEM=1 (Fail Safe Clock Monitoring) and

- IRCF<2:0> ≠ 000 or

- IRCF<2:0> = 000 and INTSRC = 1

2.5.2 HFINTOSC

The High-Frequency Intern al Oscillat or (HFINT OSC) is a precision oscillator that is factory-calibrated to operate at 16 MHz. The output of the HFINTOSC connects to a postscaler and a multiplexer (see Figure 2-1). One of eight frequencies can be selected using the IRCF<2:0> bits of the OSCCON register. The following frequencies are available from the HFINTOSC:

•16 MHZ

•8 MHZ

•4 MHZ

•2 MHZ

• 1 MHZ (Default after Reset)

• 500 kHz

• 250 kHz

•31 kHz

PIC18F1XK50/PIC18LF1XK50

2.6 Oscillator Control

The Oscillator Control (OSCCON) (Register 2-1) and the Oscillator Control 2 (OSCCON2) (Registe r 2-2) registers control the system clock and frequency selection options.

REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction 0 = Device enter s Sleep mode on SLEEP instruction

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

111 = 16 MHz 110 = 8 MHz 101 = 4 MHz 100 = 2 MHz 011 = 1 MHz 010 = 500 kHz 001 = 250 kHz 000 = 31 kHz

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

bit 2 HFIOFS: HFINTOSC Frequency Stable bit

1 = HFINTOSC frequency is stable 0 = HFINTOSC frequency is not stable

bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]).

(3)

(2)

(1)

HFIOFS SCS1 SCS0

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit of the OSCTUNE register, see text. 3: Default output frequency of HFINTOSC on Reset.

PIC18F1XK50/PIC18LF1XK50

REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-x

— — — — — PRI_SD HFIOFL LFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’ bit 2 PRI_SD: Primary Oscillator Drive Circuit shutdown bit

1 = Oscillator drive circuit on 0 = Oscillator drive circuit off (zero power)

bit 1 HFIOFL: HFINTOSC Frequency Locked bit

1 = HFINTOSC is in lock 0 = HFINTOSC has not yet locked

bit 0 LFIOFS: LFINTOSC Frequency Stable bit

1 = LFINTOSC is stabl e 0 = LFINTOSC is not stable

PIC18F1XK50/PIC18LF1XK50

2.6.1 OSCTUNE REGISTER

The HFINTOSC is factory calibrated, but can be adjusted in software by writing to the TUN<5:0> bits of the OSCTUNE register (Register 2-3).

The defaul t value of the TUN<5: 0> is ‘000000’. The value is a 6-bit two’s complement number.

When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift, while giving no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. The operation of features that depen d on the LFINTOSC clock source frequency, such as the Power-up Timer

(PWRT), Watchdog T imer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.

The OSCTUNE register also implements the INTSRC and SPLLEN bits, which control certain features of the internal oscillator block.

The INTSRC bit allows users to select which internal oscillator pr ovides the clock sourc e when the 31 kHz frequency option is se lected . This is c overed in great er detail in Section 2.5.1 “LFINTOSC”.

The SPLLEN bit co ntrols the operation o f the freque ncy multiplier. For more details about the function of the SPLLEN bit see Section 2.9 “4x Phase Lock Loop

Frequency Multiplier”

REGISTER 2-3: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled) 0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator

bit 6 SPLLEN: Software Controlled Frequency Multiplier PLL bit

1 = PLL enabled (for HFINTOS C 8 MHz only) 0 = PLL disabled

bit 5-0 TUN<5:0>: Frequency Tuning bits

011111 = Maximum frequency 011110 =

• • •

000001 = 000000 = Oscillator module is running at the factory calibrated frequency. 111111 =

• • • 100000 = Minimum frequen cy

PIC18F1XK50/PIC18LF1XK50

Old Clock

New Clock

IRCF <2:0>

System Clock

Start-up Time

(1)

Clock Sync Running

High Speed Low Speed

Select Old

Select New

New Clk Ready

Low Speed High Speed

Old Clock

New Clock

IRCF <2:0>

System Clock

Start-up Time

(1)

Clock Sync Running

Select Old Select New

New Clk Ready

Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.

2.7 Oscillator Start-up Timer

The Primary External Oscillator, when configured for LP , XT or HS modes, incorporates an Oscillator Start-up Timer (OST). The OST ensures that the oscillator starts and provides a stable clock to the oscillator module. The OST times out when 1024 oscillation s on OSC1 have occurred . Duri ng th e OST peri od, wi th th e syst em clock set to t he Primary Exte rnal Oscill ator , the prog ram counter does not increment suspending program execution. The OST period will occur following:

• Power-o n Reset (POR )

• Brown-out Reset (BOR)

• Wake-up from Sleep

• Oscillator being enabled

• Expiration of Power-up Timer (PWRT) In order to minimize laten cy between externa l oscillator

start-up and code execution, the Two-Speed Start-up mode can be selec ted. See Sectio n 2.12 “Two -Spe ed

Start-up Mode” for more information.

2.8 Clock Switching

The device cont ains circ uitry t o preve nt clo ck “gl itches” due to a change of the system clock source. To accomplish this, a short pause in the system clock occurs during the clock switch. If the new clock source is not stable (e.g., OST is active), the device will continue to execute from the old clock source until the new clock source becomes stable. The timing of a clock switch is a s follows:

1. SCS<1:0> bits of the OSCCON register are

modified.

2. The system clock will continue to operate from

the old clock until the new clock is ready.

3. Clock switch circ uitry waits for two consecuti ve

rising edges of the old clock after the new clock is ready.

4. The system c lock is hel d low, star ting at the next

falling edge of the old clock.

5. Clock switch cir cui try wait s for an ad diti onal two

rising edges of the new clock.

6. On the next falling edge of the new clock, the

low hold on the system clock is release and the new clock is switched in as the system clock.

7. Clock switch is complete.

Refer to Figure 2-5 for more details.

FIGURE 2-5: CLOCK SWITCH TIMING

PIC18F1XK50/PIC18LF1XK50

TABLE 2-2: EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING

Switch From Switch To Oscillator Delay

Sleep/POR LFINTOSC

HFINTOSC Sleep/POR LP, XT, HS 1024 clock cycles Sleep/POR EC, RC 8 Clock Cycles

Oscillator Warm-up Delay (T

WARM)

2.9 4x Phase Lock Loop Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower-frequency external oscillator or to operate at 32 MHz with the HFINTOSC. The PLL is designed for an input frequency from 4 MHz to 12 MHz. The PLL multiplies its input frequency by a factor of four when the PLL is enabled. This may be useful for customers who are concerned with EMI, due to high-frequency crystals.

Two bits control the PLL: the PLLEN bit of the CONFIG1H Configurati on reg is ter an d the SPLL EN bit of the OSCTUNE register. The PLL is enabled when the PLLEN bit is set and it is under software control when the PLLEN bit is cleared.

TABLE 2-3: PLL CONFIGURATION

PLLEN SPLLEN PLL Status

1xPLL enabled 01PLL enabled 00PLL disabled

Note: The HFINTOSC may use the PLL when

the postscaler is set to 8 MHz and the FOSC<3:0> bits of the CONFIG1H Configuration register are selected for Internal Oscillator operati on.

2.10 CPU Clock Divider

2.11 USB Operation

The USB module is des igned to operat e in two dif ferent modes:

• Low Speed

• Full Sp eed Because of timing requirements imposed by the USB

specifications, the Primary External Oscillator is required for the USB module. The FOSC bits of the CONFIG1H Configuratio n register must be se t to either External Clock (EC) High-power or HS mode with a clock frequency of 6, 12 or 48 MHz.

2.11.1 LOW SPEED OPERATION

For Low Speed USB operation, a 6MHz clock is required for the USB module. To generate the 6 MHz clock, only 2 Oscillator modes are allowed:

• EC High-power mode

•HS mode Table 2-4 shows the recommended Clock mode for

low-speed operation.

2.11.2 FULL-SPEED OPERATION

For full-speed USB operation, a 48 MHz clock is required for the USB module. To generate the 48 MHz clock, only 2 Oscillator modes are allowed:

• EC High-power mode

•HS mode T able2-5 shows the recommende d Clock mode for full-

speed operation.

The CPU Clock Divider allows the system clock to run at a slower speed than the Low/Full Speed USB module clock while sharing the same clock source. Only the oscillator defin ed by the set tin gs of the FOSC bits of the CO NFIG1H Configur ation register may be used with the CPU Clock Divider. The CPU Clock Divider is controlled by the CPUDIV bits of the CONFIG1L Configuration register. Setting the CPUDIV bits will set the system clock to:

• Equal the clock speed of the USB module

• Half the clock speed of the USB module

• One third the clock speed of the USB module

• One fourth the clock speed of the USB module

For more information on the CPU Clock Divider, see Figure 2-1 and Register 24-1 CONFIG1L.

PIC18F1XK50/PIC18LF1XK50

TABLE 2-4: LOW SPEED USB CLOCK SETTINGS

Clock Mode

EC High/HS

Clock

Frequency

12 MHz 1

6 MHz 0

USBDIV

4x PLL

Enabled

Yes

CPUDIV<1:0>

00 48 01 24 10 16 11 12 00 12 01 6 10 4 11 3 00 24 01 12 10 8 11 6 00 6 01 3 10 2 11 1.5

System Clock

Frequency (MHz)

Note: The system clock frequency in Table 2-4

only applies if the OSCCON register bits SCS<1:0> = 00. By changing these bits, the system clock can operate down to 31 kHz.

TABLE 2-5: FULL-SPEED USB CLOCK SETTINGS

Clock Mode Clock Frequency 4x PLL Enabled CPUDIV<1:0>

EC High 48 MHz No

EC High/HS 12 MHz Yes

Note: The system clock frequency in the above

table only appl i es if th e OSC CO N regi st e r bits SCS<1:0> = 00. By changing these bits, the system cl ock can opera te down to 31 kHz.

System Clock Frequency

(MHz)

00 48 01 24 10 16 11 12 00 48 01 24 10 16 11 12

PIC18F1XK50/PIC18LF1XK50

External

LFINTOSC

÷ 64

31 kHz

(~32 μs)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

2.12 Two-Speed Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Oscillator Start-up Timer (OST) and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remo ve the OST p eriod, which can reduce the overall power consumption of the device.

Two-Speed Start-up mode is enabled by setting the IESO bit of the CONFIG1H Con figuration register. With Two-Speed Start-up enabled, the device will execute instructions using the internal oscillator during the Primary External Oscillator OST period.

When the system clock is set to the Primary External Oscillator and the oscillator is configured for LP, XT or HS modes, the device wil l not ex ec ute co de du ring the OST period. The OST will suspend program execution until 1024 oscilla tions are counted. Tw o-Spee d S tart-up mode minimizes the delay in code execution by operating from the internal oscillator while the OST is active. The sys tem clock wi ll switch back to the Pr imary External Oscillator after the OST period has expired.

Two-speed Start-up will become active after:

• Power-o n Reset (POR )

• Power-up Timer (PWRT), if enabled

• Wake-up from Sleep

The OSTS bit of the OSCCON register reports which oscillator the device is currently using for operation. The device is running fro m the os cill ator defined by the FOSC bits of the CONFIG1H Configuration register when the OSTS bit is set. The device is running from the internal oscillator when the OSTS bit is clear.

2.13 Fail-Safe Clock Monitor

The Fail-Safe Clock Monit or (FSC M) al lows the dev ic e to continue operat ing sh ould the external osci ll ato r fai l. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the CONFIG1H Configuration register. The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC and RC).

FIGURE 2-6: FSCM BLOCK DIAGRAM

2.13.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by comparing the ex terna l oscil lator t o the FSC M samp le clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure2-6. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock cle ars the latch on each ris ing edge of th e sample clock. A f ail ure is detected when an ent ire hal fcycle of the sample clock elapses before the primary clock goes low.

2.13.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the device clock to an internal cl ock sourc e and set s the bit flag OSCFIF of t he PIR 2 r egi ste r. The OSCFIF flag will generate an interrupt if the OSCFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. An automatic transition back to the failed clock source will not occur.

The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.

PIC18F1XK50/PIC18LF1XK50

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The r elative frequencies in

this example have been chosen for clarity.

(Q)

Test

Test Test

Clock Monitor Output

2.13.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared by either one of the following:

• Any Reset

• By toggli ng the SCS1 bit of the OSCCON register Both of these conditions restart the OST. While the

OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device automatically switches over to the external clock source. The Fail-Safe condition need not be cleared before the OSCFIF flag is cleared.

2.13.4 RES ET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after

FIGURE 2-7: FSCM TIMING DIAGRAM

any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the R eset or wake- up has complet ed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed.

TABLE 2-6: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CONFIG1H IESO FCMEN PCLK EN PL LEN F O SC3 FOSC2 FOSC1 FOSC0 INTCON GIE/GIEH PEIE/GIEL OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 2 83 OSCTUNE INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 283 PIE2 OSCFIE PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF —285

T1CON

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power -u p) R esets include MCLR

RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 101

C1IE C2IE EEIE BCLIE USBIE TMR3IE —283

TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 283

Reset and Watchdog Timer Reset during norm a l operation.

Reset

Values on

page

283

PIC18F1XK50/PIC18LF1XK50

NOTES:

PIC18F1XK50/PIC18LF1XK50

PC<20:0>

Stack Level 1

•

Stack Level 31

Reset Vector

Low Priority Interrupt Vector

•

CALL,RCALL,RETURN RETFIE,RETLW

0000h

0018h

High Priority Interrupt Vector

0008h

User Memo ry Space

1FFFFFh

4000h

3FFFh

200000h

On-Chip

Program Memory

Read ‘0’

1FFFh

2000h

On-Chip

Program Memory

Read ‘0’

PIC18F14K50

PIC18F13K50

3.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 Enhanced microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM As Harvard architecture dev ices, the dat a and progra m

memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addresse d and accessed through a set of control registers.

Additional detailed information on the operation of the Flash program memory is provided in Section 4.0 “Flash Program Memory”. Data EEPROM is discussed s eparately in Section 5.0 “Data EEPROM

Memory”.

3.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory sp ace. Accessi ng a loca tion betwee n the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction).

This family of devices contain the following:

• PIC18F13K50: 8 Kbytes of Flash Memory, up to 4,096 single-word instructions

• PIC18F14K50: 16 Kbytes of Flash Memory, up to 8,192 single-word instructions

PIC18 devices have two interrupt vectors and one Reset vector. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h.

The program memory map for PIC18F1XK50/ PIC18LF1XK50 devices is shown in Figure 3-1. Memory block details are shown in Figure 24-2.

FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F1XK50/PIC18LF1XK50

DEVICES

PIC18F1XK50/PIC18LF1XK50

00011

001A34h

11111 11110 11101

00010 00001 00000

00010

Return Address Stack <20:0>

Top-of-Stack

000D58h

TOSLTOSHTOSU

34h1Ah00h

STKPTR<4:0>

T op -of-Stack Registers Stack Pointer

3.1.1 PROGRAM COUNTER

The Program Counter (PC ) specifies the address of th e instruction to fetch for execu tion. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byt e, or PCH re gister, contains the PC<15:8> bits; i t is not directly re adable or writ able. Updates to the PCH register are perfo rmed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register.

The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to P CLATH and PCLATU b y an operation that reads PCL. This is useful for computed offsets to the PC (see Section 3.1.4.1 “Computed GOTO”).

The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit (LSb) of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter.

3.1.2 RETURN ADDRESS STACK

The return address s tack allows any co mb ination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is execut ed or an interrupt is Acknow ledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruct ion. PC LATU and PCLATH are not affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stac k space is not part of either program or da ta sp ace. The Stack Point er is readable and writable and the address on the top of the stack is readable and writable through the Top-ofStack (TOS) Special File Registers. Data can also be pushed to, or popped from the stack, using these registers.

A CALL type instru ctio n cau ses a pu sh ont o the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Stat us bit s in dic ate if the stack is full or has overflowed or has underflowed.

3.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 3-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.

FIGURE 3-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

PIC18F1XK50/PIC18LF1XK50

3.1.2.2 Return Stack Pointer (STKPTR)

The STKPTR register (Register3-1) contains the S tac k Pointer value, the STKFUL (stack full) bit and the STKUNF (stack unde rflow) bits. The va lue of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and wri te the Stack Pointer v alue. This f eature can be used by a Real-Time Operating System (RTOS) for return stack maintenance.

After the PC is pu sh ed ont o the s ta ck 31 time s (witho ut popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR.

The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 24.1 “Configuration Bits” for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero.

If STVREN is cleared, the STKFUL bi t will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31.

When the stack has been popped enough times to unload the stac k, the next pop will ret urn a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs.

Note: Returning a value of zero to the PC on an

3.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the ability to push value s on to the st ac k an d pul l values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and T OS L can be m odifie d to plac e dat a or a return address on the stack.

The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack.

The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value.

REGISTER 3-1: STKPTR: STACK POINTER REGISTER

underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit

bit 6 STKUNF: Stack Underflow Flag bit

bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

(1)

STKUNF

1 = Stack became full or overflowed 0 = Stack has not become full or overflowed

1 = Stack und erfl ow occurred 0 = Stack underflow did not occur

(1)

— SP4 SP3 SP2 SP1 SP0

(1)

PIC18F1XK50/PIC18LF1XK50

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER ;STACK

•

SUB1 •

•

RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE ORG nn00h TABLE ADDWF PCL

RETLW nnh

3.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a ful l or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condi tion will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset.

3.1.3 FAST REGISTER STACK

A fast register stack is provided for the Status, WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt.

If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priori ty interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers by software during a low priority interrupt.

If interrupt priority is not used, all interrupts ma y use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stac k can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the Status, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack.

Example 3-1 shows a source code example that uses the fast register stack during a subroutine call and return.

EXAMPLE 3-1: FAST REGISTER STACK

CODE EXAMPLE

3.1.4 LOOK-UP TABLES IN PROGRAM MEMORY

There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways:

• Computed GOTO

• Table Reads

3.1.4.1 Computed GOTO

A computed GOTO is accompli shed by adding an offset to the program counter. An example is shown in Example 3-2.

A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an of fs et into the table before executing a call to tha t t a ble . The first instruction o f th e called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function.

The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in each instruction location and room on the return address stack is required.

EXAMPLE 3-2: COMPUTED GOTO USING

AN OFFSET VALUE

3.1.4.2 Table Reads and Table Writes

A better method of storing data in program memory allows two bytes of dat a to be stored in each instruction location.

Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (T BLPTR) register s pecifies the byt e address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time.

Table read and table write operations are discussed further in Section 4.1 “Table Reads and Table

Writes”.

+ 384 hidden pages

Datasheet PIC18F13K50, PIC18F14K50 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Universal Serial Bus Features:

High Performance RISC CPU:

Flexible Oscillator Struc ture:

Special Microcontroller Featues:

Extreme Low-Power Management PIC18LF1XK50 with nanoWatt XLP™:

Analog Features:

Peripheral Highlight s:

Pin Diagrams

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 New Core Features

1.1.1 nanoWatt XLP™ TECHNOLOGY

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F1XK50/PIC18LF1XK50 (20-PIN DEVICES)

FIGURE 1-1: PIC18F1XK50/PIC18LF1XK50 BLOCK D IA G RA M

TABLE 1-2: PIC18F1XK50/PIC18LF1XK50 PINOUT I/O DESCRIPTIONS

2.0 OSCILLATOR MODULE

2.1 Overview

2.2 System Clock Selection

TABLE 2-1: SYSTEM CLOCK SELECTION

2.3 Primary External Oscillator

FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

2.3.1 PRIMARY EXTERNAL OSCILLATOR SHUT-DOWN

2.3.2 LP, XT AND HS OSCILLATOR MODES

2.3.3 EXTERNAL RC

FIGURE 2-4: EXTERNAL RC MODES

2.3.4 EXTERNAL CLOCK

2.4 Secondary External Oscillator

2.5 Internal Oscillator

2.5.1 LFINTOSC

2.5.2 HFINTOSC

2.6 Oscillator Control

REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER

REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2

2.6.1 OSCTUNE REGISTER

REGISTER 2-3: OSCTUNE: OSCILLATOR TUNING REGISTER

2.7 Oscillator Start-up Timer

2.8 Clock Switching

FIGURE 2-5: CLOCK SWITCH TIMING

TABLE 2-2: EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING

2.9 4x Phase Lock Loop Frequency Multiplier

TABLE 2-3: PLL CONFIGURATION

2.10 CPU Clock Divider

2.11 USB Operation

2.11.1 LOW SPEED OPERATION

2.11.2 FULL-SPEED OPERATION

TABLE 2-4: LOW SPEED USB CLOCK SETTINGS

TABLE 2-5: FULL-SPEED USB CLOCK SETTINGS

2.12 Two-Speed Start-up Mode

2.13 Fail-Safe Clock Monitor

FIGURE 2-6: FSCM BLOCK DIAGRAM

2.13.1 FAIL-SAFE DETECTION

2.13.2 FAIL-SAFE OPERATION

2.13.3 FAIL-SAFE CONDITION CLEARING

2.13.4 RES ET OR WAKE-UP FROM SLEEP

FIGURE 2-7: FSCM TIMING DIAGRAM

TABLE 2-6: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

3.0 MEMORY ORGANIZATION

3.1 Program Memory Organization

3.1.1 PROGRAM COUNTER

3.1.2 RETURN ADDRESS STACK

FIGURE 3-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

REGISTER 3-1: STKPTR: STACK POINTER REGISTER

3.1.3 FAST REGISTER STACK

3.1.4 LOOK-UP TABLES IN PROGRAM MEMORY