Datasheet PIC18F1230, PIC18F1330 Datasheet

PIC18F1230/1330

Data Sheet

High-Performance Microcontrollers

with 10-bit A/D and nanoWatt Technology

 2009 Microchip Technology Inc. DS39758D

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The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC

32

logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
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© 2009, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS39758D-page 2  2009 Microchip Technology Inc.

PIC18F1230/1330

18/20/28-Pin Enhanced Fl ash Microcontrollers with

nanoWatt Technology, High-Performance PWM and A/D

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Ultra Low 50 nA Input Leakage

• Run mode currents down to 15 A, typical

• Idle mode currents down to 3.7 A, typical

• Sleep mode current down to 100 nA, typical

• Timer1 Oscillator: 1.8 A, typical; 32 kHz; 2V

• Watchdog Timer (WDT): 1.4 A, typical; 2V

• Two-Speed Oscillator Start-up

14-Bit Power Control PWM Module:

• Up to 6 PWM Channel Outputs

- Complementary or independent outputs

• Edge or Center-Aligned Operation

• Flexible Dead-Band Generator

• Hardware Fault Protection Input

• Simultaneous Update of Duty Cycle and Period:

- Flexible Special Event Trigger output

Flexible Oscillator Struc ture:

• Four Crystal modes, up to 40 MHz

• 4x Phase Lock Loop (PLL) – Available for Crystal
and Internal Oscillators

• Two External RC modes, up to 4 MHz

- Fast wake-up from Sleep and Idle, 1 s, typical

• Two External Clock modes, up to 40 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies from 31 kHz

to 8 MHz

- Provides a complete range of clock speeds from

31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock stops

Peripheral Highlight s:

• High-Current Sink/Source 25 mA/25 mA

• Up to 4 Programmable External Interrupts

• Four Input Change Interrupts

• Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN/J2602

- RS-232 operation using internal oscillator
block (no external crystal required)

- Auto-wake-up on Start bit

- Auto-Baud Detect

• 10-Bit, up to 4-Channel Analog-to-Digital Converter
module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Up to 3 Analog Comparators

• Programmable Reference Voltage for
Comparators

• Programmable, 15-Level Low-Voltage Detection
(LVD) module:

- Supports interrupt on Low-Voltage Detection

Special Microcontroller Features:

• C Compiler Optimized Architecture with Optional
Extended Instruction Set

• Flash Memory Retention: > 40 years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Programmable Code Protection

• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Wide Operating Voltage Range (2.0V to 5.5V)

Program Memory Data Memory

Device

PIC18F1230 4096 2048 256 128 16 4 Yes 3 6 2

PIC18F1330 8192 4096 256 128 16 4 Yes 3 6 2

 2009 Microchip Technology Inc. DS39758D-page 3

Flash

(bytes)

# Single-Word

Instructions

SRAM

(bytes)

EEPROM

(bytes)

I/O

10

-Bit

ADC

Channel

EUSART

Analog

Comparator

14-Bit

PWM (ch)

Timers

16-Bit

PIC18F1230/1330

18-Pin PDIP, SOIC

2

3

4

5

6

1

8

7

9

RA0/AN0/INT0/KBI0/CMP0

RA1/AN1/INT1/KBI1

RA4/T0CKI/AN2/V

REF+

V

SS/AVSS

RA2/TX/CK

RA3/RX/DT

RB0/PWM0

RB1/PWM1

PIC18F1X30

17

16

15

14

13

18

11

12

10

RB3/INT3/KBI3/CMP1/T1OSI

(1)

RA7/OSC1/CLKI/T1OSI

(1)

/FLTA

(2)

RA6/OSC2/CLKO/T1OSO

(1)

/T1CKI

(1)

/AN3

V

DD/AVDD

RB7/PWM5/PGD

RB6/PWM4/PGC

RB5/PWM3

RB4/PWM2

20-Pin SSOP

Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of

CONFIG3H.

2: Placement of FLTA

depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

MCLR/VPP/RA5/FLTA

(2)

2

3

4

5

6

1

8

7

9

RA0/AN0/INT0/KBI0/CMP0

RA1/AN1/INT1/KBI1

RA4/T0CKI/AN2/V

REF+

V

SS

RA2/TX/CK

RA3/RX/DT

RB0/PWM0

RB1/PWM1

PIC18F1X30

19

18

17

16

15

20

13

14

12

RB3/INT3/KBI3/CMP1/T1OSI

(1)

RA7/OSC1/CLKI/T1OSI

(1)

/FLTA

(2)

VDD

RB7/PWM5/PGD

RB6/PWM4/PGC

RB5/PWM3

RB4/PWM2

MCLR/VPP/RA5/FLTA

(2)

10

11

AVSS

AVDD

RB2/INT2/KBI2/CMP2/T1OSO

(1)

/T1CKI

(1)

RA6/OSC2/CLKO/T1OSO

(1)

/T1CKI

(1)

/AN3

RB2/INT2/KBI2/CMP2/T1OSO

(1)

/T1CKI

(1)

Pin Diagrams

DS39758D-page 4  2009 Microchip Technology Inc.

Pin Diagrams (Continued)

28-Pin QFN

(3)

Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of

CONFIG3H.

2: Placement of FLTA

depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

3: It is recommended that the user connect the center metal pad for this device package to the ground.

10 11

2
3

6

1

18

19

20

21

22

12 13 14

15

8

7

16

17

232425262728

9

PIC18F1X30

RA3/RX/DT

5

4

NC

RB3/INT3/KBI3/CMP1/T1OSI

(1)

NC

RA7/OSC1/CLKI/T1OSI

(1)

/FLTA

(2)

VDD
NC
AV

DD

RB7/PWM5/PGD
RB6/PWM4/PGC

NC

RB5/PWM3

RB4/PWM2

RA0/AN0/INT0/KBI0/CMP0

RA1/AN1/INT1/KBI1

RA4/T0CKI/AN2/V

REF+

MCLR/VPP/RA5/FLTA

(2)

NC

V

SS

NC

AV

SS

NC

RA2/TX/CK

RB0/PWM0

RB1/PWM1

NC

RB2/INT2/KBI2/CMP2/T1OSO

(1)

/T1CKI

(1)

RA6/OSC2/CLKO/T1OSO

(1)

/T1CKI

(1)

/AN3

PIC18F1230/1330

 2009 Microchip Technology Inc. DS39758D-page 5

PIC18F1230/1330

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Guidelines for Getting Started with PIC18F Microcontrollers..................................................................................................... 17

3.0 Oscillator Configurations ............................................................................................................................................................ 21

4.0 Power-Managed Modes ............................................................................................................................................................. 31

5.0 Reset .......................................................................................................................................................................................... 39

6.0 Memory Organization ................................................................................................................................................................. 51

7.0 Flash Program Memory.............................................................................................................................................................. 71

8.0 Data EEPROM Memory ............................................................................................................................................................. 81

9.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 85

10.0 I/O Ports ..................................................................................................................................................................................... 87

11.0 Interrupts .................................................................................................................................................................................... 93

12.0 Timer0 Module ......................................................................................................................................................................... 107

13.0 Timer1 Module ......................................................................................................................................................................... 111

14.0 Power Control PWM Module .................................................................................................................................................... 117

15.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 147

16.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 169

17.0 Comparator Module.................................................................................................................................................................. 179

18.0 Comparator Voltage Reference Module ................................................................................................................................... 183

19.0 Low-Voltage Detect (LVD)........................................................................................................................................................ 187

20.0 Special Features of
the CPU191

21.0 Development Support............................................................................................................................................................... 211

22.0 Instruction Set Summary.......................................................................................................................................................... 215

23.0 Electrical Characteristics.......................................................................................................................................................... 265

24.0 Packaging Information.............................................................................................................................................................. 295

Appendix A: Revision History............................................................................................................................................................. 303

Appendix B: Device Differences......................................................................................................................................................... 304

Appendix C: Conversion Considerations ........................................................................................................................................... 305

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 305

Appendix E: Migration from Mid-Range TO Enhanced Devices ........................................................................................................ 306

Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 306

Index .................................................................................................................................................................................................. 307

DS39758D-page 6  2009 Microchip Technology Inc.

PIC18F1230/1330

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 2009 Microchip Technology Inc. DS39758D-page 7

PIC18F1230/1330

NOTES:

DS39758D-page 8  2009 Microchip Technology Inc.

PIC18F1230/1330

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC18F1230 • PIC18F1330

• PIC18LF1230 • PIC18LF1330

This family offers the advantages of all PIC18 micro­controllers – namely, high computational performance at
an economical price – with the addition of high­endurance Enhanced Flash program memory. On top of
these features, the PIC18F1230/1330 family introduces
design enhancements that make these microcontrollers
a logical choice for many high-performance, power
control and motor control applications.

Peripheral highlights include:

• 14-bit resolution Power Control PWM module

(PCPWM) with programmable dead-time insertion

The PCPWM can generate up to six complementary
PWM outputs with dead-band time insertion. Overdrive
current is detected by off-chip analog comparators or
the digital Fault input (FLTA

PIC18F1230/1330 devices also feature Flash program
memory and an internal RC oscillator.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F1230/1330 family incor­porate a range of features that can significantly reduce
power consumption during operation. Key items
include:

• Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.

• On-the-Fly Mode Switching: The power-managed

modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.

• Low Consumption in Key Modules: The power

requirements for both Timer1 and the Watchdog

Timer are minimized. See Section 23.0 “Electrical
Characteristics” for values.

).

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F1230/1330 family offer
ten different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).

• Two External RC Oscillator modes with the same

pin options as the External Clock modes.

• An internal oscillator block which provides an 8 MHz

clock and an INTRC source (approximately 31 kHz),
as well as a range of six user-selectable clock
frequencies, between 125 kHz to 4 MHz, for a total of
eight clock frequencies. This option frees the two
oscillator pins for use as additional general
purpose I/Os.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and Internal
Oscillator modes, which allows clock speeds of up to
40 MHz. Used with the internal oscillator, the PLL
gives users a complete selection of clock speeds,
from 31 kHz to 32 MHz, all without using an external
crystal or clock circuit.

Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
low-speed operation or a safe application
shutdown.

• Two-Speed St art-u p: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

 2009 Microchip Technology Inc. DS39758D-page 9

PIC18F1230/1330

1.2 Other Special Features

• Memory Endurance: The Enhanced Flash cells for

both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles –
up to 100,000 for program memory and 1,000,000
for EEPROM. Data retention without refresh is
conservatively estimated to be greater than
40 years.

• Self-Programmability: These devices can write to

their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of
program memory, it becomes possible to create an
application that can update itself in the field.

• Extended Instruction Set: The PIC18F1230/1330

family introduces an optional extension to the PIC18
instruction set, which adds eight new instructions
and an Indexed Addressing mode. This extension,
enabled as a device configuration option, has been
specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as C.

• Power Control PWM Module: This module

provides up to six modulated outputs for controlling
half-bridge and full-bridge drivers. Other features
include auto-shutdown on Fault detection and
auto-restart to reactivate outputs once the condition
has cleared.

• Enhanced Addressable USART: This serial

communication module is capable of standard
RS-232 operation and provides support for the
LIN/J2602 bus protocol. Other enhancements
include automatic Baud Rate Detection and a 16-bit
Baud Rate Generator for improved resolution. When
the microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).

• 10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reducing code overhead.

• Extended W atchdog T imer (WDT ): This enhanced

version incorporates a 16-bit prescaler, allowing an
extended time-out range that is stable across
operating voltage and temperature. See

Section 23.0 “Electrical Characteristics” for

time-out periods.

1.3 Details on Individual Family Members

Devices in the PIC18F1230/1330 family are available
in 18-pin, 20-pin and 28-pin packages.

The devices are differentiated from each other in one
way:

1. Flash program memory (4 Kbytes for

PIC18F1230, 8 Kbytes for PIC18F1330).

All other features for devices in this family are identical.
These are summarized in Table 1-1.

A block diagram of the PIC18F1220/1320 device archi­tecture is provided in Figure 1-1. The pinouts for this
device family are listed in Table 1-2.

Like all Microchip PIC18 devices, members of the
PIC18F1230/1330 family are available as both stan­dard and low-voltage devices. Standard devices with
Enhanced Flash memory, designated with an “F” in the

part number (such as PIC18F1330), accommodate an

operating V

parts, designated by “LF” (such as PIC18LF1330),

function over an extended VDD range of 2.0V to 5.5V.

DD range of 4.2V to 5.5V. Low-voltage

DS39758D-page 10  2009 Microchip Technology Inc.

PIC18F1230/1330

TABLE 1-1: DEVICE FEATURES

Features PIC18F1230 PIC18F1330

Operating Frequency DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 4096 8192

Program Memory (Instructions) 2048 4096

Data Memory (Bytes) 256 256

Data EEPROM Memory (Bytes) 128 128

Interrupt Sources 17 17

I/O Ports Ports A, B Ports A, B

Timers 2 2

Power Control PWM Module 6 Channels 6 Channels

Serial Communications Enhanced USART Enhanced USART

10-Bit Analog-to-Digital Module 4 Input Channels 4 Input Channels

Resets (and Delays) POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow (PWRT, OST),

(optional),

MCLR

WDT

Programmable Low-Voltage Detect Yes Yes

Programmable Brown-out Reset Yes Yes

Instruction Set 75 Instructions;

83 with Extended Instruction Set

enabled

Packages 18-Pin PDIP

18-Pin SOIC

20-Pin SSOP

28-Pin QFN

Stack Underflow (PWRT, OST),

83 with Extended Instruction Set

POR, BOR,

RESET Instruction,

Stack Full,

MCLR (optional),

WDT

75 Instructions;

enabled

18-Pin PDIP
18-Pin SOIC

20-Pin SSOP

28-Pin QFN

 2009 Microchip Technology Inc. DS39758D-page 11

PIC18F1230/1330

Instruction

Decode &

Control

PORTA

RA2/TX/CK

Enhanced

Timer0

Timer1

PCPWM

MCLR/VPP/RA5

(1)

/FLTA

(4)

RA4/T0CKI/AN2/VREF+

RA1/AN1/INT1/KBI1

RA0/AN0/INT0/KBI0/CMP0

Data Latch

Data RAM

Address Latch

Address<12>

12

BSR

FSR0
FSR1
FSR2

4

12 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

WREG

8

BIT OP

8

8

ALU<8>

8

Address Latch

(8 Kbytes)

Data Latch

20

21

21

16

8

8

8

inc/dec logic

21

8

Data Bus<8>

8

Instruction

12

3

ROM Latch

Bank0, F

PCLATU

PCU

RA3/RX/DT

USART

8

Register

Table Latch

Tab l e P o i n t er < 2 >

inc/dec

logic

RB0/PWM0

Decode

Power-up

Timer

Power-on

Reset

Watchdog

Timer

V

DD, VSS

Brown-out

Reset

Precision

Reference

Volt ag e

Low-Voltage

Programming

In-Circuit

Debugger

Oscillator

Start-up Timer

Timing

Generation

OSC1

(2)

OSC2

(2)

T1OSI

T1OSO

INTRC

Oscillator

Fail-Safe

Clock Monitor

Note 1: RA5 is available only when the MCLR Reset is disabled.

2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being

used as digital I/O. Refer to Section 3.0 “Oscillator Configurations” for additional information.
3: Placement of T1OSI and T1OSO/T1CKI depends on the value of the Configuration bit, T1OSCMX, of CONFIG3H.
4: Placement of FLTA

depends on the value of the Configuration bit, FLTAMX, of CONFIG3H.

8

Program Memory

(4 Kbytes)

PIC18F1230

PIC18F1330

10-Bit

Data EEPROM

MCLR

(1)

BOR

LVD

A/D Converter

RB1/PWM1

RB7/PWM5/PGD

RA6/OSC2

(2)

/CLKO

(2)

/

RA7/OSC1

(2)

/CLKI

(2)

/

RB2/INT2/KBI2/CMP2/

RB3/INT3/KBI3/CMP1/

RB6/PWM4/PGC

RB5/PWM3

RB4/PWM2

PORTB

T1OSI

(3)

T1OSO

(3)

/T1CKI

(3)

T1OSI

(3)

/FLTA

(4)

T1OSO

(3)

/T1CKI

(3)

/AN3

FIGURE 1-1: PIC18F1230/1330 ( 18-PIN) BLOCK DI AGRAM

DS39758D-page 12  2009 Microchip Technology Inc.

PIC18F1230/1330

T ABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

/VPP/RA5/FLTA

MCLR

MCLR

VPP
RA5

(1)

FLTA

RA7/OSC1/CLKI/
T1OSI/FLTA

RA7
OSC1

CLKI

(2)

T1OSI

(1)

FLTA

RA6/OSC2/CLKO/
T1OSO/T1CKI/AN3

RA6
OSC2

CLKO
T1OSO
TICKI
AN3

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Placement of FLTA

(2)

(2)

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of

CONFIG3H.

PDIP,
SOIC

SSOP QFN

441

16 18 21

15 17 20

depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

Pin

Type

I

I
I
I

I/O

I

I
I
I

I/O

O

O
O

I
I

Buffer

Type

ST

Analog

ST
ST

ST

Analog

—

Analog

ST

ST

—

—
—

ST

Analog

Description

Master Clear (input), programming voltage (input)
or Fault detect input.

Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
Digital input.
Fault detect input for PWM.

Oscillator crystal, external clock input, Timer1
oscillator input or Fault detect input.

Digital I/O.
Oscillator crystal input or external clock source
input.
External clock source input.
Timer1 oscillator input.
Fault detect input for PWM.

Oscillator crystal, clock output, Timer1 oscillator
output or analog input.

Digital I/O.
Oscillator crystal output or external clock

source input.
External clock source output.
Timer1 oscillator output.
Timer1 clock input.
Analog input 3.

 2009 Microchip Technology Inc. DS39758D-page 13

PIC18F1230/1330

TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0/INT0/KBI0/
CMP0

RA0
AN0
INT0
KBI0
CMP0

RA1/AN1/INT1/KBI1

RA1
AN1
INT1
KBI1

RA2/TX/CK

RA2
TX
CK

RA3/RX/DT

RA3
RX
DT

RA4/T0CKI/AN2/V

RA4
T0CKI
AN2

REF+

V

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Placement of FLTA

2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of

CONFIG3H.

REF+

PDIP,
SOIC

SSOP QFN

1126

2227

677

788

3328

depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

Pin

Type

I/O

I
I
I
I

I/O

I
I
I

I/O

O

I/O

I/O

I

I/O

I/O

I
I
I

Buffer

Type

TTL

Analog

ST

TTL

Analog

TTL

Analog

ST

TTL

TTL

—

ST

TTL

ST
ST

TTL

ST
Analog
Analog

Description

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.
External interrupt 0.
Interrupt-on-change pin.
Comparator 0 input.

Digital I/O.
Analog input 1.
External interrupt 1.
Interrupt-on-change pin.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock.

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data.

Digital I/O.
Timer0 external clock input.
Analog input 2.
A/D reference voltage (high) input.

DS39758D-page 14  2009 Microchip Technology Inc.

PIC18F1230/1330

TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/PWM0

RB0
PWM0

RB1/PWM1

RB1
PWM1

RB2/INT2/KBI2/CMP2/
T1OSO/T1CKI

RB2
INT2
KBI2
CMP2
T1OSO
T1CKI

RB3/INT3/KBI3/CMP1/
T1OSI

RB3
INT3
KBI3
CMP1
T1OSI

RB4/PWM2

RB4
PWM2

RB5/PWM3

RB5
PWM3

RB6/PWM4/PGC

RB6
PWM4
PGC

RB7/PWM5/PGD

RB7
PWM5
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Placement of FLTA

(2)

(2)

(2)

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of

CONFIG3H.

PDIP,
SOIC

SSOP QFN

899

91010

17 19 23

18 20 24

10 11 12

11 12 13

12 13 15

13 14 16

depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

Pin

Buffer

Type

Type

I/OOTTL

I/OOTTL

I/O

I
I
I

Analog

O

I

I/O

I
I
I

Analog

I

Analog

I/OOTTL

I/OOTTL

I/O

O

I

I/O

O
O

PORTB is a bidirectional I/O port.

Digital I/O.

—

—

TTL

ST

TTL

—

ST

TTL

ST

TTL

—

—

TTL

—

ST

TTL

—
—

PWM module output PWM0.

Digital I/O.
PWM module output PWM1.

Digital I/O.
External interrupt 2.
Interrupt-on-change pin.
Comparator 2 input.
Timer1 oscillator output.
Timer1 clock input.

Digital I/O.
External interrupt 3.
Interrupt-on-change pin.
Comparator 1 input.
Timer1 oscillator input.

Digital I/O.
PWM module output PWM2.

Digital I/O.
PWM module output PWM3.

Digital I/O.
PWM module output PWM4.
In-Circuit Debugger and ICSP™ programming
clock pin.

Digital I/O.
PWM module output PWM5.
In-Circuit Debugger and ICSP programming
data pin.

Description

 2009 Microchip Technology Inc. DS39758D-page 15

PIC18F1230/1330

TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

VSS 5 5 3 P — Ground reference for logic and I/O pins.

VDD 14 16 19 P — Positive supply for logic and I/O pins.

SS 5 6 5 P — Ground reference for A/D Converter module.

AV

AVDD 14 15 17 P — Positive supply for A/D Converter module.

NC — — 2, 4, 6,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Placement of FLTA

2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of

CONFIG3H.

PDIP,
SOIC

SSOP QFN

11, 14,
18, 22,

depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

25

Pin

Buffer

Type

Type

— — No Connect.

Description

DS39758D-page 16  2009 Microchip Technology Inc.

PIC18F1230/1330

PIC18FXXXX

VDD

VSS

VDD

VSS

VSS

VDD

AVDD

AVSS

VDD

VSS

C1

R1

V

DD

MCLR

R2

C2

(1)

C3

(1)

C4

(1)

C5

(1)

C6

(1)

Key (all values are recommendations):

C1 through C6: 0.1 µF, 20V ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω
Note 1: The example shown is for a PIC18F device

with five V

DD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.

2.0 GUIDELINES FOR GETTING
STARTED WITH PIC18F

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTIONS

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC18F1230/1330 family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.

The following pins must always be connected:

DD and VSS pins

•All V

(see Section 2.2 “Power Supply Pins”)

•All AV

•M

These pins must also be connected if they are being
used in the end application:

• PGC/PGD pins used for In-Circuit Serial

• OSCI and OSCO pins when an external oscillator

Additionally, the following pins may be required:

•V

The minimum mandatory connections are shown in
Figure 2-1.

DD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

CLR pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

Programming™ (ICSP™) and debugging purposes

(see Section 2.4 “ICSP Pins”)

source is used

(see Section 2.5 “External Oscillator Pins”)

REF+/VREF- pins are used when external voltage

reference for analog modules is implemented

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of
the analog modules are being used.

 2009 Microchip Technology Inc. DS39758D-page 17

PIC18F1230/1330

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of
power supply pins, such as V

SS, is required.

AV

Consider the following criteria when using decoupling
capacitors:

• Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci­tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).

• Maximizing performance: On the board layout

from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.

DD, VSS, AVDD and

2.2.2 TANK CAPACITORS

On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac­itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.

2.2.3 CONSIDERATIONS WHEN USING
BOR

When the Brown-out Reset (BOR) feature is enabled,
a sudden change in V
BOR event. This can happen when the microcontroller
is operating under normal operating conditions, regard­less of what the BOR set point has been programmed
to, and even if V
The precipitating factor in these BOR events is a rise or
fall in VDD with a slew rate faster than 0.15V/s.

An application that incorporates adequate decoupling
between the power supplies will not experience such
rapid voltage changes. Additionally, the use of an
electrolytic tank capacitor across V
described above, will be helpful in preventing high slew
rate transitions.

If the application has components that turn on or off,
and share the same V
the BOR can be disabled in software by using the
SBOREN bit before switching the component. After­wards, allow a small delay before re-enabling the BOR.
By doing this, it is ensured that the BOR is disabled
during the interval that might cause high slew rate
changes of V

Note: Not all devices incorporate software BOR

DD.

control. See Section 5.0 “Reset” for

device-specific information.

DD may result in a spontaneous

DD does not approach the set point.

DD and VSS, as

DD circuit as the microcontroller,

DS39758D-page 18  2009 Microchip Technology Inc.

PIC18F1230/1330

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the
MCLR

pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR

from the external capacitor, C, in the

event of MCLR

pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR

pin

V

IH and VIL specifications are met.

C1

R2

R1

V

DD

MCLR

PIC18FXXXX

JP

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to V
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.

During programming and debugging, the resistance
and capacitance that can be added to the pin must be
considered. Device programmers and debuggers drive
the MCLR

IH and VIL) and fast signal transitions must not be

(V
adversely affected. Therefore, specific values of R1
and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated from
the MCLR
operations by using a jumper (Figure 2-2). The jumper
is replaced for normal run-time operations.

Any components associated with the MCLR
should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

DD may be all that is required. The

pin. Consequently, specific voltage levels

pin during programming and debugging

pin

CONNECTIONS

2.4 ICSP Pins

The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom­mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.

Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica­tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter­natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits and pin input voltage high (V
and input low (V

IL) requirements.

For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.

For more information on available Microchip
development tools connection requirements, refer to

Section 21.0 “Development Support”.

IH)

 2009 Microchip Technology Inc. DS39758D-page 19

PIC18F1230/1330

GND

`

`

`

OSC1

OSC2

T1OSO

T1OS I

Copper Pour

Primary Oscillator

Crystal

Timer1 Oscillator

Crystal

DEVICE PINS

Primary

Oscillator

C1

C2

T1 Oscillator: C1

T1 Oscillator: C2

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

GND

OSCO

OSCI

Bottom Layer

Copper Pour

Oscillator

Crystal

Top Layer Copper Pour

C2

C1

DEVICE PINS

(tied to ground)

(tied to ground)

2.5 External Oscillator Pins

Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to

Section 3.0 “Oscillator Configurations” for details).

The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.

Use a grounded copper pour around the oscillator cir­cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.

Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com­pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.

In planning the application’s routing and I/O assign­ments, ensure that adjacent port pins and other signals
in close proximity to the oscillator are benign (i.e., free
of high frequencies, short rise and fall times, and other
similar noise).

For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro

• AN849, “Basic PICmicro

• AN943, “Practical PICmicro
and Design”

• AN949, “Making Your Oscillator Work”

®

®

Oscillator Design”

®

Oscillator A nalysis

Devices”

2.6 Unused I/Os

Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR
CIRCUIT

DS39758D-page 20  2009 Microchip Technology Inc.

PIC18F1230/1330

Note 1: See Table 3-1 and Table 3-2 for initial values of

C1 and C2.

2: A series resistor (R

S) may be required for AT

strip cut crystals.

3: R

F varies with the oscillator mode chosen.

C1

(1)

C2

(1)

XTAL

OSC2

OSC1

RF

(3)

Sleep

To

Logic

PIC18FXXXX

RS

(2)

Internal

3.0 OSCILLATOR CONFIGURATIONS

3.1 Oscillator Types

PIC18F1230/1330 devices can be operated in ten
different oscillator modes. The user can program the
Configuration bits, FOSC3:FOSC0, in Configuration
Register 1H to select one of these ten modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL enabled

5. RC External Resistor/Capacitor with

F

OSC/4 output on RA6

6. RCIO External Resistor/Capacitor with I/O

on RA6

7. INTIO1 Internal Oscillator with F

on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

3.2 Crystal Oscilla tor/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 3-1 shows
the pin connections.

The oscillator design requires the use of a parallel
resonant crystal.

Note: Use of a series resonant crystal may give

a frequency out of the crystal
manufacturer’s specifications.

OSC/4 output

OSC/4 output

FIGURE 3-1: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)

T ABLE 3-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 3.58 MHz

4.19 MHz
4 MHz
4 MHz

Capacitor values are for design guidance only.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V

See the notes following Table 3-2 for additional
information.

15 pF
15 pF
30 pF
50 pF

15 pF
15 pF
30 pF
50 pF

 2009 Microchip Technology Inc. DS39758D-page 21

PIC18F1230/1330

OSC1

OSC2

Open

Clock from
Ext. System

PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKO

F

OSC/4

Clock from
Ext. System

PIC18FXXXX

OSC1/CLKI

I/O (OSC2)

RA6

Clock from
Ext. System

PIC18FXXXX

TABLE 3-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc T y pe

LP 32 kHz 30 pF 30 pF

XT 1 MHz

HS 4 MHz

Capacitor values are for design guidance only.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.

See the notes following this table for additional
information.

Note 1: Higher capacitance increases the stability

Crystal

Freq

4 MHz

10 MHz
20 MHz
25 MHz

of the oscillator but also increases the
start-up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

T ypical Cap acitor V alues

Tested:

C1 C2

15 pF
15 pF

15 pF
15 pF
15 pF
15 pF

15 pF
15 pF

15 pF
15 pF
15 pF
15 pF

DD, or when

An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-2.

FIGURE 3-2: EXTERNAL CLOCK

INPUT OPERATION
(HS OSCILLATOR
CONFIGURATION)

3.3 External Clock Input

The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.

FIGURE 3-3: EXTERNAL CLOCK

INPUT OPERATION
(EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 3-4 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 3-4: EXTERNAL CLOCK

INPUT OPERATION
(ECIO CONFIGURATION)

DS39758D-page 22  2009 Microchip Technology Inc.

PIC18F1230/1330

OSC2/CLKO

CEXT

REXT

PIC18FXXXX

OSC1

F

OSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 k  REXT  100 k

C

EXT > 20 pF

CEXT

REXT

PIC18FXXXX

OSC1

Internal

Clock

VDD

VSS

Recommended values: 3 k  REXT  100 k

C

EXT > 20 pF

I/O (OSC2)

RA6

MUX

VCO

Loop
Filter

Crystal

Osc

OSC2

OSC1

PLL Enable

F

IN

FOUT

SYSCLK

Phase

Comparator

HS Oscillator Enable

4

(from Configuration Register 1H)

HS Mode

3.4 RC Oscillator

For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:

• supply voltage

• values of the external resistor (R
capacitor (C

EXT)

• operating temperature

Given the same device, operating voltage and
temperature and component values, there will also be
unit-to-unit frequency variations. These are due to
factors such as:

• normal manufacturing variation

• difference in lead frame capacitance between
package types (especially for low C

• variations within the tolerance of limits of REXT

EXT

and C

In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows how the R/C combination is
connected.

EXT) and

EXT values)

3.5 PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.

3.5.1 HSPLL OSCILLATOR MODE

The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz. The PLLEN bit is not
available in this oscillator mode.

The PLL is only available to the crystal oscillator when
the FOSC3:FOSC0 Configuration bits are programmed
for HSPLL mode (= 0110).

FIGURE 3-7: PLL BLOCK DIAGRAM

(HS MODE)

FIGURE 3-5: RC OSCILLATOR MODE

The RCIO Oscillator mode (Figure 3-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).

FIGURE 3-6: RCIO OSCILLATOR MODE

 2009 Microchip Technology Inc. DS39758D-page 23

3.5.2 PLL AND INTOSC

The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock
output of up to 32 MHz. The operation of INTOSC with

the PLL is described in Section 3.6.4 “PLL in INTOSC

Modes”.

PIC18F1230/1330

3.6 Internal Oscillator Block

The PIC18F1230/1330 devices include an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s clock
source. This may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in

Section 20.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 28).

3.6.1 INTIO MODES

Using the internal oscillator as the clock source
eliminates the need for up to two external oscillator
pins, which can then be used for digital I/O. Two distinct
configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA7 for digital input and
output.

• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.

3.6.2 INTOSC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.

The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.

3.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s
application. This is done by writing to the OSCTUNE
register (Register 3-1). The tuning sensitivity is
constant throughout the tuning range.

OSC/4,

When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency.
Code execution continues during this shift. There is no
indication that the shift has occurred.

The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.

This is covered in greater detail in Section 3.7.1
“Oscillator Control Register”.

The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.

3.6.4 PLL IN INTOSC MODES

The 4x frequency multiplier can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.

Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation. If PLL is
enabled and a Two-Speed Start-up from wake is per­formed, execution is delayed until the PLL starts.

The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output fre­quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.

The PLLEN control bit is only functional in those inter­nal oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.

3.6.5 INTOSC FREQUENCY DRIFT

The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Two compensation techniques are discussed

in Section 3.6.5.1 “Compensating with the

EUSART” and Section 3.6.5.2 “Compensating with
the Timers”, but other techniques may be used.

DS39758D-page 24  2009 Microchip Technology Inc.

PIC18F1230/1330

REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 R/W-0

INTSRC PLLEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled

bit 5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

• •

• •

00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111

• •

• •
10000 = Minimum frequency

(1)

(1)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TUN4 TUN3 TUN2 TUN1 TUN0

(1)

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See

Section 3.6.4 “PLL in INTOSC Modes” for details.

3.6.5.1 Compensating with the EUSART

An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high; to
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low; to
compensate, increment OSCTUNE to increase the
clock frequency.

3.6.5.2 Compensating with the Timers

This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.

Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.

 2009 Microchip Technology Inc. DS39758D-page 25

PIC18F1230/1330

4 x PLL

FOSC3:FOSC0

T1OSCEN
Enable
Oscillator

T1OSO

T1OSI

Clock Source Option
for Other Modules

OSC1

OSC2

Sleep

HSPLL, INTOSC/PLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

Postscaler

MUX

MUX

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON<6:4>

111
110
101
100

011
010
001

000

31 kHz

INTRC

Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON<6:4>

Clock

Control

OSCCON<1:0>

Source

8 MHz

31 kHz (INTRC)

OSCTUNE<6>

0

1

OSCTUNE<7>

and Two-Speed Start-up

Primary Oscillator

Secondary Oscillator

3.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the PIC18F1230/1330
family includes a feature that allows the device clock
source to be switched from the main oscillator to an
alternate low-frequency clock source. PIC18F1230/1330
devices offer two alternate clock sources. When an alter­nate clock source is enabled, the various power-managed
operating modes are available.

Essentially, there are three clock sources for these
devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the External Crystal

and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
Configuration bits. The details of these modes are
covered earlier in this chapter.

The s econdary oscillators are those external sources

not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.

PIC18F1230/1330 devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all power­managed modes, is often the time base for functions
such as a real-time clock.

Most often, a 32.768 kHz watch crystal is connected
between the T1OSO/T1CKI and T1OSI pins. Like the
LP mode oscillator circuit, loading capacitors are also
connected from each pin to ground. The Timer1 oscil-

lator is discussed in greater detail in Section 13.2
“Timer1 Oscillator ” .

In addition to being a primary clock source, the internal
oscillator block is available as a power-managed

mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F1230/1330 devices

are shown in Figure 3-8. See Section 20.0 “Special

Features of the CPU” for Configuration register details.

FIGURE 3-8: PIC18F1230/1330 CLOCK DIAGRAM

DS39758D-page 26  2009 Microchip Technology Inc.

PIC18F1230/1330

3.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 3-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0
Configuration bits), the secondary clock (Timer1
oscillator) and the internal oscillator block. The clock
source changes immediately after one or more of the
bits is written to, following a brief clock transition
interval. The SCS bits are cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits
(IRCF2:IRCF0) select the frequency output of the
internal oscillator block to drive the device clock. The
choices are the INTRC source, the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31.25 kHz to 4 MHz). If the
internal oscillator block is supplying the device clock,
changing the states of these bits will have an immedi­ate change on the internal oscillator’s output. On
device Resets, the default output frequency of the
internal oscillator block is set at 1 MHz.

When a nominal output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which
internal oscillator acts as the source. This is done with
the INTSRC bit in the OSCTUNE register
(OSCTUNE<7>). Setting this bit selects INTOSC as a

31.25 kHz clock source by enabling the divide-by-256
output of the INTOSC postscaler. Clearing INTSRC
selects INTRC (nominally 31 kHz) as the clock source.

This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has
stabilized and is providing the device clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock or the internal oscillator block has just started and
is not yet stable.

The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.

The use of the flag and control bits in the OSCCON

register is discussed in more detail in Section 4.0

“Power-Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis­ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.

3.7.2 OSCILLATOR TRANSITIONS

PIC18F1230/1330 devices contain circuitry to prevent
clock “glitches” when switching between clock sources.
A short pause in the device clock occurs during the
clock switch. The length of this pause is the sum of two
cycles of the old clock source and three to four cycles
of the new clock source. This formula assumes that the
new clock source is stable.

Clock transitions are discussed in greater detail in

Section 4.1.2 “Entering Power-Managed Modes”.

 2009 Microchip Technology Inc. DS39758D-page 27

PIC18F1230/1330

REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER

(1)

(1)

R-0 R/W-0 R/W-0

(2)

R/W-0 R/W-1 R/W-0 R/W-0 R

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block
01 = Secondary (Timer1) oscillator
00 = Primary oscillator

(3)

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
3: Default output frequency of INTOSC on Reset.

DS39758D-page 28  2009 Microchip Technology Inc.

PIC18F1230/1330

3.8 Effects of Power-Managed Modes on the Various Clock Sources

When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the power-

managed mode (see Section 20.2 “Watchdog Timer

(WDT)”, Section 20.3 “Two-Speed Start-up” and
Section 20.4 “Fail-Safe Clock Monitor” for more

information on WDT, Fail-Safe Clock Monitor and Two­Speed Start-up). The INTOSC output at 8 MHz may be
used directly to clock the device or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).

Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real-

time clock. Other features may be operating that do not
require a device clock source (i.e., INTx pins and
others). Peripherals that may add significant current

consumption are listed in Section 23.0 “Electrical

Characteristics”.

3.9 Power-up Delays

Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal
circumstances and the primary clock is operating and
stable. For additional information on power-up delays,

see Section 5.5 “Device Reset Timers”.

The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 23-10). It is enabled by clearing (= 0) the
PWRTEN

The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.

There is a delay of interval T
Table 23-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC, RC or INTIO
modes are used as the primary clock source.

Configuration bit.

CSD (parameter 38,

TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin

RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)

RCIO Floating, external resistor should pull high Configured as PORTA, bit 6

INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6

ECIO Floating, pulled by external clock Configured as PORTA, bit 6

EC Floating, pulled by external clock At logic low (clock/4 output)

LP, XT and HS Feedback inverter disabled at quiescent

voltage level

Note: See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR

 2009 Microchip Technology Inc. DS39758D-page 29

Feedback inverter disabled at quiescent
voltage level

Reset.

PIC18F1230/1330

NOTES:

DS39758D-page 30  2009 Microchip Technology Inc.

PIC18F1230/1330

4.0 POWER-MANAGED MODES

PIC18F1230/1330 devices offer a total of seven
operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.

The power-managed modes include several power­saving features offered on previous PIC
is the clock switching feature, offered in other PIC18
devices, allowing the controller to use the Timer1
oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.

4.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of a clock source. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 4-1.

®

devices. One

4.1.1 CLOCK SOURCES

The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:

• the primary clock, as defined by the
FOSC3:FOSC0 Configuration bits

• the secondary clock (the Timer1 oscillator)

• the internal oscillator block (for RC modes)

4.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are

discussed in Section 4.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.

Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.

TABLE 4-1: POWER-MANAGED MODES

OSCCON Bits Module Clocking

Mode

IDLEN<7>

Sleep 0 N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and

SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block
PRI_IDLE 100Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 11xOff Clocked Internal Oscillator Block

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

 2009 Microchip Technology Inc. DS39758D-page 31

SCS1:SCS0

(1)

<1:0>

CPU Peripherals

Available Cl ock and Os cill ator Source

Internal Oscillator Block
This is the normal full power execution mode.

(2)

(2)

(2)

.

PIC18F1230/1330

4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS

The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.

Three bits indicate the current clock source and its
status. They are:

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a
given power-managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is
providing a stable 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit is
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is clocking the device, or the INTOSC source is
not yet stable.

If the internal oscillator block is configured as the primary
clock source by the FOSC3:FOSC0 Configuration bits,
then both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering another power-managed RC
mode at the same frequency would clear the OSTS bit.

Note 1: Caution should be used when modifying a

single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if

DD/FOSC specifications are violated.

the V

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.

DD is less than 3V, it is

4.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.

4.2 Run Modes

In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.

4.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up

is enabled (see Section 20.3 “Two-Speed Start-up”

for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is the

primary clock source (see Section 3.7.1 “Oscillator
Control Register”).

4.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.

SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary oscillator
is shut down, the T1RUN bit (T1CON<6>) is set and the
OSTS bit is cleared.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa­tions, initial oscillator operation is far from
stable and unpredictable operation may
result.

On transitions from SEC_RUN to PRI_RUN mode, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 4-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.

DS39758D-page 32  2009 Microchip Technology Inc.

PIC18F1230/1330

Q4Q3Q2

OSC1

Peripheral

Program

Q1

T1OSI

Q1

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition

(1)

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q1 Q3 Q4

OSC1

Peripheral

Program

PC

T1OSI

PLL Clock

Q1

PC + 4

Q2

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 T

OSC.

SCS1:SCS0 bits Changed

TPLL

(1)

12 n-1n

Clock

OSTS bit Set

Transition

(2)

TOST

(1)

FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

4.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.

If the primary clock source is the internal oscillator block
(either INTRC or INTOSC), there are no distinguishable
differences between PRI_RUN and RC_RUN modes
during execution. However, a clock switch delay will
occur during entry to and exit from RC_RUN mode.
Therefore, if the primary clock source is the internal
oscillator block, the use of RC_RUN mode is not
recommended.

 2009 Microchip Technology Inc. DS39758D-page 33

This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
bit also be cleared; this is to maintain software compat­ibility with future devices. When the clock source is
switched to the INTOSC multiplexer (see Figure 4-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.

Note: Caution should be used when modifying a

single IRCF bit. If V

DD is less than 3V, it is

possible to select a higher clock speed
than is supported by the low V

DD.

Improper device operation may result if

DD/FOSC specifications are violated.

the V

PIC18F1230/1330

Q4Q3Q2

OSC1

Peripheral

Program

Q1

INTRC

Q1

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition

(1)

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q1

Q3 Q4

OSC1

Peripheral

Program

PC

INTOSC

PLL Clock

Q1

PC + 4

Q2

Output

Q3

Q4

Q1

CPU Clock

PC + 2

Clock

Counter

Q2

Q2

Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 T

OSC.

SCS1:SCS0 bits Changed

TPLL

(1)

12 n-1n

Clock

OSTS bit Set

Transition

(2)

Multiplexer

TOST

(1)

If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.

If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of

IOBST.

T

On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.

If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.

FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE

FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

DS39758D-page 34  2009 Microchip Technology Inc.

PIC18F1230/1330

Q4Q3Q2

OSC1

Peripheral

Sleep

Program

Q1Q1

Counter

Clock

CPU

Clock

PC + 2PC

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program

PC

PLL Clock

Q3 Q4

Output

CPU Clock

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter

PC + 6

PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note 1:T

OST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST

(1)

TPLL

(1)

OSTS bit Set

PC + 2

4.3 Sleep Mode

The power-managed Sleep mode in the PIC18F1230/
1330 devices is identical to the legacy Sleep mode
offered in all other PIC devices. It is entered by clearing
the IDLEN bit (the default state on device Reset) and
executing the SLEEP instruction. This shuts down the
selected oscillator (Figure 4-5). All clock source status
bits are cleared.

Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.

When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled

(see Sectio n 20.0 “Special Features of the CPU”). In

either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.

4.4 Idle Modes

The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.

If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.

Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
(parameter 38, Table 23-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.

CSD

FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

 2009 Microchip Technology Inc. DS39758D-page 35

PIC18F1230/1330

Q1

Peripheral

Program

PC PC + 2

OSC1

Q3

Q4

Q1

CPU Clock

Clock

Counter

Q2

OSC1

Peripheral

Program

PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Q2

Wake Event

TCSD

4.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc­tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 4-7).

When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T

CSD is

required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake­up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 4-8).

4.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by

setting the IDLEN bit and executing a SLEEP
instruction. If the device is in another Run mode, set the
IDLEN bit first, then set the SCS1:SCS0 bits to ‘01’ and
execute SLEEP. When the clock source is switched to
the Timer1 oscillator, the primary oscillator is shut
down, the OSTS bit is cleared and the T1RUN bit is set.

When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval

CSD following the wake event, the CPU begins

of T
executing code being clocked by the Timer1 oscillator.
The IDLEN and SCS bits are not affected by the
wake-up; the Timer1 oscillator continues to run (see
Figure 4-8).

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.

FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

DS39758D-page 36  2009 Microchip Technology Inc.

PIC18F1230/1330

4.4.3 RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block using the INTOSC multiplexer. This
mode allows for controllable power conservation during
Idle periods.

From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.

If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of T
(parameter 39, Table 23-10). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled, the IOFS bit will remain clear and there will be
no indication of the current clock source.

When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay of

CSD following the wake event, the CPU begins

T
executing code being clocked by the INTOSC
multiplexer. The IDLEN and SCS bits are not affected by
the wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.

IOBST

4.5 Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed

modes (see Section 4.2 “Run Modes”, Section 4.3
“Sleep Mode” and Section 4.4 “Idle Modes”).

4.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.

On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code execution
continues or resumes without branching (see

Section 11.0 “Interrupts”).

A fixed delay of interval T
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.

CSD following the wake event

4.5.2 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.

If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the

power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 20.2 “Watchdog
Timer (WDT)”).

The WDT timer and postscaler are cleared by
executing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.

4.5.3 EXIT BY RESET

Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the IOFS bit is set instead.

The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 4-2.

Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see

Section 20.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 20.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution

as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready or a power-managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.

 2009 Microchip Technology Inc. DS39758D-page 37

PIC18F1230/1330

4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DE LAY

Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source is

not stopped; and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval

CSD following the wake event is still required when

T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.

TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Primary Device Clock

(PRI_IDLE mode)

T1OSC

INTOSC

(Sleep mode)

Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently

with any other required delays (see Section 4.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz.

2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: T

also designated as T

4: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

(3)

None

OST is the Oscillator Start-up Timer (parameter 32). t

PLL.

Clock Source

after Wake-up

Exit Delay

LP, XT, HS

EC, RC

INTOSC

(2)

LP, XT, HS TOST

EC, RC TCSD

INTOSC

(1)

LP, XT, HS TOST

EC, RC TCSD

INTOSC

(1)

LP, XT, HS TOST

EC, RC TCSD

INTOSC

(1)

is the PLL Lock-out Timer (parameter F12); it is

rc

Clock Ready Status

Bit (OSCCON)

T

CSD

TIOBST

(1)

(3)

(1)

(4)

(1)

rc

(4)

rc

(3)

(3)

OSTSHSPLL

OSTSHSPLL TOST + t

OSTSHSPLL TOST + t

None IOFS

(3)

TIOBST

(1)

rc

(4)

(3)

OSTSHSPLL TOST + t

IOFS

IOFS

IOFS

DS39758D-page 38  2009 Microchip Technology Inc.

PIC18F1230/1330

External Reset

MCLR

VDD

OSC1

WDT

Time-out

V

DD Rise

Detect

OST/PWRT

INTRC

(1)

POR Pulse

OST

10-Bit Ripple Counter

PWRT

11-Bit Ripple Counter

Enable OST

(2)

Enable PWRT

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

2: See Table 5-2 for time-out situations.

Brown-out

Reset

BOREN

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

Sleep

( )_IDLE

1024 Cycles

65.5 ms

32 s

MCLRE

S

R

Q

Chip_Reset

5.0 RESET

A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.

The PIC18F1230/1330 devices differentiate between
various kinds of Reset:

a) Power-on Reset (POR)
b) MCLR

Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during

execution)

e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset

This section discusses Resets generated by MCLR
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in

Section 6.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 20.2 “Watchdog

,

5.1 RCON Register

Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in

Section 5.6 “Reset State of Registers”.

The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in

Section 11.0 “Interrupts”. BOR is covered in
Section 5.4 “Brown-out Reset (BOR)”.

Timer (WDT)”.

FIGURE 5-1: SI MPLI FIED B LOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

 2009 Microchip Technology Inc. DS39758D-page 39

PIC18F1230/1330

REGISTER 5-1: RCON: RESET CONTROL REGISTER

R/W-0 R/W-1

IPEN SBOREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit

If BOREN1:BOREN0 =

1 = BOR is enabled
0 = BOR is disabled

If BOREN1:BOREN0 =
Bit is disabled and read as ‘0’.

bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

bit 2 PD

1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction

bit 1 POR

1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR

1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

(1)

Brown-out Reset occurs)

: Power-Down Detection Flag bit

: Power-on Reset Status bit

: Brown-out Reset Status bit

U-0 R/W-1 R-1 R-1 R/W-0

—RITO PD POR BOR

01:

00, 10 or 11:

(2)

(1)

(2)

R/W-0

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR

register and Section 5.6 “Reset State of Registers” for additional information.

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent

Power-on Resets may be detected.

2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to

‘1’ by software immediately after a Power-on Reset).

DS39758D-page 40  2009 Microchip Technology Inc.

is determined by the type of device Reset. See the notes following this

PIC18F1230/1330

Note 1: External Power-on Reset circuit is required

only if the V

DD power-up slope is too slow.

The diode D helps discharge the capacitor
quickly when V

DD powers down.

2: R < 40 k is recommended to make sure that

the voltage drop across R does not violate
the device’s electrical specification.

3: R1  1 k will limit any current flowing into

MCLR

from external capacitor C, in the event

of MCLR

/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).

C

R1

R

D

V

DD

MCLR

PIC18FXXXX

VDD

5.2 Master Clear (MCLR)

The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR

Reset path which detects and ignores small

pulses.

The MCLR

pin is not driven low by any internal Resets,

including the WDT.

In PIC18F1230/1330 devices, the MCLR

input can be
disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin becomes a digital input. See

Section 10.1 “PORTA, TRISA and LATA Registers”

for more information.

5.3 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
VDD is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for

DD is specified (parameter D004). For a slow rise

V
time, see Figure 5-2.

When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.

Power-on Reset events are captured by the POR
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR
ware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.

DD rises above a certain threshold. This

bit

is not reset to ‘1’ by any hard-

FIGURE 5-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR
SLOW V

DD POWER-UP)

 2009 Microchip Technology Inc. DS39758D-page 41

PIC18F1230/1330

5.4 Brown-out Reset (BOR)

PIC18F1230/1330 devices implement a BOR circuit that
provides the user with a number of configuration and
power-saving options. The BOR is controlled by the
BORV1:BORV0 and BOREN1:BOREN0 Configuration
bits. There are a total of four BOR configurations which
are summarized in Table 5-1.

The BOR threshold is set by the BORV1:BORV0 bits.
If BOR is enabled (any values of BOREN1:BOREN0
except ‘00’), any drop of V
D005) for greater than T
the device. A Reset may or may not occur if V
below V
Brown-out Reset until V

If the Power-up Timer is enabled, it will be invoked after
V
Reset for an additional time delay, T
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay.

BOR and the Power-on Timer (PWRT) are
independently configured. Enabling Brown-out Reset
does not automatically enable the PWRT.

BOR for less than TBOR. The chip will remain in

DD rises above VBOR; it then will keep the chip in

DD rises above VBOR, the Power-up

5.4.1 SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.

Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to

DD below VBOR (parameter

BOR (parameter 35) will reset

DD falls

DD rises above VBOR.

PWRT

change BOR configuration. It also allows the user to
tailor device power consumption in software by
eliminating the incremental current that the BOR
consumes. While the BOR current is typically very
small, it may have some impact in low-power
applications.

Note: Even when BOR is under software control,

the Brown-out Reset voltage level is still
set by the BORV1:BORV0 Configuration
bits. It cannot be changed in software.

5.4.2 DETECTING BOR

When Brown-out Reset is enabled, the BOR bit always
resets to ‘0’ on any Brown-out Reset or Power-on
Reset event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR
simultaneously check the state of both POR
This assumes that the POR
immediately after any Power-on Reset event. If BOR
‘0’ while POR
Brown-out Reset event has occurred.

alone. A more reliable method is to

and BOR.

bit is reset to ‘1’ in software

is

is ‘1’, it can be reliably assumed that a

5.4.3 DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.

This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.

TABLE 5-1: BOR CONFIGURATIONS

BOR Configuration Status of

BOREN1 BOREN0

00Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
01Available BOR enabled in software; operation controlled by SBOREN.
10Unavailable BOR enabled in hardware in Run and Idle modes, disabled during

11Unavailable BOR enabled in hardware; must be disabled by reprogramming the

DS39758D-page 42  2009 Microchip Technology Inc.

SBOREN

(RCON<6>)

Sleep mode.

Configuration bits.

BOR Operation

PIC18F1230/1330

5.5 Device Reset Timers

PIC18F1230/1330 devices incorporate three separate
on-chip timers that help regulate the Power-on Reset
process. Their main function is to ensure that the device
clock is stable before code is executed. These timers
are:

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• PLL Lock Time-out

5.5.1 POWER-UP TIMER (PWRT)

The Power-up Timer (PWRT) of PIC18F1230/1330
devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 s = 65.6 ms. While the
PWRT is counting, the device is held in Reset.

The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 for details.

The PWRT is enabled by clearing the PWRTEN
Configuration bit.

5.5.2 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.

The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power-managed modes.

5.5.3 PLL LOCK TIME-OUT

With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
the oscillator start-up time-out.

PLL) is typically 2 ms and follows

5.5.4 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

1. After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).

2. Then, the OST is activated.

The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 5-3,
Figure 5-4, Figure 5-5, Figure 5-6 and Figure 5-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 5-3 through 5-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, there will be no
time-out at all.

Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
Bringing MCLR
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.

high will begin execution immediately

TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Configuration

HSPLL 66 ms

HS, XT, LP 66 ms

EC, ECIO 66 ms

RC, RCIO 66 ms

INTIO1, INTIO2 66 ms

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the PLL to lock.

 2009 Microchip Technology Inc. DS39758D-page 43

(1)

Power-up

PWRTEN

+ 1024 TOSC + 2 ms

(1)

+ 1024 TOSC 1024 TOSC 1024 TOSC

(2)

and Brown-out Reset

= 0 PWRTEN = 1

(2)

(1)
(1)
(1)

1024 TOSC + 2 ms

——

——

——

(2)

Exit from

Power-Managed Mode

1024 TOSC + 2 ms

(2)

PIC18F1230/1330

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR

FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR

NOT TIED TO VDD): CASE 1

NOT TIED TO VDD): CASE 2

DS39758D-page 44  2009 Microchip Technology Inc.

PIC18F1230/1330

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

0V

5V

T

PWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 clock cycles.

T

PLL  2 ms max. First three stages of the PWRT timer.

FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR

TIED TO VDD)

 2009 Microchip Technology Inc. DS39758D-page 45

PIC18F1230/1330

5.6 Reset State of Registers

Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other

Table 5-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.

Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper­ation. Status bits from the RCON register, RI
POR

and BOR, are set or cleared differently in different

, TO, PD,

Reset situations, as indicated in Table 5-3. These bits
are used in software to determine the nature of the
Reset.

TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

Condition

Program

Counter

SBOREN RI

Power-on Reset 0000h 1 11100 0 0
RESET Instruction 0000h u

Brown-out Reset 0000h u

during Power-Managed

MCLR

0000h u

(2)
(2)
(2)

Run Modes

MCLR during Power-Managed

0000h u

(2)

Idle Modes and Sleep Mode

WDT Time-out during Full Power

0000h u

(2)

or Power-Managed Run Mode

MCLR during Full Power

0000h u

(2)

Execution
Stack Full Reset (STVREN = 1) 0000h u

Stack Underflow Reset

0000h u

(2)
(2)

(STVREN = 1)

Stack Underflow Error (not an

0000h u

(2)

actual Reset, STVREN = 0)

WDT Time-out during

PC + 2 u

(2)

Power-Managed Idle or
Sleep Modes

Interrupt Exit from

PC + 2

(1)

(2)

u

Power-Managed Modes

Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the

interrupt vector (008h or 0018h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

RCON Register STKPTR Register

TO PD POR BOR STKFUL STKUNF

0uuuu u u
111u0 u u
u1uuu u u

u10uu u u

u0uuu u u

uuuuu u u

uuuuu 1 u
uuuuu u 1

uuuuu u 1

u00uu u u

uu0uu u u

DS39758D-page 46  2009 Microchip Technology Inc.

PIC18F1230/1330

TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Resets,

MCLR

Register

Applicable

Devices

Power-on Reset,

Brown-out Reset

TOSU 1230 1330 ---0 0000 ---0 0000 ---0 uuuu
TOSH 1230 1330 0000 0000 0000 0000 uuuu uuuu
TOSL 1230 1330 0000 0000 0000 0000 uuuu uuuu
STKPTR 1230 1330 00-0 0000 uu-0 0000 uu-u uuuu
PCLATU 1230 1330 ---0 0000 ---0 0000 ---u uuuu
PCLATH 1230 1330 0000 0000 0000 0000 uuuu uuuu
PCL 1230 1330 0000 0000 0000 0000 PC + 2
TBLPTRU 1230 1330 --00 0000 --00 0000 --uu uuuu
TBLPTRH 1230 1330 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 1230 1330 0000 0000 0000 0000 uuuu uuuu
TABLAT 1230 1330 0000 0000 0000 0000 uuuu uuuu
PRODH 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 1230 1330 0000 000x 0000 000u uuuu uuuu
INTCON2 1230 1330 1111 1111 1111 1111 uuuu uuuu
INTCON3 1230 1330 1100 0000 1100 0000 uuuu uuuu

INDF0 1230 1330 N/A N/A N/A

POSTINC0 1230 1330 N/A N/A N/A

POSTDEC0 1230 1330 N/A N/A N/A

PREINC0 1230 1330 N/A N/A N/A

PLUSW0 1230 1330 N/A N/A N/A
FSR0H 1230 1330 ---- 0000 ---- 0000 ---- uuuu
FSR0L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 1230 1330 N/A N/A N/A

POSTINC1 1230 1330 N/A N/A N/A

POSTDEC1 1230 1330 N/A N/A N/A

PREINC1 1230 1330 N/A N/A N/A

PLUSW1 1230 1330 N/A N/A N/A
FSR1H 1230 1330 ---- 0000 ---- 0000 ---- uuuu
FSR1L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 1230 1330 ---- 0000 ---- 0000 ---- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

(3)
(3)
(3)
(3)

(2)

(1)
(1)
(1)

 2009 Microchip Technology Inc. DS39758D-page 47

PIC18F1230/1330

TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets,

MCLR

Register

INDF2 1230 1330 N/A N/A N/A

POSTINC2 1230 1330 N/A N/A N/A

POSTDEC2 1230 1330 N/A N/A N/A

PREINC2 1230 1330 N/A N/A N/A

PLUSW2 1230 1330 N/A N/A N/A
FSR2H 1230 1330 ---- 0000 ---- 0000 ---- uuuu
FSR2L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 1230 1330 ---x xxxx ---u uuuu ---u uuuu
TMR0H 1230 1330 0000 0000 0000 0000 uuuu uuuu
TMR0L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 1230 1330 1111 1111 1111 1111 uuuu uuuu
OSCCON 1230 1330 0100 q000 0100 q000 uuuu uuqu
LVDCON 1230 1330 --00 0101 --00 0101 --uu uuuu
WDTCON 1230 1330 ---- ---0 ---- ---0 ---- ---u

(4)

RCON
TMR1H 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 1230 1330 0000 0000 u0uu uuuu uuuu uuuu
ADRESH 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1230 1330 0--- 0000 0--- 0000 u--- uuuu
ADCON1 1230 1330 ---0 1111 ---0 1111 ---u uuuu
ADCON2 1230 1330 0-00 0000 0-00 0000 u-uu uuuu
BAUDCON 1230 1330 01-00 0-00 01-00 0-00 uu-uu u-uu
CVRCON 1230 1330 0-00 0000 0-00 0000 u-uu uuuu
CMCON 1230 1330 000- -000 000- -000 uuu- -uuu
SPBRGH 1230 1330 0000 0000 0000 0000 uuuu uuuu
SPBRG 1230 1330 0000 0000 0000 0000 uuuu uuuu
RCREG 1230 1330 0000 0000 0000 0000 uuuu uuuu
TXREG 1230 1330 0000 0000 0000 0000 uuuu uuuu
TXSTA 1230 1330 0000 0010 0000 0010 uuuu uuuu
RCSTA 1230 1330 0000 000x 0000 000x uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.

Applicable

Devices

1230 1330 0q-1 11q0 0q-q qquu uq-u qquu

Power-on Reset,

Brown-out Reset

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

DS39758D-page 48  2009 Microchip Technology Inc.

PIC18F1230/1330

TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets,

MCLR

Register

Applicable

Devices

EEADR 1230 1330 0000 0000 0000 0000 uuuu uuuu
EEDATA 1230 1330 0000 0000 0000 0000 uuuu uuuu
EECON2 1230 1330 0000 0000 0000 0000 0000 0000
EECON1 1230 1330 xx-0 x000 uu-0 u000 uu-0 u000
IPR3 1230 1330 ---1 ---- ---1 ---- ---u ----
PIR3 1230 1330 ---0 ---- ---0 ---- ---u ----
PIE3 1230 1330 ---0 ---- ---0 ---- ---u ----
IPIR2 1230 1330 1--1 -1-- 1--1 -1-- u--u -u--
PIR2 1230 1330 0--0 -0-- 0--0 -0-- u--u -u--
PIE2 1230 1330 0--0 -0-- 0--0 -0-- u--u -u--
IPR1 1230 1330 -111 1111 -111 1111 -uuu uuuu
PIR1 1230 1330 -000 0000 -000 0000 -uuu uuuu
PIE1 1230 1330 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 1230 1330 00-0 0000 00-0 0000 uu-u uuuu
PTCON0 1230 1330 0000 0000 uuuu uuuu uuuu uuuu
PTCON1 1230 1330 00-- ---- 00-- ---- uu-- ----
PTMRL 1230 1330 0000 0000 0000 0000 uuuu uuuu
PTMRH 1230 1330 ---- 0000 ---- 0000 ---- uuuu
PTPERL 1230 1330 1111 1111 1111 1111 uuuu uuuu
PTPERH 1230 1330 ---- 1111 ---- 1111 ---- uuuu
TRISB 1230 1330 1111 1111 1111 1111 uuuu uuuu
TRISA 1230 1330 1111 1111
PDC0L 1230 1330 0000 0000 0000 0000 uuuu uuuu
PDC0H 1230 1330 --00 0000 --00 0000 --uu uuuu
PDC1L 1230 1330 0000 0000 0000 0000 uuuu uuuu
PDC1H 1230 1330 --00 0000 --00 0000 --uu uuuu
PDC2L 1230 1330 0000 0000 0000 0000 uuuu uuuu
PDC2H 1230 1330 --00 0000 --00 0000 --uu uuuu
FLTCONFIG 1230 1330 0--- -000 0--- -000 u--- -uuu
LATB 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
LATA 1230 1330 xxxx xxxx
SEVTCMPL 1230 1330 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.

Power-on Reset,

Brown-out Reset

(5)

(5)

WDT Reset,

RESET Instruction,

Stack Resets

1111 1111

uuuu uuuu

(5)

(5)

Wake-up via WDT

or Interrupt

uuuu uuuu

uuuu uuuu

(1)

(1)

(5)

(5)

 2009 Microchip Technology Inc. DS39758D-page 49

PIC18F1230/1330

TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets,

MCLR

Register

Applicable

Devices

SEVTCMPH 1230 1330 ---- 0000 ---- 0000 ---- uuuu
PWMCON0 1230 1330 -100 -000

PWMCON1 1230 1330 0000 0-00 0000 0-00 uuuu u-uu
DTCON 1230 1330 0000 0000 0000 0000 uuuu uuuu
OVDCOND 1230 1330 --11 1111 --11 1111 --uu uuuu
OVDCONS 1230 1330 --00 0000 --00 0000 --uu uuuu
PORTB 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 1230 1330 xx0x xxxx

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.

Power-on Reset,

Brown-out Reset

(6)

-000 -000

(6)

(5)

WDT Reset,

RESET Instruction,

Stack Resets

-100 -000

-000 -000

uu0u uuuu

(6)
(6)

(5)

Wake-up via WDT

or Interrupt

-uuu -uuu

-uuu -uuu

uuuu uuuu

(6)
(6)

(5)

DS39758D-page 50  2009 Microchip Technology Inc.

PIC18F1230/1330

PC<20:0>

Stack Level 1



Stack Level 31

Reset Vector

Low-Priority Interrupt Vector




CALL,RCALL,RETURN
RETFIE,RETLW

21

0000h

0018h

On-Chip

Program Memory

High-Priority Interrupt Vector

0008h

User Memory Space

1FFFFFh

1000h

0FFFh

Read ‘0’

200000h

PC<20:0>

Stack Level 1



Stack Level 31

Reset Vector

Low-Priority Interrupt Vector




CALL,RCALL,RETURN
RETFIE,RETLW

21

0000h

0018h

2000h

1FFFh

On-Chip

Program Memory

High-Priority Interrupt Vector

0008h

User Memory Space

Read ‘0’

1FFFFFh
200000h

PIC18F1230

PIC18F1330

6.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 Enhanced
microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.

Additional detailed information on the operation of the

Flash program memory is provided in Section 7.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 8.0 “Data EEPROM

6.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).

The PIC18F1230 has 4 Kbytes of Flash memory and
can store up to 2,048 single-word instructions. The
PIC18F1330 has 8 Kbytes of Flash memory and can
store up to 4,096 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.

The program memory maps for PIC18F1230 and
PIC18F1330 devices are shown in Figure 6-1.

Memory”.

FIGURE 6-1: PROGRAM MEMORY MAP AND ST AC K F OR PIC18F1230/ 1330 D EVICES

 2009 Microchip Technology Inc. DS39758D-page 51

PIC18F1230/1330

00011

001A34h

11111
11110
11101

00010
00001
00000

00010

Return Address Stack <20:0>

To p- o f -S ta c k

000D58h

STKPTR<4:0>

T op -of-Stack Registers Stack Pointer

TOSLTOSHTOSU

34h1Ah00h

6.1.1 PROGRAM COUNTER

The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.

The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes to
the PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads the PCL. This is useful for

computed offsets to the PC (see Section 6.1.4.1
“Computed GOTO”).

The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.

6.1.2 RETURN ADDRESS STACK

The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.

The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of­Stack Special Function Registers. Data can also be
pushed to, or popped from the stack, using these
registers.

A CALL type instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.

6.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack
location pointed to by the STKPTR register (Figure 6-2).
This allows users to implement a software stack if
necessary. After a CALL, RCALL or interrupt, the
software can read the pushed value by reading the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.

FIGURE 6-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

DS39758D-page 52  2009 Microchip Technology Inc.

PIC18F1230/1330

6.1.2.2 Return Stack Pointer (STKPTR)

The STKPTR register (Register 6-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.

After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.

The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack
Overflow Reset Enable) Configuration bit. (Refer to

Section 20.1 “Configuration Bit s” for a description of

the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.

When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.

6.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu­tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.

The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.

The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.

REGISTER 6-1: STKPTR: STACK POINTER REGISTER

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit

bit 6 STKUNF: Stack Underflow Flag bit

bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

(1)

STKUNF

1 = Stack became full or overflowed
0 = Stack has not become full or overflowed

1 = Stack underflow occurred
0 = Stack underflow did not occur

(1)

— SP4 SP3 SP2 SP1 SP0

(1)

(1)

 2009 Microchip Technology Inc. DS39758D-page 53

PIC18F1230/1330

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER
;STACK




SUB1 



RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE
ORG nn00h
TABLE ADDWF PCL

RETLW nnh

RETLW nnh

RETLW nnh

.

.

.

6.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bit is cleared
by the user software or a Power-on Reset.

6.1.3 FAST REGISTER STACK

A Fast Register Stack is provided for the STATUS,
WREG and BSR registers, to provide a “fast return”
option for interrupts. The stack for each register is only
one level deep and is neither readable nor writable. It is
loaded with the current value of the corresponding
register when the processor vectors for an interrupt. All
interrupt sources will push values into the Stack
registers. The values in the registers are then loaded
back into their associated registers if the
RETFIE, FAST instruction is used to return from the
interrupt.

If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack regis­ter values stored by the low-priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.

If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR regis­ters at the end of a subroutine call. To use the Fast
Register Stack for a subroutine call, a CALL
label, FAST instruction must be executed to save the
STATUS, WREG and BSR registers to the Fast Regis­ter Stack. A RETURN, FAST instruction is then exe­cuted to restore these registers from the Fast Register
Stack.

Example 6-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.

EXAMPLE 6-1: FAST REGISTER STACK

CODE EXAMPLE

DS39758D-page 54  2009 Microchip Technology Inc.

6.1.4 LOOK-UP TABLES IN PROGRAM MEMORY

There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:

• Computed GOTO

• Table Reads

6.1.4.1 Computed GOTO

A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 6-2.

A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.

The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.

EXAMPLE 6-2: COMPUTED GOTO USING

AN OFFSET VALUE

6.1.4.2 Table Reads and Table Writes

A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.

Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the data that is read from or written to program
memory. Data is transferred to or from program
memory one byte at a time.

Table read and table write operations are discussed

further in Section 7.1 “Table Reads and Table

Writes”.

PIC18F1230/1330

Q1

Q2 Q3 Q4

Q1

Q2 Q3 Q4

Q1

Q2 Q3 Q4

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKO

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal
Phase
Clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. BRA SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP)

Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

6.2 PIC18 Instruction Cycle

6.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruc­tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 6-3.

FIGURE 6-3: CLOCK/INSTRUCTION CYCLE

6.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 6-3).

A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.

In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).

EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW

 2009 Microchip Technology Inc. DS39758D-page 55

PIC18F1230/1330

Word Address

LSB = 1 LSB = 0 

Program Memory
Byte Locations



000000h
000002h
000004h
000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h
000014h

6.2.3 INSTRUCTIONS IN PROGRAM MEMORY

The program memory is addressed in bytes.
Instructions are stored as two bytes or four bytes in
program memory. The Least Significant Byte of an
instruction word is always stored in a program memory
location with an even address (LSb = 0). To maintain
alignment with instruction boundaries, the PC
increments in steps of 2 and the LSb will always read

‘0’ (see Section 6.1.1 “Program Counter”).

Figure 6-4 shows an example of how instruction words
are stored in the program memory.

The CALL and GOTO instructions have the absolute
program memory address embedded into the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 6-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 22.0 “Instruction Set Summary”
provides further details of the instruction set.

FIGURE 6-4: INS TRUCTIONS IN PROGRAM MEMORY

6.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed

and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.

Note: See Section 6.6 “PIC18 Instruction

Execution and the Extended Instruc­tion Set” for information on two-word

instructions in the extended instruction set.

EXAMPLE 6-4: TWO-WORD INSTRUCTIONS

CASE 1:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code

DS39758D-page 56  2009 Microchip Technology Inc.

PIC18F1230/1330

6.3 Data Memory Organization

Note: The operation of some aspects of data

memory are changed when the PIC18
extended instruction set is enabled. See

Section 6.5 “Data Memory and the
Extended Instruction Set” for more

information.

The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each; PIC18F1230/
1330 devices implement 1 bank. Figure 6-5 shows the
data memory organization for the PIC18F1230/1330
devices.

The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.

The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.

To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the

BSR. Section 6.3.2 “Access Bank” provides a

detailed description of the Access RAM.

6.3.1 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is
accomplished with a RAM banking scheme. This
divides the memory space into 16 contiguous banks of
256 bytes. Depending on the instruction, each location
can be addressed directly by its full 12-bit address, or
an 8-bit low-order address and a 4-bit Bank Pointer.

Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the four Most Significant bits of
a location’s address; the instruction itself includes the
eight Least Significant bits. Only the four lower bits of
the BSR are implemented (BSR3:BSR0). The upper
four bits are unused; they will always read ‘0’ and can­not be written to. The BSR can be loaded directly by
using the MOVLB instruction.

The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 6-6.

Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h, while the BSR
is 0Fh, will end up resetting the program counter.

While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 6-5 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.

 2009 Microchip Technology Inc. DS39758D-page 57

PIC18F1230/1330

Bank 0

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 1111

080h

07Fh

F80h
FFFh

00h

7Fh

80h

FFh

Access Bank

When a = 0:

The BSR is ignored and the
Access Bank is used.

The first 128 bytes are
general purpose RAM
(from Bank 0).

The second 128 bytes are
Special Function Registers
(from Bank 15).

When a = 1:

The BSR specifies the Bank
used by the instruction.

F7Fh

F00h

EFFh

0FFh

000h

Access RAM

FFh

00h

FFh

00h

GPR

SFR

Access RAM High

Access RAM Low

Bank 1

(SFRs)

= 0001

= 1110

Unused

Read ‘00h’

to

Unused

Read ‘00h’

FIGURE 6-5: DATA MEMORY MAP FOR PIC18F1230/1330 DEVICES

DS39758D-page 58  2009 Microchip Technology Inc.

PIC18F1230/1330

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data

Memory

Bank Select

(2)

7

0

From Opcode

(2)

0000

000h

100h

F00h

E00h

FFFh

Bank 0

Bank 14

Bank 15

00h

FFh
00h

00h

FFh
00h

FFh

FFh

Bank 1

through

Bank 13

0000

11111111

7

0

BSR

(1)

FIGURE 6-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

6.3.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.

To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 128 bytes of
memory (00h-7Fh) in Bank 0 and the last 128 bytes of
memory (80h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 6-5).

The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.

Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 80h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 80h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.

The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail

in Section 6.5.3 “Mapping the Access Bank in
Indexed Literal Offset Addressing Mode”.

6.3.3 GENERAL PURPOSE REGISTER FILE

PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.

 2009 Microchip Technology Inc. DS39758D-page 59

PIC18F1230/1330

6.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 6-1 and Table 6-2.

The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of a peripheral feature
are described in the chapter for that peripheral.

The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.

TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F1230/1330 DEVICES

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2

FFEh TOSH FDEh POSTINC2

FFDh TOSL FDDh POSTDEC2

FFCh STKPTR FDCh PREINC2

FFBh PCLATU FDBh PLUSW2

(1)

FBFh —

(1)

(1)

(1)

(1)

FBEh —

FBDh —

FBCh —

FBBh —

FFAh PCLATH FDAh FSR2H FBAh —

FF9h PCL FD9h FSR2L FB9h

FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h PTMRL

FF7h TBLPTRH FD7h TMR0H FB7h —

FF6h TBLPTRL FD6h TMR0L FB6h

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h PTPERH

FF4h PRODH FD4h —

(2)

FB4h CMCON F94h —

FF3h PRODL FD3h OSCCON FB3h —

FF2h INTCON FD2h LVDCON FB2h —

FF1h INTCON2 FD1h WDTCON FB1h —

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h PDC0H

(1)

FEFh INDF0

FEEh POSTINC0

FEDh POSTDEC0

FECh PREINC0

FEBh PLUSW0

FEAh FSR0H FCAh

FE9h FSR0L FC9h —

FE8h WREG FC8h

FE7h INDF1

FE6h POSTINC1

FE5h POSTDEC1

FE4h PREINC1

FE3h PLUSW1

FCFh TMR1H FAFh SPBRG F8Fh PDC1L

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

FCEh TMR1L FAEh RCREG F8Eh PDC1H

FCDh T1CON FADh TXREG F8Dh PDC2L

—

—

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

FACh TXSTA F8Ch PDC2H

FABh RCSTA F8Bh FLTCONFIG

FAAh —

FA9h EEADR F89h LATA

FA8h EEDATA F88h SEVTCMPL

FA7h EECON2

FA6h EECON1 F86h PWMCON0

FA5h IPR3 F85h PWMCON1

FCCh —

FCBh —

FC7h —

FC6h —

FC5h —

FC4h ADRESH FA4h PIR3 F84h DTCON

FC3h ADRESL FA3h PIE3 F83h OVDCOND

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h OVDCONS

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

—

—

(2)
(2)
(2)
(2)
(2)
(2)
(2)

(2)
(2)

(2)
(2)
(2)

(2)

(1)

F9Fh IPR1

F9Eh PIR1

F9Dh PIE1

F9Ch —

F9Bh OSCTUNE

F9Ah PTCON0

F99h PTCON1

F97h PTMRH

F96h PTPERL

F93h TRISB

F92h TRISA

F91h PDC0L

F8Ah LATB

F87h SEVTCMPH

(2)

(2)

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

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PIC18F1230/1330

TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TOSU
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 47, 52
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 47, 52

STKPTR STKFUL

PCLATU
PCLATH Holding Register for PC<15:8> 0000 0000 47, 52
PCL PC Low Byte (PC<7:0>) 0000 0000 47, 52

TBLPTRU
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 47, 74
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 47, 74
TABLAT Program Memory Table Latch 0000 0000 47, 74
PRODH Product Register High Byte xxxx xxxx 47, 85
PRODL Product Register Low Byte xxxx xxxx 47, 85
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 47, 95

INTCON2 RBPU
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 47, 97

INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 47, 66

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 47, 66

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 47, 66

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 47, 66

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

FSR0H
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 47, 66
WREG Working Register xxxx xxxx 47, 54

INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 47, 66

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 47, 66

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 47, 66

PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 47, 66

PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –

FSR1H
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 47, 66

BSR

INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 48, 66

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 48, 66

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 48, 66

PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 48, 66

PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

FSR2H
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 48, 66

— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 47, 52

(5)

— — — Holding Register for PC<20:16> ---0 0000 47, 52

— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 47, 74

value of FSR0 offset by W

— — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 47, 66

value of FSR1 offset by W

— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 47, 66

— — — — Bank Select Register ---- 0000 47, 57

value of FSR2 offset by W

— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 48, 66

(5)

STKUNF

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 47, 96

— SP4 SP3 SP2 SP1 SP0 00-0 0000 47, 53

Value on

POR, BOR

N/A 47, 66

N/A 47, 66

N/A 48, 66

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads

as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.

2: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See

Section 3.6.4 “PLL in INTOSC Modes”.

3: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as

‘0’. This bit is read-only.

4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

5: Bit 7 and bit 6 are cleared by user software or by a POR.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.

7: This bit has no effect if the Configuration bit, WDTEN, is enabled.

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PIC18F1230/1330

TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STATUS — — —NOVZ DCC---x xxxx 48, 64
TMR0H Timer0 Register High Byte 0000 0000 48, 109
TMR0L Timer0 Register Low Byte xxxx xxxx 48, 109
T0CON TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 48, 107
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 48, 28

LVDCON

WDTCON

RCON IPEN SBOREN
TMR1H Timer1 Register High Byte xxxx xxxx 48, 115
TMR1L Timer1 Register Low Byte xxxx xxxx 48, 115

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
ADRESH A/D Result Register High Byte xxxx xxxx 48, 178
ADRESL A/D Result Register Low Byte xxxx xxxx 48, 178

ADCON0 SEVTEN

ADCON1

ADCON2 ADFM

BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16

CVRCON CVREN

CMCON C2OUT C1OUT C0OUT
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 48, 152
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 48, 152
RCREG EUSART Receive Register 0000 0000 48, 160
TXREG EUSART Transmit Register 0000 0000 48, 157
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 48, 148
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 48, 149
EEADR EEPROM Address Register 0000 0000 49, 81
EEDATA EEPROM Data Register 0000 0000 49, 81
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 49, 72

EECON1 EEPGD CFGS

IPR3

PIR3

PIE3

IPR2 OSCFIP

PIR2 OSCFIF

PIE2 OSCFIE

IPR1

PIR1

PIE1

OSCTUNE INTSRC PLLEN
PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 49, 122

PTCON1 PTEN PTDIR

— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 48, 187

— — — — — — —SWDTEN

(1)

—RITO PD POR BOR 0q-1 11q0 48, 40

TMR1CS TMR1ON 0000 0000 48, 111

— — — CHS1 CHS0 GO/DONE ADON 0--- 0000 48, 169

— — — VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 ---0 1111 48, 170

— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 48, 171

— WUE ABDEN 01-0 00-00 48, 150

— CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0-00 0000 48, 184

— — CMEN2 CMEN1 CMEN0 000- -000 48, 179

— FREE WRERR WREN WR RD xx-0 x000 48, 73
— — —PTIP— — — — ---1 ---- 49, 103
— — —PTIF— — — — ---0 ---- 49, 99
— — —PTIE— — — — ---0 ---- 49, 101

— — EEIP —LVDIP — — 1--1 -1-- 49, 103
— —EEIF—LVDIF — — 0--0 -0-- 49, 99

— — EEIE —LVDIE — — 0--0 -0-- 49, 101
— ADIP RCIP TXIP CMP2IP CMP1IP CMP0IP TMR1IP -111 1111 49, 102
— ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF -000 0000 49, 98
— ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE -000 0000 49, 100

(2)

— TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 49, 25

— — — — — — 00-- ---- 49, 122

Value on

POR, BOR

(7)

---- ---0 48, 203

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads

as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.

2: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See

Section 3.6.4 “PLL in INTOSC Modes”.

3: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as

‘0’. This bit is read-only.

4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

5: Bit 7 and bit 6 are cleared by user software or by a POR.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
7: This bit has no effect if the Configuration bit, WDTEN, is enabled.

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PIC18F1230/1330

TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PTMRL PWM Time Base Register (lower 8 bits) 0000 0000 49, 125

PTMRH
PTPERL PWM Time Base Period Register (lower 8 bits) 1111 1111 49, 125

PTPERH
TRISB PORTB Data Direction Control Register 1111 1111 49, 90

TRISA TRISA7
PDC0L PWM Duty Cycle #0L Register (lower 8 bits) 0000 0000 49, 131

PDC0H
PDC1L PWM Duty Cycle #1L Register (lower 8 bits) 0000 0000 49, 131

PDC1H
PDC2L PWM Duty Cycle #2L Register (lower 8 bits) 0000 0000 49, 131

PDC2H

FLTCONFIG BRFEN
LATB PORTB Output Latch Register (Read and Write to Data Latch) xxxx xxxx 49, 90

LATA LATA7
SEVTCMPL PWM Special Event Compare Register (lower 8 bits) 0000 0000 49, 144

SEVTCMPH

PWMCON0

PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR
DTCON DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 0000 0000 50, 136

OVDCOND

OVDCONS
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 50, 90

PORTA RA7

— — — — PWM Time Base Register (upper 4 bits) ---- 0000 49, 125

— — — — PWM Time Base Period Register (upper 4 bits) ---- 1111 49, 125

(4)

— — PWM Duty Cycle #0H Register (upper 6 bits) --00 0000 49, 131

— — PWM Duty Cycle #1H Register (upper 6 bits) --00 0000 49, 131

— — PWM Duty Cycle #2H Register (upper 6 bits) --00 0000 49, 131

(4)

— — — — PWM Special Event Compare Register (upper 4 bits) ---- 0000 50, 144

—PWMEN2

— — POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 --11 1111 50, 140
— — POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 --00 0000 50, 140

(4)

(4)

TRISA6

LATA6

RA6

PORTA Data Direction Control Register 1111 1111 49, 87

— — — — FLTAS FLTAMOD FLTAEN 0--- -000 49, 143

(4)

PORTA Output Latch Register (Read and Write to Data Latch) xxxx xxxx 49, 87

(4)

(6)

PWMEN1

RA5

(3)

(6)

PWMEN0

(6)

— PMOD2 PMOD1 PMOD0 -100 -000 50, 123

— UDIS OSYNC 0000 0-00 50, 124

RA4 RA3 RA2 RA1 RA0 xx0x xxxx 50, 87

Value on

POR, BOR

-000 -000

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads

as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.

2: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See

Section 3.6.4 “PLL in INTOSC Modes”.

3: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as

‘0’. This bit is read-only.

4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

5: Bit 7 and bit 6 are cleared by user software or by a POR.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.

7: This bit has no effect if the Configuration bit, WDTEN, is enabled.

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 2009 Microchip Technology Inc. DS39758D-page 63

PIC18F1230/1330

6.3.5 STATUS REGISTER

The STATUS register, shown in Register 6-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.

If the STATUS register is the destination for an instruc­tion that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the STATUS
register is updated according to the instruction
performed. Therefore, the result of an instruction with
the STATUS register as its destination may be different
than intended. As an example, CLRF STATUS will set
the Z bit and leave the remaining Status bits
unchanged (‘000u u1uu’).

It is recommended that only BCF, BSF, SWAPF , MOVFF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.

For other instructions that do not affect Status bits, see
the instruction set summaries in Table 22-2 and
Table 22-3.

Note: The C and DC bits operate as the borrow

and digit borrow bits, respectively, in
subtraction.

REGISTER 6-2: STATUS REGI STER

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOV ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

(2)

C

bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).

1 = Result was negative
0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7 of the result) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

(2)

(1)

bit

bit 1 DC: Digit Carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.

2: For borrow

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.

, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

bit

DS39758D-page 64  2009 Microchip Technology Inc.

PIC18F1230/1330

LFSR FSR0, 00h ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then
; inc pointer

BTFSS FSR0H, 0 ; All done with

; Bank0?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

6.4 Data Addressing Modes

Note: The execution of some instructions in the

core PIC18 instruction set are changed
when the PIC18 extended instruction set is

enabled. See Section 6.5 “Data Memory
and the Extended Instruction Set” for

more information.

The data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect

An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is

discussed in greater detail in Section 6.5.1 “Indexed
Addressing with Literal Offset”.

6.4.1 INHERENT AND LITERAL ADDRESSING

Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.

Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.

6.4.2 DIRECT ADDRESSING

Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and byte­oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in

one of the banks of data RAM (Sectio n 6.3.3 “Gener al
Purpose Register File”) or a location in the Access
Bank (Section 6.3.2 “Access Bank”) as the data

source for the instruction.

 2009 Microchip Technology Inc. DS39758D-page 65

The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR

(Section 6.3.1 “Bank Select Register (BSR)”) are

used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.

The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its
original contents. When ‘d’ is ‘0’, the results are stored
in the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.

6.4.3 INDIRECT ADDRESSING

Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory.

The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 6-5.

EXAMPLE 6-5: HOW TO CLEAR RAM

(BANK 0) USING
INDIRECT ADDRESSING

PIC18F1230/1330

FSR1H:FSR1L

0

7

Data Memory

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

Bank 3

through

Bank 13

ADDWF, INDF1, 1

07

Using an instruction with one of the
indirect addressing registers as the

operand....

...uses the 12-bit address stored in
the FSR pair associated with that

register....

...to determine the data memory
location to be used in that operation.

In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.

xxxx1110 11001100

6.4.3.1 FSR Registers and the
INDF Operand

At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.

Indirect Addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.

Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.

6.4.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:

• POSTDEC: accesses the FSR value, then

automatically decrements it by 1 afterwards

• POSTINC: accesses the FSR value, then

automatically increments it by 1 afterwards

• PREINC: increments the FSR value by 1, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses
the new value in the operation.

In this context, accessing an INDF register uses the
value in the FSR registers without changing them. Sim­ilarly, accessing a PLUSW register gives the FSR value
offset by that in the W register; neither value is actually
changed in the operation. Accessing the other virtual
registers changes the value of the FSR registers.

Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll­overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).

FIGURE 6-7: INDIR ECT ADDRESSI NG

DS39758D-page 66  2009 Microchip Technology Inc.

PIC18F1230/1330

The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.

6.4.3.3 Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.

On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.

Similarly, operations by Indirect Addressing are gener­ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.

6.5 Data Memory and the Extended Instruction Set

Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different; this is due to the introduction of
a new addressing mode for the data memory space.

What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.

6.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET

Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions – can
invoke a form of Indexed Addressing using an offset
specified in the instruction. This special addressing
mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this
addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0);

and

• The file address argument is less than or equal to

5Fh.

Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing), or
as an 8-bit address in the Access Bank. Instead, the
value is interpreted as an offset value to an Address
Pointer, specified by FSR2. The offset and the contents
of FSR2 are added to obtain the target address of the
operation.

6.5.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 6-8.

Those who desire to use bit-oriented or byte-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.

This is described in more detail in Section 22.2.1
“Extended Instruction Syntax”.

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PIC18F1230/1330

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When ‘a’ = 0 and f  60h:

The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations 060h to 07Fh
(Bank 0) and F80h to FFFh
(Bank 15) of data memory.

Locations below 60h are not
available in this addressing
mode.

When ‘a’ = 0 and f5Fh:

The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.

Note that in this mode, the
correct syntax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

When ‘a’ = 1 (all values of f):

The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.

000h

060h

100h

F00h

F80h

FFFh

Valid range

00h

60h
80h

FFh

Data Memory

Access RAM

Bank 0

Bank 1
through

Bank 14

Bank 15

SFRs

000h

080h

100h

F00h

F80h

FFFh

Data Memory

Bank 0

Bank 1
through

Bank 14

Bank 15

SFRs

FSR2H FSR2L

ffffffff001001da

ffffffff001001da

000h

080h

100h

F00h

F80h

FFFh

Data Memory

Bank 0

Bank 1
through

Bank 14

Bank 15

SFRs

for ‘f’

BSR

00000000

080h

FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

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PIC18F1230/1330

Data Memory

000h

100h

F80h

F00h

FFFh

Bank 0

Bank 15

Bank 1

through

Bank 14

SFRs

05Fh

ADDWF f, d, a

FSR2H:FSR2L = 090h

Locations in the region
from the FSR2 Pointer
(090h) to the pointer plus
05Fh (0EFh) are mapped
to the bottom of the
Access RAM (000h-05Fh).

Locations in Bank 0 from
060h to 07Fh are mapped,
as usual, to the middle of
the Access Bank.

Special Function Regis­ters at F80h through FFFh
are mapped to 80h
through FFh, as usual.

Bank 0 addresses below
5Fh can still be addressed
by using the BSR.

Access Bank

00h

80h

FFh

7Fh

SFRs

Bank 0 “Window”

Bank 0

Bank 0

Window

Example Situation:

07Fh
090h

0EFh

5Fh

6.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET ADDRESSING MODE

The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user-defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2

Remapping of the Access Bank applies only to

operations using the Indexed Literal Offset Addressing
mode. Operations that use the BSR (Access RAM bit is
‘1’) will continue to use Direct Addressing as before.

6.6 PIC18 Instruction Execution and the Extended Instruction Set

Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in

Section 22.2 “Extended Instruction Set”.

plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see

Section 6.3.2 “Access Ban k”). An example of Access

Bank remapping in this addressing mode is shown in
Figure 6-9.

FIGURE 6-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET

ADDRESSING MODE

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Table Pointer

(1)

Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL

TABL AT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer register points to a byte in program memory.

Program Memory
(TBLPTR)

7.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and
erasable during normal operation over the entire V
range.

A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.

Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.

A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.

DD

7.1 Table Reads and Table Writes

In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).

Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 7-1 shows the operation of a table read with
program memory and data RAM.

Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers

into program memory is detailed in Section 7.5 “Writin g
to Flash Program Memory”. Figure 7-2 shows the

operation of a table write with program memory and data
RAM.

Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.

FIGURE 7-1: TABLE READ OPERATION

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PIC18F1230/1330

Table Pointer

(1)

Table Latch (8-bit)

TBLPTRH TBLPTRL

TABL AT

Program Memory
(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of 8 holding registers, the address of which is determined by

TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.

Holding Registers

Program Memory

FIGURE 7-2: TABLE WRITE OPERATION

7.2 Control Registers

Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

7.2.1 EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.

The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.

The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on Configuration

registers regardless of EEPGD (see Section 20.0
“Special Featur es of the CPU”). When clear, memory

selection access is determined by EEPGD.

The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.

Note: During normal operation, the WRERR

may read as ‘1’. This can indicate that a
write operation was prematurely termi­nated by a Reset, or a write operation was
attempted improperly.

The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be
cleared in software.

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REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory
0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write-only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

(1)

WREN WR RD

(1)

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

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21 16 15 87 0

TABLE ERASE

TABLE WRITE

TABLE READ – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

TBLPTR<21:3>

TBLPTR<21:6>

7.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.

7.2.3 TBLPTR – TABLE POINTER REGISTER

The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte,
Table Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three
registers join to form a 22-bit wide pointer. The low­order 21 bits allow the device to address up to
2 Mbytes of program memory space. The 22nd bit
allows access to the device ID, the user ID and the
Configuration bits.

The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. These operations on the TBLPTR only affect
the low-order 21 bits.

7.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the
Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.

When the timed write to program memory begins (via
the WR bit), the 19 MSbs of the TBLPTR
(TBLPTR<21:3>) determine which program memory
block of 8 bytes is written to. The Table Pointer regis­ter’s three LSBs (TBLPTR<2:0>) are ignored. For more

detail, see Section 7.5 “Writing to Flash Program
Memory”.

When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.

Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.

TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Example Operation on Table Pointer

TBLRD*
TBLWT*

TBLRD*+
TBLWT*+

TBLRD*­TBLWT*-

TBLRD+*
TBLWT+*

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLPTR is not modified

FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

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(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD

TAB LAT

TBLPTR = xxx xx1

FETCH

Instruction Register

(IR)

Read Register

TBLPTR = xxxxx0

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_ODD

7.3 Reading the Flash Program Memory

The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table

The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 7-4
shows the interface between the internal program
memory and the TABLAT.

reads from program memory are performed one byte at
a time.

TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.

FIGURE 7-4: REA D S FROM FLASH PROGRAM MEMORY

EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD

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PIC18F1230/1330

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL

ERASE_ROW

BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts

Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h

MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts

7.4 Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the Flash array is not
supported.

When initiating an erase sequence from the micro­controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.

For protection, the write initiate sequence for EECON2
must be used.

A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write

7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE

The sequence of events for erasing a block of internal
program memory location is:

1. Load Table Pointer register with address of row

being erased.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

cycle. The long write will be terminated by the internal
programming timer.

EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW

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TABL AT

TBLPTR = xxxxx7TBLPTR = xxxxx1TBLPTR = xxxxx0

Write Register

TBLPTR = xxxx x2

Program Memory

Holding Register Holding Register Holding Register Holding Register

8

8 8 8

7.5 Writing to Flash Program Memory

The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.

Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.

Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 8 times
for each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. At the end of updating
the 8 holding registers, the EECON1 register must be
written to in order to start the programming operation with
a long write.

The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.

The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.

Note: The default value of the holding registers on

device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 8 holding registers
before executing a write operation.

FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY

7.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE

The sequence of events for programming an internal
program memory location should be:

1. Read 8 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer register with address being

erased.

4. Execute the row erase procedure.

5. Load Table Pointer register with address of first

byte being written.

6. Write the 8 bytes into the holding registers with

auto-increment.

7. Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

 2009 Microchip Technology Inc. DS39758D-page 77

8. Disable interrupts.

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about
2 ms using internal timer).

13. Re-enable interrupts.

14. Verify the memory (table read).

This procedure will require about 6 ms to update one
row of 8 bytes of memory. An example of the required
code is given in Example 7-3.

Note: Before setting the WR bit, the Table

Pointer address needs to be within the
intended address range of the 8 bytes in
the holding register.

PIC18F1230/1330

MOVLW D'88 ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL

READ_BLOCK

TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat

MODIFY_WORD

MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0

ERASE_BLOCK

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h

Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L

WRITE_BUFFER_BACK

MOVLW D’8 ; number of bytes in holding register
MOVWF COUNTER

WRITE_BYTE_TO_HREGS

MOVFF POSTINC0, WREG ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_WORD_TO_HREGS

EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY

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PROGRAM_MEMORY

BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h

Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory

EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

7.5.2 WRITE VERIFY

Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.

7.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION

7.5.4 PROTECTION AGAINST SPURIOUS WRITES

To protect against spurious writes to Flash program
memory, the write initiate sequence must also be

followed. See Section 20.0 “Special Features of the

CPU” for more detail.

7.6 Flash Program Operation During

Code Protection

If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed, if needed. If the write operation is
interrupted by a MCLR

Reset or a WDT Time-out Reset

See Section 20.5 “Program Verification and Code
Protection” for details on code protection of Flash

program memory.

during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.

TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TBLPTRU

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 47

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 47

TABLAT Program Memory Table Latch 47

INTCON GIE/GIEH PEIE/GIEL

EECON2 EEPROM Control Register 2 (not a physical register) 49

EECON1 EEPGD CFGS

IPR2

PIR2

PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 47

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

— FREE WRERR WREN WR RD 49

OSCFIP — —EEIP — LVDI P — —49

OSCFIF — —EEIF — LV DIF — —49

OSCFIE — —EEIE — LVDI E — —49

Reset

Val ues on

Page:

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8.0 DATA EEPROM MEMORY

The data EEPROM is readable and writable during
normal operation over the entire V
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).

There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:

• EECON1

• EECON2

• EEDATA

• EEADR

The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 128 bytes of data EEPROM with
an address range from 00h to FFh.

The EEPROM data memory is rated for high erase/
write cycle endurance. A byte write automatically
erases the location and writes the new data (erase­before-write). The write time is controlled by an on-chip
timer. The write time will vary with voltage and
temperature, as well as from chip-to-chip. Please

refer to parameter D122 (Table in Section 23.0

“Electrical Characteristics”) for exact limits.

8.1 EEADR Register

The EEPROM Address register can address 256 bytes
of data EEPROM.

DD range. The data

8.2 EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.

The EECON1 register (Register 7-1) is the control reg­ister for data and program memory access. Control bit
EEPGD determines if the access will be to program or
data EEPROM memory. When clear, operations will
access the data EEPROM memory. When set, program
memory is accessed.

Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.

The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.

Note 1: During normal operation, the WRERR bit

is read as ‘1’. This can indicate that a
write operation was prematurely termi­nated by a Reset, or a write operation
was attempted improperly. The WR con­trol bit initiates write operations. The bit
cannot be cleared, only set, in software; it
is cleared in hardware at the completion
of the write operation.

2: The Interrupt Flag bit, EEIF in the PIR2

register, is set when write is complete. It
must be cleared in the software Control
bits RD and WR, start read and erase/
write operations, respectively. These bits
are set by firmware and cleared by
hardware at the completion of the
operation.

The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 7.1 “Tabl e Reads

and Table Writes” regarding table reads.

Note: The EECON2 register is not a physical

register. It is used exclusively in the mem­ory write and erase sequences. Reading
EECON2 will read all ‘0’s.

 2009 Microchip Technology Inc. DS39758D-page 81

PIC18F1230/1330

REGISTER 8-1: EECON1: EEPROM CONTROL REGISTER 1

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory
0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write-only

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated

or WDT Reset during self-timed erase or program operation)

(MCLR

0 = The write operation completed

bit 2 WREN: Erase/Write Enable bit

1 = Allows erase/write cycles
0 = Inhibits erase/write cycles

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)

0 = Write cycle to is completed

bit 0 RD: Read Control bit

1 = Initiates a memory read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be

set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Read completed

(1)

(1)

WREN WR RD

Note 1: When a WRERR occurs, the EEPGD or FREE bit is not cleared. This allows tracing of the error condition.

DS39758D-page 82  2009 Microchip Technology Inc.

PIC18F1230/1330

MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA

MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts

MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BSF INTCON, GIE ; Enable Interrupts

BTFSC EECON1, WR ; Wait for write to complete

BRA $-2

SLEEP ; Wait for interrupt to signal write complete

BCF EECON1, WREN ; Disable writes

8.3 Reading the Data EEPROM Memory

To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).

8.4 Writing to the Data EEPROM Memory

To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 8-2 must be followed to initiate the write cycle.

The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.

Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared
by hardware.

After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc­tion. Both WR and WREN cannot be set with the same
instruction.

At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.

8.5 Write Verify

Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.

8.6 Protection Against Spurious Write

There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.

The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.

EXAMPLE 8-1: DATA EEPROM READ

EXAMPLE 8-2: DATA EEPROM WRITE

 2009 Microchip Technology Inc. DS39758D-page 83

PIC18F1230/1330

CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes

LOOP ; Loop to refresh array

BSF EECON1, RD ; Read current address

MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BTFSC EECON1, WR ; Wait for write to complete

BRA $-2

INCFSZ EEADR, F ; Increment address

BRA LOOP ; Not zero, do it again

BCF EECON1, WREN ; Disable writes

BSF INTCON, GIE ; Enable interrupts

8.7 Operation During Code-Protect

Data EEPROM memory has its own code-protect bits
in Configuration Words. External read and write
operations are disabled if either of these mechanisms
are enabled.

The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 20.0
“Special Features of the CPU” for additional

information.

8.8 Using the Data EEPROM

The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specification D124. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.

A simple data EEPROM refresh routine is shown in
Example 8-3.

EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE

Note: If data EEPROM is only used to store

constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.

TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL

EEADR EEPROM Address Register 49

EEDATA EEPROM Data Register 49

EECON2 EEPROM Control Register 2 (not a physical register) 49

EECON1 EEPGD CFGS

IPR2 OSCFIP — — EEIP — LVD IP — —49

PIR2

PIE2

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

DS39758D-page 84  2009 Microchip Technology Inc.

OSCFIF — — EEIF — LVD IF — —49

OSCFIE — — EEIE — LVDIE — —49

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

— FREE WRERR WREN WR RD 49

Reset

Values on

Page:

PIC18F1230/1330

MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

9.0 8 x 8 HARDWARE MULTIPLIER

9.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
Product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.

Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many
applications previously reserved for digital signal
processors. A comparison of various hardware and
software multiply operations, along with the savings in
memory and execution time, is shown in Table 9-1.

9.2 Operation

Example 9-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.

Example 9-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.

EXAMPLE 9-1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Routine Multiply Method

8 x 8 unsigned

8 x 8 signed

16 x 16 unsigned

16 x 16 signed

 2009 Microchip Technology Inc. DS39758D-page 85

Program

Memory
(Words)

Without hardware multiply 13 69 6.9 s27.6 s69 s

Hardware multiply 1 1 100 ns 400 ns 1 s

Without hardware multiply 33 91 9.1 s36.4 s91 s

Hardware multiply 6 6 600 ns 2.4 s6 s

Without hardware multiply 21 242 24.2 s96.8 s242 s

Hardware multiply 28 28 2.8 s 11.2 s28 s

Without hardware multiply 52 254 25.4 s 102.6 s254 s

Hardware multiply 35 40 4.0 s16.0 s40 s

Cycles

(Max)

@ 40 MHz @ 10 MHz @ 4 MHz

Time

PIC18F1230/1330

RES3:RES0= ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  2

16

) +

(ARG1H  ARG2L  2

8

) +

(ARG1L  ARG2H  2

8

) +

(ARG1L  ARG2L)

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->

; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->

; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->

; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->

; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

RES3:RES0=ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  2

16

) +

(ARG1H  ARG2L  2

8

) +

(ARG1L  ARG2H  2

8

) +
(ARG1L  ARG2L) +
(-1  ARG2H<7>  ARG1H:ARG1L  2

16

) +

(-1  ARG1H<7>  ARG2H:ARG2L  2

16

)

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3

;
SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3

;
CONT_CODE
:

Example 9-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 9-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).

EQUATION 9-1: 16 x 16 UNSIGNED

MULTIPLICATION
ALGORITHM

EXAMPLE 9-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

Example 9-4 shows the sequence to do a 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.

DS39758D-page 86  2009 Microchip Technology Inc.

EQUATION 9-2: 16 x 16 SIGNED

MULTIPLICATION
ALGORITHM

EXAMPLE 9-4: 16 x 16 SIGNED

MULTIPLY ROUTINE

PIC18F1230/1330

Data
Bus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Input
Buffer

I/O pin

(1)

QD

CK

QD

CK

EN

QD

EN

RD LAT

or

Port

Note 1: I/O pins have diode protection to V

DD and VSS.

CLRF PORTA ; Initialize PORTA by

; clearing output
; data latches

CLRF LATA ; Alternate method

; to clear output

; data latches
MOVLW 07h ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVWF 07h ; Configure comparators
MOVWF CMCON ; for digital input
MOVLW 0CFh ; Value used to

; initialize data

; direction
MOVWF TRISA ; Set RA<7:6,3:0> as inputs

; RA<5:4> as outputs

10.0 I/O PORTS

Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.

Each port has three registers for its operation. These
registers are:

• TRIS register (Data Direction register)

• PORT register (reads the levels on the pins of the
device)

• LAT register (Output Latch register)

The Output Latch (LAT register) is useful for read­modify-write operations on the value that the I/O pins
are driving.

A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.

FIGURE 10-1: GENERIC I/O PORT

OPERATION

Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.

The Output Latch (LATA) register is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.

Pins RA6 and RA7 are multiplexed with the main
oscillator pins; they are enabled as oscillator or I/O pins
by the selection of the main oscillator in the Configura-

tion register (see Section 20.1 “Configuration Bits”

for details). When they are not used as port pins, RA6
and RA7 and their associated TRIS and LAT bits are
read as ‘0’.

The RA0 pin is multiplexed with one of the analog
inputs, one of the external interrupt inputs, one of the
interrupt-on-change inputs and one of the analog
comparator inputs to become RA0/AN0/INT0/KBI0/
CMP0 pin.

The RA1 pin is multiplexed with one of the analog
inputs, one of the external interrupt inputs and one of
the interrupt-on-change inputs to become RA1/AN1/
INT1/KBI1 pin.

Pins RA2 and RA3 are multiplexed with the Enhanced
USART transmission and reception input (see

Section 20.1 “Configuration Bits” for details).

The RA4 pin is multiplexed with the Timer0 module
clock input, one of the analog inputs and the analog

REF+ input to become the RA4/T0CKI/AN2/VREF+ pin.

V

The Fault detect input for PWM FLTA

is multiplexed with
pins RA5 and RA7. Its placement is decided by clearing
or setting the FLTAMX bit of Configuration Register 3H.

10.1 PORTA, TRISA and LATA Registers

PORTA is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).

 2009 Microchip Technology Inc. DS39758D-page 87

Note: On a Power-on Reset, RA0, RA1, RA4

and RA5 are configured as analog inputs
and read as ‘0’. RA2 and RA3 are
configured as digital inputs.

The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.

EXAMPLE 10-1: INITIALIZING PORTA

PIC18F1230/1330

TABLE 10-1: PORTA I/O SUMMARY

Pin Function

RA0/AN0/INT0/
KBI0/CMP0

RA1/AN1/INT1/
KBI1

RA2/TX/CK RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when

RA3/RX/DT RA3 0 O DIG LATA<3> data output; not affected by analog input.

RA4/T0CKI/AN2/

REF+

V

MCLR

/VPP/RA5/

FLTA

RA6/OSC2/CLKO/
T1OSO/T1CKI/AN3

RA7/OSC1/CLKI/
T1OSI/FLTA

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Placement of FLTA

2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.

RA0 0 O DIG LATA<0> data output; not affected by analog input.

AN0 1 I ANA Analog input 0.
INT0 1 I ST External interrupt 0.
KBI0 1 I TTL Interrupt-on-change pin.

CMP0 1 I ANA Comparator 0 input.

RA1 0 O DIG LATA<1> data output; not affected by analog input.

AN1 1 I ANA Analog input 1.
INT1 1 I ST External interrupt 1.
KBI1 1 I TTL Interrupt-on-change pin.

TX 0 0 DIG EUSART asynchronous transmit.

CK 0 O DIG EUSART synchronous clock.

RX 1 I ANA EUSART asynchronous receive.
DT 0 O DIG EUSART synchronous data.

RA4 0 O DIG LATA<4> data output.

T0CKI 1 I ST Timer0 external clock input.

AN2 1 I ANA Analog input 2.

REF+ 1 I ANA A/D reference voltage (high) input.

V
MCLR 1 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

PP 1 I ANA Programming voltage input.

V

RA5 1 I ST Digital input.

FLTA

RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.

OSC2 0 O ANA Oscillator crystal output or external clock source output.
CLKO 0 O ANA Oscillator crystal output.

T1OSO

T1CKI

AN3 1 I ANA Analog input 3.

RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes.

OSC1 1 I ANA Oscillator crystal input or external clock source input.

CLKI 1 I ANA External clock source input.

T1OSI

FLTA

TRIS

Setting

1 I TTL PORTA<0> data input; disabled when analog input enabled.

1 I TTL PORTA<1> data input; disabled when analog input enabled.

1 I TTL PORTA<2> data input. Disabled when analog functions enabled;

1 IST

1 I TTL PORTA<3> data input; disabled when analog input enabled.

1 ITTL

1 I ST PORTA<4> data input; default configuration on POR.

(1)

(1)

1 I ST Fault detect input for PWM.

1 I ST PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.

(2)

0 O ANA Timer1 oscillator output.

(2)

1 I ST Timer1 clock input.

1 I TTL PORTA<7> data input. Disabled in external oscillator modes.

(2)

1 I ANA Timer1 oscillator input.
1 I ST Fault detect input for PWM.

depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

I/O

I/O

Type

CV

disabled when CV

Description

REF output enabled.

REF output enabled.

DS39758D-page 88  2009 Microchip Technology Inc.

PIC18F1230/1330

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Reset

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PORTA RA7

LATA LATA7

TRISA TRISA7

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

INTCON2

ADCON1

CMCON C2OUT C1OUT C0OUT — — CMEN2 CMEN1 CMEN0 48

CVRCON CVREN — CVRR CVRSS CVR3 CVR2 CVR1 CVR0 48

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

(1)

(1)

(1)

RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 47

— — — VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48

RA6

LATA6

TRISA6

(1)

(1)

RA5 RA4 RA3 RA2 RA1 RA0 50

PORTA Output Latch Register (Read and Write to Data Latch) 49

(1)

PORTA Data Direction Control Register 49

Values

on Page:

 2009 Microchip Technology Inc. DS39758D-page 89

PIC18F1230/1330

CLRF PORTB ; Initialize PORTB by

; clearing output
; data latches

CLRF LATB ; Alternate method

; to clear output

; data latches
MOVLW 0Fh ; Set RB<4:0> as
MOVWF ADCON1 ; digital I/O pins

; (required if config bit

; PBADEN is set)
MOVLW 0CFh ; Value used to

; initialize data

; direction
MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

10.2 PORTB, TRISB and LATB Registers

PORTB is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).

The Output Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.

EXAMPLE 10-2: INITIALIZI NG PORTB

Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.

Note: On a Power-on Reset, PORTB is

configured as digital inputs except for RB2
and RB3.

RB2 and RB3 are configured as analog
inputs when the T1OSCMX bit of Configu­ration Register 3H is cleared. Otherwise,
RB2 and RB3 are also configured as
digital inputs.

(INTCON2<7>). The

Pins RB0, RB1 and RB4:RB7 are multiplexed with the
Power Control PWM outputs.

Pins RB2 and RB3 are multiplexed with external interrupt
inputs, interrupt-on-change input, the analog comparator
inputs and the Timer1 oscillator input and output to
become RB2/INT2/KBI2/CMP2/T1OSO/T1CKI and
RB3/INT3/KNBI3/CMP1/T1OSI, respectively.

When the interrupt-on-change feature is enabled, only
pins configured as inputs can cause this interrupt to
occur (i.e., any RB2, RB3, RA0 and RA1 pin configured
as an output is excluded from the interrupt-on-change
comparison). The input pins (RB2, RB3, RA0 and RA1)
are compared with the old value latched on the last
read of PORTA and PORTB. The “mismatch” outputs of
these pins are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from Sleep mode, or
any of the Idle modes. The user, in the Interrupt Service
Routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB (except with the

MOVFF (ANY), PORTB instruction).

b) 1 T

CY

c) Clear flag bit, RBIF.

A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB and waiting 1 T

CY will end the mis-

match condition and allow flag bit, RBIF, to be cleared.
Additionally, if the port pin returns to its original state,
the mismatch condition will be cleared.

The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTA and PORTB are used for the interrupt­on-change feature. Polling of PORTA and PORTB is
not recommended while using the interrupt-on-change
feature.

DS39758D-page 90  2009 Microchip Technology Inc.

PIC18F1230/1330

TABLE 10-3: PORTB I/O SUMMARY

Pin Function

RB0/PWM0 RB0 0 O DIG LATB<0> data output; not affected by analog input.

PWM0 0 O DIG PWM module output PWM0.

RB1PWM1 RB1 0 O DIG LATB<1> data output; not affected by analog input.

PWM1 0 O DIG PWM module output PWM1.

RB2/INT2/KBI2/
CMP2/T1OSO/
T1CKI

RB3/INT3/KBI3/
CMP1/T1OSI

RB4/PWM2 RB4 0 O DIG LATB<4> data output; not affected by analog input.

RB5/PWM3 RB5 0 O DIG LATB<5> data output.

RB6/PWM4/PGC RB6 0 O DIG LATB<6> data output.

RB7/PWM5/PGD RB7 0 O DIG LATB<7> data output.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default

when PBADEN is set and digital inputs when PBADEN is cleared.

2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.

RB2 0 O DIG LATB<2> data output; not affected by analog input.

INT2 1 I ST External interrupt 2 input.
KBI2 1 I TTL Interrupt-on-change pin.

CMP2 1 I ANA Comparator 2 input.

T1OSO

T1CKI

RB3 0 O DIG LATB<3> data output; not affected by analog input.

INT3 1 I ST External interrupt 3 input.
KBI3 1 I TTL Interrupt-on-change pin.

CMP1 1 I ANA Comparator 1 input.

T1OSI

PWM2 0 O DIG PWM module output PWM2.

PWM3 0 O DIG PWM module output PWM3.

PWM4 0 O DIG PWM module output PWM4.

PGC 1 I ST In-Circuit Debugger and ICSP™ programming clock pin.

PWM5 0 O TTL PWM module output PWM4.

PGD 0 O DIG In-Circuit Debugger and ICSP programming data pin.

TRIS

Setting

(2)

(2)

(2)

I/O

1 I TTL PORTB<0> data input; weak pull-up when RBPU

1 I TTL PORTB<1> data input; weak pull-up when RBPU

1 I TTL PORTB<2> data input; weak pull-up when RBPU

0 O ANA Timer1 oscillator output.
1 I ST Timer1 clock input.

1 I TTL PORTB<3> data input; weak pull-up when RBPU

1 I ANA Timer1 oscillator input.

1 I TTL PORTB<4> data input; weak pull-up when RBPU

1 I TTL PORTB<5> data input; weak pull-up when RBPU

1 I TTL PORTB<6> data input; weak pull-up when RBPU

1 I TTL PORTB<7> data input; weak pull-up when RBPU

I/O

Type

Description

Disabled when analog input enabled.

Disabled when analog input enabled.

Disabled when analog input enabled.

Disabled when analog input enabled.

Disabled when analog input enabled.

(1)

(1)

(1)

(1)

(1)

bit is cleared.

bit is cleared.

bit is cleared.

bit is cleared.

bit is cleared.

bit is cleared.

bit is cleared.

bit is cleared.

 2009 Microchip Technology Inc. DS39758D-page 91

PIC18F1230/1330

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Reset

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50

LATB PORTB Output Latch Register (Read and Write to Data Latch) 49

TRISB PORTB Data Direction Control Register 49

INTCON

INTCON2 RBPU

INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 47

CMCON C2OUT C1OUT

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 47

C0OUT — — CMEN2 CMEN1 CMEN0 48

Values

on Page:

DS39758D-page 92  2009 Microchip Technology Inc.

PIC18F1230/1330

11.0 INTERRUPTS

The PIC18F1230/1330 devices have multiple interrupt
sources and an interrupt priority feature that allows
most interrupt sources to be assigned a high-priority
level or a low-priority level. The high-priority interrupt
vector is at 0008h and the low-priority interrupt vector
is at 0018h. High-priority interrupt events will interrupt
any low-priority interrupts that may be in progress.

There are thirteen registers which are used to control
interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files
supplied with MPLAB
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.

In general, interrupt sources have three bits to control
their operation. They are:

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the
flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.

®

IDE be used for the symbolic bit

When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.

When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a low­priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.

The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

®

mid-range devices. In

 2009 Microchip Technology Inc. DS39758D-page 93

PIC18F1230/1330

RBIE

GIE/GIEH

PEIE/GIEL

Wake-up if in

Interrupt to CPU
Vector to Location

0008h

INT2IF
INT2IE

INT2IP

INT1IF
INT1IE

INT1IP

TMR0IF
TMR0IE

TMR0IP

RBIF

RBIE
RBIP

IPEN

RBIF

RBIP

INT2IF
INT2IE
INT2IP

INT0IF
INT0IE

INT1IF
INT1IE

PEIE/GIEL

Interrupt to CPU
Vector to Location

IPEN

IPEN

0018h

Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit

Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit

ADIF
ADIE
ADIP

PTIF
PTIE
PTIP

Additional Peripheral Interrupts

ADIF
ADIE
ADIP

High-Priority Interrupt Generation

Low-Priority Interrupt Generation

PTIF
PTIE
PTIP

Additional Peripheral Interrupts

Idle or Sleep modes

GIE/GIEH

TMR0IE

TMR0IF

TMR0IP

INT1IP

From Power Control PWM
Interrupt Logic

From Power Control

PWM Interrupt Logic

FIGURE 11-1: PIC18 INTERRUPT LOGIC

DS39758D-page 94  2009 Microchip Technology Inc.

PIC18F1230/1330

11.1 INTCON Registers

The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.

REGISTER 11-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN =

1 = Enables all unmasked interrupts
0 = Disables all interrupts

When IPEN =

1 = Enables all high-priority interrupts
0 = Disables all interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN =

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

When IPEN =

1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

0:

1:

0:

1:

(1)

(1)

Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and

allow the bit to be cleared.

 2009 Microchip Technology Inc. DS39758D-page 95

PIC18F1230/1330

REGISTER 11-2: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP

bit 7 RBPU

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

bit 3 INTEDG3: External Interrupt 3 Edge Select bit

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

bit 1 INT3IP: INT3 External Interrupt Priority bit

bit 0 RBIP: RB Port Change Interrupt Priority bit

: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = High priority
0 = Low priority

1 = High priority
0 = Low priority

1 = High priority
0 = Low priority

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

DS39758D-page 96  2009 Microchip Technology Inc.

PIC18F1230/1330

REGISTER 11-3: INTCON3: INTERRUPT CONTROL REGISTER 3

R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority
0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority
0 = Low priority

bit 5 INT3IE: INT3 External Interrupt Enable bit

1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt

bit 2 INT3IF: INT3 External Interrupt Flag bit

1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

 2009 Microchip Technology Inc. DS39758D-page 97

PIC18F1230/1330

11.2 PIR Registers

The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2 and PIR3).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state
of its corresponding enable bit or the Glo­bal Interrupt Enable bit, GIE
(INTCON<7>).

2: User software should ensure the

appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.

REGISTER 11-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete

bit 5 RCIF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty

bit 4 TXIF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full

bit 3 CMP2IF: Analog Comparator 2 Flag bit

1 = The output of CMP2 has changed since last read
0 = The output of CMP2 has not changed since last read

bit 2 CMP1IF: Analog Comparator 1 Flag bit

1 = The output of CMP1 has changed since last read
0 = The output of CMP1 has not changed since last read

bit 1 CMP0IF: Analog Comparator 0 Flag bit

1 = The output of CMP0 has changed since last read
0 = The output of CMP0 has not changed since last read

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

DS39758D-page 98  2009 Microchip Technology Inc.

PIC18F1230/1330

REGISTER 11-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0

OSCFIF — — EEIF —LVDIF — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock operating

bit 6-5 Unimplemented: Read as ‘0’
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started

bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit

1 = A low-voltage condition occurred
0 = A low-voltage condition has not occurred

bit 1-0 Unimplemented: Read as ‘0’

REGISTER 11-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3

U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0

— — —PTIF— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’
bit 4 PTIF: PWM Time Base Interrupt bit

1 = PWM time base matched the value in PTPER register. Interrupt is issued according to the

postscaler settings. PTIF must be cleared in software.

0 = PWM time base has not matched the value in PTPER register

bit 3-0 Unimplemented: Read as ‘0’

 2009 Microchip Technology Inc. DS39758D-page 99

PIC18F1230/1330

11.3 PIE Registers

The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2 and PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.

REGISTER 11-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt
0 = Disables the A/D interrupt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt

bit 3 CMP2IE: Analog Comparator 2 Interrupt Enable bit

1 = Enables the CMP2 interrupt
0 = Disables the CMP2 interrupt

bit 2 CMP1IE: Analog Comparator 1 Interrupt Enable bit

1 = Enables the CMP1 interrupt
0 = Disables the CMP1 interrupt

bit 1 CMP0IE: Analog Comparator 0 Interrupt Enable bit

1 = Enables the CMP0 interrupt
0 = Disables the CMP0 interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

DS39758D-page 100  2009 Microchip Technology Inc.