Datasheet PIC16F707, PIC16LF707 Datasheet

PIC16F707/PIC16LF707

Data Sheet

40/44-Pin, Flash Microcontrollers

with nanoWatt XLP and

mTouch™ Technology

 2010 Microchip Technology Inc. Preliminary DS41418A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-60932-148-2

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41418A-page 2 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

40/44-Pin, Flash Microcontrollers with

nanoWatt XLP and mTouch™ Technology

Devices included in this data sheet:

•PIC16F707

• PIC16LF707

High-Performance RISC CPU:

• Only 35 Single-Word Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 20 MHz clock input

- DC – 200 ns instruction cycle

• 8K x 14 Words of Flash Program Memory

• 363 Bytes of Data Memory (SRAM)

• Interrupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Read Access to Program Memory

• Pinout Compatible to other 40-pin PIC16CXXX
and PIC16FXXX Microcontrollers

Special Microcontroller Features:

• Precision Internal Oscillator:

- 16 MHz or 500 kHz operation

- Factory calibrated to ±1%, typical

- Software selectable ÷1, ÷2, ÷4 or ÷8 divider

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- 3 crystal/resonator modes up to 20 MHz

- 3 external clock modes up to 20 MHz

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Oscillator Start-Up Timer (OST)

• Brown-out Reset (BOR):

- Selectable between two trip points

- Disabled in Sleep option

• Watchdog Timer (WDT)

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via two
pins

• In-Circuit Debug (ICD) via Two Pins

• Multiplexed Master Clear with Pull-up/Input Pin

• Industrial and Extended Temperature Range

• High-Endurance Flash Cell:

- 1,000 Write Flash Endurance (typical)

- Flash Retention: >40 years

- Power-Saving Sleep mode

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF707)

• 1.8V to 5.5V (PIC16F707)

Extreme Low-Power Management PIC16LF707 with nanoWatt XLP:

• Sleep mode: 20 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Timer1 Oscillator: 600 nA @ 1.8V, typical
@ 32 kHz

mTouch™ Technology Features:

• Up to 32 Channels

• Two Capacitive Sensing modules:

- Acquire 2 samples simultaneously

• Multiple Power modes:

- Operation during Sleep

- Proximity sensing with ultra low µA current

• Adjustable Waveform Min. and Max. for Optimal
Noise Performance

• 1.8V to 5.5V Operation (3.6V max. for
PIC16LF707)

Analog Features:

• A/D Converter:

- 8-bit resolution and up to 14 channels

- Conversion available during Sleep

- Selectable 1.024V/2.048V/4.096V voltage

reference

• On-chip 3.2V Regulator (PIC16F707 device only)

Peripheral Highlights:

• Up to 35 I/O Pins and 1 Input-only Pin:

- High current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• Timer0/A/B: 8-Bit Timer/Counter with 8-Bit
Prescaler

• Enhanced Timer1/3:

- Dedicated low-power 32 kHz oscillator driver

- 16-bit timer/counter with prescaler

- External Gate Input mode with toggle and

single shot modes

- Interrupt-on-gate completion

• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler

• Two Capture, Compare, PWM modules (CCP):

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)

 2010 Microchip Technology Inc. Preliminary DS41418A-page 3

PIC16F707/PIC16LF707

40-PIN PDIP

PIC16F707/PIC16LF707

1

2

3

4

5

6

7

8

9

10

VPP/MCLR/RE3

V

CAP

(3)

/SS

(2)

/AN0/RA0

CPSA0

/AN1/RA1

DACOUT/CPSA1/AN2/RA2

CPSA2/V

REF/AN3/RA3

TACKI/T0CKI/CPSA3/RA4

V

CAP

(3)

/SS

(2)

/CPSA4/AN4/RA5

CPSA5/AN5/RE0

CPSA6/AN6/RE1

CPSA7/AN7/RE2

RB6/CPSB14/ICSPCLK

RB5/AN13/CPSB13/T1G/T3CKI

RB4/AN11/CPSB12

RB3/AN9/CPSB11/CCP2

(1)

RB2/AN8/CPSB10

RB1/AN10/CPSB9

RB0/AN12/CPSB8/INT

V

DD

VSS

RD2/CPSB7

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

V

DD

VSS

CLKIN/OSC1/CPSB0/RA7

V

CAP

(3)

/CLKOUT/OSC2/CPSB1/RA6

T1CKI/T1OSO/CPSB2/RC0

CCP2

(1)

/T1OSI/CPSB3/RC1

TBCKI/CCP1/CPSB4/RC2

SCL/SCK/RC3

T3G/CPSB5/RD0

CPSB6/RD1

RC5/CPSA9/SDO

RC4/SDI/SDA

RD3/CPSA8

RD4/CPSA12

RC7/CPSA11/RX/DT

RC6/CPSA10/TX/CK

RD7/CPSA15

RD6/CPSA14

RD5/CPSA13

RB7/CPSB15/ICSPDAT

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS

pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

• Synchronous Serial Port (SSP):

- SPI (Master/Slave)

-I2C™ (Slave) with Address Mask

• Voltage Reference module:

- Fixed voltage reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive
reference selection

Device

PIC16F707 8192 363 36 32 14 Yes 2 4/2

PIC16LF707 8192 363 36 32 14 Yes 2 4/2

Pin Diagrams

Memory Flash

Program

(words)

SRAM
(bytes)

Capacitive Touch

I/Os

Channels

8-bit A/D

(ch)

AUSART CCP

Timers

8/16-bit

DS41418A-page 4 Preliminary  2010 Microchip Technology Inc.

Pin Diagrams

10
11

2
3
4
5
6

1

181920

21

22

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

CPSA2/V

REF/AN3/RA3

DACOUT/CPSA1/AN2/RA2

CPSA0/AN1/RA1

V

CAP

(3)

/SS

(2)

/AN0/RA0

VPP/MCLR/RE3

CCP2

(1)

/CPSB11/AN9/RB3

ICSPDAT/CPSB15/RB7

ICSPCLK/CPSB14/RB6

T3CKI/T1G/CPSB13/AN13/RB5

CPSB12/AN11/RB4

NC

RC6/CPSA10/TX/CK

RC5/CPSA9/SDO

RC4/SDI/SDA

RD3/CPSA8

RD2/CPSB7

RD1/CPSB6

RD0/CPSB5/T3G

RC3/SCK/SCL

RC2/CPSB4/CCP1/TBCKI

RC1/CPSB3/T1OSI/CCP2

(1)

RC0/CPSB2/T1OSO/T1CKI

RA6/OSC2/CLKOUT/CPSB1/VCAP

(3)

RA7/OSC1/CLKIN/CPSB0
V

SS

VSS
NC
V

DD

RE2/AN7/CPSA7
RE1/AN6/CPSA6
RE0/AN5/CPSA5
RA5/AN4/CPSA4/SS

(2)

/VCAP

(3)

RA4/CPSA3/T0CKI/TACKI

DT/RX/CPSA11/RC7

CPSA12/RD4
CPSA13/RD5
CPSA14/RD6
CPSA15/RD7

V

SS

VDD
VDD

INT/CPSB8/AN12/RB0

CPSB9/AN10/RB1
CPSB10/AN8/RB2

44-PIN QFN (8x8x0.9)

PIC16F707

PIC16LF707

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS

pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 5

PIC16F707/PIC16LF707

10
11

2
3

6

1

1819202122

121314

15

38

8

7

44

43

42

414039

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

VREF/CPSA2/AN3/RA3

DACOUT/CPSA1/AN2/RA2

CPSA0/AN1/RA1

V

CAP

(3)

/SS

(2)

/AN0/RA0

V

PP/MCLR/RE3

NC

ICSPDAT/CPSB15/RB7

ICSPCLK/CPSB14/RB6

T1G/CPSB13/AN13/RB5

CPSB12/AN11/RB4

NC

RC6/CPSA10/TX/CK

RC5/CPSA9/SDO

RC4/SDI/SDA

RD3/CPSA8

RD2/CPSB7

RD1/CPSB6

RD0CPSB5/T3G

RC3//SCK/SCL

RC2CPSB4/CCP1/TBCKI

RC1/CPSB3/T1OSI/CCP2

(1)

NC

NC
RC0/T1OSO/T1CKI/CPSB2
RA6/OSC2/CLKOUT/CPSB1/V

CAP

(3)

RA7/OSC1/CLKIN/CPSB0
V

SS

VDD
RE2/AN7/CPSA7
RE1/AN6/CPSA6
RE0/AN5/CPSA5
RA5/AN4/CPSA4/SS

(2)

/VCAP

(3)

RA4/CPSA3/T0CKI/TACKI

DT/RX/CPSA11/RC7

CPSA12/RD4
CPSA13/RD5
CPSA14/RD6

V

SS

VDD

INT/CPSB8/AN12/RB0

CPSB9/AN10/RB1
CPSB10/AN8/RB2

CCP2

(1)

/CPSB11/AN9/RB3

CPSA15/RD7

5

4

PIC16F707

PIC16LF707

44-PIN TQFP

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS

pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

Pin Diagrams

DS41418A-page 6 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707

I/O

44-Pin TQFP

44-Pin QFN

CAP functionality is selectable by the VCAPEN bits in Configuration Word 2.

40-Pin PDIP

RA0 2 19 19 Y AN0 — — — —

RA1 3 20 20 Y AN1 — CPSA0 — — — — — — —

RA2 4 21 21 Y AN2 DACOUT CPSA1 — — — — — — —

RA3 5 22 22 Y AN3/

RA4 6 23 23 Y — — CPSA3 T0CKI/

RA5 7 24 24 Y AN4 — CPSA4 — — — SS

RA6 14 31 33 Y — — CPSB1 — — — — — — OSC2/

RA7 13 30 32 Y — — CPSB0 — — — — — — OSC1/

RB0 33 8 9 Y AN12 — CPSB8 — — — — IOC/INT Y —

RB1 34 9 10 Y AN10 — CPSB9 — — — — IOC Y —

RB2 35 10 11 Y AN8 — CPSB10 — — — — IOC Y —

RB3 36 11 12 Y AN9 — CPSB11 — CCP2

RB4 37 14 14 Y AN11 — CPSB12 — — — — IOC Y —

RB5 38 15 15 Y AN13 — CPSB13 T1G/

RB6 39 16 16 Y — — CPSB14 — — — — IOC Y ICSPCLK/

RB7 40 17 17 Y — — CPSB15 — — — — IOC Y ICSPDAT/

RC0 15 32 34 Y — — CPSB2 T1OSO/

RC1 16 35 35 Y — — CPSB3 T1OSI CCP2

RC2 17 36 36 Y — — CPSB4 TBCKI CCP1 — — — — —

RC3 18 37 37 — — — — — — — SCK/SCL — — —

RC4 23 42 42 — — — — — — — SDI/SDA — — —

RC5 24 43 43 Y — — CPSA9 — — — SDO — — —

RC6 25 44 44 Y — — CPSA10 — — TX/CK — — — —

RC7 26 1 1 Y — — CPSA11 — — RX/DT — — — —

RD0 19 38 38 Y — — CPSB5 T3G — — — — — —

RD1 20 39 39 Y — — CPSB6 — — — — — — —

RD2 21 40 40 Y — — CPSB7 — — — — — — —

RD3 22 41 41 Y — — CPSA8 — — — — — — —

RD4 27 2 2 Y — — CPSA12 — — — — — — —

RD5 28 3 3 Y — — CPSA13 — — — — — — —

RD6 29 4 4 Y — — CPSA14 — — — — — — —

RD7 30 5 5 Y — — CPSA15 — — — — — — —

RE0 8 25 25 Y AN5 — CPSA5 — — — — — — —

RE1 9 26 26 Y AN6 — CPSA6 — — — — — — —

RE2 10 27 27 Y AN7 — CPSA7 — — — — — — —

RE3 1 18 18 — — — — — — — — — Y

VDD 11 , 32 7, 28 7,8,28 — — — — — — — — — VDD

Vss 12, 31 6, 29 6, 30, 31 — — — — — — — — — VSS

Note 1: Pull-up activated only with external MCLR configuration.

2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.

3: RA5 is the default pin location for SS

4: PIC16F707 only. V

ANSEL

V

A/D

REF

DAC

Cap Sensor

VREF CPSA2 — — — — — — —

. RA0 may be selected by changing the SSSEL bit in the APFCON register.

Timers

TAC KI

T3CKI

T1CKI

CCP

— — — — — —

— — — IOC Y —

— — — — — —

AUSART

(2)

— — IOC Y —

(2)

—— ———

SS

SSP

(3)

(3)

— — VCAP

——VCAP

Basic

Pull-up

Interrupt

(4)

(4)

CLKOUT/

(4)

V

CAP

CLKIN

ICDCLK

ICDDAT

(1)

MCLR/

PP

V

 2010 Microchip Technology Inc. Preliminary DS41418A-page 7

PIC16F707/PIC16LF707

Table of Contents

1.0 Device Overview ....................................................................................................................................................................... 11

2.0 Memory Organization ................................................................................................................................................................ 17

3.0 Resets ....................................................................................................................................................................................... 29

4.0 Interrupts ................................................................................................................................................................................... 39

5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 49

6.0 I/O Ports .................................................................................................................................................................................... 51

7.0 Oscillator Module....................................................................................................................................................................... 69

8.0 Device Configuration................................................................................................................................................................. 75

9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 79

10.0 Fixed Voltage Reference ........................................................................................................................................................... 89

11.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................... 91

12.0 Timer0 Module .......................................................................................................................................................................... 95

13.0 Timer1/3 Modules with Gate Control......................................................................................................................................... 99

14.0 TimerA/B Modules................................................................................................................................................................... 111

15.0 Timer2 Module ........................................................................................................................................................................ 115

16.0 Capacitive Sensing Module ..................................................................................................................................................... 117

17.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 127

18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .......................................................... 137

19.0 SSP Module Overview ............................................................................................................................................................ 157

20.0 Program Memory Read........................................................................................................................................................... 179

21.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 183

22.0 In-Circuit Serial Programming™ (ICSP™) .............................................................................................................................. 185

23.0 Instruction Set Summary ......................................................................................................................................................... 187

24.0 Development Support.............................................................................................................................................................. 197

25.0 Electrical Specifications........................................................................................................................................................... 201

26.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 231

27.0 Packaging Information............................................................................................................................................................. 267

Appendix A: Data Sheet Revision History ......................................................................................................................................... 273

Appendix B: Migrating From Other PIC® Devices ............................................................................................................................ 273

The Microchip Web Site.................................................................................................................................................................... 281

Customer Change Notification Service ............................................................................................................................................. 281

Customer Support ............................................................................................................................................................................. 281

Reader Response ............................................................................................................................................................................. 282

Product Identification System............................................................................................................................................................. 283

DS41418A-page 8 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 9

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 10 Preliminary  2010 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16F707/PIC16LF707 devices are covered by
this data sheet. They are available in 40/44-pin
packages. Figure 1-1 shows a block diagram of the
PIC16F707/PIC16LF707 devices. Table 1-1 shows the
pinout descriptions.

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 11

PIC16F707/PIC16LF707

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

RAM Addr

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

PORTA

PORTB

PORTC

PORTD

PORTE

RA4
RA5

RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7

RE0

RE1

RE2

8

8

Timer0

RA3

RA1

RA0

8

3

RA6
RA7

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

RB0
RB1
RB2

RB3
RB4
RB5

RB7

AN6

AN0 AN1

AN2

AN3 AN4

AN5

AN7

Synchronous

SDA

SCL

SSSDO

Serial Port

SDI/

SCK/

TX/CK

RX/DT

Internal

Oscillator

Block

Configuration

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

PORTB

PORTC

PORTD

PORTE

RC1

8

8

8

3

Synchronous

SDA

SCL

SSSDO

Serial Port

SDI/

SCK/

Internal

Oscillator

Block

Configuration

13

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

8 Level Stack

(13-bit)

7

Addr MUX

FSR Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

PORTB

PORTC

PORTD

PORTE

RC1

8

8

8

3

Analog-To-Digital Converter

RB6

Synchronous

SDA

SCL

SSSDO

Serial Port

SDI/

SCK/

Internal

Oscillator

Block

Configuration

RE3

CCP2

CCP2

CCP1

CCP1

VREF

RA2

AN9AN8

AN10

AN11

AN12 AN13

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR

VDD

Brown-out

Reset

VSS

T0CKI

T1G

T1CKI

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR

VDD

Brown-out

Reset

VSS

T0CKI

MCLR

VDD VSS

T0CKI

Timer1

32 kHz

Oscillator

T1OSI

T1OSO

LDO

Regulator

Capacitive Sensing Module A

CPSA6CPSA0 CPSA1 CPSA2 CPSA3 CPSA4

CPSA7

CPSA8 CPSA9 CPSA10 CPSA11 CPSA12 CPSA13 CPSA14 CPSA15

CPSA5

Flash

Program

Memory

RAM

T3G

T3CKI

Timer1 Timer2 Timer3

TimerA Timer B

AUSART

TACKI

TBCKI

CPSB6CPSB0 CPSB1 CPSB2 CPSB3 CPSB4

CPSB7

CPSB8 CPSB9 CPSB10 CPSB11 CPSB12 CPSB13 CPSB14 CPSB15

CPSB5

Capacitive Sensing Module B

Digital-To-Analog

DACOUT

Converter

FIGURE 1-1: PIC16F707/PIC16LF707 BLOCK DIAGRAM

DS41418A-page 12 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION

Input

Name Function

Typ e

Output

Typ e

Description

RA0/AN0/SS

RA1/AN1/CPSA0 RA1 TTL CMOS General purpose I/O.

RA2/AN2/CPSA1/DACOUT RA2 TTL CMOS General purpose I/O.

RA3/AN3/V

RA4/CPSA3/T0CKI/TACKI RA4 TTL CMOS General purpose I/O.

RA5/AN4/CPSA4/SS/

RA6/OSC2/CLKOUT/V
CPSB1

RA7/OSC1/CLKIN/CPSB0 RA7 TTL CMOS General purpose I/O.

RB0/AN12/CPSB8/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

RB1/AN10/CPSB9 RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

/VCAP RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

SS

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).

V

AN1 AN — A/D Channel 1 input.

CPSA0 AN — Capacitive sensing A input 0.

AN2 AN — A/D Channel 2 input.

CPSA1 AN — Capacitive sensing A input 1.

DACOUT — AN Voltage Reference Output.

REF/CPSA2 RA3 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

REF AN — A/D Voltage Reference input.

V

CPSA2 AN — Capacitive sensing A input 2.

CPSA3 AN — Capacitive sensing A input 3.

T0CKI ST — Timer0 clock input.

TACKI ST — TimerA clock input.

VCAP RA5 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

CPSA4 AN — Capacitive sensing A input 4.

SS

V

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).

CAP/

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).

V

CPSB1 AN — Capacitive sensing B input 1.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN CMOS — External clock input (EC mode).

CLKIN ST — RC oscillator connection (RC mode).

CPSB0 AN — Capacitive sensing B input 0.

AN12 AN — A/D Channel 12 input.

CPSB8 AN — Capacitive sensing B input 8.

INT ST — External interrupt.

AN10 AN — A/D Channel 10 input.

CPSB9 AN — Capacitive sensing B input 9.

ST — Slave Select input.

ST — Slave Select input.

OSC/4 output.

Individually enabled pull-up.

Individually enabled pull-up.

2

C™ = Schmitt Trigger input with I2C

 2010 Microchip Technology Inc. Preliminary DS41418A-page 13

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB2/AN8/CPSB10 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN8 AN — A/D Channel 8 input.

CPSB10 AN — Capacitive sensing B input 10.

RB3/AN9/CPSB11/CCP2 RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN9 AN — A/D Channel 9 input.

CPSB11 AN — Capacitive sensing B input 11.

CCP2 ST CMOS Capture/Compare/PWM2.

RB4/AN11/CPSB12 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN11 AN — A/D Channel 11 input.

CPSB12 AN — Capacitive sensing B input 12.

RB5/AN13/CPSB13/T1G/T3CKI RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN13 AN — A/D Channel 13 input.

CPSB13 AN — Capacitive sensing B input 13.

T1G ST — Timer1 gate input.

T3CKI ST — Timer3 clock input.

RB6/ICSPCLK/ICDCLK/CPSB14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

ICSPCLK ST — Serial Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

CPSB14 AN — Capacitive sensing B input 14.

RB7/ICSPDAT/ICDDAT/CPSB15 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST — In-Circuit Data I/O.

CPSB15 AN — Capacitive sensing B input 15.

RC0/T1OSO/T1CKI/CPSB2 RC0 ST CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

CPSB2 AN — Capacitive sensing B input 2.

RC1/T1OSI/CCP2/CPSB3 RC1 ST CMOS General purpose I/O.

T1OSI XTAL XTAL Timer1 oscillator connection.

CCP2 ST CMOS Capture/Compare/PWM2.

CPSB3 AN — Capacitive sensing B input 3.

RC2/CCP1/CPSB4/TBCKI RC2 ST CMOS General purpose I/O.

CCP1 ST CMOS Capture/Compare/PWM1.

CPSB4 AN — Capacitive sensing B input 4.

TBCKI ST — TimerB clock input.

RC3/SCK/SCL RC3 ST CMOS General purpose I/O.

SCK ST CMOS SPI clock.

SCL I

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Output

Typ e

2

Typ e

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

C™ OD I2C™ clock.

Description

2

C™ = Schmitt Trigger input with I2C

DS41418A-page 14 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RC4/SDI/SDA RC4 ST CMOS General purpose I/O.

SDI ST — SPI data input.

SDA I

RC5/SDO/CPSA9 RC5 ST CMOS General purpose I/O.

SDO — CMOS SPI data output.

CPSA9 AN — Capacitive sensing A input 9.

RC6/TX/CK/CPSA10 RC6 ST CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

CPSA10 AN — Capacitive sensing A input 10.

RC7/RX/DT/CPSA11 RC7 ST CMOS General purpose I/O.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

CPSA11 AN — Capacitive sensing A input 11.

RD0/CPSB5/T3G RD0 ST CMOS General purpose I/O.

CPSB5 AN — Capacitive sensing B input 5.

T3G ST — Timer3 Gate input.

RD1/CPSB6 RD1 ST CMOS General purpose I/O.

CPSB6 AN — Capacitive sensing B input 6.

RD2/CPSB7 RD2 ST CMOS General purpose I/O.

CPSB7 AN — Capacitive sensing B input 7.

RD3/CPSA8 RD3 ST CMOS General purpose I/O.

CPSA8 AN — Capacitive sensing A input 8.

RD4/CPSA12

RD5/CPSA13

RD6/CPSA14

RD7/CPSA15

RE0/AN5/CPSA5 RE0 ST CMOS General purpose I/O.

RE1/AN6/CPSA6 RE1 ST CMOS General purpose I/O.

RE2/AN7/CPSA7 RE2 ST CMOS General purpose I/O.

RE3/MCLR

V

DD VDD Power — Positive supply.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

/VPP RE3 TTL — General purpose input.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

RD4 ST

CPSA12 AN — Capacitive sensing A input 12.

RD5 ST

CPSA13 AN — Capacitive sensing A input 13.

RD6 ST

CPSA14 AN — Capacitive sensing A input 14.

RD7 ST

CPSA15 AN — Capacitive sensing A input 15.

AN5 AN — A/D Channel 5 input.

CPSA5 AN — Capacitive sensing A input 5.

AN6 AN — A/D Channel 6 input.

CPSA6 AN — Capacitive sensing A input 6.

AN7 AN — A/D Channel 7 input.

CPSA7 AN — Capacitive sensing A input 7.

MCLR

PP HV — Programming voltage.

V

Output

Typ e

2

Typ e

C™ OD I2C™ data input/output.

CMOS

CMOS

CMOS

CMOS

ST — Master Clear with internal pull-up.

General purpose I/O.

General purpose I/O.

General purpose I/O.

General purpose I/O.

Description

2

C™ = Schmitt Trigger input with I2C

 2010 Microchip Technology Inc. Preliminary DS41418A-page 15

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

V

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note: The PIC16F707 devices have an internal low dropout voltage regulator. An external capacitor must be

connected to one of the available V
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF707 devices do not have the voltage
regulator and therefore no external capacitor is required.

Output

Typ e

Typ e

CAP pins to stabilize the regulator. For more information, see

Description

2

C™ = Schmitt Trigger input with I2C

DS41418A-page 16 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

PC<12:0>

13

0000h

0004h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN
RETFIE, RETLW

Stack Level 2

0005h

On-chip

1FFFh

Program

Memory

Page 0

Page 1

07FFh
0800h

0FFFh
1000h

Page 2

Page 3

17FFh
1800h

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F707/PIC16LF707 has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The Reset vector is at 0000h and the
interrupt vector is at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16F707/PIC16LF707

2.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.

RP1

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.

2.2.1 GENERAL PURPOSE REGISTER

The register file is organized as 363 x 8 bits. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing, INDF and FSR Registers”).

RP0

00 Bank 0 is selected
01 Bank 1 is selected
10 Bank 2 is selected
11 Bank 3 is selected

FILE

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (refer to Table 2-2).
These registers are static RAM.

The Special Function Registers can be classified into

 2010 Microchip Technology Inc. Preliminary DS41418A-page 17

two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.

PIC16F707/PIC16LF707

Legend: = Unimplemented data memory locations, read as ‘0’,

* = Not a physical register

File Address

Indirect addr.

(*)

00h Indirect addr.

(*)

80h Indirect addr.

(*)

100h Indirect addr.

(*)

180h

TMR0 01h OPTION 81h TMR0 101h OPTION 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h TACON 105h

ANSELA

185h

PORTB 06h TRISB 86h

CPSBCON0

106h

ANSELB

186h

PORTC 07h TRISC 87h

CPSBCON1

107h ANSELC 187h

PORTD 08h TRISD 88h

CPSACON0

108h

ANSELD

188h

PORTE 09h TRISE 89h

CPSACON1

109h

ANSELE

189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch

PIR2 0Dh PIE2 8Dh PMADRL 10Dh

Reserved 18Dh

TMR1L 0Eh PCON 8Eh PMDATH 10Eh

Reserved 18Eh

TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh

Reserved 18Fh

T1CON 10h OSCCON 90h TMRA 110h

General
Purpose
Register

16 Bytes

190h

TMR2 11h OSCTUNE 91h TBCON 111h 191h

T2CON 12h PR2 92h TMRB 112h 192h

SSPBUF 13h SSPADD/SSPMSK 93h DACCON0 113h 193h

SSPCON 14h SSPSTAT 94h DACCON1 114h 194h

CCPR1L 15h WPUB 95h

General
Purpose
Register
11 Bytes

115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h T3CON 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah TMR3L 9Ah 11Ah 19Ah

CCPR2L 1Bh TMR3H 9Bh 11Bh 19Bh

CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch

CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh

ADRES

1Eh T3GCON 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General
Purpose
Register
96 Bytes

20h

7Fh

General
Purpose
Register
80 Bytes

A0h

EFh

General
Purpose
Register

80 Bytes

120h

16Fh

General
Purpose
Register

80 Bytes

1A0h

1EFh

Accesses

70h – 7Fh

F0h

FFh

Accesses

70h – 7Fh

170h

17Fh

Accesses

70h – 7Fh

1F0h

1FFh

BANK 0 BANK 1 BANK 2 BANK 3

TABLE 2-1: DATA MEMORY MAP FOR PIC16F707/PIC16LF707

DS41418A-page 18 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

(2)

00h

01h TMR0 Timer0 Module Register 0000 0000 0000 0000

02h

03h

04h

05h PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h PORTE

0Ah

0Bh

0Ch PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

11h TMR2 Timer2 Module Register 0000 0000 0000 0000

12h T2CON

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transmit Data Register 0000 0000 0000 0000

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

1Dh CCP2CON

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

— — — — RE3 RE2 RE1 RE0 ---- xxxx ---- uuuu

— — — CCP2IF 0000 ---0 0000 ---0

—TMR1ON0000 00-0 uuuu uu-u

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

Val ue o n:

POR, BOR

Value on all

other

resets

 2010 Microchip Technology Inc. Preliminary DS41418A-page 19

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(2)

80h

81h OPTION_REG RBPU

82h

83h

84h

85h TRISA PORTA Data Direction Register 1111 1111 1111 1111

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h TRISD PORTD Data Direction Register 1111 1111 1111 1111

89h TRISE

8Ah

8Bh

8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE

8Eh PCON

8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

90h OSCCON

91h OSCTUNE

92h PR2 Timer2 Period Register 1111 1111 1111 1111

93h SSPADD Synchronous Serial Port (I

93h

94h SSPSTAT SMP CKE D/A

95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000

97h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0

98h TXSTA CSRC TX9 TXEN SYNC

99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

9Ah TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu

9Bh TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu

9Ch APFCON

9Dh FVRCON FVRRDY FVREN

9Eh T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/

9Fh ADCON1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

(3)

SSPMSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— — — — ‘1’ TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111

— — — CCP2IE 0000 ---0 0000 ---0

— — — — — —PORBOR ---- --qq ---- --uu

DONE

— — IRCF1 IRCF0 ICSL ICSS — — --10 00-- --10 uu--

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000

2

C mode) Address Register 0000 0000 0000 0000

PSR/WUA BF 0000 0000 0000 0000

— T3SYNC —TMR3ON0000 -0-0 uuuu -u-u

— BRGH TRMT TX9D 0000 -010 0000 -010

— — — — — — SSSEL CCP2SEL ---- --00 ---- --00

— — CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 x000 0000 x000 0000

DONE

— ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 -000 --00 -000 --00

T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

T3GVAL T3GSS1 T3GSS0 0000 0x00 uuuu uxuu

Val ue o n:

POR, BOR

Value on all

other

resets

DS41418A-page 20 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

(2)

100h

101h TMR0 Timer0 Module Register 0000 0000 0000 0000

102h

103h

104h

105h TACON TMRAON

106h CPSBCON0 CPSBON CPSBRM

107h CPSBCON1

108h CPSACON0 CPSAON CPSARM

109h CPSACON1

10Ah

10Bh

10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

10Dh PMADRL Program Memory Read Address Register Low Byte xxxx xxxx uuuu uuuu

10Eh PMDATH

10Fh PMADRH

110h TMRA TimerA Module Register 0000 0000 0000 0000

111h TBCON TMRBON

112h TMRB TimerB Module Register 0000 0000 0000 0000

113h DACCON0 DACEN DACLPS DACOE

114h DACCON1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

— TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000

— — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

— — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

— — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 0--- 0000 0--- 0000

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

— — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

— — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— — — Program Memory Read Address Register High Byte ---x xxxx ---u uuuu

— TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000

— DACPSS1 DACPSS0 — — 000- 00-- 000- 00--

— — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000

Val ue o n:

POR, BOR

Value on all

other

resets

 2010 Microchip Technology Inc. Preliminary DS41418A-page 21

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

(2)

180h

181h OPTION_REG RB

182h

183h

184h

185h ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111

186h ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111

187h ANSELC ANSC7 ANSC6 ANSC5

188h ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111

189h ANSELE

18Ah

18Bh

18Ch PMCON1

18Dh — Reserved — —

18Eh — Reserved — —

18Fh — Reserved — —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

PU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— — ANSC2 ANSC1 ANSC0 111- -111 111- -111

— — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

— — — — — — —RD1--- ---0 1--- ---0

Val ue o n:

POR, BOR

Value on all

other

resets

DS41418A-page 22 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 23.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow and

Digit Borrow
subtraction.

out bits, respectively, in

REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

(1)

C

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(1)

(1)

Note 1: For Borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 23

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

PIC16F707/PIC16LF707

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Bit Value Timer0 Rate WDT Rate

2.2.2.2 OPTION register

The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:

• Timer0/WDT prescaler

• External RB0/INT interrupt

•Timer0

• Weak pull-ups on PORTB

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by
setting PSA bit of the OPTION register to
‘1’. Refer to Section 13.3 “Timer1/3
Prescaler”.

bit 7 R

BPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual bits in the WPUB register

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 5 TMR0CS: Timer0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (F

OSC/4)

bit 4 TMR0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

DS41418A-page 24 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2.2.2.3 PCON Register

The Power Control (PCON) register contains flag bits
(refer to Table 3-4) to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

The PCON register bits are shown in Register 2-3.

REGISTER 2-3: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

)

: Power-on Reset Status bit

: Brown-out Reset Status bit

occurs)

 2010 Microchip Technology Inc. Preliminary DS41418A-page 25

PIC16F707/PIC16LF707

PC

12 8 7 0

5

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE<10:0>

8

PC

12 11 10 0

11

PCLATH<4:3>

PCH PCL

87

2

PCLATH

PCH PCL

PCL as

Destination

ORG 500h
PAGESEL SUB_P1 ;Select page 1

;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 900h ;page 1 (800h-FFFh)

SUB1_P1

: ;called subroutine

;page 1 (800h-FFFh)
:
RETURN ;return to

;Call subroutine

;in page 0

;(000h-7FFh)

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from
PCLATH. On any Reset, the PC is cleared. Figure 2-2
shows the two situations for the loading of the PC. The
upper example in Figure 2-2 shows how the PC is
loaded on a write to PCL (PCLATH<4:0>  PCH).
The lower example in Figure 2-2 shows how the PC is
loaded during a CALL or GOTO instruction
(PCLATH<4:3>  PCH).

FIGURE 2-2: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When
performing a table read using a computed GOTO
method, care should be exercised if the table location
crosses a PCL memory boundary (each 256-byte
block). Refer to Application Note AN556,
“Implementing a Table Read” (DS00556).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc­tions or the vectoring to an interrupt
address.

2.4 Program Memory Paging

All devices are capable of addressing a continuous 8K
word block of program memory. The CALL and GOTO
instructions provide only 11 bits of address to allow
branching within any 2K program memory page. When
doing a CALL or GOTO instruction, the upper 2 bits of
the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is POPed off the stack. Therefore,
manipulation of the PCLATH<4:3> bits is not required
for the RETURN instructions (which POPs the address
from the stack).

Note: The contents of the PCLATH register are

unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis­ter for any subsequent subroutine calls or
GOTO instructions.

Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine

EXAMPLE 2-1: CALL OF A SUBROUTINE

(if interrupts are used).

IN PAGE 1 FROM PAGE 0

2.3.2 STACK

All devices have an 8-level x 13-bit wide hardware
stack (refer to Figure 2-1). The stack space is not part
of either program or data space and the Stack Pointer
is not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an
interrupt causes a branch. The stack is POPed in the
event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.

The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).

DS41418A-page 26 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

MOVLW 020h ;initialize pointer
MOVWF FSR ;to RAM
BANKISEL 020h

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next

CONTINUE ;yes continue

Note: For memory map detail, refer to Table 2-2.

Data
Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1 RP0 6

0

From Opcode

IRP File Select Register

7

0

Bank Select

Location Select

00 01 10 11

180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-3.

A simple program to clear RAM location 020h-02Fh
using indirect addressing is shown in Example 2-2.

FIGURE 2-3: DIRECT/INDIRECT ADDRESSING

EXAMPLE 2-2: INDIRECT ADDRESSING

 2010 Microchip Technology Inc. Preliminary DS41418A-page 27

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 28 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

MCLR/VPP

VDD

OSC1/

WDT

Module

POR

OST/PWRT

WDTOSC

WDT
Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

11-bit Ripple Counter

Reset

Enable OST

Enable PWRT

Sleep

Brown-out

(1)

Reset

BOREN

CLKIN

Note 1: Refer to the Configuration Word Register 1 (Register 8-1).

MCLRE

3.0 RESETS

Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal

The PIC16F707/PIC16LF707 differentiates between
various kinds of Reset:

a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR
e) MCLR

Reset during normal operation
Reset during Sleep

f) Brown-out Reset (BOR)

operation. TO

and PD bits are set or cleared differently
in different Reset situations, as indicated in Table 3-3.
These bits are used in software to determine the nature
of the Reset.

A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.

The MCLR

Reset path has a noise filter to detect and

ignore small pulses. See Section 25.0 “Electrical
Specifications” for pulse width specifications.

Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:

• Power-on Reset (POR)

•MCLR

•MCLR

Reset
Reset during Sleep

•WDT Reset

• Brown-out Reset (BOR)

FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

 2010 Microchip Technology Inc. Preliminary DS41418A-page 29

PIC16F707/PIC16LF707

TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE

POR BOR TO PD Condition

0x11Power-on Reset or LDO Reset

0x0xIllegal, TO

0xx0Illegal, PD is set on POR

1011Brown-out Reset

1101WDT Reset

1100WDT Wake-up

11uuMCLR

1110MCLR

is set on POR

Reset during normal operation

Reset during Sleep or interrupt wake-up from Sleep

(1)

(2)

STATUS

Register

uuu1 0uuu ---- --uu

PCON

Register

TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 0000h 000u uuuu ---- --uu

Reset during Sleep 0000h 0001 0uuu ---- --uu

MCLR

WDT Reset 0000h 0000 1uuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 0000h 0001 1uuu ---- --u0

Interrupt Wake-up from Sleep PC + 1

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program
Counter

DS41418A-page 30 Preliminary  2010 Microchip Technology Inc.