PIC16F193X/LF193X
Data Sheet
28/40/44-Pin Flash-Based, 8-Bit
CMOS Microcontrollers wtih
LCD Driver and nanoWatt XLP Technology
2009 Microchip Technology Inc. Preliminary DS41364D
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC
32
logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS41364D-page 2 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
28/40/44-Pin Flash-Based, 8-Bit CMOS Microc ontrollers with
LCD Driver with nanoWatt XLP Technology
Devices Included In This Data Sheet:
PIC16F193X Devices:
• PIC16F1933 • PIC16F1934
• PIC16F1936 • PIC16F1937
• PIC16F1938 • PIC16F1939
PIC16LF193X Devices:
• PIC16LF1933 • PIC16LF1934
• PIC16LF1936 • PIC16LF1937
• PIC16LF1938 • PIC16LF1939
High-Performance RISC CPU:
• Only 49 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 32 MHz oscillator/clock input
- DC – 125 ns instruction cycle
• Up to 16K x 14 Words of Flash Program Memory
• Up to 1024 Bytes of Data Memory (RAM)
• Interrupt Capability with automatic context saving
• 16-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Processor Read Access to Program Memory
• Pinout Compatible to other 28/40-pin PIC16CXXX
and PIC16FXXX Microcontrollers
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
32 MHz to 31 kHz
• Power-Saving Sleep mode
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR)
- Selectable between two trip points
- Disable in Sleep option
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• High Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
• Wide Operating Voltage Range:
- 1.8V-5.5V (PIC16F193X)
- 1.8V-3.6V (PIC16LF193X)
PIC16LF193X Low-Power Features:
• Standby Current:
- 60 nA @ 1.8V, typical
• Operating Current:
-7.0A @ 32 kHz, 1.8V, typical (PIC16LF193X)
-150A @ 1 MHz, 1.8V, typical (PIC16LF193X)
• Timer1 Oscillator Current:
- 600 nA @ 32 kHz, 1.8V, typical
• Low-Power Watchdog Timer Current:
- 500 nA @ 1.8V, typical (PIC16LF193X)
Peripheral Features:
• Up to 35 I/O Pins and 1 Input-only pin:
- High-current source/sink for direct LED drive
- Individually programmable Interrupt-on-pin
change pins
- Individually programmable weak pull-ups
• Integrated LCD Controller:
- Up to 96 segments
- Variable clock input
- Contrast control
- Internal voltage reference selections
• Capacitive Sensing Module (mTouch
- Up to 16 selectable channels
• A/D Converter:
- 10-bit resolution and up to 14 channels
- Selectable 1.024/2.048/4.096V voltage
reference
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1
- Dedicated low-power 32 kHz oscillator driver
- 16-bit timer/counter with prescaler
- External Gate Input mode with toggle and
single shot modes
- Interrupt-on-gate completion
• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture, Compare, PWM Modules (CCP)
- 16-bit Capture, max. resolution 125 ns
- 16-bit Compare, max. resolution 125 ns
- 10-bit PWM, max. frequency 31.25 kHz
• Three Enhanced Capture, Compare, PWM
modules (ECCP)
- 3 PWM time-base options
- Auto-shutdown and auto-restart
- PWM steering
- Programmable Dead-band Delay
TM
)
2009 Microchip Technology Inc. Preliminary DS41364D-page 3
PIC16F193X/LF193X
Peripheral Features (Continued):
• Master Synchronous Serial Port (MSSP) with SPI
2
TM
C
and I
- 7-bit address masking
- SMBUS/PMBUSTM compatibility
- Auto-wake-up on start
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
• SR Latch (555 Timer):
- Multiple Set/Reset input options
- Emulates 555 Timer applications
• 2 Comparators:
- Rail-to-rail inputs/outputs
- Power mode control
- Software enable hysteresis
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
- 5-bit rail-to-rail resistive DAC with positive
with:
2.048V and 4.096V output levels
and negative reference selection
PIC16F193X/LF193X Family Types
Device
Flash (words)
Program Memory
PIC16F1933
PIC16LF1933
PIC16F1934
PIC16LF1934
PIC16F1936
PIC16LF1936
PIC16F1937
PIC16LF1937
PIC16F1938
PIC16LF1938
PIC16F1939
PIC16LF1939
Note 1: COM3 and SEG15 share the same physical pin on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore,
4096 256 256 25 11 8 2 4/1 Yes Yes 3 2 16
4096 256 256 36 14 16 2 4/1 Yes Yes 3 2 24/4
8192 256 512 25 11 8 2 4/1 Yes Yes 3 2 16
8192 256 512 36 14 16 2 4/1 Yes Yes 3 2 24/4
16384 256 1024 25 11 8 2 4/1 Yes Yes 3 2 16
16384 256 1024 36 14 16 2 4/1 Yes Yes 3 2 24/4
SEG15 is not available when using 1/4 multiplex displays.
Data EEPROM
(bytes)
SRAM (bytes)
I/O’s
(ch)
10-bit A/D
CapSense
(ch)
Timers
8/16-bit
Comparators
EUSART
C™/SPI
2
I
ECCP
CCP
LCD
(1)
/4
(1)
/4
(1)
/4
DS41364D-page 4 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
28-pin SPDIP, SOIC, SSOP
PIC16F1933/1936/1938
PIC16LF1933/1936/1938
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
SEG12/V
CAP
(2)
/SS
(1)
/SRNQ
(1)
/C2OUT
(1)
/C12IN0-/AN0/RA0
SEG7/C12IN1-/AN1/RA1
COM2/DACOUT/V
REF-/C2IN+/AN2/RA2
SEG15/COM3/V
REF+/C1IN+/AN3/RA3
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5/V
CAP
(2)
/SS
(1)
/SRNQ
(1)
/CPS7/C2OUT
(1)
/AN4/RA5
RB6/ICSPCLK/ICDCLK/SEG14
RB5/AN13/CPS5/P2B
(1)
/CCP3
(1)
/P3A
(1)
/T1G
(1)
/COM1
RB4/AN11/CPS4/P1D/COM0
RB3/AN9/C12IN2-/CPS3/CCP2
(1)
/P2A
(1)
/VLCD3
RB2/AN8/CPS2/P1B/VLCD2
RB1/AN10/C12IN3-/CPS1/P1C/VLCD1
RB0/AN12/CPS0/CCP4/SRI/INT/SEG0
V
DD
VSS
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
V
SS
SEG2/CLKIN/OSC1/RA7
SEG1/V
CAP
(2)
/CLKOUT/OSC2/RA6
P2B
(1)
/T1CKI/T1OSO/RC0
P2A
(1)
/CCP2
(1)
/T1OSI/RC1
SEG3/P1A/CCP1/RC2
SEG6/SCL/SCK/RC3
RC5/SDO/SEG10
RC4/SDI/SDA/T1G
(1)
/SEG11
RC7/RX/DT/P3B/SEG8
RC6/TX/CK/CCP3
(1)
/P3A
(1)
/SEG9
RB7/ICSPDAT/ICDDAT/SEG13
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
2009 Microchip Technology Inc. Preliminary DS41364D-page 5
PIC16F193X/LF193X
2
3
6
1
18
19
20
21
15
7
16
17
P2B
(1)
/T1CKI/T1OSO/RC0
5
4
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCLK/SEG14
RB5/AN13/CPS5/P2B
(1)
/CCP3
(1)
/P3A
(1)
/T1G
(1)
/COM1
RB4/AN11/CPS4/P1D/COM0
RB3/AN9/C12IN2-/CPS3/CCP2
(1)
/P2A
(1)
/VLCD3
RB2/AN8/CPS2/P1B/VLCD2
RB1/AN10/C12IN3-/CPS1/P1C/VLCD1
RB0/AN12/CPS0/CCP4/SRI/INT/SEG0
V
DD
VSS
RC7/RX/DT/P3B/SEG8
SEG9/P3A
(1)
/CCP3
(1)
/CK/TX/RC6
SEG10/SDO/RC5
SEG11/T1G
(1)
/SDA/SDI/RC4
RE3/MCLR
/VPP
RA0/AN0/C12IN0-/C2OUT
(1)
/SRNQ
(1)
/SS
(1)
/VCAP
(2)
/SEG12
RA1/AN1/C12IN1-/SEG7
COM2/DACOUT/VREF-/C2IN+/AN2/RA2
SEG15/COM3/V
REF+/C1IN+/AN3/RA3
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5
(1)
/VCAP
(2)
/SS
(1)
/SRNQ/CPS7/C2OUT
(1)
/AN4/RA5
V
SS
SEG2/CLKIN/OSC1/RA7
SEG1/V
CAP
(2)
/CLKOUT/OSC2/RA6
(1)
P2A/
(1)
CCP2/T1OSI/RC1
SEG3/P1A/CCP1/RC2
SEG6/SCL/SCK/RC3
9
10
13814
12
11
27
26
232822
24
25
PIC16F1933/1936/1938
PIC16LF1933/1936/1938
28-pin QFN/UQFN
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
Pin Diagram – 28-Pin QFN/UQFN (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
DS41364D-page 6 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
T ABLE 1: 28-PIN SUMMARY (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
I/O
28-Pin SIP
ANSEL
A/D
Cap Sense
Comparator
SR Latch
Timers
CCP
EUSART
MSSP
LCD
Pull-up
Interrupt
Basic
28-Pin QFN/UQFN
RA0 2 27 Y AN0 — C12IN0-/
C2OUT
SRNQ
(1)
SS
— — —
(1)
SEG12 — — VCAP
(1)
(2)
RA1 3 28 Y AN1 — C12IN1- — — — — — SEG7 — — —
RA2 4 1 Y AN2/
V
RA3 5 2 Y AN3/
V
REF+
REF-
— C2IN+/
DACOUT
— — — — — COM2 — — —
— C1IN+ — — — — — SEG15/
COM3
—— —
RA4 6 3 Y — CPS6 C1OUT SRQ T0CKI CCP5 — — SEG4 — — —
RA5 7 4 Y AN4 CPS7 C2OUT
(1)
RA6 10 7 — — — — — — — — — SEG1 — — OSC2/
RA7 9 6 — — — — — — — — — SEG2 — — OSC1/
RB0 21 18 Y AN12 CPS0 — SRI — CCP4 — — SEG0 INT/
SRNQ
(1)
———SS
(1)
SEG5 — — VCAP
CLKOUT
V
CAP
CLKIN
Y —
(2)
(2)
IOC
RB1 22 19 Y AN10 CPS1 C12IN3- — — P1C — — VLCD1 IOC Y —
RB2 23 20 Y AN8 CPS2 — — — P1B — — VLCD2 IOC Y —
RB3 24 21 Y AN9 CPS3 C12IN2- — — CCP2
P2A
(1)
/
— — VLCD3 IOC Y —
(1)
RB4 25 22 Y AN11 CPS4 — — — P1D — — COM0 IOC Y —
RB5 26 23 Y AN13 CPS5 — — T1G
(1)
RB6 27 24 — — — — — — — — — SEG14 IOC Y ICSPCLK/
P2B
CCP3
P3A
(1)
——COM1IOCY —
(1)
/
(1)
ICDCLK
RB7 28 25 — — — — — — — — — SEG13 IOC Y ICSPDAT/
ICDDAT
RC0 11 8 — — — — — T1OSO/
P2B
(1)
— — — — — —
T1CKI
(1)
/
RC1 12 9 — — — — — T1OSI CCP2
P2A
RC2 13 10 — — — — — — CCP1/
—— ——— —
(1)
— — SEG3 — — —
P1A
RC3 14 11 — — — — — — — — SCK/SCL SEG6 — — —
RC4 15 12 — — — — — T1G
(1)
— — SDI/SDA SEG11 — — —
RC51613———— —— — —SDOSEG10—— —
RC6 17 14 — — — — — — CCP3
P3A
(1)
TX/CK — SEG9 — — —
(1)
RC7 18 15 — — — — — — P3B RX/DT — SEG8 — — —
RE3126———— —— — —— ——YMCLR
/VPP
VDD 20 17 — — — — — — — — — — — — VDD
Vss 8,195,16———— —— — —— ——— VSS
Note 1: Pin functions can be moved using the APFCON register.
2: PIC16F193X devices only.
2009 Microchip Technology Inc. Preliminary DS41364D-page 7
PIC16F193X/LF193X
40-Pin PDIP
PIC16F1934/1937/1939
PIC16LF1934/1937/1939
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
SEG12/V
CAP
(2)
/SS
(1)
/SRNQ
(1)
/C2OUT
(1)
/C12IN0-/AN0/RA0
SEG7/C12IN1-/AN1/RA1
COM2/DACOUT/V
REF-/C2IN+/AN2/RA2
SEG15/V
REF+/C1IN+/AN3/RA3
SEG4/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5/V
CAP
(2)
/SS
(1)
/SRNQ
(1)
/CPS7/C2OUT
(1)
/AN4/RA5
SEG21/CCP3
(1)
/P3A
(1)
/AN5/RE0
SEG22/P3B/AN6/RE1
SEG23/CCP5/AN7/RE2
RB6/ICSPCLK/ICDCLK/SEG14
RB5/AN13/CPS5/CCP3
(1)
/P3A
(1)
/T1G
(1)
/COM1
RB4/AN11/CPS4/COM0
RB3/AN9/C12IN2-/CPS3/CCP2
(1)
/P2A
(1)
/VLCD3
RB2/AN8/CPS2/VLCD2
RB1/AN10/C12IN3-/CPS1/VLCD1
RB0/AN12/CPS0/SRI/INT/SEG0
V
DD
VSS
RD2/CPS10/P2B
(1)
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
VSS
SEG2/CLKIN/OSC1/RA7
SEG1/V
CAP
(2)
/CLKOUT/OSC2/RA6
P2B
(1)
/T1CKI/T1OSO/RC0
P2A
(1)
/CCP2
(1)
/T1OSI/RC1
SEG3/P1A/CCP1/RC2
SEG6/SCK/SCL/RC3
COM3/CPS8/RD0
CCP4/CPS9/RD1
RC5/SDO/SEG10
RC4/SDI/SDA/T1G
(1)
/SEG11
RD3/CPS11/P2C/SEG16
RD4/CPS12/P2D/SEG17
RC7/RX/DT/SEG8
RC6/TX/CK/SEG9
RD7/CPS15/P1D/SEG20
RD6/CPS14/P1C/SEG19
RD5/CPS13/P1B/SEG18
RB7/ICSPDAT/ICDDAT/SEG13
1
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
Pin Diagram – 40-Pin PDIP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
DS41364D-page 8 Preliminary 2009 Microchip Technology Inc.
10
11
2
3
4
5
6
1
181920
21
22
121314
15
38
8
7
4443424140
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
37
SEG7/C12IN1-/AN1/RA1
SEG12/V
CAP
(2)
/SS
(1)
/SRNQ
(1)
/C2OUT
(1)
/C12IN0-/AN0/RA0
V
PP/MCLR/RE3
VLCD3/P2A
(1)
/CCP2
(1)
/CPS3/C12IN2-/AN9/RB3
SEG13/ICDDAT/ICSPDAT/RB7
SEG14/ICDCLK/ICSPCLK/RB6
COM1/T1G
(1)
/P3A
(1)
/CCP3
(1)
/CPS5/AN13/RB5
COM0/CPS4/AN11/RB4
NC
RC6/TX/CK/SEG9
RC5/SDO/SEG10
RC4/SDI/SDA/T1G
(1)
/SEG11
RD3/CPS11/P2C/SEG16
RD2/CPS10/P2B
(1)
RD1/CPS9/CCP4
RD0/CPS8/COM3
RC3/SCL/SCK/SEG6
RC2/CCP1/P1A/SEG3
RC1/T1OSI/CCP2
(1)
/P2A
(1)
RC0/T1OSO/T1CKI/P2B
(1)
RA6/OSC2/CLKOUT/VCAP
(2)
/SEG1
RA7/OSC1/CLKIN/SEG2
V
SS
VSS
NC
V
DD
RE2/AN7/CCP5/SEG23
RE1/AN6/P3B/SEG22
RE0/AN5/CCP3
(1)
/P3A
(1)
/SEG21
RA5/AN4/C2OUT
(1)
/CPS7/SRNQ
(1)
/SS
(1)
/VCAP
(2)
/SEG5
RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
SEG8/DT/RX/RC7
SEG17/P2D/CPS12/RD4
SEG18/P1B/CPS13/RD5
SEG19/P1C/CPS14/RD6
SEG20/P1D/CPS15/RD7
V
SS
VDD
VDD
SEG0/INT/SRI/CPS0/AN12/RB0
VLCD1/CPS1/C12IN3-/AN10/RB1
VLCD2/CPS2/AN8/RB2
44-pin QFN
PIC16F1934/1937/1939
PIC16LF1934/1937/1939
SEG15VREF+/C1IN+/AN3/RA3
COM2/DACOUT/V
REF-/C2IN+/AN2/RA2
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
PIC16F193X/LF193X
Pin Diagram – 44-Pin QFN (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
2009 Microchip Technology Inc. Preliminary DS41364D-page 9
PIC16F193X/LF193X
44-pin TQFP
10
11
2
3
6
1
1819202122
121314
15
38
8
7
44
43
42
414039
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
37
SEG15/VREF+/C1IN+/AN3/RA3
COM2/DACOUT/V
REF-/C2IN+/AN2/RA2
SEG7/C12IN1-/AN1/RA1
SEG12/V
CAP
(2)
/SS
(1)
/SRNQ
(1)
/C2OUT
(1)
/C12IN0-/AN0/RA0
VPP/MCLR/RE3
NC
SEG13/ICDDAT/ICSPDAT/RB7
SEG14/ICDCLK/ICSPCLK/RB6
COM1/T1G
(1)
/P3A
(1)
/CCP3
(1)
/CPS5/AN13/RB5
COM0/CPS4/AN11/RB4
NC
NC
NC
RC0/T1OSO/T1CKI/P2B
(1)
VSS
VDD
SEG0/INT/SRI/CPS0/AN12/RB0
VLCD1/CPS1/C12IN3-/AN10/RB1
VLCD2/CPS2/AN8/RB2
VLCD3/P2A
(1)
/CCP2
(1)
/CPS3/C12IN2-/AN9/RB3
5
4
PIC16F1934/1937/1939
PIC16LF1934/1937/1939
RA6/OSC2/CLKOUT/VCAP
(2)
/SEG1
RA7/OSC1/CLKIN/SEG2
V
SS
VDD
RE2/AN7/CCP5/SEG23
RE1/AN6/P3B/SEG22
RE0/AN5/CCP3
(1)
/P3A
(1)
/SEG21
RA5/AN4/C2OUT
(1)
/CPS7/SRNQ
(1)
/SS
(1)
/VCAP
(2)
/SEG5
RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
SEG8/DT/RX/RC7
SEG17/P2D/CPS12/RD4
SEG18/P1B/CPS13/RD5
SEG19/P1C/CPS14/RD6
SEG20/P1D/CPS15/RD7
RC6/TX/CK/SEG9
RC5/SDO/SEG10
RC4/SDI/SDA/T1G
(1)
/SEG11
RD3/CPS11/P2C/SEG16
RD2/CPS10/P2B
(1)
RD1/CPS9/CCP4
RD0/CPS8/COM3
RC3/SCL/SCK/SEG6
RC2/CCP1/P1A/SEG3
RC1/T1OSI/CCP2
(1)
/P2A
(1)
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
Pin Diagram – 44-Pin TQFP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
DS41364D-page 10 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
T ABLE 2: 40/44-PIN SUMMARY(PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
I/O
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
RA0 2 19 19 Y AN0 — C12IN0-/
ANSEL
A/D
SRNQ
SR Latch
(1)
Cap Sense
C2OUT
Comparator
(1)
Timers
— — —
CCP
EUSART
SS
MSSP
(1)
LCD
Pull-up
Interrupt
SEG12 — — VCAP
Basic
RA1 3 20 20 Y AN1 — C12IN1- — — — — — SEG7 — — —
RA2 4 21 21 Y AN2/
V
RA3 5 22 22 Y AN3/
V
— C2IN+/
REF-
REF+
DACOUT
— C1IN+ — — — — — SEG15 — — —
— — — — — COM2 — — —
RA4 6 23 23 Y — CPS6 C1OUT SRQ T0CKI — — SEG4 — — —
RA5 7 24 24 Y AN4 CPS7 C2OUT
(1)
SRNQ
(1)
———SS
(1)
SEG5 — — VCAP
RA6 14 31 33 — — — — — — — — — SEG1 — — OSC2/
CLKOUT
CAP
V
RA7 13 30 32 — — — — — — — — — SEG2 — — OSC1/
RB0 33 8 9 Y AN12 CPS0 — SRI — — — — SEG0 INT/
CLKIN
Y —
IOC
RB1 34 9 10 Y AN10 CPS1 C12IN3- — — — — — VLCD1 IOC Y —
RB2 35 10 11 Y AN8 CPS2 — — — — — — VLCD2 IOC Y —
RB3 36 11 12 Y AN9 CPS3 C12IN2- — — CCP2
P2A
(1)
/
— — VLCD3 IOC Y —
(1)
RB4 37 14 14 Y AN11 CPS4 — — — — — — COM0 IOC Y —
RB5 38 15 15 Y AN13 CPS5 — — T1G
(1)
CCP3
P3A
(1)
/
——COM1IOCY—
(1)
RB6 39 16 16 — — — — — — — — — SEG14 IOC Y ICSPCLK/
ICDCLK
RB7 40 17 17 — — — — — — — — — SEG13 IOC Y ICSPDAT/
ICDDAT
RC0 15 32 34 — — — — — T1OSO/
T1CKI
RC1 16 35 35 — — — — — T1OSI CCP2
RC2 17 36 36 — — — — — — CCP1/
P2B
P2A
(1)
— — — — — —
(1)
/
—— ————
(1)
— — SEG3 — — —
P1A
RC3 18 37 37 — — — — — — — — SCK/SCL SEG6 — — —
RC4 23 42 42 — — — — — T1G
(1)
— — SDI/SDA SEG11 — — —
RC5 24 43 43 — — — — — — — — SDO SEG10 — — —
RC6 25 44 44 — — — — — — — TX/CK — SEG9 — — —
RC7 26 1 1 — — — — — — — RX/DT — SEG8 — — —
RD0 19 38 38 Y — CPS8 — — — — — — COM3 — — —
RD1 20 39 39 Y — CPS9 — — — CCP4 — — — — — —
RD2 21 40 40 Y — CPS10 — — — P2B
(1)
— — — — — —
RD3 22 41 41 Y — CPS11 — — — P2C — — SEG16 — — —
RD4 27 2 2 Y — CPS12 — — — P2D — — SEG17 — — —
RD5 28 3 3 Y — CPS13 — — — P1B — — SEG18 — — —
RD6 29 4 4 Y — CPS14 — — — P1C — — SEG19 — — —
RD7 30 5 5 Y — CPS15 — — — P1D — — SEG20 — — —
RE0 8 25 25 Y AN5 — — — — CCP3
P3A
(1)
— — SEG21 — — —
(1)
RE1 9 26 26 Y AN6 — — — — P3B — — SEG22 — — —
RE2 10 27 27 Y AN7 — — — — CCP5 — — SEG23 — — —
RE3 1 18 18 — — — — — — — — — — — Y MCLR
VDD 11,327,287,8,
— — — — — — — — — — — — VDD
/VPP
28
Vss 12,316,296,30,31—— — — — — — — — — — — VSS
Note 1: Pin functions can be moved using the APFCON register.
2009 Microchip Technology Inc. Preliminary DS41364D-page 11
PIC16F193X/LF193X
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 23
3.0 Memory Organization ................................................................................................................................................................. 25
4.0 Device Configuration.................................................................................................................................................................. 63
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 69
6.0 Resets ........................................................................................................................................................................................ 85
7.0 Interrupts .................................................................................................................................................................................... 93
8.0 Low Dropout (LDO) Voltage Regulator .................................................................................................................................... 107
9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 109
10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 111
11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 115
12.0 I/O Ports ................................................................................................................................................................................... 129
13.0 Interrupt-On-Change ................................................................................................................................................................ 149
14.0 Fixed Voltage Reference .......................................................................................................................................................... 153
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 155
16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 169
17.0 Comparator Module.................................................................................................................................................................. 175
18.0 SR Latch................................................................................................................................................................................... 183
19.0 Timer0 Module ......................................................................................................................................................................... 189
20.0 Timer1 Module with Gate Control............................................................................................................................................. 193
21.0 Timer2/4/6 Modules.................................................................................................................................................................. 205
22.0 Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5) .......................................................................... 209
23.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 237
24.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 289
25.0 Capacitive Sensing Module ...................................................................................................................................................... 317
26.0 Liquid Crystal Display (LCD) Driver Module ............................................................................................................................. 327
27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 361
28.0 Instruction Set Summary.......................................................................................................................................................... 365
29.0 Electrical Specifications (PIC16F/LF1933) ............................................................................................................................... 379
30.0 Electrical Specifications (PIC16F/LF1934/36/37) ..................................................................................................................... 411
31.0 Electrical Specifications (PIC16F/LF1938/39) .......................................................................................................................... 443
32.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 475
33.0 Development Support............................................................................................................................................................... 477
34.0 Packaging Information.............................................................................................................................................................. 481
Appendix A: Data Sheet Revision History .......................................................................................................................................... 495
Appendix B: Migrating From Other PIC
Index .................................................................................................................................................................................................. 497
The Microchip Web Site..................................................................................................................................................................... 505
Customer Change Notification Service .............................................................................................................................................. 505
Customer Support .............................................................................................................................................................................. 505
Reader Response .............................................................................................................................................................................. 506
Product Identification System............................................................................................................................................................. 507
®
Devices.............................................................................................................................. 495
DS41364D-page 12 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
TO OUR VALUED CUSTOMERS
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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2009 Microchip Technology Inc. Preliminary DS41364D-page 13
PIC16F193X/LF193X
NOTES:
DS41364D-page 14 Preliminary 2009 Microchip Technology Inc.
1.0 DEVICE OVERVIEW
The PIC16F193X/LF193X are described within this
data sheet. They are available in 28/40/44-pin packages. Figure 1-1 shows a block diagram of the
PIC16F193X/LF193X devices. Table 1-2 shows the
pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16F193X/LF193X
PIC16F193X
ADC ●●
Capacitive Sensing Module ●●
Digital-to-Analog Converter (DAC) ●●
EUSART ●●
Fixed Voltage Reference (FVR) ●●
LCD ●●
SR Latch ●●
Capture/Compare/PWM Modules
ECCP1 ●●
ECCP2 ●●
ECCP3 ●●
CCP4 ●●
CCP5 ●●
Comparators
C1 ●●
C2 ●●
Master Synchronous Serial Ports
MSSP1 ●●
Timers
Timer0 ●●
Timer1 ●●
Timer2 ●●
Timer4 ●●
Timer6 ●●
PIC16LF193X
2009 Microchip Technology Inc. Preliminary DS41364D-page 15
PIC16F193X/LF193X
PORTA
EUSART
Comparators
MSSP
Timer2Timer1 Timer4Timer0
ECCP1
ADC
10-Bit
ECCP2 ECCP3 CCP4 CCP5
Timer6
PORTB
PORTC
PORTD
PORTE
LCD
SR
Latch
Note 1: See applicable chapters for more information on peripherals.
CPU
Program
Flash Memory
EEPROM
RAM
Timing
Generation
INTRC
Oscillator
MCLR
Figure 2-1
OSC1/CLKI
OSC2/CLKO
FIGURE 1-1: PIC16F193X/LF193X BLOCK DIAGRAM
DS41364D-page 16 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
T ABLE 1-2: PIC16F193X/LF193X PINOUT DESCRIPTION
Input
Name Function
RA0/AN0/C12IN0-/C2OUT
(1)
(1)
/SS
SRNQ
/VCAP
(2)
/SEG12
(1)
/
RA0 TTL CMOS General purpose I/O.
AN0 AN — A/D Channel 0 input.
C12IN0-
C2OUT — CMOS Comparator C2 output.
SRNQ — CMOS SR Latch inverting output.
SS
CAP Power Power Filter capacitor for Voltage Regulator (PIC16F193X only).
V
SEG12 — AN LCD Analog output.
RA1/AN1/C12IN1-/SEG7 RA1 TTL CMOS General purpose I/O.
AN1 AN — A/D Channel 1 input.
C12IN1-
SEG7 — AN LCD Analog output.
RA2/AN2/C2IN+/V
DACOUT/COM2
REF-/
RA2 TTL CMOS General purpose I/O.
AN2 AN — A/D Channel 2 input.
C2IN+
VREF- AN — A/D Negative Voltage Reference input.
DACOUT — AN Voltage Reference output.
COM2 — AN LCD Analog output.
RA3/AN3/C1IN+/V
(3)
COM3
/SEG15
REF+/
RA3 TTL CMOS General purpose I/O.
AN3 AN — A/D Channel 3 input.
C1IN+
VREF+ AN — A/D Voltage Reference input.
(3)
COM3
SEG15 — AN LCD Analog output.
RA4/C1OUT/CPS6/T0CKI/SRQ/
CCP5/SEG4
RA4 TTL CMOS General purpose I/O.
C1OUT — CMOS Comparator C1 output.
CPS6 AN — Capacitive sensing input 6.
T0CKI ST — Timer0 clock input.
SRQ
CCP5 ST CMOS Capture/Compare/PWM5.
SEG4 — AN LCD Analog output.
RA5/AN4/C2OUT
(1)
(1)
/SS
SRNQ
/VCAP
(1)
/CPS7/
(2)
/SEG5
RA5 TTL CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
C2OUT — CMOS Comparator C2 output.
CPS7 AN — Capacitive sensing input 7.
SRNQ — CMOS SR Latch inverting output.
SS
V
CAP Power Power Filter capacitor for Voltage Regulator (PIC16F193X only).
SEG5 — AN LCD Analog output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
3: PIC16F/LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F/LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only.
Output
Type
Type
AN — Comparator C1 or C2 negative input.
Description
ST — Slave Select input.
AN — Comparator C1 or C2 negative input.
AN — Comparator C2 positive input.
AN — Comparator C1 positive input.
— AN LCD Analog output.
— CMOS SR Latch non-inverting output.
ST — Slave Select input.
2
C™ = Schmitt Trigger input with I2C
2009 Microchip Technology Inc. Preliminary DS41364D-page 17
PIC16F193X/LF193X
TABLE 1-2: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RA6/OSC2/CLKOUT/V
SEG1
RA7/OSC1/CLKIN/SEG2 RA7 TTL CMOS General purpose I/O.
RB0/AN12/CPS0/CCP4/SRI/INT/
SEG0
RB1/AN10/C12IN3-/CPS1/P1C/
VLCD1
RB2/AN8/CPS2/P1B/VLCD2 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB3/AN9/C12IN2-/CPS3/
(1)
(1)
/P2A
CCP2
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
Note 1: Pin function is selectable via the APFCON register.
/VLCD3
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: PIC16F193X devices only.
3: PIC16F/LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F/LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only.
CAP
(2)
/
RA6 TTL CMOS General purpose I/O.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS F
CAP Power Power Filter capacitor for Voltage Regulator (PIC16F193X only).
V
SEG1 — AN LCD Analog output.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN CMOS — External clock input (EC mode).
SEG2 — AN LCD Analog output.
RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN12 AN — A/D Channel 12 input.
CPS0 AN — Capacitive sensing input 0.
CCP4 ST CMOS Capture/Compare/PWM4.
SRI — ST SR Latch input.
INT ST — External interrupt.
SEG0 — AN LCD analog output.
RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN10 AN — A/D Channel 10 input.
C12IN3-
CPS1 AN — Capacitive sensing input 1.
P1C — CMOS PWM output.
VLCD1 AN — LCD analog input.
AN8 AN — A/D Channel 8 input.
CPS2 AN — Capacitive sensing input 2.
P1B — CMOS PWM output.
VLCD2 AN — LCD analog input.
RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN9 AN — A/D Channel 9 input.
C12IN2-
CPS3 AN — Capacitive sensing input 3.
CCP2 ST CMOS Capture/Compare/PWM2.
P2A — CMOS PWM output.
VLCD3 AN — LCD analog input.
Output
Type
Type
OSC/4 output.
Individually enabled pull-up.
Individually enabled pull-up.
AN — Comparator C1 or C2 negative input.
Individually enabled pull-up.
Individually enabled pull-up.
AN — Comparator C1 or C2 negative input.
Description
2
C™ = Schmitt Trigger input with I2C
DS41364D-page 18 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
T ABLE 1-2: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RB4/AN11/CPS4/P1D/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN11 AN — A/D Channel 11 input.
CPS4 AN — Capacitive sensing input 4.
P1D — CMOS PWM output.
COM0 — AN LCD Analog output.
(1)
/
RB5/AN13/CPS5/P2B/CCP3
(1)
P3A
RB6/ICSPCLK/ICDCLK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/T1OSO/T1CKI/P2B
RC1/T1OSI/CCP2
RC2/CCP1/P1A/SEG3 RC2 ST CMOS General purpose I/O.
RC3/SCK/SCL/SEG6 RC3 ST CMOS General purpose I/O.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
Note 1: Pin function is selectable via the APFCON register.
(1)
/T1G
/COM1
(1)
(1)
(1)
/P2A
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: PIC16F193X devices only.
3: PIC16F/LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F/LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only.
RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN13 AN — A/D Channel 13 input.
CPS5 AN — Capacitive sensing input 5.
P2B — CMOS PWM output.
CCP3 ST CMOS Capture/Compare/PWM3.
P3A — CMOS PWM output.
T1G ST — Timer1 Gate input.
COM1 — AN LCD Analog output.
ICSPCLK ST — Serial Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
SEG14 — AN LCD Analog output.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST CMOS In-Circuit Data I/O.
SEG13 — AN LCD Analog output.
RC0 ST CMOS General purpose I/O.
T1OSO XTAL XTAL Timer1 oscillator connection.
T1CKI ST — Timer1 clock input.
P2B — CMOS PWM output.
RC1 ST CMOS General purpose I/O.
T1OSI XTAL XTAL Timer1 oscillator connection.
CCP2 ST CMOS Capture/Compare/PWM2.
P2A — CMOS PWM output.
CCP1 ST CMOS Capture/Compare/PWM1.
P1A — CMOS PWM output.
SEG3 — AN LCD Analog output.
SCK ST CMOS SPI clock.
SCL I
SEG6 — AN LCD Analog output.
Output
Type
Type
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
2
CODI2C™ clock.
Description
2
C™ = Schmitt Trigger input with I2C
2009 Microchip Technology Inc. Preliminary DS41364D-page 19
PIC16F193X/LF193X
TABLE 1-2: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RC4/SDI/SDA/T1G
RC5/SDO/SEG10 RC5 ST CMOS General purpose I/O.
RC6/TX/CK/CCP3/P3A/SEG9 RC6 ST CMOS General purpose I/O.
RC7/RX/DT/P3B/SEG8 RC7 ST CMOS General purpose I/O.
(4)
/CPS8/COM3 RD0 ST CMOS General purpose I/O.
RD0
(4)
/CPS9/CCP4 RD1 ST CMOS General purpose I/O.
RD1
(4)
/CPS10/P2B RD2 ST CMOS General purpose I/O.
RD2
(4)
/CPS11/P2C/SEG16 RD3 ST CMOS General purpose I/O.
RD3
(4)
/CPS12/P2D/SEG17 RD4 ST CMOS General purpose I/O.
RD4
(4)
/CPS13/P1B/SEG18 RD5 ST CMOS General purpose I/O.
RD5
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
Note 1: Pin function is selectable via the APFCON register.
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: PIC16F193X devices only.
3: PIC16F/LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F/LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only.
(1)
/SEG11 RC4 ST CMOS General purpose I/O.
SDI ST — SPI data input.
SDA I
T1G ST — Timer1 Gate input.
SEG11 — AN LCD Analog output.
SDO — CMOS SPI data output.
SEG10 — AN LCD Analog output.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
CCP3 ST CMOS Capture/Compare/PWM3.
P3A — CMOS PWM output.
SEG9 — AN LCD Analog output.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
P3B — CMOS PWM output.
SEG8 — AN LCD Analog output.
CPS8 AN — Capacitive sensing input 8.
COM3 — AN LCD analog output.
CPS9 AN — Capacitive sensing input 9.
CCP4 ST CMOS Capture/Compare/PWM4.
CPS10 AN — Capacitive sensing input 10.
P2B — CMOS PWM output.
CPS11 AN — Capacitive sensing input 11.
P2C — CMOS PWM output.
SEG16 — AN LCD analog output.
CPS12 AN — Capacitive sensing input 12.
P2D — CMOS PWM output.
SEG17 — AN LCD analog output.
CPS13 AN — Capacitive sensing input 13.
P1D — CMOS PWM output.
SEG18 — AN LCD analog output.
Output
Type
Type
2
CODI2C™ data input/output.
Description
2
C™ = Schmitt Trigger input with I2C
DS41364D-page 20 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
T ABLE 1-2: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
(4)
RD6
/CPS14/P1C/SEG19 RD6 ST CMOS General purpose I/O.
CPS14 AN — Capacitive sensing input 14.
P1C — CMOS PWM output.
SEG19 — AN LCD analog output.
(4)
/CPS15/P1D/SEG20 RD7 ST CMOS General purpose I/O.
RD7
CPS15 AN — Capacitive sensing input 15.
P1D — CMOS PWM output.
SEG20 — AN LCD analog output.
(5)
RE0
SEG21
/AN5/P3A
(1)
/CCP3
(1)
/
RE0 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
P3A — CMOS PWM output.
CCP3 ST CMOS Capture/Compare/PWM3.
SEG21 — AN LCD analog output.
(5)
/AN6/P3B/SEG22 RE1 ST CMOS General purpose I/O.
RE1
AN6 AN — A/D Channel 6 input.
P3B — CMOS PWM output.
SEG22 — AN LCD analog output.
(5)
/AN7/CCP5/SEG23 RE2 ST CMOS General purpose I/O.
RE2
AN7 AN — A/D Channel 7 input.
CCP5 ST CMOS Capture/Compare/PWM5.
SEG23 — AN LCD analog output.
RE3/MCLR
/VPP RE3 TTL — General purpose input.
MCLR
PP HV — Programming voltage.
V
DD VDD Power — Positive supply.
V
V
SS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
3: PIC16F/LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F/LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only.
Type
Output
Type
Description
ST — Master Clear with internal pull-up.
2
C™ = Schmitt Trigger input with I2C
2009 Microchip Technology Inc. Preliminary DS41364D-page 21
PIC16F193X/LF193X
NOTES:
DS41364D-page 22 Preliminary 2009 Microchip Technology Inc.
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, indirect, and relative
addressing modes are available. Two File Select
Registers (FSRs) provide the ability to read program
and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1 Automatic Interrupt Context Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
PIC16F193X/LF193X
2.2 16-level Stack with Overflow and Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 “St ack” for more
details.
2.3 File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one data pointer for all memory. When an
FSR points to program memory, there is 1 additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 28.0 “Instruction Set Summary” for more
details.
2009 Microchip Technology Inc. Preliminary DS41364D-page 23
PIC16F193X/LF193X
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
9
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
V
DD
8
8
Brown-out
Reset
12
3
VSS
Internal
Oscillator
Block
Configuration
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W reg
Instruction
Decode &
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
15
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr
7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FIGURE 2-1: CORE BLOCK DIAGRAM
DS41364D-page 24 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
3.0 MEMORY ORGANIZATION
There are three types of memory in
PIC16F193X/LF193X devices: Data Memory, Program
Memory and Data EEPROM Memory
• Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
- Device Memory Maps
- Special Function Registers Summary
• Data EEPROM memory
Note 1: The Data EEPROM Memory and the
method to access Flash memory through
the EECON registers is described in
Section 11.0 “Data EEPROM and Flash
Program Memory Control”.
(1)
(1)
.
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16F193X/LF193X family.
Accessing a location above these boundaries will cause
a wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1, 3-2 and 3-3).
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words) Last Program Memory Address
PIC16F1933
PIC16F1934/PIC16LF1934 4,096 0FFFh
PIC16F1936/PIC16LF1936 8,192 1FFFh
PIC16F1937
PIC16F1938/PIC16LF1938 16,384 3FFFh
PIC16F1939/PIC16LF1939 16,384 3FFFh
/PIC16LF1933 4,096 0FFFh
/PIC16LF1937 8,192 1FFFh
2009 Microchip Technology Inc. Preliminary DS41364D-page 25
PIC16F193X/LF193X
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
CALL, CALLW
RETURN, RETLW
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh
1000h
7FFFh
Page 1
Rollover to Page 1
Interrupt, RETFIE
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh
1000h
7FFFh
Page 1
Rollover to Page 3
Page 2
Page 3
17FFh
1800h
1FFFh
2000h
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
4KW PARTS
FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR
8KW PARTS
DS41364D-page 26 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh
1000h
7FFFh
Page 1
Rollover to Page 7
Page 2
Page 3
17FFh
1800h
1FFFh
2000h
Page 4
Page 7
3FFFh
4000h
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
constants
brw ;Add Index in W to
;program counter to
;select data
retlw DATA0 ;Index0 data
retlw DATA1 ;Index1 data
retlw DATA2
retlw DATA3
my_function
;… LOTS OF CODE…
movlw DATA_INDEX
call constants
;… THE CONSTANT IS IN W
FIGURE 3-3: PROGRAM MEMORY MAP
AND STACK FOR
16KW PARTS
3.1.1 READING PROGRAM MEMORY AS DATA
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
The BRW instruction makes this type of table very simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
2009 Microchip Technology Inc. Preliminary DS41364D-page 27
PIC16F193X/LF193X
constants
retlw DATA0 ;Index0 data
retlw DATA1 ;Index1 data
retlw DATA2
retlw DATA3
my_function
;… LOTS OF CODE…
movlw LOW constants
movwf FSR1L
movlw HIGH constants
movwf FSR1H
moviw 0[INDF1]
;THE PROGRAM MEMORY IS IN W
3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the program memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
3.2.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation of the PIC16F193X/LF193X.
These registers are listed below:
• INDF0
• INDF1
•PCL
•STATUS
•FSR0 Low
• FSR0 High
•FSR1 Low
• FSR1 High
• BSR
•WREG
•PCLATH
• INTCON
Note: The core registers are the first 12
addresses of every data memory bank.
3.2 Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-4):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
DS41364D-page 28 Preliminary 2009 Microchip Technology Inc.
PIC16F193X/LF193X
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 28.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow and
Digit Borrow
subtraction.
out bits, respectively, in
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TO
PD ZDC
(1)
(1)
C
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Digit Borrow
bit 0 C: Carry/Borrow
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
(1)
(1)
2009 Microchip Technology Inc. Preliminary DS41364D-page 29
PIC16F193X/LF193X
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset
3.2.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The registers associated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
3.2.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank.
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-4: BANKED MEMORY
PARTITIONING
3.2.5 DEVICE MEMORY MAPS
The memory maps for the device family are as shown
in Table 3-2.
TABLE 3-2: MEMORY MAP TABLES
Device Banks Table No.
PIC16F1933
PIC16LF1933
PIC16F1934
PIC16LF1934
PIC16F1936
PIC16LF1936
PIC16F1937
PIC16LF1937
PIC16F1938
PIC16LF1938
PIC16F1939
PIC16LF1939
0-7 Table 3-3
8-15 Table 3-4,Table 3-11
16-23 Table 3-9
23-31 Table 3-10, Table 3-13
0-7 Table 3-3
8-15 Table 3-4,Table 3-12
16-23 Table 3-9
23-31 Table 3-10, Table 3-13
0-7 Table 3-5
8-15 Table 3-6, Table 3-11
16-23 Table 3-9
23-31 Table 3-10, Table 3-13
0-7 Table 3-5
8-15 Table 3-6, Table 3-12
16-23 Table 3-9
23-31 Table 3-10, Table 3-13
0-7 Table 3-7
8-15 Table 3-8, Table 3-11
16-23 Table 3-9
23-31 Table 3-10, Table 3-13
0-7 Table 3-7
8-15 Table 3-8, Table 3-12
16-23 Table 3-9
23-31 Table 3-10, Table 3-13
DS41364D-page 30 Preliminary 2009 Microchip Technology Inc.
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