PIC16(L)F1933
28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
LCD Driver with XLP Technology
High-Performance RISC CPU:
• Only 49 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 32 MHz oscillator/clock input
- DC – 125 ns instruction cycle
• Up to 16K x 14 Words of Flash Program Memory
• Up to 1024 Bytes of Data Memory (RAM)
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Processor Read Access to Program Memory
• Pinout Compatible to other 28-pin PIC16CXXX
and PIC16FXXX Microcontrollers
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
32 MHz to 31 kHz
• Power-Saving Sleep mode
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR)
- Selectable between two trip points
- Disable in Sleep option
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• Wide Operating Voltage Range:
- 1.8V-5.5V (PIC16F1933)
- 1.8V-3.6V (PIC16LF1933)
PIC16LF1933 Low-Power Features:
• Standby Current:
- 60 nA @ 1.8V, typical
• Operating Current:
-75A/MHz, 1.8V, typical
• Timer1 Oscillator Current:
- 600 nA @ 32 kHz, 1.8V, typical
• Low-Power Watchdog Timer Current:
- 500 nA @ 1.8V, typical
Peripheral Features:
• Up to 35 I/O Pins and 1 Input-only pin:
- High-current source/sink for direct LED drive
- Individually programmable interrupt-on-pin
change pins
- Individually programmable weak pull-ups
• Integrated LCD Controller:
- Up to 96 segments
- Variable clock input
- Contrast control
- Internal voltage reference selections
• Capacitive Sensing module (mTouch
- Up to 16 selectable channels
• A/D Converter:
- 10-bit resolution and up to 14 channels
- Selectable 1.024/2.048/4.096V voltage
reference
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1
- Dedicated low-power 32 kHz oscillator driver
- 16-bit timer/counter with prescaler
- External Gate Input mode with Toggle and
Single Shot modes
- Interrupt-on-gate completion
• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture, Compare, PWM modules (CCP)
- 16-bit Capture, max. resolution 125 ns
- 16-bit Compare, max. resolution 125 ns
- 10-bit PWM, max. frequency 31.25 kHz
• Three Enhanced Capture, Compare, PWM
modules (ECCP)
- 3 PWM time-base options
- Auto-shutdown and auto-restart
- PWM steering
- Programmable dead-band delay
TM
)
2011-2012 Microchip Technology Inc. DS41575C-page 1
PIC16(L)F1933
Peripheral Features (Continued):
• Master Synchronous Serial Port (MSSP) with SPI
2
CTM with:
and I
- 7-bit address masking
- SMBus/PMBusTM compatibility
- Auto-wake-up on start
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
• SR Latch (555 Timer):
- Multiple Set/Reset input options
- Emulates 555 Timer applications
• 2 Comparators:
- Rail-to-rail inputs/outputs
- Power mode control
- Software enable hysteresis
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
PIC16(L)F193X/194X Family Types
(Com/Seg/Total)
(3)
(3)
(3)
(1)
Debug
I/H Y
I/H Y
I/H Y
(bytes)
Data SRAM
(2)
I/O’s
CapSense (ch)
10-bit ADC (ch)
Timers
Comparators
(8/16-bit)
Device
(bytes)
Flash (words)
Data Sheet Index
Program Memory
PIC16(L)F1933 (1) 4096 256 256 25 11 8 2 4/1 1 1 3 2 4/16/60
PIC16(L)F1934 (2) 4096 256 256 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1936 (2) 8192 256 512 25 11 8 2 4/1 1 1 3 2 4/16/60
PIC16(L)F1937 (2) 8192 256 512 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1938 (3) 16384 256 1024 25 11 8 2 4/1 1 1 3 2 4/16/60
PIC16(L)F1939 (3) 16384 256 1024 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1946 (4) 8192 256 512 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y
PIC16(L)F1947 (4) 16384 256 1024 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.
2: One pin is input-only.
3: COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multiplex
displays.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS41575 PIC16(L)F1933 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.
2: DS41364 PIC16(L)F1934/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.
3: DS41574 PIC16(L)F1938/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.
4: DS41414 PIC16(L)F1946/1947 Data Sheet, 64-Pin Flash, 8-bit Microcontrollers.
Data EEPROM
C™/SPI)
2
EUSART
ECCP
MSSP (I
CCP
LCD
XLP
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS41575C-page 2 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
28-pin SPDIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
VSS
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
V
SS
RA7
RA6
RC0
RC1
RC2
RC3
RC5
RC4
RC7
RC6
RB7/ICSPDAT
PIC16F1933
PIC16LF1933
2
3
6
1
18
19
20
21
15
7
16
17
RC0
5
4
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
VSS
RC7
RC6
RC5
RC4
RE3/MCLR
/VPP
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
RC1
RC2
RC3
9
10
13814
12
11
27
26
232822
24
25
PIC16F1933
PIC16LF1933
28-pin QFN/UQFN
Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16F1933, PIC16LF1933)
Pin Diagram – 28-Pin QFN/UQFN
2011-2012 Microchip Technology Inc. DS41575C-page 3
(PIC16F1933, PIC16LF1933)
PIC16(L)F1933
TABLE 1: 28-PIN SUMMARY (PIC16F1933, PIC16LF1933)
I/O
28-Pin
28-Pin
QFN/UQFN
A/D
ANSEL
Cap Sense
Comparator
SR Latch
Timers
CCP
EUSART
MSSP
LCD
Pull-up
Interrupt
Basic
SPDIP/SOIC/SSOP
RA0 2 27 Y AN0 — C12IN0-/
C2OUT
SRNQ
(1)
SS
— — —
(1)
SEG12 — — VCAP
(1)
(2)
RA1 3 28 Y AN1 — C12IN1- — — — — — SEG7 — — —
RA2 4 1 Y AN2/
V
RA3 5 2 Y AN3/
V
REF-
— C2IN+/
DACOUT
— — — — — COM2 — — —
— C1IN+ — — — — — SEG15/
REF+
COM3
—— —
RA4 6 3 Y — CPS6 C1OUT SRQ T0CKI CCP5 — — SEG4 — — —
RA5 7 4 Y AN4 CPS7 C2OUT
(1)
SRNQ
(1)
———SS
(1)
SEG5 — — VCAP
(2)
RA6 10 7 — — — — — — — — — SEG1 — — OSC2/
CLKOUT
(2)
CAP
V
RA7 9 6 — — — — — — — — — SEG2 — — OSC1/
CLKIN
RB0 21 18 Y AN12 CPS0 — SRI — CCP4 — — SEG0 INT/
IOC
Y —
RB1 22 19 Y AN10 CPS1 C12IN3- — — P1C — — VLCD1 IOC Y —
RB2 23 20 Y AN8 CPS2 — — — P1B — — VLCD2 IOC Y —
(1)
/
RB3 24 21 Y AN9 CPS3 C12IN2- — — CCP2
P2A
— — VLCD3 IOC Y —
(1)
RB4 25 22 Y AN11 CPS4 — — — P1D — — COM0 IOC Y —
RB5 26 23 Y AN13 CPS5 — — T1G
(1)
P2B
CCP3
P3A
(1)
— — COM1 IOC Y —
(1)
/
(1)
RB6 27 24 — — — — — — — — — SEG14 IOC Y ICSPCLK/
ICDCLK
RB7 28 25 — — — — — — — — — SEG13 IOC Y ICSPDAT/
RC0 11 8 — — — — — T1OSO/
P2B
(1)
— — — — — —
ICDDAT
T1CKI
RC1 12 9 — — — — — T1OSI CCP2
RC2 13 10 — — — — — — CCP1/
P2A
P1A
(1)
/
—— ——— —
(1)
— — SEG3 — — —
RC3 14 11 — — — — — — — — SCK/SCL SEG6 — — —
RC4 15 12 — — — — — T1G
(1)
— — SDI/SDA SEG11 — — —
RC5 16 13 — — — — — — — — SDO SEG10 — — —
RC6 17 14 — — — — — — CCP3
P3A
(1)
TX/CK — SEG9 — — —
(1)
RC7 18 15 — — — — — — P3B RX/DT — SEG8 — — —
RE3 1 26 — — — — — — — — — — — Y MCLR
/VPP
VDD 20 17 — — — — — — — — — — — — VDD
Vss 8,195,16 — — — — — — — — — — — — VSS
Note 1: Pin functions can be moved using the APFCON register.
2: PIC16F1933 devices only.
DS41575C-page 4 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 15
4.0 Device Configuration.................................................................................................................................................................. 45
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51
6.0 Resets ........................................................................................................................................................................................ 69
7.0 Interrupts.................................................................................................................................................................................... 77
8.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 91
9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 93
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 95
11.0 Data EEPROM and Flash Program Memory Control ................................................................................................................. 99
12.0 I/O Ports ................................................................................................................................................................................... 113
13.0 Interrupt-On-Change ................................................................................................................................................................ 129
14.0 Fixed Voltage Reference.......................................................................................................................................................... 133
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 137
16.0 Temperature Indicator Module ................................................................................................................................................. 151
17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 153
18.0 Comparator Module.................................................................................................................................................................. 157
19.0 SR Latch................................................................................................................................................................................... 167
20.0 Timer0 Module ......................................................................................................................................................................... 171
21.0 Timer1 Module with Gate Control............................................................................................................................................. 175
22.0 Timer2/4/6 Modules.................................................................................................................................................................. 187
23.0 Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5) .......................................................................... 191
24.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 219
25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 275
26.0 Capacitive Sensing Module...................................................................................................................................................... 305
27.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 313
28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 347
29.0 Instruction Set Summary.......................................................................................................................................................... 351
30.0 Electrical Specifications............................................................................................................................................................ 365
31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 397
32.0 Development Support............................................................................................................................................................... 433
33.0 Packaging Information.............................................................................................................................................................. 437
Appendix A: Data Sheet Revision History.......................................................................................................................................... 449
Appendix B: Migrating From Other PIC
Index .................................................................................................................................................................................................. 451
The Microchip Web Site..................................................................................................................................................................... 459
Customer Change Notification Service .............................................................................................................................................. 459
Customer Support .............................................................................................................................................................................. 459
Reader Response .............................................................................................................................................................................. 460
Product Identification System ............................................................................................................................................................ 461
®
Devices.............................................................................................................................. 449
2011-2012 Microchip Technology Inc. DS41575C-page 5
PIC16(L)F1933
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS41575C-page 6 2011-2012 Microchip Technology Inc.
1.0 DEVICE OVERVIEW
The PIC16(L)F1933 are described within this data
sheet. They are available in 28-pin packages.
Figure 1-1 shows a block diagram of the
PIC16(L)F1933 devices. Tab le 1 -2 shows the pinout
descriptions.
Reference Ta bl e 1- 1 for peripherals available per
device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F1933
PIC16F1933
ADC ●●
Capacitive Sensing Module ●●
Digital-to-Analog Converter (DAC) ●●
EUSART ●●
Fixed Voltage Reference (FVR) ●●
LCD ●●
SR Latch ●●
Temperature Indicator ●●
Capture/Compare/PWM Modules
ECCP1 ●●
ECCP2 ●●
ECCP3 ●●
CCP4 ●●
CCP5 ●●
Comparators
C1 ●●
C2 ●●
Master Synchronous Serial Ports
MSSP1 ●●
Timers
Timer0 ●●
Timer1 ●●
Timer2 ●●
Timer4 ●●
Timer6 ●●
PIC16LF1933
2011-2012 Microchip Technology Inc. DS41575C-page 7
PIC16(L)F1933
PORTA
EUSART
Comparators
MSSP
Timer2Timer1 Timer4Timer0
ECCP1
ADC
10-Bit
ECCP2 ECCP3 CCP4 CCP5
Timer6
PORTB
PORTC
PORTE
LCD
SR
Latch
Note 1: See applicable chapters for more information on peripherals.
CPU
Program
Flash Memory
EEPROM
RAM
Timing
Generation
INTRC
Oscillator
MCLR
Figure 2-1
OSC1/CLKIN
OSC2/CLKOUT
FIGURE 1-1: PIC16(L)F1933 BLOCK DIAGRAM
DS41575C-page 8 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION
Input
Name Function
RA0/AN0/C12IN0-/C2OUT
(1)
(1)
/SS
SRNQ
/VCAP
(2)
/SEG12
(1)
/
RA0 TTL CMOS General purpose I/O.
AN0 AN — A/D Channel input.
C12IN0-
C2OUT — CMOS Comparator output.
SRNQ — CMOS SR latch inverting output.
SS
CAP Power Power Filter capacitor for Voltage Regulator (PIC16F1933 only).
V
SEG12 — AN LCD Analog output.
RA1/AN1/C12IN1-/SEG7 RA1 TTL CMOS General purpose I/O.
AN1 AN — A/D Channel input.
C12IN1-
SEG7 — AN LCD Analog output.
RA2/AN2/C2IN+/V
DACOUT/COM2
REF-/
RA2 TTL CMOS General purpose I/O.
AN2 AN — A/D Channel input.
C2IN+
VREF- AN — A/D Negative Voltage Reference input.
DACOUT — AN Voltage Reference output.
COM2 — AN LCD Analog output.
RA3/AN3/C1IN+/V
COM3/SEG15
REF+/
RA3 TTL CMOS General purpose I/O.
AN3 AN — A/D Channel input.
C1IN+ AN — Comparator positive input.
REF+ AN — A/D Voltage Reference input.
V
COM3 — AN LCD Analog output.
SEG15 — AN LCD Analog output.
RA4/C1OUT/CPS6/T0CKI/SRQ/
CCP5/SEG4
RA4 TTL CMOS General purpose I/O.
C1OUT — CMOS Comparator output.
CPS6 AN — Capacitive sensing input.
T0CKI ST — Timer0 clock input.
SRQ — CMOS SR latch non-inverting output.
CCP5 ST CMOS Capture/Compare/PWM.
SEG4 — AN LCD Analog output.
RA5/AN4/C2OUT
(1)
SRNQ
/SS
(1)
/VCAP
/CPS7/
(2)
/SEG5
RA5 TTL CMOS General purpose I/O.
AN4 AN — A/D Channel input.
(1)
C2OUT — CMOS Comparator output.
CPS7 AN — Capacitive sensing input.
SRNQ — CMOS SR latch inverting output.
SS
V
CAP Power Power Filter capacitor for Voltage Regulator (PIC16F1933 only).
SEG5 — AN LCD Analog output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F1933 devices only.
Output
Typ e
Typ e
AN — Comparator negative input.
ST — Slave Select input.
AN — Comparator negative input.
AN — Comparator positive input.
ST — Slave Select input.
Description
2
C™ = Schmitt Trigger input with I2C
2011-2012 Microchip Technology Inc. DS41575C-page 9
PIC16(L)F1933
TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RA6/OSC2/CLKOUT/V
SEG1
RA7/OSC1/CLKIN/SEG2 RA7 TTL CMOS General purpose I/O.
RB0/AN12/CPS0/CCP4/SRI/INT/
SEG0
RB1/AN10/C12IN3-/CPS1/P1C/
VLCD1
RB2/AN8/CPS2/P1B/VLCD2 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB3/AN9/C12IN2-/CPS3/
(1)
(1)
/P2A
CCP2
RB4/AN11/CPS4/P1D/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
Note 1: Pin function is selectable via the APFCON register.
/VLCD3
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: PIC16F1933 devices only.
CAP
(2)
/
RA6 TTL CMOS General purpose I/O.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS F
CAP Power Power Filter capacitor for Voltage Regulator (PIC16F1933 only).
V
SEG1 — AN LCD Analog output.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN CMOS — External clock input (EC mode).
SEG2 — AN LCD Analog output.
RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN12 AN — A/D Channel input.
CPS0 AN — Capacitive sensing input.
CCP4 ST CMOS Capture/Compare/PWM.
SRI — ST SR latch input.
INT ST — External interrupt.
SEG0 — AN LCD analog output.
RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN10 AN — A/D Channel input.
C12IN3-
CPS1 AN — Capacitive sensing input.
P1C — CMOS PWM output.
VLCD1 AN — LCD analog input.
AN8 AN — A/D Channel input.
CPS2 AN — Capacitive sensing input.
P1B — CMOS PWM output.
VLCD2 AN — LCD analog input.
RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN9 AN — A/D Channel input.
C12IN2-
CPS3 AN — Capacitive sensing input.
CCP2 ST CMOS Capture/Compare/PWM.
P2A — CMOS PWM output.
VLCD3 AN — LCD analog input.
AN11 AN — A/D Channel input.
CPS4 AN — Capacitive sensing input.
P1D — CMOS PWM output.
COM0 — AN LCD Analog output.
Output
Typ e
Typ e
OSC/4 output.
Individually enabled pull-up.
Individually enabled pull-up.
AN — Comparator negative input.
Individually enabled pull-up.
Individually enabled pull-up.
AN — Comparator negative input.
Individually enabled pull-up.
Description
2
C™ = Schmitt Trigger input with I2C
DS41575C-page 10 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RB5/AN13/CPS5/P2B/CCP3
(1)
P3A
RB6/ICSPCLK/ICDCLK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/T1OSO/T1CKI/P2B
RC1/T1OSI/CCP2
RC2/CCP1/P1A/SEG3 RC2 ST CMOS General purpose I/O.
RC3/SCK/SCL/SEG6 RC3 ST CMOS General purpose I/O.
RC4/SDI/SDA/T1G
RC5/SDO/SEG10 RC5 ST CMOS General purpose I/O.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
Note 1: Pin function is selectable via the APFCON register.
(1)
/T1G
/COM1
(1)
(1)
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: PIC16F1933 devices only.
(1)
/
RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN13 AN — A/D Channel input.
CPS5 AN — Capacitive sensing input.
P2B — CMOS PWM output.
CCP3 ST CMOS Capture/Compare/PWM.
P3A — CMOS PWM output.
T1G ST — Timer1 gate input.
COM1 — AN LCD Analog output.
ICSPCLK ST — Serial Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
SEG14 — AN LCD Analog output.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST CMOS In-Circuit Data I/O.
(1)
(1)
/P2A
/SEG11 RC4 ST CMOS General purpose I/O.
SEG13 — AN LCD Analog output.
RC0 ST CMOS General purpose I/O.
T1OSO XTAL XTAL Timer1 oscillator connection.
T1CKI ST — Timer1 clock input.
P2B — CMOS PWM output.
RC1 ST CMOS General purpose I/O.
T1OSI XTAL XTAL Timer1 oscillator connection.
CCP2 ST CMOS Capture/Compare/PWM.
P2A — CMOS PWM output.
CCP1 ST CMOS Capture/Compare/PWM.
P1A — CMOS PWM output.
SEG3 — AN LCD Analog output.
SCK ST CMOS SPI clock.
SCL I
SEG6 — AN LCD Analog output.
SDI ST — SPI data input.
SDA I
T1G ST — Timer1 gate input.
SEG11 — AN LCD Analog output.
SDO — CMOS SPI data output.
SEG10 — AN LCD Analog output.
Output
Typ e
Typ e
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
2
CODI2C™ clock.
2
CODI2C™ data input/output.
Description
2
C™ = Schmitt Trigger input with I2C
2011-2012 Microchip Technology Inc. DS41575C-page 11
PIC16(L)F1933
TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RC6/TX/CK/CCP3/P3A/SEG9 RC6 ST CMOS General purpose I/O.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
CCP3 ST CMOS Capture/Compare/PWM.
P3A — CMOS PWM output.
SEG9 — AN LCD Analog output.
RC7/RX/DT/P3B/SEG8 RC7 ST CMOS General purpose I/O.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
P3B — CMOS PWM output.
SEG8 — AN LCD Analog output.
RE3/MCLR
DD VDD Power — Positive supply.
V
SS VSS Power — Ground reference.
V
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
Note 1: Pin function is selectable via the APFCON register.
/VPP RE3 TTL — General purpose input.
MCLR
V
PP HV — Programming voltage.
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: PIC16F1933 devices only.
Output
Typ e
Typ e
ST — Master Clear with internal pull-up.
Description
2
C™ = Schmitt Trigger input with I2C
DS41575C-page 12 2011-2012 Microchip Technology Inc.
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1 Automatic Interrupt Context Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
PIC16(L)F1933
2.2 16-level Stack with Overflow and Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON register, and if enabled will
cause a software Reset. See section Section 3.5
“Stack” for more details.
2.3 File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.6 “Indirect Addressing” for more details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 29.0 “Instruction Set Summary” for more
details.
2011-2012 Microchip Technology Inc. DS41575C-page 13
PIC16(L)F1933
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
V
DD
8
8
Brown-out
Reset
12
3
VSS
Internal
Oscillator
Block
Configuration
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W reg
Instruction
Decode &
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
15
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr
7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
Oscillator
Start-up Timer
FIGURE 2-1: CORE BLOCK DIAGRAM
DS41575C-page 14 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
3.0 MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
-User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
• Data EEPROM memory
Note 1: The Data EEPROM Memory and the
method to access Flash memory through
the EECON registers is described in
Section 11.0 “Data EEPROM and Flash
Program Memory Control”.
(1)
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1933 family. Accessing a
location above these boundaries will cause a
wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 3-1).
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words) Last Program Memory Address
PIC16(L)F1933 4,096 0FFFh
2011-2012 Microchip Technology Inc. DS41575C-page 15
PIC16(L)F1933
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
CALL, CALLW
RETURN, RETLW
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh
1000h
7FFFh
Page 1
Rollover to Page 1
Interrupt, RETFIE
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
4 KW PARTS
3.1.1 READING PROGRAM MEMORY AS DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
DS41575C-page 16 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
constants
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
3.2.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation of the PIC16(L)F1933. These
registers are listed below:
• INDF0
• INDF1
•PCL
•STATUS
•FSR0 Low
• FSR0 High
•FSR1 Low
• FSR1 High
• BSR
•WREG
•PCLATH
• INTCON
Note: The core registers are the first 12
addresses of every data memory bank.
3.2 Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 “Indirect
Addressing” for more information.
2011-2012 Microchip Technology Inc. DS41575C-page 17
PIC16(L)F1933
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 29.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
3.3 Register Definitions: Status
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TO
PD ZDC
(1)
(1)
C
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Digit Borrow
bit 0 C: Carry/Borrow
Note 1: For Borrow
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(1)
(1)
DS41575C-page 18 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset
3.3.1 SPECIAL FUNCTION REGISTER
The Special Function Registers (SFRs) are registers
used by the application to control the desired operation
of peripheral functions in the device. The Special
Function Registers occupy the 20 bytes after the core
registers of every data memory bank (addresses
x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described
in the appropriate peripheral chapter of this data sheet.
3.3.2 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank.
3.3.2.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2
“Linear Data Memory” for more information.
3.3.3 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-2: BANKED MEMORY
PARTITIONING
2011-2012 Microchip Technology Inc. DS41575C-page 19
3.3.4 DEVICE MEMORY MAPS
The memory maps for the device family are as shown
in Table 3-2.
TABLE 3-2: MEMORY MAP TABLES
Device Banks Table No.
PIC16F1933
PIC16LF1933
0-7 Table 3-3
8-15 Table 3-4,Ta b le 3 -7
16-23 Table 3-5
23-31 Table 3-6, Ta bl e 3 -8
DS41575C-page 20 2011-2012 Microchip Technology Inc.
TABLE 3-3: PIC16(L)F1933 MEMORY MAP, BANKS 0-7
PIC16(L)F1933
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0
001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1
002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL
003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS
004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L
005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H
006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L
007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H
008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR
009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG
00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH
00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh
00Fh
010h PORTE 090h TRISE 110h
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h CCPR3L 391h
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h CCPR3H 392h
013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSPMSK 293h CCP1CON 313h CCP3CON 393h
014h
015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON1 295h CCP1AS 315h CCP3AS 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h PSTR3CON 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h
018h T1CON 098h OSCTUNE 118h DACCON0 198h
019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h
01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah
01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh
01Ch T2CON 09Ch ADRESH 11Ch
01Dh
01Eh CPSCON0 09Eh ADCON1 11Eh
01Fh CPSCON1 09Fh
020h
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
—094h— 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h PWM3CON 394h IOCBP
— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh PSTR2CON 31Dh CCPR5H 39Dh —
—11Fh— 19Fh BAUDCTR 21Fh — 29Fh CCPTMRS1 31Fh —39Fh—
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
120h
170h
General
Purpose
Register
80 Bytes
Common RAM
0A0h
0F0h
—190h— 210h WPUE 290h — 310h — 390h —
— 19Ch SPBRGH 21Ch — 29Ch CCP2AS 31Ch CCPR5L 39Ch —
— 19Eh TXSTA 21Eh — 29Eh CCPTMRS0 31Eh CCP5CON 39Eh —
1A0h
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
1F0h
—20Eh—28Eh—30Eh—38Eh—
— 217h SSPCON3 297h — 317h — 397h —
—218h— 298h CCPR2L 318h CCPR4L 398h —
220h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh)
270h
— 28Ch — 30Ch — 38Ch —
— 299h CCPR2H 319h CCPR4H 399h —
— 29Ah CCP2CON 31Ah CCP4CON 39Ah —
— 29Bh PWM2CON 31Bh —39Bh—
2A0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
2F0h
— 30Dh — 38Dh —
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
320h
Unimplemented
Read as ‘0’
36Fh 3EFh
370h
Accesses
70h – 7Fh
3A0h
3F0h
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
Legend: = Unimplemented data memory locations, read as ‘0’.
DS41575C-page 21 2011-2012 Microchip Technology Inc.
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
INDF0
480h
INDF0
500h
INDF0
580h
INDF0
600h
INDF0
680h
INDF0
700h
INDF0
780h
INDF0
401h
INDF1
481h
INDF1
501h
INDF1
581h
INDF1
601h
INDF1
681h
INDF1
701h
INDF1
781h
INDF1
402h
PCL
482h
PCL
502h
PCL
582h
PCL
602h
PCL
682h
PCL
702h
PCL
782h
PCL
403h
STATUS
483h
STATUS
503h
STATUS
583h
STATUS
603h
STATUS
683h
STATUS
703h
STATUS
783h
STATUS
404h
FSR0L
484h
FSR0L
504h
FSR0L
584h
FSR0L
604h
FSR0L
684h
FSR0L
704h
FSR0L
784h
FSR0L
405h
FSR0H
485h
FSR0H
505h
FSR0H
585h
FSR0H
605h
FSR0H
685h
FSR0H
705h
FSR0H
785h
FSR0H
406h
FSR1L
486h
FSR1L
506h
FSR1L
586h
FSR1L
606h
FSR1L
686h
FSR1L
706h
FSR1L
786h
FSR1L
407h
FSR1H
487h
FSR1H
507h
FSR1H
587h
FSR1H
607h
FSR1H
687h
FSR1H
707h
FSR1H
787h
FSR1H
408h
BSR
488h
BSR
508h
BSR
588h
BSR
608h
BSR
688h
BSR
708h
BSR
788h
BSR
409h
WREG
489h
WREG
509h
WREG
589h
WREG
609h
WREG
689h
WREG
709h
WREG
789h
WREG
40Ah
PCLATH
48Ah
PCLATH
50Ah
PCLATH
58Ah
PCLATH
60Ah
PCLATH
68Ah
PCLATH
70Ah
PCLATH
78Ah
PCLATH
40Bh
INTCON
48Bh
INTCON
50Bh
INTCON
58Bh
INTCON
60Bh
INTCON
68Bh
INTCON
70Bh
INTCON
78Bh
INTCON
40Ch
—
48Ch
—
50Ch
—
58Ch
—
60Ch
—
68Ch
—
70Ch
—
78Ch
—
40Dh
—
48Dh
—
50Dh
—
58Dh
—
60Dh
—
68Dh
—
70Dh
—
78Dh
—
40Eh
—
48Eh
—
50Eh
—
58Eh
—
60Eh
—
68Eh
—
70Eh
—
78Eh
—
40Fh
—
48Fh
—
50Fh
—
58Fh
—
60Fh
—
68Fh
—
70Fh
—
78Fh
—
410h
—
490h
—
510h
—
590h
—
610h
—
690h
—
710h
—
790h
—
411h
—
491h
—
511h
—
591h
—
611h
—
691h
—
711h
—
791h
See Ta bl e 3 -7
412h
—
492h
—
512h
—
592h
—
612h
—
692h
—
712h
—
792h
413h
—
493h
—
513h
—
593h
—
613h
—
693h
—
713h
—
793h
414h
—
494h
—
514h
—
594h
—
614h
—
694h
—
714h
—
794h
415h
TMR4
495h
—
515h
—
595h
—
615h
—
695h
—
715h
—
795h
416h
PR4
496h
—
516h
—
596h
—
616h
—
696h
—
716h
—
796h
417h
T4CON
497h
—
517h
—
597h
—
617h
—
697h
—
717h
—
797h
418h
—
498h
—
518h
—
598h
—
618h
—
698h
—
718h
—
798h
419h
—
499h
—
519h
—
599h
—
619h
—
699h
—
719h
—
799h
41Ah
—
49Ah
—
51Ah
—
59Ah
—
61Ah
—
69Ah
—
71Ah
—
79Ah
41Bh
—
49Bh
—
51Bh
—
59Bh
—
61Bh
—
69Bh
—
71Bh
—
79Bh
41Ch
TMR6
49Ch
—
51Ch
—
59Ch
—
61Ch
—
69Ch
—
71Ch
—
79Ch
41Dh
PR6
49Dh
—
51Dh
—
59Dh
—
61Dh
—
69Dh
—
71Dh
—
79Dh
41Eh
T6CON
49Eh
—
51Eh
—
59Eh
—
61Eh
—
69Eh
—
71Eh
—
79Eh
41Fh
—
49Fh
—
51Fh
—
59Fh
—
61Fh
—
69Fh
—
71Fh
—
79Fh
420h
Unimplemented
Read as ‘0’
4A0h
Unimplemented
Read as ‘0’
520h
Unimplemented
Read as ‘0’
5A0h
Unimplemented
Read as ‘0’
620h
Unimplemented
Read as ‘0’
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h – 7Fh
4F0h
Accesses
70h – 7Fh
570h
Accesses
70h – 7Fh
5F0h
Accesses
70h – 7Fh
670h
Accesses
70h – 7Fh
6F0h
Accesses
70h – 7Fh
770h
Accesses
70h – 7Fh
7F0h
Accesses
70h – 7Fh
47Fh
4FFh 57Fh
5FFh 67Fh 6FFh 77Fh 7FFh
TABLE 3-4: PIC16(L)F1933 MEMORY MAP, BANKS 8-15
PIC16(L)F1933
DS41575C-page 22 2011-2012 Microchip Technology Inc.
TABLE 3-5: PIC16(L)F1933 MEMORY MAP, BANKS 16-23
PIC16(L)F1933
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0
801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1
802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL
803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS
804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L
805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H
806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L
807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H
808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR
809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG
80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH
80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
81Fh
820h
— 88Ch — 90Ch — 98Ch —A0Ch—A8Ch—B0Ch—B8Ch—
— 88Dh — 90Dh — 98Dh —A0Dh—A8Dh—B0Dh—B8Dh—
—88Eh—90Eh—98Eh—A0Eh—A8Eh—B0Eh—B8Eh—
—88Fh—90Fh—98Fh—A0Fh—A8Fh—B0Fh—B8Fh—
—890h—910h—990h—A10h—A90h—B10h—B90h—
—891h—911h—991h—A11h—A91h—B11h—B91h—
—892h—912h—992h—A12h—A92h—B12h—B92h—
—893h—913h—993h—A13h—A93h—B13h—B93h—
—894h—914h—994h—A14h—A94h—B14h—B94h—
—895h—915h—995h—A15h—A95h—B15h—B95h—
—896h—916h—996h—A16h—A96h—B16h—B96h—
—897h—917h—997h—A17h—A97h—B17h—B97h—
—898h—918h—998h—A18h—A98h—B18h—B98h—
—899h—919h—999h—A19h—A99h—B19h—B99h—
—89Ah—91Ah—99Ah—A1Ah—A9Ah—B1Ah—B9Ah—
—89Bh—91Bh—99Bh—A1Bh—A9Bh—B1Bh—B9Bh—
— 89Ch — 91Ch — 99Ch —A1Ch—A9Ch—B1Ch—B9Ch—
— 89Dh — 91Dh — 99Dh —A1Dh—A9Dh—B1Dh—B9Dh—
—89Eh—91Eh—99Eh—A1Eh—A9Eh—B1Eh—B9Eh—
—89Fh—91Fh—99Fh—A1Fh—A9Fh—B1Fh—B9Fh—
8A0h
920h
9A0h
A20h
AA0h
B20h
BA0h
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh
870h
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Accesses
70h – 7Fh
8F0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
970h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
9EFh
9F0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
A6Fh
A70h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
AEFh
AF0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
B6Fh
B70h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
BEFh
BF0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
DS41575C-page 23 2011-2012 Microchip Technology Inc.
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0
C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1
C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL
C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS
C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L
C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H
C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L
C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H
C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR
C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG
C0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATH
C0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCON
C0Ch
—C8Ch—D0Ch—D8Ch—E0Ch—E8Ch—F0Ch—F8Ch
See Ta bl e 3 -8
C0Dh
—C8Dh—D0Dh—D8Dh—E0Dh—E8Dh—F0Dh—F8Dh
C0Eh
—C8Eh—D0Eh—D8Eh—E0Eh—E8Eh—F0Eh—F8Eh
C0Fh
—C8Fh—D0Fh—D8Fh—E0Fh—E8Fh—F0Fh—F8Fh
C10h
—C90h—D10h—D90h—E10h—E90h—F10h—F90h
C11h
—C91h—D11h—D91h—E11h—E91h—F11h—F91h
C12h
—C92h—D12h—D92h—E12h—E92h—F12h—F92h
C13h
—C93h—D13h—D93h—E13h—E93h—F13h—F93h
C14h
—C94h—D14h—D94h—E14h—E94h—F14h—F94h
C15h
—C95h—D15h—D95h—E15h—E95h—F15h—F95h
C16h
—C96h—D16h—D96h—E16h—E96h—F16h—F96h
C17h
—C97h—D17h—D97h—E17h—E97h—F17h—F97h
C18h
—C98h—D18h—D98h—E18h—E98h—F18h—F98h
C19h
—C99h—D19h—D99h—E19h—E99h—F19h—F99h
C1Ah
—C9Ah—D1Ah—D9Ah—E1Ah—E9Ah—F1Ah—F9Ah
C1Bh
—C9Bh—D1Bh—D9Bh—E1Bh—E9Bh—F1Bh—F9Bh
C1Ch
—C9Ch—D1Ch—D9Ch—E1Ch—E9Ch—F1Ch—F9Ch
C1Dh
—C9Dh—D1Dh—D9Dh—E1Dh—E9Dh—F1Dh—F9Dh
C1Eh
—C9Eh—D1Eh—D9Eh—E1Eh—E9Eh—F1Eh—F9Eh
C1Fh
—C9Fh—D1Fh—D9Fh—E1Fh—E9Fh—F1Fh—F9Fh
C20h
Unimplemented
Read as ‘0’
CA0h
Unimplemented
Read as ‘0’
D20h
Unimplemented
Read as ‘0’
DA0h
Unimplemented
Read as ‘0’
E20h
Unimplemented
Read as ‘0’
EA0h
Unimplemented
Read as ‘0’
F20h
Unimplemented
Read as ‘0’
FA0h
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h
Accesses
70h – 7Fh
CF0h
Accesses
70h – 7Fh
D70h
Accesses
70h – 7Fh
DF0h
Accesses
70h – 7Fh
E70h
Accesses
70h – 7Fh
EF0h
Accesses
70h – 7Fh
F70h
Accesses
70h – 7Fh
FF0h
Accesses
70h – 7Fh
CFFh
CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
TABLE 3-6: PIC16(L)F1933 MEMORY MAP, BANKS 24-31
PIC16(L)F1933
PIC16(L)F1933
Legend: = Unimplemented data memory locations, read
as ‘0’.
Bank 15
791h
LCDCON
792h
LCDPS
793h
LCDREF
794h
LCDCST
795h
LCDRL
796h
—
797h
—
798h
LCDSE0
799h
LCDSE1
79Ah
—
79Bh
—
79Ch
—
79Dh
—
79Eh
—
79Fh
—
7A0h LCDDATA0
7A1h LCDDATA1
7A2h
—
7A3h LCDDATA3
7A4h LCDDATA4
7A5h
—
7A6h LCDDATA6
7A7h LCDDATA7
7A8h
—
7A9h LCDDATA9
7AAh LCDDATA10
7ABh
—
7ACh
—
7ADh
—
7AEh
—
7AFh
—
7B0h
—
7B1h
—
7B2h
—
7B3h
—
7B4h
—
7B5h
—
7B6h
—
7B7h
—
7B8h
Unimplemented
Read as ‘0’
7EFh
Legend: = Unimplemented data memory locations, read
as ‘0’.
Bank 31
F8Ch
Unimplemented
Read as ‘0’
FE3h
FE4h
STATUS_SHAD
FE5h
WREG_SHAD
FE6h
BSR_SHAD
FE7h
PCLATH_SHAD
FE8h
FSR0L_SHAD
FE9h
FSR0H_SHAD
FEAh
FSR1L_SHAD
FEBh
FSR1H_SHAD
FECh
—
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
TABLE 3-7: PIC16(L)F1933 MEMORY MAP,
BANK 15
DS41575C-page 24 2011-2012 Microchip Technology Inc.
TABLE 3-8: PIC16(L)F1933 MEMORY MAP,
BANK 31
3.3.5 SPECIAL FUNCTION REGISTERS SUMMARY
The Special Function Register Summary for the device
family are as follows:
Device Bank(s) Page No.
0 25
1 26
2 27
3 28
4 29
5 30
PIC16(L)F1933
6 31
7 32
8 33
9-14 34
15 35
16-30 36
31 37
PIC16(L)F1933
=
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
(2)
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
00Fh
010h PORTE
011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF
013h PIR3
014h
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111
01Ch T2CON
01Dh
01Eh CPSCON0 CPSON CPSRM
01Fh CPSCON1
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
(2)
WREG Working Register 0000 0000 uuuu uuuu
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
Shaded locations are unimplemented, read as ‘0’.
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
(not a physical register)
(not a physical register)
— — — —RE3— — — ---- x--- ---- u---
— CCP2IF 0000 00-0 0000 00-0
— CCP5IF CCP4IF CCP3IF TMR6IF —TMR4IF— -000 0-0- -000 0-0-
—TMR1ON0000 00-0 uuuu uu-u
T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
— — CPSRNG1 CPSRNG0 CPSOUT T0XCS 00-- 0000 00-- 0000
— — — — —CPSCH<2:0>---- -000 ---- -000
Val ue o n
POR, BOR
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
Value on all
other
Resets
2011-2012 Microchip Technology Inc. DS41575C-page 25
PIC16(L)F1933
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(2)
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111
08Fh
090h TRISE
091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE
093h PIE3
094h
095h OPTION_REG WPUEN
096h PCON STKOVF STKUNF
097h WDTCON
098h OSCTUNE
099h OSCCON SPLLEN IRCF<3:0>
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0
09Eh ADCON1 ADFM ADCS<2:0>
09Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
(2)
WREG Working Register 0000 0000 uuuu uuuu
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
Shaded locations are unimplemented, read as ‘0’.
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
(not a physical register)
(not a physical register)
— — — — —
— CCP5IE CCP4IE CCP3IE TMR6IE —TMR4IE— -000 0-0- -000 0-0-
INTEDG TMROCS TMROSE PSA PS<2:0> 1111 1111 1111 1111
— —RMCLRRI POR BOR 00-- 11qq qq-- qquu
— —WDTPS<4:0>SWDTEN--01 0110 --01 0110
— — TUN<5:0> --00 0000 --00 0000
— CHS<4:0>
(3)
— ADNREF
— — — ---- 1--- ---- 1---
—SCS<1:0>0011 1-00 0011 1-00
— CCP2IE 0000 00-0 0000 00-0
HFIOFS 00q0 0q0- qqqq qq0-
GO/DONE
ADPREF1
ADON -000 0000 -000 0000
ADPREF0 0000 -000 0000 -000
Val ue o n
POR, BOR
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
Value on all
other
Resets
DS41575C-page 26 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 2
(2)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu
10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu
10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu
10Fh
110h
111h CM1CON0 C1ON C1OUT C1OE C1POL
112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0
113h CM2CON0 C2ON C2OUT C2OE C2POL
114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0
115h CMOUT
116h BORCON SBOREN
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN DACLPS DACOE
119h DACCON1
11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
11Ch
11Dh APFCON
11Eh
11Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
(2)
WREG Working Register 0000 0000 uuuu uuuu
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
Shaded locations are unimplemented, read as ‘0’.
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
(not a physical register)
(not a physical register)
— C1SP C1HYS C1SYNC 0000 -100 0000 -100
— —C1NCH<1:0>0000 --00 0000 --00
— C2SP C2HYS C2SYNC 0000 -100 0000 -100
— —C2NCH<1:0>0000 --00 0000 --00
— — — — — — MC2OUT MC1OUT ---- --00 ---- --00
— — — — — — BORRDY 1--- ---q u--- ---u
--- DACPSS<1:0> --- DACNSS 000- 00-0 000- 00-0
--- --- --- DACR<4:0> ---0 0000 ---0 0000
— CCP3SEL T1GSEL P2BSEL SRNQSEL
C2OUTSEL
SSSEL CCP2SEL -000 0000 -000 0000
Val ue o n
POR, BOR
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
Value on all
other
Resets
2011-2012 Microchip Technology Inc. DS41575C-page 27
PIC16(L)F1933
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 3
(2)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch ANSELA
18Dh ANSELB
18Eh
18Fh
190h
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000
197h
198h
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000
19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
(2)
WREG Working Register 0000 0000 uuuu uuuu
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
Shaded locations are unimplemented, read as ‘0’.
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
(not a physical register)
(not a physical register)
— — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
(3)
—
EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000
— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Val ue o n
POR, BOR
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
Value on all
other
Resets
DS41575C-page 28 2011-2012 Microchip Technology Inc.
PIC16(L)F1933
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 4
(2)
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh
20Fh
210h WPUE
211h SSPBUF
212h SSPADD
213h SSPMSK
214h SSPSTAT SMP CKE D/A
215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
(2)
WREG Working Register 0000 0000 uuuu uuuu
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
Shaded locations are unimplemented, read as ‘0’.
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
(not a physical register)
(not a physical register)
— — — — WPUE3 — — — ---- 1--- ---- 1---
Synchronous Serial Port Receive Buffer/Transmit Register
ADD<7:0>
MSK<7:0>
PSR/WUA BF 0000 0000 0000 0000
Val ue o n
POR, BOR
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
Value on all
other
Resets
2011-2012 Microchip Technology Inc. DS41575C-page 29
PIC16(L)F1933
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 5
(2)
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000
294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000
295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000
296h PSTR1CON
297h
298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000 0000 0000
29Bh PWM2CON P2RSEN P2DC<6:0> 0000 0000 0000 0000
29Ch CCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 0000 0000 0000 0000
29Dh PSTR2CON
29Eh CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
29Fh CCPTMRS1
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
(2)
WREG Working Register 0000 0000 uuuu uuuu
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
Shaded locations are unimplemented, read as ‘0’.
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
(not a physical register)
(not a physical register)
— — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001
— — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001
— — — — — — C5TSEL<1:0> ---- --00 ---- --00
Val ue o n
POR, BOR
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
Value on all
other
Resets
DS41575C-page 30 2011-2012 Microchip Technology Inc.
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