Datasheet PIC16F1933, PIC16LF1933 Datasheet

PIC16(L)F1933

28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

LCD Driver with XLP Technology

High-Performance RISC CPU:

• Only 49 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 32 MHz oscillator/clock input

- DC – 125 ns instruction cycle

• Up to 16K x 14 Words of Flash Program Memory

• Up to 1024 Bytes of Data Memory (RAM)

• Interrupt Capability with Automatic Context
Saving

• 16-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Read Access to Program Memory

• Pinout Compatible to other 28-pin PIC16CXXX
and PIC16FXXX Microcontrollers

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range from

32 MHz to 31 kHz

• Power-Saving Sleep mode

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)

• Brown-out Reset (BOR)

- Selectable between two trip points

- Disable in Sleep option

• Multiplexed Master Clear with Pull-up/Input Pin

• Programmable Code Protection

• Wide Operating Voltage Range:

- 1.8V-5.5V (PIC16F1933)

- 1.8V-3.6V (PIC16LF1933)

PIC16LF1933 Low-Power Features:

• Standby Current:

- 60 nA @ 1.8V, typical

• Operating Current:

-75A/MHz, 1.8V, typical

• Timer1 Oscillator Current:

- 600 nA @ 32 kHz, 1.8V, typical

• Low-Power Watchdog Timer Current:

- 500 nA @ 1.8V, typical

Peripheral Features:

• Up to 35 I/O Pins and 1 Input-only pin:

- High-current source/sink for direct LED drive

- Individually programmable interrupt-on-pin
change pins

- Individually programmable weak pull-ups

• Integrated LCD Controller:

- Up to 96 segments

- Variable clock input

- Contrast control

- Internal voltage reference selections

• Capacitive Sensing module (mTouch

- Up to 16 selectable channels

• A/D Converter:

- 10-bit resolution and up to 14 channels

- Selectable 1.024/2.048/4.096V voltage
reference

• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler

• Enhanced Timer1

- Dedicated low-power 32 kHz oscillator driver

- 16-bit timer/counter with prescaler

- External Gate Input mode with Toggle and

Single Shot modes

- Interrupt-on-gate completion

• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler

• Two Capture, Compare, PWM modules (CCP)

- 16-bit Capture, max. resolution 125 ns

- 16-bit Compare, max. resolution 125 ns

- 10-bit PWM, max. frequency 31.25 kHz

• Three Enhanced Capture, Compare, PWM
modules (ECCP)

- 3 PWM time-base options

- Auto-shutdown and auto-restart

- PWM steering

- Programmable dead-band delay

TM

)

 2011-2012 Microchip Technology Inc. DS41575C-page 1

PIC16(L)F1933

Peripheral Features (Continued):

• Master Synchronous Serial Port (MSSP) with SPI

2

CTM with:

and I

- 7-bit address masking

- SMBus/PMBusTM compatibility

- Auto-wake-up on start

• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

• SR Latch (555 Timer):

- Multiple Set/Reset input options

- Emulates 555 Timer applications

• 2 Comparators:

- Rail-to-rail inputs/outputs

- Power mode control

- Software enable hysteresis

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive

and negative reference selection

PIC16(L)F193X/194X Family Types

(Com/Seg/Total)

(3)

(3)

(3)

(1)

Debug

I/H Y

I/H Y

I/H Y

(bytes)

Data SRAM

(2)

I/O’s

CapSense (ch)

10-bit ADC (ch)

Timers

Comparators

(8/16-bit)

Device

(bytes)

Flash (words)

Data Sheet Index

Program Memory

PIC16(L)F1933 (1) 4096 256 256 25 11 8 2 4/1 1 1 3 2 4/16/60
PIC16(L)F1934 (2) 4096 256 256 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1936 (2) 8192 256 512 25 11 8 2 4/1 1 1 3 2 4/16/60
PIC16(L)F1937 (2) 8192 256 512 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1938 (3) 16384 256 1024 25 11 8 2 4/1 1 1 3 2 4/16/60
PIC16(L)F1939 (3) 16384 256 1024 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1946 (4) 8192 256 512 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y
PIC16(L)F1947 (4) 16384 256 1024 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.

2: One pin is input-only.
3: COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multiplex

displays.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS41575 PIC16(L)F1933 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.
2: DS41364 PIC16(L)F1934/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.
3: DS41574 PIC16(L)F1938/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.
4: DS41414 PIC16(L)F1946/1947 Data Sheet, 64-Pin Flash, 8-bit Microcontrollers.

Data EEPROM

C™/SPI)

2

EUSART

ECCP

MSSP (I

CCP

LCD

XLP

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

DS41575C-page 2  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

28-pin SPDIP, SOIC, SSOP

1

2

3

4

5

6

7
8
9

10

VPP/MCLR/RE3

RA0
RA1

RA2

RA3
RA4
RA5

RB6/ICSPCLK

RB5

RB4
RB3

RB2
RB1

RB0
V

DD

VSS

11
12

13

14

15

16

17

18

19

20

28

27

26
25
24

23

22
21

V

SS

RA7

RA6
RC0
RC1
RC2
RC3

RC5

RC4

RC7
RC6

RB7/ICSPDAT

PIC16F1933

PIC16LF1933

2
3

6

1

18

19

20

21

15

7

16

17

RC0

5

4

RB7/ICSPDAT

RB6/ICSPCLK

RB5

RB4

RB3
RB2

RB1
RB0
V

DD

VSS
RC7

RC6

RC5

RC4

RE3/MCLR

/VPP

RA0

RA1

RA2
RA3
RA4
RA5

V

SS

RA7
RA6

RC1

RC2

RC3

9

10

13814

12

11

27

26

232822

24

25

PIC16F1933
PIC16LF1933

28-pin QFN/UQFN

Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16F1933, PIC16LF1933)

Pin Diagram – 28-Pin QFN/UQFN

 2011-2012 Microchip Technology Inc. DS41575C-page 3

(PIC16F1933, PIC16LF1933)

PIC16(L)F1933

TABLE 1: 28-PIN SUMMARY (PIC16F1933, PIC16LF1933)

I/O

28-Pin

28-Pin

QFN/UQFN

A/D

ANSEL

Cap Sense

Comparator

SR Latch

Timers

CCP

EUSART

MSSP

LCD

Pull-up

Interrupt

Basic

SPDIP/SOIC/SSOP

RA0 2 27 Y AN0 — C12IN0-/

C2OUT

SRNQ

(1)

SS

— — —

(1)

SEG12 — — VCAP

(1)

(2)

RA1 3 28 Y AN1 — C12IN1- — — — — — SEG7 — — —

RA2 4 1 Y AN2/

V

RA3 5 2 Y AN3/

V

REF-

— C2IN+/

DACOUT

— — — — — COM2 — — —

— C1IN+ — — — — — SEG15/

REF+

COM3

—— —

RA4 6 3 Y — CPS6 C1OUT SRQ T0CKI CCP5 — — SEG4 — — —

RA5 7 4 Y AN4 CPS7 C2OUT

(1)

SRNQ

(1)

———SS

(1)

SEG5 — — VCAP

(2)

RA6 10 7 — — — — — — — — — SEG1 — — OSC2/

CLKOUT

(2)

CAP

V

RA7 9 6 — — — — — — — — — SEG2 — — OSC1/

CLKIN

RB0 21 18 Y AN12 CPS0 — SRI — CCP4 — — SEG0 INT/

IOC

Y —

RB1 22 19 Y AN10 CPS1 C12IN3- — — P1C — — VLCD1 IOC Y —

RB2 23 20 Y AN8 CPS2 — — — P1B — — VLCD2 IOC Y —

(1)

/

RB3 24 21 Y AN9 CPS3 C12IN2- — — CCP2

P2A

— — VLCD3 IOC Y —

(1)

RB4 25 22 Y AN11 CPS4 — — — P1D — — COM0 IOC Y —

RB5 26 23 Y AN13 CPS5 — — T1G

(1)

P2B

CCP3

P3A

(1)

— — COM1 IOC Y —

(1)

/

(1)

RB6 27 24 — — — — — — — — — SEG14 IOC Y ICSPCLK/

ICDCLK

RB7 28 25 — — — — — — — — — SEG13 IOC Y ICSPDAT/

RC0 11 8 — — — — — T1OSO/

P2B

(1)

— — — — — —

ICDDAT

T1CKI

RC1 12 9 — — — — — T1OSI CCP2

RC2 13 10 — — — — — — CCP1/

P2A

P1A

(1)

/

—— ——— —

(1)

— — SEG3 — — —

RC3 14 11 — — — — — — — — SCK/SCL SEG6 — — —

RC4 15 12 — — — — — T1G

(1)

— — SDI/SDA SEG11 — — —

RC5 16 13 — — — — — — — — SDO SEG10 — — —

RC6 17 14 — — — — — — CCP3

P3A

(1)

TX/CK — SEG9 — — —

(1)

RC7 18 15 — — — — — — P3B RX/DT — SEG8 — — —

RE3 1 26 — — — — — — — — — — — Y MCLR

/VPP

VDD 20 17 — — — — — — — — — — — — VDD

Vss 8,195,16 — — — — — — — — — — — — VSS

Note 1: Pin functions can be moved using the APFCON register.

2: PIC16F1933 devices only.

DS41575C-page 4  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13

3.0 Memory Organization ................................................................................................................................................................. 15

4.0 Device Configuration.................................................................................................................................................................. 45

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51

6.0 Resets ........................................................................................................................................................................................ 69

7.0 Interrupts.................................................................................................................................................................................... 77

8.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 91

9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 93

10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 95

11.0 Data EEPROM and Flash Program Memory Control ................................................................................................................. 99

12.0 I/O Ports ................................................................................................................................................................................... 113

13.0 Interrupt-On-Change ................................................................................................................................................................ 129

14.0 Fixed Voltage Reference.......................................................................................................................................................... 133

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 137

16.0 Temperature Indicator Module ................................................................................................................................................. 151

17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 153

18.0 Comparator Module.................................................................................................................................................................. 157

19.0 SR Latch................................................................................................................................................................................... 167

20.0 Timer0 Module ......................................................................................................................................................................... 171

21.0 Timer1 Module with Gate Control............................................................................................................................................. 175

22.0 Timer2/4/6 Modules.................................................................................................................................................................. 187

23.0 Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5) .......................................................................... 191

24.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 219

25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 275

26.0 Capacitive Sensing Module...................................................................................................................................................... 305

27.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 313

28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 347

29.0 Instruction Set Summary.......................................................................................................................................................... 351

30.0 Electrical Specifications............................................................................................................................................................ 365

31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 397

32.0 Development Support............................................................................................................................................................... 433

33.0 Packaging Information.............................................................................................................................................................. 437

Appendix A: Data Sheet Revision History.......................................................................................................................................... 449

Appendix B: Migrating From Other PIC

Index .................................................................................................................................................................................................. 451

The Microchip Web Site..................................................................................................................................................................... 459

Customer Change Notification Service .............................................................................................................................................. 459

Customer Support .............................................................................................................................................................................. 459

Reader Response .............................................................................................................................................................................. 460

Product Identification System ............................................................................................................................................................ 461

®

Devices.............................................................................................................................. 449

 2011-2012 Microchip Technology Inc. DS41575C-page 5

PIC16(L)F1933

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS41575C-page 6  2011-2012 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16(L)F1933 are described within this data
sheet. They are available in 28-pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1933 devices. Tab le 1 -2 shows the pinout
descriptions.

Reference Ta bl e 1- 1 for peripherals available per
device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1933

PIC16F1933

ADC ●●
Capacitive Sensing Module ●●
Digital-to-Analog Converter (DAC) ●●
EUSART ●●
Fixed Voltage Reference (FVR) ●●
LCD ●●
SR Latch ●●
Temperature Indicator ●●
Capture/Compare/PWM Modules

ECCP1 ●●
ECCP2 ●●
ECCP3 ●●

CCP4 ●●
CCP5 ●●

Comparators

C1 ●●
C2 ●●

Master Synchronous Serial Ports

MSSP1 ●●

Timers

Timer0 ●●
Timer1 ●●
Timer2 ●●
Timer4 ●●
Timer6 ●●

PIC16LF1933

 2011-2012 Microchip Technology Inc. DS41575C-page 7

PIC16(L)F1933

PORTA

EUSART

Comparators

MSSP

Timer2Timer1 Timer4Timer0

ECCP1

ADC

10-Bit

ECCP2 ECCP3 CCP4 CCP5

Timer6

PORTB

PORTC

PORTE

LCD

SR

Latch

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

EEPROM

RAM

Timing

Generation

INTRC

Oscillator

MCLR

Figure 2-1

OSC1/CLKIN

OSC2/CLKOUT

FIGURE 1-1: PIC16(L)F1933 BLOCK DIAGRAM

DS41575C-page 8  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/C12IN0-/C2OUT

(1)

(1)

/SS

SRNQ

/VCAP

(2)

/SEG12

(1)

/

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel input.

C12IN0-

C2OUT — CMOS Comparator output.

SRNQ — CMOS SR latch inverting output.

SS

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F1933 only).

V

SEG12 — AN LCD Analog output.

RA1/AN1/C12IN1-/SEG7 RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel input.

C12IN1-

SEG7 — AN LCD Analog output.

RA2/AN2/C2IN+/V
DACOUT/COM2

REF-/

RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel input.

C2IN+

VREF- AN — A/D Negative Voltage Reference input.

DACOUT — AN Voltage Reference output.

COM2 — AN LCD Analog output.

RA3/AN3/C1IN+/V
COM3/SEG15

REF+/

RA3 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel input.

C1IN+ AN — Comparator positive input.

REF+ AN — A/D Voltage Reference input.

V

COM3 — AN LCD Analog output.

SEG15 — AN LCD Analog output.

RA4/C1OUT/CPS6/T0CKI/SRQ/
CCP5/SEG4

RA4 TTL CMOS General purpose I/O.

C1OUT — CMOS Comparator output.

CPS6 AN — Capacitive sensing input.

T0CKI ST — Timer0 clock input.

SRQ — CMOS SR latch non-inverting output.

CCP5 ST CMOS Capture/Compare/PWM.

SEG4 — AN LCD Analog output.

RA5/AN4/C2OUT

(1)

SRNQ

/SS

(1)

/VCAP

/CPS7/

(2)

/SEG5

RA5 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel input.

(1)

C2OUT — CMOS Comparator output.

CPS7 AN — Capacitive sensing input.

SRNQ — CMOS SR latch inverting output.

SS

V

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F1933 only).

SEG5 — AN LCD Analog output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1933 devices only.

Output

Typ e

Typ e

AN — Comparator negative input.

ST — Slave Select input.

AN — Comparator negative input.

AN — Comparator positive input.

ST — Slave Select input.

Description

2

C™ = Schmitt Trigger input with I2C

 2011-2012 Microchip Technology Inc. DS41575C-page 9

PIC16(L)F1933

TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RA6/OSC2/CLKOUT/V
SEG1

RA7/OSC1/CLKIN/SEG2 RA7 TTL CMOS General purpose I/O.

RB0/AN12/CPS0/CCP4/SRI/INT/
SEG0

RB1/AN10/C12IN3-/CPS1/P1C/
VLCD1

RB2/AN8/CPS2/P1B/VLCD2 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

RB3/AN9/C12IN2-/CPS3/

(1)

(1)

/P2A

CCP2

RB4/AN11/CPS4/P1D/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: Pin function is selectable via the APFCON register.

/VLCD3

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

2: PIC16F1933 devices only.

CAP

(2)

/

RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F1933 only).

V

SEG1 — AN LCD Analog output.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN CMOS — External clock input (EC mode).

SEG2 — AN LCD Analog output.

RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN12 AN — A/D Channel input.

CPS0 AN — Capacitive sensing input.

CCP4 ST CMOS Capture/Compare/PWM.

SRI — ST SR latch input.

INT ST — External interrupt.

SEG0 — AN LCD analog output.

RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN10 AN — A/D Channel input.

C12IN3-

CPS1 AN — Capacitive sensing input.

P1C — CMOS PWM output.

VLCD1 AN — LCD analog input.

AN8 AN — A/D Channel input.

CPS2 AN — Capacitive sensing input.

P1B — CMOS PWM output.

VLCD2 AN — LCD analog input.

RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN9 AN — A/D Channel input.

C12IN2-

CPS3 AN — Capacitive sensing input.

CCP2 ST CMOS Capture/Compare/PWM.

P2A — CMOS PWM output.

VLCD3 AN — LCD analog input.

AN11 AN — A/D Channel input.

CPS4 AN — Capacitive sensing input.

P1D — CMOS PWM output.

COM0 — AN LCD Analog output.

Output

Typ e

Typ e

OSC/4 output.

Individually enabled pull-up.

Individually enabled pull-up.

AN — Comparator negative input.

Individually enabled pull-up.

Individually enabled pull-up.

AN — Comparator negative input.

Individually enabled pull-up.

Description

2

C™ = Schmitt Trigger input with I2C

DS41575C-page 10  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB5/AN13/CPS5/P2B/CCP3

(1)

P3A

RB6/ICSPCLK/ICDCLK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

RC0/T1OSO/T1CKI/P2B

RC1/T1OSI/CCP2

RC2/CCP1/P1A/SEG3 RC2 ST CMOS General purpose I/O.

RC3/SCK/SCL/SEG6 RC3 ST CMOS General purpose I/O.

RC4/SDI/SDA/T1G

RC5/SDO/SEG10 RC5 ST CMOS General purpose I/O.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: Pin function is selectable via the APFCON register.

(1)

/T1G

/COM1

(1)

(1)

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

2: PIC16F1933 devices only.

(1)

/

RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN13 AN — A/D Channel input.

CPS5 AN — Capacitive sensing input.

P2B — CMOS PWM output.

CCP3 ST CMOS Capture/Compare/PWM.

P3A — CMOS PWM output.

T1G ST — Timer1 gate input.

COM1 — AN LCD Analog output.

ICSPCLK ST — Serial Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

SEG14 — AN LCD Analog output.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST CMOS In-Circuit Data I/O.

(1)

(1)

/P2A

/SEG11 RC4 ST CMOS General purpose I/O.

SEG13 — AN LCD Analog output.

RC0 ST CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

P2B — CMOS PWM output.

RC1 ST CMOS General purpose I/O.

T1OSI XTAL XTAL Timer1 oscillator connection.

CCP2 ST CMOS Capture/Compare/PWM.

P2A — CMOS PWM output.

CCP1 ST CMOS Capture/Compare/PWM.

P1A — CMOS PWM output.

SEG3 — AN LCD Analog output.

SCK ST CMOS SPI clock.

SCL I

SEG6 — AN LCD Analog output.

SDI ST — SPI data input.

SDA I

T1G ST — Timer1 gate input.

SEG11 — AN LCD Analog output.

SDO — CMOS SPI data output.

SEG10 — AN LCD Analog output.

Output

Typ e

Typ e

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

2

CODI2C™ clock.

2

CODI2C™ data input/output.

Description

2

C™ = Schmitt Trigger input with I2C

 2011-2012 Microchip Technology Inc. DS41575C-page 11

PIC16(L)F1933

TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RC6/TX/CK/CCP3/P3A/SEG9 RC6 ST CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

CCP3 ST CMOS Capture/Compare/PWM.

P3A — CMOS PWM output.

SEG9 — AN LCD Analog output.

RC7/RX/DT/P3B/SEG8 RC7 ST CMOS General purpose I/O.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

P3B — CMOS PWM output.

SEG8 — AN LCD Analog output.

RE3/MCLR

DD VDD Power — Positive supply.

V

SS VSS Power — Ground reference.

V

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: Pin function is selectable via the APFCON register.

/VPP RE3 TTL — General purpose input.

MCLR

V

PP HV — Programming voltage.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

2: PIC16F1933 devices only.

Output

Typ e

Typ e

ST — Master Clear with internal pull-up.

Description

2

C™ = Schmitt Trigger input with I2C

DS41575C-page 12  2011-2012 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.

PIC16(L)F1933

2.2 16-level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON register, and if enabled will
cause a software Reset. See section Section 3.5

“Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary” for more

details.

 2011-2012 Microchip Technology Inc. DS41575C-page 13

PIC16(L)F1933

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Power-on

Reset

Watchdog

Timer

Instruction
Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

V

DD

8

8

Brown-out

Reset

12

3

VSS

Internal

Oscillator

Block

Configuration

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction
Decode &

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

15

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory

RAM

FSR regFSR reg

FSR1 Reg

15

15

MUX

15

Program Memory

Read (PMR)

12

FSR regFSR reg

BSR Reg

5

Oscillator

Start-up Timer

FIGURE 2-1: CORE BLOCK DIAGRAM

DS41575C-page 14  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

• Data EEPROM memory

Note 1: The Data EEPROM Memory and the

method to access Flash memory through
the EECON registers is described in

Section 11.0 “Data EEPROM and Flash
Program Memory Control”.

(1)

The following features are associated with access and
control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1933 family. Accessing a
location above these boundaries will cause a
wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1933 4,096 0FFFh

 2011-2012 Microchip Technology Inc. DS41575C-page 15

PIC16(L)F1933

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh
1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

constants

BRW ;Add Index in W to

;program counter to

;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR
4 KW PARTS

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

DS41575C-page 16  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

constants

RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.

The HIGH directive will set bit<7> if a label points to a
location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2.1 CORE REGISTERS

The core registers contain the registers that directly
affect the basic operation of the PIC16(L)F1933. These
registers are listed below:

• INDF0

• INDF1

•PCL

•STATUS

•FSR0 Low

• FSR0 High

•FSR1 Low

• FSR1 High

• BSR

•WREG

•PCLATH

• INTCON

Note: The core registers are the first 12

addresses of every data memory bank.

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

 2011-2012 Microchip Technology Inc. DS41575C-page 17

PIC16(L)F1933

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in
subtraction.

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

TO

PD ZDC

(1)

(1)

C

bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

(1)

(1)

DS41575C-page 18  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

0Bh
0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.3.1 SPECIAL FUNCTION REGISTER

The Special Function Registers (SFRs) are registers
used by the application to control the desired operation
of peripheral functions in the device. The Special
Function Registers occupy the 20 bytes after the core
registers of every data memory bank (addresses
x0Ch/x8Ch through x1Fh/x9Fh). The registers associ­ated with the operation of the peripherals are described
in the appropriate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory
bank.

3.3.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

3.3.3 COMMON RAM

There are 16 bytes of common RAM accessible from all
banks.

FIGURE 3-2: BANKED MEMORY

PARTITIONING

 2011-2012 Microchip Technology Inc. DS41575C-page 19

3.3.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown
in Table 3-2.

TABLE 3-2: MEMORY MAP TABLES

Device Banks Table No.

PIC16F1933
PIC16LF1933

0-7 Table 3-3

8-15 Table 3-4,Ta b le 3 -7
16-23 Table 3-5
23-31 Table 3-6, Ta bl e 3 -8

DS41575C-page 20  2011-2012 Microchip Technology Inc.

TABLE 3-3: PIC16(L)F1933 MEMORY MAP, BANKS 0-7

PIC16(L)F1933

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0
001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1
002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL
003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS
004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L
005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H
006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L
007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H
008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR
009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG
00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH
00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh
00Fh
010h PORTE 090h TRISE 110h
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h CCPR3L 391h
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h CCPR3H 392h
013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSPMSK 293h CCP1CON 313h CCP3CON 393h
014h
015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON1 295h CCP1AS 315h CCP3AS 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h PSTR3CON 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h
018h T1CON 098h OSCTUNE 118h DACCON0 198h
019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h
01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah
01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh
01Ch T2CON 09Ch ADRESH 11Ch
01Dh
01Eh CPSCON0 09Eh ADCON1 11Eh

01Fh CPSCON1 09Fh
020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—094h— 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h PWM3CON 394h IOCBP

— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh PSTR2CON 31Dh CCPR5H 39Dh —

—11Fh— 19Fh BAUDCTR 21Fh — 29Fh CCPTMRS1 31Fh —39Fh—

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

120h

170h

General
Purpose
Register

80 Bytes

Common RAM

0A0h

0F0h

—190h— 210h WPUE 290h — 310h — 390h —

— 19Ch SPBRGH 21Ch — 29Ch CCP2AS 31Ch CCPR5L 39Ch —

— 19Eh TXSTA 21Eh — 29Eh CCPTMRS0 31Eh CCP5CON 39Eh —

1A0h

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

1F0h

—20Eh—28Eh—30Eh—38Eh—

— 217h SSPCON3 297h — 317h — 397h —
—218h— 298h CCPR2L 318h CCPR4L 398h —

220h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh)

270h

— 28Ch — 30Ch — 38Ch —

— 299h CCPR2H 319h CCPR4H 399h —
— 29Ah CCP2CON 31Ah CCP4CON 39Ah —
— 29Bh PWM2CON 31Bh —39Bh—

2A0h

Unimplemented

Read as ‘0’

Accesses
70h – 7Fh

2F0h

— 30Dh — 38Dh —

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

320h

Unimplemented

Read as ‘0’

36Fh 3EFh
370h

Accesses

70h – 7Fh

3A0h

3F0h

—
—
—

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

Legend: = Unimplemented data memory locations, read as ‘0’.

DS41575C-page 21  2011-2012 Microchip Technology Inc.

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

INDF0

480h

INDF0

500h

INDF0

580h

INDF0

600h

INDF0

680h

INDF0

700h

INDF0

780h

INDF0

401h

INDF1

481h

INDF1

501h

INDF1

581h

INDF1

601h

INDF1

681h

INDF1

701h

INDF1

781h

INDF1

402h

PCL

482h

PCL

502h

PCL

582h

PCL

602h

PCL

682h

PCL

702h

PCL

782h

PCL

403h

STATUS

483h

STATUS

503h

STATUS

583h

STATUS

603h

STATUS

683h

STATUS

703h

STATUS

783h

STATUS

404h

FSR0L

484h

FSR0L

504h

FSR0L

584h

FSR0L

604h

FSR0L

684h

FSR0L

704h

FSR0L

784h

FSR0L

405h

FSR0H

485h

FSR0H

505h

FSR0H

585h

FSR0H

605h

FSR0H

685h

FSR0H

705h

FSR0H

785h

FSR0H

406h

FSR1L

486h

FSR1L

506h

FSR1L

586h

FSR1L

606h

FSR1L

686h

FSR1L

706h

FSR1L

786h

FSR1L

407h

FSR1H

487h

FSR1H

507h

FSR1H

587h

FSR1H

607h

FSR1H

687h

FSR1H

707h

FSR1H

787h

FSR1H

408h

BSR

488h

BSR

508h

BSR

588h

BSR

608h

BSR

688h

BSR

708h

BSR

788h

BSR

409h

WREG

489h

WREG

509h

WREG

589h

WREG

609h

WREG

689h

WREG

709h

WREG

789h

WREG

40Ah

PCLATH

48Ah

PCLATH

50Ah

PCLATH

58Ah

PCLATH

60Ah

PCLATH

68Ah

PCLATH

70Ah

PCLATH

78Ah

PCLATH

40Bh

INTCON

48Bh

INTCON

50Bh

INTCON

58Bh

INTCON

60Bh

INTCON

68Bh

INTCON

70Bh

INTCON

78Bh

INTCON

40Ch

—

48Ch

—

50Ch

—

58Ch

—

60Ch

—

68Ch

—

70Ch

—

78Ch

—

40Dh

—

48Dh

—

50Dh

—

58Dh

—

60Dh

—

68Dh

—

70Dh

—

78Dh

—

40Eh

—

48Eh

—

50Eh

—

58Eh

—

60Eh

—

68Eh

—

70Eh

—

78Eh

—

40Fh

—

48Fh

—

50Fh

—

58Fh

—

60Fh

—

68Fh

—

70Fh

—

78Fh

—

410h

—

490h

—

510h

—

590h

—

610h

—

690h

—

710h

—

790h

—

411h

—

491h

—

511h

—

591h

—

611h

—

691h

—

711h

—

791h

See Ta bl e 3 -7

412h

—

492h

—

512h

—

592h

—

612h

—

692h

—

712h

—

792h

413h

—

493h

—

513h

—

593h

—

613h

—

693h

—

713h

—

793h

414h

—

494h

—

514h

—

594h

—

614h

—

694h

—

714h

—

794h

415h

TMR4

495h

—

515h

—

595h

—

615h

—

695h

—

715h

—

795h

416h

PR4

496h

—

516h

—

596h

—

616h

—

696h

—

716h

—

796h

417h

T4CON

497h

—

517h

—

597h

—

617h

—

697h

—

717h

—

797h

418h

—

498h

—

518h

—

598h

—

618h

—

698h

—

718h

—

798h

419h

—

499h

—

519h

—

599h

—

619h

—

699h

—

719h

—

799h

41Ah

—

49Ah

—

51Ah

—

59Ah

—

61Ah

—

69Ah

—

71Ah

—

79Ah

41Bh

—

49Bh

—

51Bh

—

59Bh

—

61Bh

—

69Bh

—

71Bh

—

79Bh

41Ch

TMR6

49Ch

—

51Ch

—

59Ch

—

61Ch

—

69Ch

—

71Ch

—

79Ch

41Dh

PR6

49Dh

—

51Dh

—

59Dh

—

61Dh

—

69Dh

—

71Dh

—

79Dh

41Eh

T6CON

49Eh

—

51Eh

—

59Eh

—

61Eh

—

69Eh

—

71Eh

—

79Eh

41Fh

—

49Fh

—

51Fh

—

59Fh

—

61Fh

—

69Fh

—

71Fh

—

79Fh

420h

Unimplemented

Read as ‘0’

4A0h

Unimplemented

Read as ‘0’

520h

Unimplemented

Read as ‘0’

5A0h

Unimplemented

Read as ‘0’

620h

Unimplemented

Read as ‘0’

6A0h

Unimplemented

Read as ‘0’

720h

Unimplemented

Read as ‘0’

7A0h

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h

Accesses
70h – 7Fh

4F0h

Accesses
70h – 7Fh

570h

Accesses

70h – 7Fh

5F0h

Accesses

70h – 7Fh

670h

Accesses

70h – 7Fh

6F0h

Accesses

70h – 7Fh

770h

Accesses

70h – 7Fh

7F0h

Accesses

70h – 7Fh

47Fh

4FFh 57Fh

5FFh 67Fh 6FFh 77Fh 7FFh

TABLE 3-4: PIC16(L)F1933 MEMORY MAP, BANKS 8-15

PIC16(L)F1933

DS41575C-page 22  2011-2012 Microchip Technology Inc.

TABLE 3-5: PIC16(L)F1933 MEMORY MAP, BANKS 16-23

PIC16(L)F1933

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0
801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1
802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL
803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS
804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L
805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H
806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L
807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H
808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR
809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG
80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH
80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
81Fh

820h

— 88Ch — 90Ch — 98Ch —A0Ch—A8Ch—B0Ch—B8Ch—
— 88Dh — 90Dh — 98Dh —A0Dh—A8Dh—B0Dh—B8Dh—
—88Eh—90Eh—98Eh—A0Eh—A8Eh—B0Eh—B8Eh—
—88Fh—90Fh—98Fh—A0Fh—A8Fh—B0Fh—B8Fh—
—890h—910h—990h—A10h—A90h—B10h—B90h—
—891h—911h—991h—A11h—A91h—B11h—B91h—
—892h—912h—992h—A12h—A92h—B12h—B92h—
—893h—913h—993h—A13h—A93h—B13h—B93h—
—894h—914h—994h—A14h—A94h—B14h—B94h—
—895h—915h—995h—A15h—A95h—B15h—B95h—
—896h—916h—996h—A16h—A96h—B16h—B96h—
—897h—917h—997h—A17h—A97h—B17h—B97h—
—898h—918h—998h—A18h—A98h—B18h—B98h—
—899h—919h—999h—A19h—A99h—B19h—B99h—
—89Ah—91Ah—99Ah—A1Ah—A9Ah—B1Ah—B9Ah—
—89Bh—91Bh—99Bh—A1Bh—A9Bh—B1Bh—B9Bh—
— 89Ch — 91Ch — 99Ch —A1Ch—A9Ch—B1Ch—B9Ch—
— 89Dh — 91Dh — 99Dh —A1Dh—A9Dh—B1Dh—B9Dh—
—89Eh—91Eh—99Eh—A1Eh—A9Eh—B1Eh—B9Eh—
—89Fh—91Fh—99Fh—A1Fh—A9Fh—B1Fh—B9Fh—

8A0h

920h

9A0h

A20h

AA0h

B20h

BA0h

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh
870h

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Accesses
70h – 7Fh

8F0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

970h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

9EFh
9F0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

A6Fh
A70h

Unimplemented

Read as ‘0’

Accesses
70h – 7Fh

AEFh
AF0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

B6Fh
B70h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

BEFh
BF0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

DS41575C-page 23  2011-2012 Microchip Technology Inc.

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0
C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1
C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL
C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS
C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L
C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H
C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L
C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H
C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR

C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG
C0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATH
C0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCON
C0Ch

—C8Ch—D0Ch—D8Ch—E0Ch—E8Ch—F0Ch—F8Ch

See Ta bl e 3 -8

C0Dh

—C8Dh—D0Dh—D8Dh—E0Dh—E8Dh—F0Dh—F8Dh

C0Eh

—C8Eh—D0Eh—D8Eh—E0Eh—E8Eh—F0Eh—F8Eh

C0Fh

—C8Fh—D0Fh—D8Fh—E0Fh—E8Fh—F0Fh—F8Fh

C10h

—C90h—D10h—D90h—E10h—E90h—F10h—F90h

C11h

—C91h—D11h—D91h—E11h—E91h—F11h—F91h

C12h

—C92h—D12h—D92h—E12h—E92h—F12h—F92h

C13h

—C93h—D13h—D93h—E13h—E93h—F13h—F93h

C14h

—C94h—D14h—D94h—E14h—E94h—F14h—F94h

C15h

—C95h—D15h—D95h—E15h—E95h—F15h—F95h

C16h

—C96h—D16h—D96h—E16h—E96h—F16h—F96h

C17h

—C97h—D17h—D97h—E17h—E97h—F17h—F97h

C18h

—C98h—D18h—D98h—E18h—E98h—F18h—F98h

C19h

—C99h—D19h—D99h—E19h—E99h—F19h—F99h

C1Ah

—C9Ah—D1Ah—D9Ah—E1Ah—E9Ah—F1Ah—F9Ah

C1Bh

—C9Bh—D1Bh—D9Bh—E1Bh—E9Bh—F1Bh—F9Bh

C1Ch

—C9Ch—D1Ch—D9Ch—E1Ch—E9Ch—F1Ch—F9Ch

C1Dh

—C9Dh—D1Dh—D9Dh—E1Dh—E9Dh—F1Dh—F9Dh

C1Eh

—C9Eh—D1Eh—D9Eh—E1Eh—E9Eh—F1Eh—F9Eh

C1Fh

—C9Fh—D1Fh—D9Fh—E1Fh—E9Fh—F1Fh—F9Fh

C20h

Unimplemented

Read as ‘0’

CA0h

Unimplemented

Read as ‘0’

D20h

Unimplemented

Read as ‘0’

DA0h

Unimplemented

Read as ‘0’

E20h

Unimplemented

Read as ‘0’

EA0h

Unimplemented

Read as ‘0’

F20h

Unimplemented

Read as ‘0’

FA0h

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh

C70h

Accesses
70h – 7Fh

CF0h

Accesses
70h – 7Fh

D70h

Accesses

70h – 7Fh

DF0h

Accesses

70h – 7Fh

E70h

Accesses

70h – 7Fh

EF0h

Accesses

70h – 7Fh

F70h

Accesses

70h – 7Fh

FF0h

Accesses

70h – 7Fh

CFFh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-6: PIC16(L)F1933 MEMORY MAP, BANKS 24-31

PIC16(L)F1933

PIC16(L)F1933

Legend: = Unimplemented data memory locations, read

as ‘0’.

Bank 15

791h

LCDCON

792h

LCDPS

793h

LCDREF

794h

LCDCST

795h

LCDRL

796h

—

797h

—

798h

LCDSE0

799h

LCDSE1

79Ah

—

79Bh

—

79Ch

—

79Dh

—

79Eh

—

79Fh

—
7A0h LCDDATA0
7A1h LCDDATA1

7A2h

—
7A3h LCDDATA3
7A4h LCDDATA4

7A5h

—
7A6h LCDDATA6
7A7h LCDDATA7

7A8h

—
7A9h LCDDATA9

7AAh LCDDATA10
7ABh

—
7ACh

—
7ADh

—
7AEh

—
7AFh

—
7B0h

—
7B1h

—

7B2h

—
7B3h

—
7B4h

—
7B5h

—
7B6h

—
7B7h

—
7B8h

Unimplemented

Read as ‘0’

7EFh

Legend: = Unimplemented data memory locations, read

as ‘0’.

Bank 31

F8Ch

Unimplemented

Read as ‘0’

FE3h
FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

TABLE 3-7: PIC16(L)F1933 MEMORY MAP,

BANK 15

DS41575C-page 24  2011-2012 Microchip Technology Inc.

TABLE 3-8: PIC16(L)F1933 MEMORY MAP,

BANK 31

3.3.5 SPECIAL FUNCTION REGISTERS SUMMARY

The Special Function Register Summary for the device
family are as follows:

Device Bank(s) Page No.

0 25
1 26
2 27
3 28
4 29
5 30

PIC16(L)F1933

6 31
7 32
8 33

9-14 34

15 35

16-30 36

31 37

PIC16(L)F1933

=

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

(2)

000h

001h

002h

003h

004h

005h

006h

007h

008h

009h

00Ah

00Bh

00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu

00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

00Fh

010h PORTE

011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF

013h PIR3

014h

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000

01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111

01Ch T2CON

01Dh

01Eh CPSCON0 CPSON CPSRM

01Fh CPSCON1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

— — — —RE3— — — ---- x--- ---- u---

— CCP2IF 0000 00-0 0000 00-0

— CCP5IF CCP4IF CCP3IF TMR6IF —TMR4IF— -000 0-0- -000 0-0-

—TMR1ON0000 00-0 uuuu uu-u

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

DONE

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

— — CPSRNG1 CPSRNG0 CPSOUT T0XCS 00-- 0000 00-- 0000

— — — — —CPSCH<2:0>---- -000 ---- -000

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

 2011-2012 Microchip Technology Inc. DS41575C-page 25

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(2)

080h

081h

082h

083h

084h

085h

086h

087h

088h

089h

08Ah

08Bh

08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111

08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111

08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111

08Fh

090h TRISE

091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE

093h PIE3

094h

095h OPTION_REG WPUEN

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

099h OSCCON SPLLEN IRCF<3:0>

09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR

09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu

09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS<2:0>

09Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

— — — — —

— CCP5IE CCP4IE CCP3IE TMR6IE —TMR4IE— -000 0-0- -000 0-0-

INTEDG TMROCS TMROSE PSA PS<2:0> 1111 1111 1111 1111

— —RMCLRRI POR BOR 00-- 11qq qq-- qquu

— —WDTPS<4:0>SWDTEN--01 0110 --01 0110

— — TUN<5:0> --00 0000 --00 0000

— CHS<4:0>

(3)

— ADNREF

— — — ---- 1--- ---- 1---

—SCS<1:0>0011 1-00 0011 1-00

— CCP2IE 0000 00-0 0000 00-0

HFIOFS 00q0 0q0- qqqq qq0-

GO/DONE

ADPREF1

ADON -000 0000 -000 0000

ADPREF0 0000 -000 0000 -000

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41575C-page 26  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

(2)

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu

10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu

10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu

10Fh

110h

111h CM1CON0 C1ON C1OUT C1OE C1POL

112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0

113h CM2CON0 C2ON C2OUT C2OE C2POL

114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0

115h CMOUT

116h BORCON SBOREN

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR<1:0> 0q00 0000 0q00 0000

118h DACCON0 DACEN DACLPS DACOE

119h DACCON1

11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000

11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000

11Ch

11Dh APFCON

11Eh

11Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

— C1SP C1HYS C1SYNC 0000 -100 0000 -100

— —C1NCH<1:0>0000 --00 0000 --00

— C2SP C2HYS C2SYNC 0000 -100 0000 -100

— —C2NCH<1:0>0000 --00 0000 --00

— — — — — — MC2OUT MC1OUT ---- --00 ---- --00

— — — — — — BORRDY 1--- ---q u--- ---u

--- DACPSS<1:0> --- DACNSS 000- 00-0 000- 00-0

--- --- --- DACR<4:0> ---0 0000 ---0 0000

— CCP3SEL T1GSEL P2BSEL SRNQSEL

C2OUTSEL

SSSEL CCP2SEL -000 0000 -000 0000

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

 2011-2012 Microchip Technology Inc. DS41575C-page 27

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

(2)

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch ANSELA

18Dh ANSELB

18Eh

18Fh

190h

191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000

192h EEADRH

193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h EEDATH

195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000

196h EECON2 EEPROM control register 2 0000 0000 0000 0000

197h

198h

199h RCREG USART Receive Data Register 0000 0000 0000 0000

19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000

19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000

19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

— — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

(3)

—

EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000

— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41575C-page 28  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 4

(2)

200h

201h

202h

203h

204h

205h

206h

207h

208h

209h

20Ah

20Bh

20Ch

20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

20Eh

20Fh

210h WPUE

211h SSPBUF

212h SSPADD

213h SSPMSK

214h SSPSTAT SMP CKE D/A

215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

219h

21Ah

21Bh

21Ch

21Dh

21Eh

21Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

— — — — WPUE3 — — — ---- 1--- ---- 1---

Synchronous Serial Port Receive Buffer/Transmit Register

ADD<7:0>

MSK<7:0>

PSR/WUA BF 0000 0000 0000 0000

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

Value on all

other

Resets

 2011-2012 Microchip Technology Inc. DS41575C-page 29

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 5

(2)

280h

281h

282h

283h

284h

285h

286h

287h

288h

289h

28Ah

28Bh

28Ch

28Dh

28Eh

28Fh

290h

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000

294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000

295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000

296h PSTR1CON

297h

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

29Ah CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000 0000 0000

29Bh PWM2CON P2RSEN P2DC<6:0> 0000 0000 0000 0000

29Ch CCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 0000 0000 0000 0000

29Dh PSTR2CON

29Eh CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000

29Fh CCPTMRS1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

— — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001

— — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001

— — — — — — C5TSEL<1:0> ---- --00 ---- --00

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41575C-page 30  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 6

(2)

300h

301h

302h

303h

304h

305h

306h

307h

308h

309h

30Ah

30Bh

30Ch

30Dh

30Eh

30Fh

310h

311h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu

312h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu

313h CCP3CON P3M<1:0> DC3B<1:0> CCP3M<1:0> 0000 0000 0000 0000

314h PWM3CON P3RSEN P3DC<6:0> 0000 0000 0000 0000

315h CCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 0000 0000 0000 0000

316h PSTR3CON

317h

318h CCPR4L Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu

319h CCPR4H Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu

31Ah CCP4CON

31Bh

31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) xxxx xxxx uuuu uuuu

31Dh CCPR5H Capture/Compare/PWM Register 5 (MSB) xxxx xxxx uuuu uuuu

31Eh CCP5CON

31Fh — Unimplemented — —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

— — — STR3SYNC STR3D STR3C STR3B STR3A ---0 0001 ---0 0001

— — DC4B<1:0> CCP4M<3:0> --00 0000 --00 0000

— — DC5B<1:0> CCP5M<3:0> --00 0000

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

--00 0000

 2011-2012 Microchip Technology Inc. DS41575C-page 31

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 7

(2)

380h

381h

382h

383h

384h

385h

386h

387h

388h

389h

38Ah

38Bh

38Ch

38Dh

38Eh

38Fh

390h

391h

392h

393h

394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000

395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000

396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000

397h

398h

399h

39Ah

39Bh

39Ch

39Dh

39Eh

39Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41575C-page 32  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 8

(2)

400h

401h

402h

403h

404h

405h

406h

407h

408h

409h

40Ah

40Bh

40Ch

40Dh

40Eh

40Fh

410h

411h

412h

413h

414h

415h TMR4 Timer 4 Module Register 0000 0000 0000 0000

416h PR4 Timer 4 Period Register 1111 1111 1111 1111

417h T4CON

418h

419h

41Ah

41Bh

41Ch TMR6 Timer 6 Module Register 0000 0000 0000 0000

41Dh PR6 Timer 6 Period Register 1111 1111 1111 1111

41Eh T6CON

41Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

—

—

T4OUTPS<3:0>

T6OUTPS<3:0>

TMR4ON T4CKPS<1:0> -000 0000 -000 0000

TMR6ON T6CKPS<1:0> -000 0000 -000 0000

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

 2011-2012 Microchip Technology Inc. DS41575C-page 33

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Banks 9-14

x00h/
x80h

x00h/
x81h

x02h/
x82h

x03h/
x83h

x04h/
x84h

x05h/
x85h

x06h/
x86h

x07h/
x87h

x08h/
x88h

x09h/
x89h

x0Ah/
x8Ah

x0Bh/
x8Bh

x0Ch/
x8Ch
—
x1Fh/
x9Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1),(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

(2)

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41575C-page 34  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 15

(2)

780h

781h

782h

783h

784h

785h

786h

787h

788h

789h

78Ah

78Bh

78Ch
—
790h

791h LCDCON LCDEN SLPEN WERR

792h LCDPS WFT BIASMD LCDA WA LP

793h LCDREF LCDIRE LCDIRS LCDIRI

794h LCDCST

795h LCDRL LRLAP

796h

797h

798h LCDSE0 SE<7:0> 0000 0000 uuuu uuuu

799h LCDSE1 SE<15:8> 0000 0000 uuuu uuuu

79Ah
—
79Fh

7A0h LCDDATA0 SEG7

7A1h LCDDATA1 SEG15

7A2h

7A3h LCDDATA3 SEG7

7A4h LCDDATA4 SEG15

7A5h

7A6h LCDDATA6 SEG7

7A7h LCDDATA7 SEG15

7A8h

7A9h LCDDATA9 SEG7

7AAh LCDDATA10 SEG15

7ABh
—
7EFh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1, 2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

—CS<1:0> LMUX<1:0> 000- 0011 000- 0011

<3:0> 0000 0000 0000 0000

— VLCD3PE VLCD2PE VLCD1PE — 000- 000- 000- 000-

— — — — — LCDCST<2:0> ---- -000 ---- -000

<1:0> LRLBP<1:0> —LRLAT<2:0> 0000 -000 0000 -000

COM0

COM0

COM1

COM1

COM2

COM2

COM3

COM3

SEG6
COM0

SEG14

COM0

SEG6
COM1

SEG14

COM1

SEG6
COM2

SEG14

COM2

SEG6
COM3

SEG14

COM3

SEG5

COM0

SEG13

COM0

SEG5

COM1

SEG13

COM1

SEG5

COM2

SEG13

COM2

SEG5

COM3

SEG13

COM3

SEG4
COM0

SEG12

COM0

SEG4
COM1

SEG12

COM1

SEG4
COM2

SEG12

COM2

SEG4
COM3

SEG12

COM3

SEG3

COM0

SEG11
COM0

SEG3

COM1

SEG11
COM1

SEG3

COM2

SEG11
COM2

SEG3

COM3

SEG11
COM3

SEG2

COM0

SEG10

COM0

SEG2

COM1

SEG10

COM1

SEG2

COM2

SEG10

COM2

SEG2

COM3

SEG10

COM3

SEG1

COM0

SEG9

COM0

SEG1

COM1

SEG9

COM1

SEG1

COM2

SEG9

COM2

SEG1

COM3

SEG9

COM3

SEG0

COM0

SEG8

COM0

SEG0

COM1

SEG8

COM1

SEG0

COM2

SEG8

COM2

SEG0

COM3

SEG8

COM3

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Value on all

other

Resets

 2011-2012 Microchip Technology Inc. DS41575C-page 35

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Banks 16-30

x00h/
x80h

x00h/
x81h

x02h/
x82h

x03h/
x83h

x04h/
x84h

x05h/
x85h

x06h/
x86h

x07h/
x87h

x08h/
x88h

x09h/
x89h

x0Ah/
x8Ah

x0Bh/
x8Bh

x0Ch/
x8Ch
—
x1Fh/
x9Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1),(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

(2)

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41575C-page 36  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 31

(2)

F80h

F81h

F82h

F83h

F84h

F85h

F86h

F87h

F88h

F89h

F8Ah

F8Bh

F8Ch
—
FE3h

FE4h STATUS_

FE5h WREG_

FE6h BSR_

FE7h PCLATH_

FE8h FSR0L_

FE9h FSR0H_

FEAh FSR1L_

FEBh FSR1H_

FECh

FEDh

FEEh

FEFh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(2)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(2)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(2)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(2)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(2)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(2)

WREG Working Register 0000 0000 uuuu uuuu

(1),(2)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(2)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

— Unimplemented — —

SHAD

SHAD

SHAD

SHAD

SHAD

SHAD

SHAD

SHAD

— Unimplemented — —

STKPTR

TOSL

TOSH

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

(not a physical register)

(not a physical register)

Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu

Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

Bank Select Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu

Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx uuuu uuuu

Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

— — — Current Stack pointer ---1 1111 ---1 1111

Top of Stack Low byte xxxx xxxx uuuu uuuu

— Top of Stack High byte -xxx xxxx -uuu uuuu

Val ue o n

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

 2011-2012 Microchip Technology Inc. DS41575C-page 37

PIC16(L)F1933

PCLPCH

0

14

PC

06

7

ALU Result

8

PCLATH

PCLPCH

0

14

PC

06

4

OPCODE <10:0>

11

PCLATH

PCLPCH

0

14

PC

06

7

W

8

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH

0

14

PC

PC + W

15

BRW

PCLPCH

0

14

PC

PC + OPCODE <8:0>

15

BRA

3.4 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-3 shows the five
situations for the loading of the PC.

FIGURE 3-3: LOADING OF PC IN

DIFFERENT SITUATIONS

3.4.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by com­bining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.

3.4.4 BRANCHING

The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.

If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.

3.4.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program Counter
PC<14:8> bits (PCH) to be replaced by the contents of
the PCLATH register. This allows the entire contents of
the program counter to be changed by writing the
desired upper seven bits to the PCLATH register. When
the lower eight bits are written to the PCL register, all 15
bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.

3.4.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).

DS41575C-page 38  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled
(STVREN = 0)

Stack Reset Enabled
(STVREN = 1)

TOSH:TOSL

TOSH:TOSL

3.5 Stack

All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-4 through 3-7). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Word 2). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over­flow/Underflow, regardless of whether the Reset is
enabled.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the

CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to

an interrupt address.

3.5.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time, STKPTR can be inspected to see how much
stack is left. The STKPTR always points at the currently
used place on the stack. Therefore, a CALL or CALLW
will increment the STKPTR and then write the PC, and
a return will unload the PC and then decrement the
STKPTR.

Reference Figure 3-4 through Figure 3-7 for examples
of accessing the stack.

FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1

 2011-2012 Microchip Technology Inc. DS41575C-page 39

PIC16(L)F1933

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00

STKPTR = 0x00

This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.

TOSH:TOSL

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3

DS41575C-page 40  2011-2012 Microchip Technology Inc.

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

TOSH:TOSL

PIC16(L)F1933

3.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.

3.6 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

 2011-2012 Microchip Technology Inc. DS41575C-page 41

PIC16(L)F1933

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000

Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

FIGURE 3-8: INDIRECT ADDRESSING

DS41575C-page 42  2011-2012 Microchip Technology Inc.

3.6.1 TRADITIONAL DATA MEMORY

Indirect AddressingDirect Addressing

Bank Select

Location Select

4 BSR 6

0

From Opcode

FSRxL70

Bank Select

Location Select

0000 0001 0010 1111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

0

FSRxH70

0000

The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.

FIGURE 3-9: TRADITIONAL DATA MEMORY MAP

PIC16(L)F1933

 2011-2012 Microchip Technology Inc. DS41575C-page 43

PIC16(L)F1933

7

0

1

7

0

0

Location Select

0x2000

FSRnH

FSRnL

0x020

Bank 0

0x06F

0x0A0
Bank 1
0x0EF
0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

0

7

1

7

0

0

Location Select

0x8000

FSRnH

FSRnL

0x0000

0x7FFF

0xFFFF

Program
Flash
Memory
(low 8
bits)

3.6.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.

The 16 bytes of common memory are not included in
the linear data memory region.

FIGURE 3-10: LINEAR DATA MEMORY

MAP

3.6.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.

FIGURE 3-11: PROGRAM FLASH

MEMORY MAP

DS41575C-page 44  2011-2012 Microchip Technology Inc.

4.0 DEVICE CONFIGURATION

Device configuration consists of Configuration Words,
Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Words is

managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.

PIC16(L)F1933

 2011-2012 Microchip Technology Inc. DS41575C-page 45

PIC16(L)F1933

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FCMEN IESO CLKOUTEN BOREN<1:0> CPD

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CP

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

bit 12 IESO: Internal External Switchover bit

bit 11 CLKOUTEN

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

bit 8 CPD

bit 7 CP

bit 6 MCLRE: MCLR

bit 5 PWRTE

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled

1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled

: Clock Out Enable bit

1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT
0 = CLKOUT function is enabled on RA6/CLKOUT

(1)

11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled

: Data Code Protection bit

1 = Data memory code protection is disabled
0 = Data memory code protection is enabled

: Code Protection bit

1 = Program memory code protection is disabled
0 = Program memory code protection is enabled

/VPP Pin Function Select bit

If LVP bit =

This bit is ignored.

If LVP bit = 0:

1 =MCLR
0 =MCLR

1 = PWRT disabled
0 = PWRT enabled

1:

/VPP pin function is MCLR; Weak pull-up enabled.
/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

: Power-up Timer Enable bit

(2)

(3)

(1)

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off during
3: The entire program memory will be erased when the code protection is turned off.

DS41575C-page 46  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit

11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off during
3: The entire program memory will be erased when the code protection is turned off.

 2011-2012 Microchip Technology Inc. DS41575C-page 47

PIC16(L)F1933

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1

LVP

(1)

DEBUG

bit 13 bit 8

U-1 U-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1

— — VCAPEN<1:0>

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

(2)

(3)

—BORVSTVRENPLLEN

— —WRT<1:0>

bit 13 LVP: Low-Voltage Programming Enable bit

(1)

1 = Low-voltage programming enabled
0 = High-voltage on MCLR

bit 12 DEBUG: In-Circuit Debugger Mode bit

must be used for programming

(3)

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11 Unimplemented: Read as ‘1’
bit 10 BORV: Brown-out Reset Voltage Selection bit

(4)

1 = Brown-out Reset voltage (Vbor), low trip point selected.
0 = Brown-out Reset voltage (Vbor), high trip point selected.

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset

bit 8 PLLEN: PLL Enable bit

1 = 4xPLL enabled
0 = 4xPLL disabled

bit 7-5 Unimplemented: Read as ‘1’
bit 4 VCAPEN

: Voltage Regulator Capacitor Enable bits

(2)

00 =VCAP functionality is enabled on RA0
01 =V

CAP functionality is enabled on RA5
CAP functionality is enabled on RA6

10 =V
11 = No capacitor on V

CAP pin

bit 3-2 Unimplemented: Read as ‘1’
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

CAP functionality is enabled on RA0

00 =V
01 =V

CAP functionality is enabled on RA5
CAP functionality is enabled on RA6

10 =V
11 = No capacitor on V

CAP pin

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: Reads as ‘11’ on PIC16LF193X only.
3: The DEBUG

bit in Configuration Words is managed automatically by device development tools including

debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

4: See Vbor parameter for specific trip point voltages.

DS41575C-page 48  2011-2012 Microchip Technology Inc.

4.3 Code Protection

Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data EEPROM protection are controlled independently.
Internal access to the program memory and data
EEPROM are unaffected by any code protection
setting.

4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP
Words. When CP
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write

Protection” for more information.

= 0, external reads and writes of

4.3.2 DATA EEPROM PROTECTION

The entire data EEPROM is protected from external
reads and writes by the CPD
external reads and writes of data EEPROM are
inhibited. The CPU can continue to read and write data
EEPROM regardless of the protection bit settings.

bit in Configuration

bit. When CPD = 0,

PIC16(L)F1933

4.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.

4.5 User ID

Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See

Section 4.6 “Device ID and Revision ID” for more

information on accessing these memory locations.
more information on checksum calculation, see the
“PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF
190X Memory Programming Specification” (DS41397).

For

 2011-2012 Microchip Technology Inc. DS41575C-page 49

PIC16(L)F1933

Device

DEVID<13:0> Values

DEV<8:0> REV<4:0>

PIC16F1933 10 0011 001 x xxxx

PIC16LF1933 10 0100 001 x xxxx

4.6 Device ID and Revision ID

The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See

Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.

4.7 Register Definitions: Device ID

REGISTER 4-3: DEVID: DEVICE ID REGISTER

RRRRRR

DEV<8:3>

bit 13 bit 8

RRRRRRRR

DEV<2:0> REV<4:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-5 DEV<8:0>: Device ID bits

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

DS41575C-page 50  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

5.1 Overview

The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor­mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds
selectable via software. Additional clock features
include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and
code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

The oscillator module can be configured in one of eight
clock modes.

1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode
(0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode
(4 MHz to 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 32 MHz).

Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.

The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT, and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.

The INTOSC internal oscillator block produces low,
medium, and high-frequency clock sources,
designated LFINTOSC, MFINTOSC and HFINTOSC.
(see Internal Oscillator Block, Figure 5-1). A wide
selection of device clock frequencies may be derived
from these three clock sources.

 2011-2012 Microchip Technology Inc. DS41575C-page 51

PIC16(L)F1933

4x PLL

FOSC<2:0>

Oscillator

T1OSCEN
Enable
Oscillator

T1OSO

T1OSI

Clock Source Option
for other modules

OSC1

OSC2

Sleep

LP, XT, HS, RC, EC

T1OSC

CPU and

Postscaler

MUX

MUX

16 MHz

8 MHz
4 MHz
2 MHz
1 MHz

250 kHz

500 kHz

IRCF<3:0>

31 kHz

500 kHz

Source

Internal

Oscillator

Block

WDT, PWRT, Fail-Safe Clock Monitor

16 MHz

Internal Oscillator

(HFINTOSC)

Clock

Control

SCS<1:0>

HFPLL

31 kHz (LFINTOSC)

Two-Speed Start-up and other modules

Oscillator

31 kHz
Source

500 kHz

(MFINTOSC)

125 kHz

31.25 kHz

62.5 kHz

FOSC<2:0> = 100

Peripherals

Sleep

External

Timer1

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS41575C-page 52  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

OSC1/CLKIN

OSC2/CLKOUT

Clock from
Ext. System

PIC

®

MCU

FOSC/4 or

I/O

(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

5.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator
modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.

Internal clock sources are contained within the
oscillator module. The internal oscillator block has two
internal oscillators and a dedicated Phase-Lock Loop
(HFPLL) that are used to generate three internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC)
and the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).

The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3

“Clock Switching” for additional information.

5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device
system clock by performing one of the following
actions:

• Program the FOSC<2:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.

• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:

- Timer1 oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “Clock Switching”for more
information.

5.2.1.1 EC Mode

The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.

EC mode has three power modes to select from through
Configuration Words:

• High power, 4-32 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low power, 0-0.5 MHz (FOSC = 101)

The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC

®

MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

5.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.

LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).

XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.

HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

 2011-2012 Microchip Technology Inc. DS41575C-page 53

PIC16(L)F1933

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

C1

C2

Quartz

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (R

P)

may be required for proper ceramic resonator
operation.

C1

C2

Ceramic

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

RP

(3)

Resonator

OSC2/CLKOUT

FIGURE 5-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR
HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC
Devices” (DS00826)

• AN849, “Basic PIC
(DS00849)

• AN943, “Practical PIC
Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”
(DS00949)

®

and PIC®

®

Oscillator Design”

®

Oscillator

FIGURE 5-4: CERAMIC RESONATOR

OPERATION
(XT OR HS MODE)

5.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended unless
either FSCM or Two-Speed Start-Up are enabled. In
this case code will continue to execute at the selected
INTOSC frequency while the OST is counting. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.

In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4

“Two-Speed Clock Start-up Mode”).

DS41575C-page 54  2011-2012 Microchip Technology Inc.

5.2.1.4 4x PLL

The oscillator module contains a 4x PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4x PLL must fall within specifications. See the PLL
Clock Timing specifications in Section 30.0

“Electrical Specifications”.

PIC16(L)F1933

C1

C2

32.768 kHz

T1OSI

To Internal
Logic

PIC® MCU

Crystal

T1OSO

Quartz

The 4x PLL may be enabled for use by one of two
methods:

1. Program the PLLEN bit in Configuration Words
to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to
a ‘1’. If the PLLEN bit in Configuration Words is
programmed to a ‘1’, then the value of SPLLEN
is ignored.

5.2.1.5 TIMER1 Oscillator

The Timer1 oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is opti­mized for timekeeping operations with a 32.768 kHz
crystal connected between the T1OSO and T1OSI
device pins.

The Timer1 oscillator can be used as an alternate
system clock source and can be selected during
run-time using clock switching. Refer to Section 5.3

“Clock Switching” for more information.

FIGURE 5-5: QUARTZ CRYSTAL

OPERATION (TIMER1
OSCILLATOR)

Note 1: Quartz crystal characteristics vary

according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

®

and PIC®

Devices” (DS00826)

®

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

®

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”
(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for
Low-Power External Oscillators”

(DS01288)

5.2.1.6 External RC Mode

The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.

The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN

Figure 5-6 shows the external RC mode connections.

bit in Configuration Words.

 2011-2012 Microchip Technology Inc. DS41575C-page 55

PIC16(L)F1933

OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

F

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  R

EXT  100 k, 3-5V

C

EXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

I/O

(1)

FIGURE 5-6: EXTERNAL RC MODES

The RC oscillator frequency is a function of the supply
voltage, the resistor (R
and the operating temperature. Other factors affecting
the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due
to tolerance of external RC components used.

EXT) and capacitor (CEXT) values

DS41575C-page 56  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

5.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal
oscillator block as the system clock by performing one
of the following actions:

• Program the FOSC<2:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.

• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3

“Clock Switching”for more information.

In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN

The internal oscillator block has two independent
oscillators and a dedicated Phase-Lock Loop, HFPLL
that can produce one of three internal system clock
sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
dedicated Phase-Lock Loop, HFPLL. The
frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 5-3).

2. The MFINTOSC (Medium-Frequency Internal

Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the

OSCTUNE register (Register 5-3).

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at
31 kHz.

bit in Configuration Words.

5.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).

The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of multiple
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.

A fast start-up oscillator allows internal circuits to
power-up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.

The High-Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.

The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.

5.2.2.2 MFINTOSC

The Medium-Frequency Internal Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 5-3).

The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The MFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’

The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.

 2011-2012 Microchip Technology Inc. DS41575C-page 57

PIC16(L)F1933

5.2.2.3 Internal Oscillator Frequency
Adjustment

The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator a change in
the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.

When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.

5.2.2.4 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a multiplexer
(see Figure 5-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See

Section 5.2.2.7 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also

the frequency for the Power-up Timer (PWRT),
Watchdog Timer (WDT) and Fail-Safe Clock Monitor
(FSCM).

The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired LF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.

5.2.2.5 Internal Oscillator Frequency
Selection

The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 5-1). The Internal Oscillator Frequency
Select bits IRCF<3:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
the following frequencies can be selected via software:

- 32 MHz (requires 4x PLL)

-16 MHz

-8 MHz

-4 MHz

-2 MHz

-1 MHz

- 500 kHz (default after Reset)

-250 kHz

-125 kHz

-62.5 kHz

-31.25 kHz

- 31 kHz (LFINTOSC)

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These
duplicate choices can offer system design trade-offs.
Lower power consumption can be obtained when
changing oscillator sources for a given frequency.
Faster transition times can be obtained between
frequency changes that use the same oscillator source.

DS41575C-page 58  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

5.2.2.6 32 MHz Internal Oscillator
Frequency Selection

The Internal Oscillator Block can be used with the 4x
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz
internal clock source:

• The FOSC bits in Configuration Words must be

set to use the INTOSC source as the device
system clock (FOSC<2:0> = 100).

• The SCS bits in the OSCCON register must be

cleared to use the clock determined by
FOSC<2:0> in Configuration Words
(SCS<1:0> = 00).

• The IRCF bits in the OSCCON register must be

set to the 8 MHz HFINTOSC set to use
(IRCF<3:0> = 1110).

• The SPLLEN bit in the OSCCON register must be

set to enable the 4x PLL, or the PLLEN bit of the
Configuration Words must be programmed to a
‘1’.

Note: When using the PLLEN bit of the

Configuration Words, the 4x PLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.

The 4x PLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator.

5.2.2.7 Internal Oscillator Clock Switch
Timing

When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new
clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.

Start-up delay specifications are located in the
oscillator tables in Section 30.0 “Electrical

Specifications”.

 2011-2012 Microchip Technology Inc. DS41575C-page 59

PIC16(L)F1933

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

0 0

0 0

Start-up Time

2-cycle Sync Running

2-cycle Sync Running

HFINTOSC/ LFINTOSC (FSCM and WDT disabled)

HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC/

IRCF <3:0>

System Clock

= 0  0

Start-up Time 2-cycle Sync

Running

LFINTOSC HFINTOSC/MFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

MFINTOSC

MFINTOSC

MFINTOSC

MFINTOSC

MFINTOSC

FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING

DS41575C-page 60  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

5.3 Clock Switching

The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:

• Default system oscillator determined by FOSC
bits in Configuration Words

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

5.3.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.

• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.

5.3.3 TIMER1 OSCILLATOR

The Timer1 oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSO and T1OSI device
pins.

The Timer1 oscillator is enabled using the T1OSCEN
control bit in the T1CON register. See Section 21.0

“Timer1 Module with Gate Control” for more

information about the Timer1 peripheral.

5.3.4 TIMER1 OSCILLATOR READY

(T1OSCR) BIT

The user must ensure that the Timer1 oscillator is
ready to be used before it is selected as a system clock
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.

When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.

5.3.2 OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
counted 1024 clock cycles for LP, XT or HS modes. The
OST does not reflect the status of the Timer1 oscillator.

 2011-2012 Microchip Technology Inc. DS41575C-page 61

PIC16(L)F1933

5.4 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the
oscillator module is configured for LP, XT or HS
modes. The Oscillator Start-up Timer (OST) is enabled
for these modes and must count 1024 oscillations
before the oscillator can be used as the system clock
source.

If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.

If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT

register is set and program execution switches to the

external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.

5.4.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the
following settings:

• IESO (of the Configuration Words) = 1;

Internal/External Switchover bit (Two-Speed
Start-up mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

Note: When FSCM is enabled, Two-Speed

Start-Up will automatically be enabled.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.

TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

31 kHz

31.25 kHz-500 kHz

31.25kHz-16MHz
DC – 32 MHz 2 cycles
DC – 32 MHz 1 cycle of each

32 kHz-20 MHz 1024 Clock Cycles (OST)

31.25 kHz-500 kHz

31.25kHz-16MHz
31 kHz 1 cycle of each

2 cycles

2 s (approx.)

LFINTOSC

Sleep/POR

Sleep/POR EC, RC
LFINTOSC EC, RC

Sleep/POR

Any clock source

Any clock source LFINTOSC
Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST)
PLL inactive PLL active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.

MFINTOSC
HFINTOSC

Timer1 Oscillator
LP, XT, HS

MFINTOSC
HFINTOSC

DS41575C-page 62  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N

PC

5.4.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 5-8: TWO-SPEED START-UP

5.4.3 CHECKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Words, or the
internal oscillator.

 2011-2012 Microchip Technology Inc. DS41575C-page 63

PIC16(L)F1933

External

LFINTOSC

÷ 64

S

R

Q

31 kHz

(~32 s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Q

Sample Clock

5.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, Timer1
Oscillator and RC).

FIGURE 5-9: FSCM BLOCK DIAGRAM

5.5.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.

5.5.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared after successfully
switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
OSFIF flag will again become set by hardware.

5.5.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.

5.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.

The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

DS41575C-page 64  2011-2012 Microchip Technology Inc.

FIGURE 5-10: FSCM TIMING DIAGRAM

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator
Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te st

Test Test

Clock Monitor Output

PIC16(L)F1933

 2011-2012 Microchip Technology Inc. DS41575C-page 65

PIC16(L)F1933

5.6 Register Definitions: Oscillator Control

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
SPLLEN IRCF<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words =
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz HF
1110 = 8 MHz or 32 MHz HF(see Section 5.2.2.1 “HFINTOSC”)
1101 =4MHz HF
1100 =2MHz HF
1011 =1MHz HF
1010 = 500 kHz HF
1001 = 250 kHz HF
1000 = 125 kHz HF
0111 = 500 kHz MF (default upon Reset)
0110 = 250 kHz MF
0101 = 125 kHz MF
0100 = 62.5 kHz MF
0011 = 31.25 kHz HF
0010 = 31.25 kHz MF
000x =31kHz LF

bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block
01 = Timer1 oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.

(1)

(1)

(1)

(1)

1:

—

SCS<1:0>

Note 1: Duplicate frequency derived from HFINTOSC.

DS41575C-page 66  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q

T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional

bit 7 T1OSCR: Timer1 Oscillator Ready bit

If T1OSCEN =

1 = Timer1 oscillator is ready
0 = Timer1 oscillator is not ready

If T1OSCEN = 0
1 = Timer1 clock source is always ready

bit 6 PLLR 4x PLL Ready bit

1 = 4x PLL is ready
0 = 4x PLL is not ready

bit 5 OSTS: Oscillator Start-up Timer Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready
0 = HFINTOSC is not ready

bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit

1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate

bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit

1 = MFINTOSC is ready
0 = MFINTOSC is not ready

bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready
0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC is at least 0.5% accurate
0 = HFINTOSC is not 0.5% accurate

1:

:

 2011-2012 Microchip Technology Inc. DS41575C-page 67

PIC16(L)F1933

REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — TUN<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits

100000 = Minimum frequency

•

•

•

111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =

•

•

•

011110 =
011111 = Maximum frequency

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON SPLLEN IRCF<3:0>

OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR

OSCTUNE

PIE2 OSFIE

PIR2

T1CON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

— —TUN<5:0>68

C2IE C1IE EEIE BCLIE

OSFIF

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON

C2IF C1IF EEIF BCLIF LCDIF — CCP2IF

—SCS<1:0>66

HFIOFS 67

LCDIE

—

CCP2IE

TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

CONFIG2

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
Note 1: PIC16F1933 only.

13:8

7:0

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN<1:0> CPD

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

— — LVP DEBUG — BORV STVREN PLLEN

— — VCAPEN<1:0>

(1)

— — WRT<1:0>

Register
on Page

84

87

183

Register
on Page

46

48

DS41575C-page 68  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

External Reset

MCLR

VDD

WDT

Time-out

Power-on

Reset

LFINTOSC

PWRT

64 ms

PWRTEN

Brown-out

Reset

BOR

RESET Instruction

Stack

Pointer

Stack Overflow/Underflow Reset

Sleep

MCLRE

Enable

Device
Reset

Zero

Programming Mode Exit

6.0 RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To a l l o w V
can be enabled to extend the Reset time after a BOR
or POR event.

A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.

FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Reset

DD to stabilize, an optional power-up timer

 2011-2012 Microchip Technology Inc. DS41575C-page 69

PIC16(L)F1933

6.1 Power-On Reset (POR)

The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising V
performance may require greater than minimum V
The PWRT, BOR or MCLR
extend the start-up period until all device operation
conditions have been met.

6.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time­out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the V
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.

The Power-up Timer starts after the release of the POR
and BOR.

For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 6-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

DD, fast operating speeds or analog

DD.

features can be used to

DD to

11 X X Active Waits for BOR ready

6.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.

The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu­ration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 6 -3 for more information.

The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.

DD noise rejection filter prevents the BOR from

A V
triggering on small events. If V
a duration greater than parameter T
will reset. See Figure 6-2 for more information.

Instruction Execution upon:

Release of POR or Wake-up from Sleep

DD falls below VBOR for

BORDC, the device

(1)

(BORRDY = 1)

10 X

01

00 X XDisabled

Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.

1 X Active Waits for BOR ready

0 XDisabled

6.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and V
is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.

6.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and V

BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.

DD is higher than the BOR threshold.

Awake Active

Sleep Disabled

6.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the

DD

SBOREN bit of the BORCON register. The device start­up is not delayed by the BOR ready condition or the

DD level.

V

BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

Waits for BOR ready (BORRDY = 1)

(1)

(BORRDY = 1)

Begins immediately (BORRDY = x)

DS41575C-page 70  2011-2012 Microchip Technology Inc.

FIGURE 6-2: BROWN-OUT SITUATIONS

TPWRT

(1)

VBOR

V

DD

Internal

Reset

VBOR

V

DD

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

V

DD

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

PIC16(L)F1933

6.3 Register Definitions: BOR Control

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

bit 6-1 Unimplemented: Read as ‘0’

bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

— — — — — —BORRDY

If BOREN <1:0> in Configuration Words

 01:

SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words =

01:

1 = BOR Enabled
0 = BOR Disabled

1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive

 2011-2012 Microchip Technology Inc. DS41575C-page 71

PIC16(L)F1933

6.4 MCLR

The MCLR is an optional external input that can reset
the device. The MCLR
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).

TABLE 6-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled
10Enabled
x1Enabled

6.4.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR

DD through an internal weak pull-up.

V

The device has a noise filter in the MCLR
The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR pin low.

6.4.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.6 “PORTE

Registers” for more information.

function is controlled by the

pin is connected to

Reset path.

6.9 Power-up Timer

The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to

DD to stabilize before allowing the device to start

allow V
running.

The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.

6.10 Start-up Sequence

Upon the release of a POR or BOR, the following must
occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if
required for oscillator source).

3. MCLR

The total time-out will vary based on oscillator configu­ration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for more information.

The Power-up Timer and oscillator start-up timer run
independently of MCLR
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.

must be released (if enabled).

Reset. If MCLR is kept low long

6.5 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer (WDT)” for more information.

6.6 RESET Instruction

A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Ta b le 6- 4
for default conditions after a RESET instruction has
occurred.

6.7 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.5.2 “Overflow/Underflow

Reset” for more information.

6.8 Programming Mode Exit

Upon exit of Programming mode, the device will
behave as if a POR had just occurred.

DS41575C-page 72  2011-2012 Microchip Technology Inc.

FIGURE 6-3: RESET START-UP SEQUENCE

TOST

TMCLR

TPWRT

VDD

Internal POR

Power-Up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-Up Timer

Oscillator

F

OSC

Internal Oscillator

Oscillator

F

OSC

External Clock (EC)

CLKIN

F

OSC

External Crystal

PIC16(L)F1933

 2011-2012 Microchip Technology Inc. DS41575C-page 73

PIC16(L)F1933

6.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Ta b le 6 - 3 and Ta bl e 6 -4 show the Reset
conditions of these registers.

TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RMCLR RI POR BOR TO PD Condition

00110x11Power-on Reset

00110x0xIllegal, TO

00110xx0Illegal, PD is set on POR

0011u011Brown-out Reset

uuuuuu0uWDT Reset

uuuuuu00WDT Wake-up from Sleep

uuuuuu10Interrupt Wake-up from Sleep

uu0uuuuuMCLR

uu0uuu10MCLR

u u u 0 u u u u RESET Instruction Executed

1uuuuuuuStack Overflow Reset (STVREN = 1)

u1uuuuuuStack Underflow Reset (STVREN = 1)

is set on POR

Reset during normal operation

Reset during Sleep

(1)

(2)

STATUS

Register

---1 0uuu uu-- uuuu

PCON

Register

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-- 110x

MCLR

Reset during normal operation 0000h ---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu

WDT Reset 0000h ---0 uuuu uu-- uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu

Brown-out Reset 0000h ---1 1uuu 00-- 11u0

Interrupt Wake-up from Sleep PC + 1

RESET Instruction Executed 0000h ---u uuuu uu-- u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program
Counter

DS41575C-page 74  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

6.12 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits
to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI

• Stack Overflow Reset (STKOVF)

• Stack Underflow Reset (STKUNF)

•MCLR

The PCON register bits are shown in Register 6-2.

Reset (RMCLR)

6.13 Register Definitions: Power Control

REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF

bit 7 bit 0

)

)

— —

RMCLR

RI POR BOR

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or set to ‘0’ by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or set to ‘0’ by firmware

bit 5-4 Unimplemented: Read as ‘0’
bit 3 RMCLR

1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR

bit 2 RI: RESET Instruction Flag bit

1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction)

bit 1 POR

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

: MCLR Reset Flag bit

Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

: Power-on Reset Status bit

: Brown-out Reset Status bit

occurs)

 2011-2012 Microchip Technology Inc. DS41575C-page 75

PIC16(L)F1933

TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register

on Page

BORCON SBOREN

PCON STKOVF STKUNF

STATUS

WDTCON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR

— — —TOPD Z DC C 18

— — WDTPS<4:0> SWDTEN 97

— — — — — — BORRDY 71

— —RMCLRRI POR BOR 75

Reset and Watchdog Timer Reset during normal operation.

DS41575C-page 76  2011-2012 Microchip Technology Inc.

7.0 INTERRUPTS

TMR0IF

TMR0IE

INTF
INTE

IOCIF
IOCIE

Interrupt
to CPU

Wake-up
(If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7>
PIEn<7>

PEIE

Peripheral Interrupts

(TMR1IF) PIR1<0>

The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.

This chapter contains the following information for
Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the
corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 7-1.

FIGURE 7-1: INTERRUPT LOGIC

PIC16(L)F1933

 2011-2012 Microchip Technology Inc. DS41575C-page 77

PIC16(L)F1933

7.1 Operation

Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt
event(s)

• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)

The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.

The following events happen when an interrupt event
occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the
stack

• Critical registers are automatically saved to the
shadow registers (See Section 7.5 “Automatic

Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.

For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.

7.2 Interrupt Latency

Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 7-2 and Figure 7-3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other
enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

DS41575C-page 78  2011-2012 Microchip Technology Inc.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

PC 0004h 0005h

PC

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

PC

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC )

Interrupt Sam pled
during Q1

Inst(PC)

PC-1 PC+1

NOP

PC

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

PC

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(0005h)

Execute

Execute

Execute

PIC16(L)F1933

FIGURE 7-2: INTERRUPT LATENCY

 2011-2012 Microchip Technology Inc. DS41575C-page 79

PIC16(L)F1933

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

PC

Instruction
Fetched

Instruction
Executed

Interrupt Latency

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 T

CY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 30.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

FIGURE 7-3: INT PIN INTERRUPT TIMING

DS41575C-page 80  2011-2012 Microchip Technology Inc.

7.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 9.0 “Power-

Down Mode (Sleep)” for more details.

7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.

PIC16(L)F1933

7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine (ISR), these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding Shadow register should be modified
and the value will be restored when exiting the ISR.
The Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.

and PD)

 2011-2012 Microchip Technology Inc. DS41575C-page 81

PIC16(L)F1933

7.6 Register Definitions: Interrupt Control

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt
0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed
0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state

Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register

have been cleared by software.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri­ate interrupt flag bits are clear prior to
enabling an interrupt.

DS41575C-page 82  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

7.6.1 PIE1 REGISTER

REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 Gate Acquisition interrupt
0 = Disables the Timer1 Gate Acquisition interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt
0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2011-2012 Microchip Technology Inc. DS41575C-page 83

PIC16(L)F1933

7.6.2 PIE2 REGISTER

REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0

OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt

bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit

1 = Enables the EEPROM Write Completion interrupt
0 = Disables the EEPROM Write Completion interrupt

bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt

bit 2 LCDIE: LCD Module Interrupt Enable bit

1 = Enables the LCD module interrupt
0 = Disables the LCD module interrupt

bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS41575C-page 84  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

7.6.3 PIE3 REGISTER

REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0

— CCP5IE CCP4IE CCP3IE TMR6IE —TMR4IE—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’
bit 6 CCP5IE: CCP5 Interrupt Enable bit

1 = Enables the CCP5 interrupt
0 = Disables the CCP5 interrupt

bit 5 CCP4IE: CCP4 Interrupt Enable bit

1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt

bit 4 CCP3IE: CCP3 Interrupt Enable bit

1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt

bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

1 = Enables the TMR6 to PR6 match interrupt
0 = Disables the TMR6 to PR6 match interrupt

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

1 = Enables the TMR4 to PR4 match interrupt
0 = Disables the TMR4 to PR4 match interrupt

bit 0 Unimplemented: Read as ‘0’

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2011-2012 Microchip Technology Inc. DS41575C-page 85

PIC16(L)F1933

7.6.4 PIR1 REGISTER

REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 3 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 CCP1IF: CCP1 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

DS41575C-page 86  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

7.6.5 PIR2 REGISTER

REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0

OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 6 C2IF: Comparator C2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 LCDIF: LCD Module Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

 2011-2012 Microchip Technology Inc. DS41575C-page 87

PIC16(L)F1933

7.6.6 PIR3 REGISTER

REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— CCP5IF CCP4IF CCP3IF TMR6IF —TMR4IF—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’
bit 6 CCP5IF: CCP5 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 5 CCP4IF: CCP4 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 CCP3IF: CCP3 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 0 Unimplemented: Read as ‘0’

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

DS41575C-page 88  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 82

OPTION_REG

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 83

PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE

PIE3

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 86

PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF

PIR3
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.

WPUEN INTEDG TMROCS TMROSE PSA PS<2:0> 173

— CCP2IE 84

— CCP5IE CCP4IE CCP3IE TMR6IE —TMR4IE— 85

— CCP2IF 87

— CCP5IF CCP4IF CCP3IF TMR6IF —TMR4IF— 88

Register
on Page

 2011-2012 Microchip Technology Inc. DS41575C-page 89

PIC16(L)F1933

NOTES:

DS41575C-page 90  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

8.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR

The PIC16F193X has an internal Low Dropout
Regulator (LDO) which provides operation above 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the V
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
PIC16LF193X operates at a maximum V
does not incorporate an LDO.

A device I/O pin may be configured as the LDO voltage
output, identified as the V
required, an external low-ESR capacitor may be
connected to the VCAP pin for additional regulator
stability.

The VCAPEN<1:0> bits of Configuration Words
determines which pin is assigned as the V
Refer to Table 8-1.

TABLE 8-1: VCAPEN<1:0> SELECT BITS

VCAPEN<1:0> Pin

00 RA0
01 RA5
10 RA6
11 No VCAP

DD and I/O pins to operate

DD of 3.6V and

CAP pin. Although not

CAP pin.

On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on the constant current rate, refer to the
LDO Regulator Characteristics Table in Section 30.0

“Electrical Specifications”.

TABLE 8-2: SUMMARY OF CONFIGURATION WORD WITH LDO

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG2

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
Note 1: PIC16F1933 only.

13:8

7:0 — —

— — LV P DEBUG — BORV STVREN PLLEN

VCAPEN<1:0>

(1)

— — WRT1 WRT0

Register
on Page

48

 2011-2012 Microchip Technology Inc. DS41575C-page 91

PIC16(L)F1933

NOTES:

DS41575C-page 92  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

9.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a
SLEEP instruction.

Upon entering Sleep mode, the following conditions
exist:

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

bit of the STATUS register is cleared.

2. PD

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in
Sleep.

6. Timer1 and peripherals that operate from

Timer1 continue operation in Sleep when the
Timer1 clock source selected is:

•LFINTOSC

•T1CKI

• Timer1 oscillator

• CapSense oscillator

7. ADC is unaffected, if the dedicated FRC clock is

selected.

8. Capacitive Sensing oscillator is unaffected.

9. I/O ports maintain the status they had before

SLEEP was executed (driving high, low or high­impedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on
peripheral operation during Sleep.

To minimize current consumption, the following
conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be
pulled to V
currents caused by floating inputs.

Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 17.0 “Digital-to-Analog

Converter (DAC) Module” and Section 14.0 “Fixed
Voltage Reference (FVR)” for more information on

these modules.

DD or VSS externally to avoid switching

9.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the
following events:

1. External Reset input on MCLR

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)

The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution. To determine whether a device
Reset or wake-up event occurred, refer to Section 6.11

“Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.

pin, if enabled

 2011-2012 Microchip Technology Inc. DS41575C-page 93

PIC16(L)F1933

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(1)

CLKOUT

(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

PC

Instruction
Fetched

Instruction
Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2 0004h 0005h

Forced NOP

T

OST

(3)

PC + 2

Note 1: XT, HS or LP Oscillator mode assumed.

2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

9.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a
SLEEP instruction

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

bit of the STATUS register will not be set

-TO

-PD

bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the execution
of a SLEEP instruction

- SLEEP instruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared.

Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD
was executed as a NOP.

FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 82

IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 131

IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 131

IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 131

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 83

PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE

PIE3

PIR1

PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF

PIR3

STATUS

WDTCON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.

DS41575C-page 94  2011-2012 Microchip Technology Inc.

— CCP5IE CCP4IE CCP3IE TMR6IE —TMR4IE— 85

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

— CCP5IF CCP4IF CCP3IF TMR6IF —TMR4IF— 88

— — —TOPD ZDCC 18

— — WDTPS<4:0> SWDTEN 97

Register on

Page

— CCP2IE 84

86

— CCP2IF 87

10.0 WATCHDOG TIMER (WDT)

LFINTOSC

23-bit Programmable

Prescaler WDT

WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256
seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM

PIC16(L)F1933

 2011-2012 Microchip Technology Inc. DS41575C-page 95

PIC16(L)F1933

10.1 Independent Clock Source

The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
the Electrical Specifications Chapters for the
LFINTOSC tolerances.

10.2 WDT Operating Modes

The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 10-1.

10.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always on.

WDT protection is active during Sleep.

10.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.

WDT protection is unchanged by Sleep. See

Table 10-1 for more details.

TABLE 10-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN

11 X XActive

10 X

01

Device

Mode

Awake Active

Sleep Disabled

1 XActive

0 X Disabled

WDT

Mode

10.3 Time-Out Period

The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.

10.4 Clearing the WDT

The WDT is cleared when any of the following
conditions occur:

•Any Reset

• CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail

• WDT is disabled

• Oscillator Start-up TImer (OST) is running

See Table 10-2 for more information.

10.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.

When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator

Module (with Fail-Safe Clock Monitor)” for more

information on the OST.

When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device wakes
up and resumes operation. The TO
STATUS register are changed to indicate the event. See

Section 3.0 “Memory Organization” and STATUS

register (Register 3-1) for more information.

and PD bits in the

00 X X Disabled

TABLE 10-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected

DS41575C-page 96  2011-2012 Microchip Technology Inc.

Cleared

PIC16(L)F1933

10.6 Register Definitions: Watchdog Control

REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

— — WDTPS<4:0> SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’
bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)

•

•

•

10011 = Reserved. Results in minimum interval (1:32)

23

10010 = 1:8388608 (2
10001 = 1:4194304 (2
10000 = 1:2097152 (2
01111 = 1:1048576 (2
01110 = 1:524288 (2
01101 = 1:262144 (2
01100 = 1:131072 (2
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> =
This bit is ignored.
If WDTE<1:0> = 01:

1 = WDT is turned on
0 = WDT is turned off

If WDTE<1:0> =
This bit is ignored.

00:

1x:

) (Interval 256s nominal)

22

) (Interval 128s nominal)

21

) (Interval 64s nominal)

20

) (Interval 32s nominal)

19

) (Interval 16s nominal)

18

) (Interval 8s nominal)

17

) (Interval 4s nominal)

 2011-2012 Microchip Technology Inc. DS41575C-page 97

PIC16(L)F1933

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

STATUS

WDTCON

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

SPLLEN IRCF<3:0> —SCS<1:0>

— — —TOPD Z DC C

— — WDTPS<4:0> SWDTEN

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN<1:0> CPD

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

Register
on Page

66

18

97

Register
on Page

46

DS41575C-page 98  2011-2012 Microchip Technology Inc.

PIC16(L)F1933

11.0 DATA EEPROM AND FLASH

PROGRAM MEMORY
CONTROL

The Data EEPROM and Flash program memory are
readable and writable during normal operation (full V
range). These memories are not directly mapped in the
register file space. Instead, they are indirectly
addressed through the Special Function Registers
(SFRs). There are six SFRs used to access these
memories:

• EECON1

• EECON2

• EEDATL

•EEDATH

• EEADRL

•EEADRH

When interfacing the data memory block, EEDATL
holds the 8-bit data for read/write, and EEADRL holds
the address of the EEDATL location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 0h to 0FFh.

When accessing the program memory block, the
EEDATH:EEDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
EEADRL and EEADRH registers form a 2-byte word
that holds the 15-bit address of the program memory
location being read.

The EEPROM data memory allows byte read and write.
An EEPROM byte write automatically erases the
location and writes the new data (erase before write).

The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.

Depending on the setting of the Flash Program
Memory Self Write Enable bits WRT<1:0> of the
Configuration Words, the device may or may not be
able to write certain blocks of the program memory.
However, reads from the program memory are always
allowed.

When the device is code-protected, the device
programmer can no longer access data or program
memory. When code-protected, the CPU may continue
to read and write the data EEPROM memory and Flash
program memory.

DD

11.1 EEADRL and EEADRH Registers

The EEADRH:EEADRL register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 32K words of program memory.

When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is written to the EEADRL register. When selecting
a EEPROM address value, only the LSB of the address
is written to the EEADRL register.

11.1.1 EECON1 AND EECON2 REGISTERS

EECON1 is the control register for EE memory
accesses.

Control bit EEPGD determines if the access will be a
program or data memory access. When clear, any
subsequent operations will operate on the EEPROM
memory. When set, any subsequent operations will
operate on the program memory. On Reset, EEPROM is
selected by default.

Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.

The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.

Interrupt flag bit EEIF of the PIR2 register is set when
write is complete. It must be cleared in the software.

Reading EECON2 will read all ‘0’s. The EECON2
register is used exclusively in the data EEPROM write
sequence. To enable writes, a specific pattern must be
written to EECON2.

 2011-2012 Microchip Technology Inc. DS41575C-page 99

PIC16(L)F1933

BANKSEL EEADRL ;
MOVLW DATA_EE_ADDR ;
MOVWF EEADRL ;Data Memory

;Address to read
BCF EECON1, CFGS ;Deselect Config space
BCF EECON1, EEPGD;Point to DATA memory
BSF EECON1, RD ;EE Read
MOVF EEDATL, W ;W = EEDATL

11.2 Using the Data EEPROM

The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). When variables in one section change
frequently, while variables in another section do not
change, it is possible to exceed the total number of
write cycles to the EEPROM without exceeding the
total number of write cycles to a single byte. Refer to

Section 30.0 “Electrical Specifications”. If this is the

case, then a refresh of the array must be performed.
For this reason, variables that change infrequently
(such as constants, IDs, calibration, etc.) should be
stored in Flash program memory.

11.2.1 READING THE DATA EEPROM MEMORY

To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD and
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next
cycle, in the EEDATL register; therefore, it can be read
in the next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).

11.2.2 WRITING TO THE DATA EEPROM MEMORY

To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.

The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set the WR bit) for each byte. Interrupts
should be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.

After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.

EXAMPLE 11-1: DATA EEPROM READ

Note: Data EEPROM can be read regardless of

the setting of the CPD

bit.

11.2.3 PROTECTION AGAINST SPURIOUS WRITE

There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up Timer (64 ms duration) prevents EEPROM
write.

The write initiate sequence and the WREN bit together
help prevent an accidental write during:

• Brown-out

• Power Glitch

• Software Malfunction

11.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT

Data memory can be code-protected by programming
the CPD

When the data memory is code-protected, only the
CPU is able to read and write data to the data
EEPROM. It is recommended to code-protect the
program memory when code-protecting data memory.
This prevents anyone from replacing your program with
a program that will access the contents of the data
EEPROM.

bit in the Configuration Words to ‘0’.

DS41575C-page 100  2011-2012 Microchip Technology Inc.