Datasheet PIC16LF1902 Datasheet

PIC16LF1902/3

Data Sheet

28-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

LCD Driver and nanoWatt XLP Technology

 2011 Microchip Technology Inc. Preliminary DS41455B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-030-1

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41455B-page 2 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

28-Pin Flash-Based, 8-Bit CMOS MCUs with LCD Driver and

nanoWatt XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• Up to 7 Kbytes Self-Write/Read Flash Program
Memory Addressing

• Up to 256 Bytes Data Memory Addressing

• Operating Speed:

- DC – 20 MHz clock input @ 3.6V

- DC – 16 MHz clock input @ 1.8V

- DC – 200 ns instruction cycle

• Interrupt Capability with Automatic Context
Saving

• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Struc ture:

• 16 MHz Internal Oscillator:

- Accuracy to ± 3%, typical

- Software selectable frequency range from

16 MHz to 31.25 kHz

• 31 kHz Low-Power Internal Oscillator

• Three External Clock modes up to 20 MHz

• Two-Speed Oscillator Start-up

• Low-Power RTC Implementation via LPT1OSC

Special Microcontroller Features:

• Operating Voltage Range:

-1.8V-3.6V

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Low-Power Brown-Out Reset (LPBOR)

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming™ (ICSP™) via
Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Enhanced Low-Voltage Programming (LVP)

• Programmable Code Protection

• Power-Saving Sleep mode

Extreme Low-Power Management PIC16LF1902/3 with nanoWatt XLP:

• Sleep mode: 30 nA @ 1.8V, typical

• Watchdog Timer: 300 nA @ 1.8V, typical

• Timer1 Oscillator: 500 nA @ 1.8V, typical

Analog Features:

• Analog-to-Digital Converter (ADC):

- 10-bit resolution, up to 11 channels

- Conversion available during Sleep

- Dedicated ADC RC oscillator

- Fixed Voltage Reference (FVR) as channel

• Integrated Temperature Indicator

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V
and 2.048V output levels

Peripheral Highlight s:

• Up to 25 I/O Pins and 1 Input-only Pin:

- High current 25 mA sink/source

- Individually programmable weak pull-ups

- Individually programmable interrupt-on­change (IOC) pins

• Integrated LCD Controller:

- 19 segment pins and 72 total segments

- Variable clock input

- Contrast control

- Internal voltage reference selections

• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated low-power 32 kHz oscillator driver

 2011 Microchip Technology Inc. Preliminary DS41455B-page 3

PIC16LF1902/3

PIC16LF1902/3

1

2

3

4

5

6

7

8
9

10

VPP/MCLR/RE3

SEG12/AN0/RA0

SEG7/AN1/RA1

COM2/AN2/RA2

SEG15/COM3/V

REF+/AN3/RA3

SEG4/T0CKI/RA4

SEG5/AN4/RA5

RB6

(1)

/SEG14/ICSPCLK

RB5

(1)

/AN13/COM1

RB4

(1)

/AN11/COM0

RB3

(1)

/AN9/SEG26/VLCD3

RB2

(1)

/AN8/SEG25/VLCD2

RB1

(1)

/AN10/SEG24/VLCD1

RB0

(1)

/AN12/INT/SEG0

V

DD

VSS

11

12

13

14

15

16

17

18

19

20

28

27

26

25

24
23

22

21

V

SS

SEG2/CLKIN/RA7

SEG1/CLKOUT/RA6

T1CKI/T1OSO/RC0

T1OSI/RC1

SEG3/RC2

SEG6/RC3

RC5/SEG10

RC4/T1G/SEG11

RC7/SEG8

RC6/SEG9

RB7

(1)

/SEG13/ICSPDAT

28-Pin PDIP, SOIC, SSOP

Note 1: These pins have interrupt-on-change functionality.

PIC16LF1902/3 Family Types

LCD

Device

(words)

SRAM (bytes)

I/Os

10-bit A/D (ch)

Timers

8/16-bit

Common Pins

Segment Pins

Program Memory Flash

PIC16LF1902 2048 128 25 11 1/1 4 19 72 PIC16LF1903 4096 256 25 11 1/1 4 19 72

Note 1: COM3 and SEG15 share a pin, so the total segments are limited to 72 for 28-pin devices.

FIGURE 1: 28-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16LF1902/3

Total Segme nts

(1)
(1)

DS41455B-page 4 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

28-Pin UQFN

2
3

6

1

18

19

20

21

15

7

16

17

T1CKI/T1OSO/RC0

5

4

RB7

(1)

/ICSPDAT/SEG13

RB6

(1)

/ICSPCLK/SEG14

RB5

(1)

/AN13/COM1

RB4

(1)

/AN11/COM0

RB0

(1)

/AN12/INT/SEG0

V

DD

VSS
RC7/SEG8

SEG9/RC6

SEG10/RC5

SEG11/T1G/RC4

RE3/MCLR

/VPP

RA0/AN0/SEG12

RA1/AN1/SEG7

COM2/AN2/RA2

SEG15/COM3/V

REF+/AN3/RA3

SEG4/T0CKI/RA4

SEG5/AN4/RA5

V

SS

SEG2/CLKIN/RA7

SEG1/CLKOUT/RA6

T1OSI/RC1

SEG3/RC2

SEG6/RC3

9

10

13814

12

11

27

26

232822

24

25

PIC16LF1902/3

RB3

(1)

/AN9/SEG26/VLCD3

RB2

(1)

/AN8/SEG25/VLCD2

RB1

(1)

/AN10/SEG24/VLCD1

Note 1: These pins have interrupt-on-change functionality.

FIGURE 2: 28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1902/3

 2011 Microchip Technology Inc. Preliminary DS41455B-page 5

PIC16LF1902/3

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16LF1902/3)

I/O

28-Pin DIP/

SOIC/SSOP

RA0 2 27 AN0 — SEG12 — — — RA1 3 28 AN1 — SEG7 — — — RA2 4 1 AN2 — COM2 — — — RA3 5 2 AN3/VREF+— SEG15/COM3——— RA4 6 3 — T0CKI SEG4 — — — RA5 7 4 AN4 — SEG5 — — — RA6 10 7 — — SEG1 — — CLKOUT RA7 9 6 — — SEG2 — — CLKIN RB0 21 18 AN12 — SEG0 INT/IOC Y — RB1 22 19 AN10 — VLCD1/SEG24 IOC Y — RB2 23 20 AN8 — VLCD2/SEG25 IOC Y — RB3 24 21 AN9 — VLCD3/SEG26 IOC Y — RB4 25 22 AN11 — COM0 IOC Y — RB5 26 23 AN13 — COM1 IOC Y — RB6 27 24 — — SEG14 IOC Y ICSPCLK RB7 28 25 — — SEG13 IOC Y ICSPDAT RC0 11 8 — T1OSO/T1CKI — — — — RC1 12 9 — T1OSI — — — — RC2 13 10 — — SEG3 — — — RC3 14 11 — — SEG6 — — — RC4 15 12 — T1G SEG11 — — — RC5 16 13 — — SEG10 — — — RC6 17 14 — — SEG9 — — — RC7 18 15 — — SEG8 — — —

RE3 1 26 — — — — Y
VDD 20 17 — — — — — VDD

Vss 8,19 5,16 — — — — — VSS

Note 1: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

28-Pin UQFN

A/D

Timers

LCD

Interrupt

Pull-up

(1)

Basic

MCLR/VPP

DS41455B-page 6 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Enhanced Mid-Range CPU........................................................................................................................................................ 13

3.0 Memory Organization................................................................................................................................................................. 15

4.0 Device Configuration.................................................................................................................................................................. 37

5.0 Resets ........................................................................................................................................................................................ 43

6.0 Oscillator Module........................................................................................................................................................................ 51

7.0 Interrupts .................................................................................................................................................................................... 61

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 73

9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 75

10.0 Flash Program Memory Control ................................................................................................................................................. 79

11.0 I/O Ports ..................................................................................................................................................................................... 95

12.0 Interrupt-on-Change ................................................................................................................................................................. 107

13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 111

14.0 Temperature Indicator .............................................................................................................................................................. 113

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 115

16.0 Timer0 Module ......................................................................................................................................................................... 129

17.0 Timer1 Module ......................................................................................................................................................................... 133

18.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 145

19.0 In-Circuit Serial Programming

20.0 Instruction Set Summary.......................................................................................................................................................... 183

21.0 Electrical Specifications............................................................................................................................................................ 197

22.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 215

23.0 Development Support............................................................................................................................................................... 217

24.0 Packaging Information.............................................................................................................................................................. 221

Appendix A: Revision History............................................................................................................................................................. 231

Index .................................................................................................................................................................................................. 233

The Microchip Web Site..................................................................................................................................................................... 237

Customer Change Notification Service .............................................................................................................................................. 237

Customer Support .............................................................................................................................................................................. 237

Reader Response .............................................................................................................................................................................. 238

Product Identification System ............................................................................................................................................................ 239

™ (ICSP™) ................................................................................................................................ 179

 2011 Microchip Technology Inc. Preliminary DS41455B-page 7

PIC16LF1902/3

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS41455B-page 8 Preliminary  2011 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16LF1902/3 are described within this data
sheet. They are available in 28-pin packages.

Figure 1-1 shows a block diagram of the

PIC16LF1902/3 devices. Table 1-2 shows the pinout
descriptions.

Reference Ta bl e 1 -1 for peripherals available per
device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16LF1902/3

PIC16LF1902

ADC ●●
Fixed Voltage Reference (FVR) ●●
LCD ●●
Temperature Indicator ●●
Timers

Timer0 ●●
Timer1 ●●

PIC16LF1903

 2011 Microchip Technology Inc. Preliminary DS41455B-page 9

PIC16LF1902/3

PORTA

Timer1

Timer0

PORTB

PORTC

PORTE

LCD

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

INTRC

Oscillator

MCLR

Figure 2-1

CLKIN

CLKOUT

ADC

10-Bit

FVR

Te mp .

Indicator

FIGURE 1-1: PIC16LF1902/3 BLOCK DIAGRAM

DS41455B-page 10 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

TABLE 1-2: PIC16LF1902/3 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/SEG12 RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

SEG12 — AN LCD Analog output.

RA1/AN1/SEG7 RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

SEG7 — AN LCD Analog output.

RA2/AN2/COM2 RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

COM2 — AN LCD Analog output.

RA3/AN3/V

RA4/T0CKI/SEG4 RA4 TTL CMOS General purpose I/O.

RA5/AN4/SEG5 RA5 TTL CMOS General purpose I/O.

RA6/CLKOUT/SEG1 RA6 TTL CMOS General purpose I/O.

RA7/CLKIN/SEG2 RA7 TTL CMOS General purpose I/O.

RB0/AN12/INT/SEG0 RB0 TTL CMOS General purpose I/O.

RB1

RB2

RB3

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: These pins have interrupt-on-change functionality.

REF+/COM3/SEG15 RA3 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

REF+ AN — A/D Voltage Reference input.

V

COM3 — AN LCD Analog output.

SEG15 — AN LCD Analog output.

T0CKI ST — Timer0 clock input.

SEG4 — AN LCD Analog output.

AN4 AN — A/D Channel 4 input.

SEG5 — AN LCD Analog output.

CLKOUT — CMOS F

SEG1 — AN LCD Analog output.

CLKIN CMOS — External clock input (EC mode).

SEG2 — AN LCD Analog output.

AN12 AN — A/D Channel 12 input.

INT ST — External interrupt.

(1)

/AN10/SEG24/VLCD1 RB1 TTL CMOS General purpose I/O.

(1)

/AN8/SEG25/VLCD2 RB2 TTL CMOS General purpose I/O.

(1)

/AN9/SEG26/VLCD3 RB3 TTL CMOS General purpose I/O.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

SEG0 — AN LCD Analog output.

AN10 AN — A/D Channel 10 input.

SEG24 — AN LCD Analog output.

VLCD1 AN — LCD analog input.

AN8 AN — A/D Channel 8 input.

SEG25 — AN LCD Analog output.

VLCD2 AN — LCD analog input.

AN9 AN — A/D Channel 9 input.

SEG26 — AN LCD Analog output.

VLCD3 AN — LCD analog input.

Type

Output

Type

OSC/4 output.

Description

2

C™ = Schmitt Trigger input with I2C

 2011 Microchip Technology Inc. Preliminary DS41455B-page 11

PIC16LF1902/3

TABLE 1-2: PIC16LF1902/3 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

(1)

/AN11/COM0 RB4 TTL CMOS General purpose I/O.

RB4

AN11 AN — A/D Channel 11 input.

COM0 — AN LCD Analog output.

(1)

RB5

/AN13/COM1 RB5 TTL CMOS General purpose I/O.

AN13 AN — A/D Channel 13 input.

COM1 — AN LCD Analog output.

(1)

/ICSPCLK/SEG14 RB6 TTL CMOS General purpose I/O.

RB6

ICSPCLK ST — Serial Programming Clock.

SEG14 — AN LCD Analog output.

(1)

RB7

/ICSPDAT/SEG13 RB7 TTL CMOS General purpose I/O.

ICSPDAT ST CMOS ICSP™ Data I/O.

SEG13 — AN LCD Analog output.

RC0/T1OSO/T1CKI RC0 TTL CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

RC1/T1OSI RC1 TTL CMOS General purpose I/O.

T1OSI XTAL XTAL Timer1 oscillator connection.

RC2/SEG3 RC2 TTL CMOS General purpose I/O.

SEG3 — AN LCD Analog output.

RC3/SEG6 RC3 TTL CMOS General purpose I/O.

SEG6 — AN LCD Analog output.

RC4/T1G/SEG11 RC4 TTL CMOS General purpose I/O.

T1G XTAL XTAL Timer1 oscillator connection.

SEG11 — AN LCD Analog output.

RC5/SEG10 RC5 TTL CMOS General purpose I/O.

SEG10 — AN LCD Analog output.

RC6/SEG9 RC6 ST CMOS General purpose I/O.

SEG9 — AN LCD Analog output.

RC7/SEG8 RC7 ST CMOS General purpose I/O.

SEG8 — AN LCD Analog output.

RE3/MCLR

V

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

V

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: These pins have interrupt-on-change functionality.

/VPP RE3 TTL CMOS General purpose I/O.

MCLR

PP HV — Programming voltage.

V

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Output

Type

Type

ST — Master Clear with internal pull-up.

Description

2

C™ = Schmitt Trigger input with I2C

DS41455B-page 12 Preliminary  2011 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.

PIC16LF1902/3

2.2 16-level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under­flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft­ware Reset. See Section 3.4 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See

Section 20.0 “Instruction Set Summary” for more

details.

 2011 Microchip Technology Inc. Preliminary DS41455B-page 13

PIC16LF1902/3

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction
Decode &

Control

Timing

Generation

CLKIN

CLKOUT

V

DD

8

8

Brown-out

Reset

12

3

VSS

Internal

Oscillator

Block

Configuration

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction
Decode &

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

15

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory

RAM

FSR regFSR reg

FSR1 Reg

15

15

MUX

15

Program Memory

Read (PMR)

12

FSR regFSR reg

BSR Reg

5

FIGURE 2-1: CORE BLOCK DIAGRAM

DS41455B-page 14 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and
control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16LF1902 2,048 07FFh
PIC16LF1903 4,096 0FFFh

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16LF1902/3 family. Accessing a
location above these boundaries will cause a
wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1, and 3-2).

 2011 Microchip Technology Inc. Preliminary DS41455B-page 15

PIC16LF1902/3

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Wraps to Page 0

Wraps to Page 0

Wraps to Page 0

0800h

CALL, CALLW
RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

Rollover to Page 0

7FFFh

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh
1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR
PIC16LF1902

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR
PIC16LF1903

DS41455B-page 16 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

constants

BRW ;Add Index in W to

;program counter to

;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[INDF1]

;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in pro­gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

The BRW instruction makes this type of table very sim­ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by set­ting bit 7 of the FSRxH register and reading the match­ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro­gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access­ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a
location in program memory.

 2011 Microchip Technology Inc. Preliminary DS41455B-page 17

PIC16LF1902/3

Addresses BANKx

x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR

x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

Data Memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For for detailed
information, see Table 3-4.

TABLE 3-2: CORE REGISTERS

DS41455B-page 18 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 20.0

“Instruction Set Summary”).

Note: The C and DC bits operate as Borrow and

Digit Borrow
subtraction.

out bits, respectively, in

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

TO

PD ZDC

(1)

(1)

C

bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(1)

(1)

 2011 Microchip Technology Inc. Preliminary DS41455B-page 19

PIC16LF1902/3

0Bh
0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers (SFRs) are registers
used by the application to control the desired operation
of peripheral functions in the device. The Special
Function Registers occupy the 20 bytes after the core
registers of every data memory bank (addresses
x0Ch/x8Ch through x1Fh/x9Fh). The registers
associated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all
banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

DS41455B-page 20 Preliminary  2011 Microchip Technology Inc.

3.2.5 DEVICE MEMORY MAPS

The memory maps for PIC16LF1902 and
PIC16LF1903 are as shown in Table 3-3.

 2011 Microchip Technology Inc. Preliminary DS41455B-page 21

TABLE 3-3: PIC16LF1902/3 MEMORY MAP

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 - 2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh
00Fh
010h PORTE 090h
011h PIR1 091h PIE1 111h
012h PIR2 092h PIE2 112h
013h
014h
015h TMR0 095h OPTION_REG 115h
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h
017h TMR1H 097h WDTCON 117h FVRCON 197h
018h T1CON 098h
019h T1GCON 099h OSCCON 119h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h 0F0h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: PIC16LF1903 only.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—093h—113h— 193h PMDATL 213h —293h— 313h — 393h —
—094h—114h— 194h PMDATH 214h —294h— 314h — 394h IOCBP

— 09Ah OSCSTAT 11Ah —19Ah—21Ah—29Ah—31Ah—39Ah—
— 09BhADRESL11Bh —19Bh—21Bh—29Bh—31Bh—39Bh—
— 09Ch ADRESH 11Ch — 19Ch — 21Ch — 29Ch — 31Ch — 39Ch —
— 09Dh ADCON0 11Dh — 19Dh — 21Dh — 29Dh — 31Dh — 39Dh —
— 09Eh ADCON1 11Eh —19Eh—21Eh—29Eh—31Eh—39Eh—

—09Fh—11Fh—19Fh—21Fh—29Fh—31Fh—39Fh—

General
Purpose
Register
96 Bytes

080h

0A0h

General Purpose

General Purpose

Core Registers

(Ta bl e 3 - 2)

—110h—190h— 210h WPUE 290h — 310h — 390h —

—118h—198h—218h—298h— 318h — 398h —

Register

32 Bytes

Register

48 Bytes

Accesses

70h – 7Fh

100h

Core Registers

(Table 3-2)

— 191h PMADRL 211h —291h— 311h — 391h —
— 192h PMADRH 212h —292h— 312h — 392h —

— 195h PMCON1 215h —295h— 315h — 395h IOCBN

—199h—219h—299h— 319h — 399h —

120h

13Fh
140h

(1)

170h

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

180h

Core Registers

(Table 3-2)

—20Eh—28Eh—30Eh—38Eh—

—217h—297h— 317h — 397h —

1A0h

Unimplemented

(1)

1F0h

Read as ‘0’

Accesses

70h – 7Fh

200h

220h

270h

Core Registers

(Table 3-2)

— 28Ch — 30Ch — 38Ch —

—296h— 316h — 396h IOCBF

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

280h

2A0h

2F0h

Core Registers

(Table 3-2)

— 30Dh — 38Dh —

Unimplemented

Read as ‘0’

Accesses
70h – 7Fh

300h

Core Registers

(Table 3-2)

320h

Unimplemented

Read as ‘0’

36Fh 3EFh
370h

Accesses

70h – 7Fh

380h

3A0h

3F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

PIC16LF1902/3

DS41455B-page 22 Preliminary  2011 Microchip Technology Inc.

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14

400h

40Bh

Core Registers

(Ta bl e 3 -2 )

480h

48Bh

Core Registers

(Ta bl e 3 -2 )

500h

50Bh

Core Registers

(Ta bl e 3 -2 )

580h

58Bh

Core Registers

(Ta bl e 3 -2 )

600h

60Bh

Core Registers

(Ta bl e 3 -2 )

680h

68Bh

Core Registers

(Ta bl e 3 -2 )

700h

70Bh

Core Registers

(Ta bl e 3 -2 )

40Ch

Unimplemented

Read as ‘0’

48Ch

Unimplemented

Read as ‘0’

50Ch

Unimplemented

Read as ‘0’

58Ch

Unimplemented

Read as ‘0’

60Ch

Unimplemented

Read as ‘0’

68Ch

Unimplemented

Read as ‘0’

70Ch

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh
470h

Common RAM

(Accesses
70h – 7Fh)

4F0h

Common RAM

(Accesses
70h – 7Fh)

570h

Common RAM

(Accesses
70h – 7Fh)

5F0h

Common RAM

(Accesses

70h – 7Fh)

670h

Common RAM

(Accesses

70h – 7Fh)

6F0h

Common RAM

(Accesses
70h – 7Fh)

770h

Common RAM

(Accesses
70h – 7Fh)

47Fh

4FFh 57Fh

5FFh 67Fh 6FFh 77Fh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

80Bh

Core Registers

(Table 3-2)Table

3-2

880h

88Bh

Core Registers

(Ta bl e 3 -2 )

900h

90Bh

Core Registers

(Ta bl e 3 -2 )

980h

98Bh

Core Registers

(Ta bl e 3 -2 )

A00h

A0Bh

Core Registers

(Ta bl e 3 -2 )

A80h

A8Bh

Core Registers

(Ta bl e 3 -2 )

B00h

B0Bh

Core Registers

(Ta bl e 3 -2 )

B80h

B8Bh

Core Registers

(Ta bl e 3 -2 )

80Ch

Unimplemented

Read as ‘0’

88Ch

Unimplemented

Read as ‘0’

90Ch

Unimplemented

Read as ‘0’

98Ch

Unimplemented

Read as ‘0’

A0Ch

Unimplemented

Read as ‘0’

A8Ch

Unimplemented

Read as ‘0’

B0Ch

Unimplemented

Read as ‘0’

B8Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh

9EFh

A6Fh

AEFh

B6Fh

BEFh

870h

Common RAM

(Accesses
70h – 7Fh)

8F0h

Common RAM

(Accesses
70h – 7Fh)

970h

Common RAM

(Accesses
70h – 7Fh)

9F0h

Common RAM

(Accesses

70h – 7Fh)

A70h

Common RAM

(Accesses

70h – 7Fh)

AF0h

Common RAM

(Accesses
70h – 7Fh)

B70h

Common RAM

(Accesses
70h – 7Fh)

BF0h

Common RAM

(Accesses
70h – 7Fh)

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30

C00h

C0Bh

Core Registers

(Ta bl e 3 -2 )

C80h

C8Bh

Core Registers

(Ta bl e 3 -2 )

D00h

D0Bh

Core Registers

(Ta bl e 3 -2 )

D80h

D8Bh

Core Registers

(Ta bl e 3 -2 )

E00h

E0Bh

Core Registers

(Ta bl e 3 -2 )

E80h

E8Bh

Core Registers

(Ta bl e 3 -2 )

F00h

F0Bh

Core Registers

(Ta bl e 3 -2 )

C0Ch

C6Fh

Unimplemented

Read as ‘0’

C8Ch

CEFh

Unimplemented

Read as ‘0’

D0Ch

D6Fh

Unimplemented

Read as ‘0’

D8Ch

DEFh

Unimplemented

Read as ‘0’

E0Ch

E6Fh

Unimplemented

Read as ‘0’

E8Ch

EEFh

Unimplemented

Read as ‘0’

F0Ch

F6Fh

Unimplemented

Read as ‘0’

C70h

Common RAM

(Accesses
70h – 7Fh)

CF0h

Common RAM

(Accesses
70h – 7Fh)

D70h

Common RAM

(Accesses
70h – 7Fh)

DF0h

Common RAM

(Accesses

70h – 7Fh)

E70h

Common RAM

(Accesses

70h – 7Fh)

EF0h

Common RAM

(Accesses
70h – 7Fh)

F70h

Common RAM

(Accesses
70h – 7Fh)

C7Fh

CFFh D7Fh DFFh E7Fh EFFh F7Fh

TABLE 3-3: PIC16LF1902/3 MEMORY MAP (CONTINUED)

PIC16LF1902/3

TABLE 3-3: PIC16LF1902/3 MEMORY MAP (CONTINUED)

Legend: = Unimplemented data memory locations, read as ‘0’,

Bank 15

780h

78Bh

Core Registers

(Ta bl e 3 -2 )

78Ch

790h

Unimplemented

Read as ‘0’

791h

LCDCON

792h

LCDPS

793h

LCDREF

794h

LCDCST

795h

LCDRL

796h

—

797h

—

798h

LCDSE0

799h

LCDSE1

79Ah

—

79Bh

LCDSE3

79Ch

79Fh

Unimplemented

Read as ‘0’

7A0h LCDDATA0
7A1h LCDDATA1
7A2h

—

7A3h LCDDATA3
7A4h LCDDATA4
7A5h

—

7A6h LCDDATA6
7A7h LCDDATA7
7A8h

—
7A9h LCDDATA9
7AAh LCDDATA10
7ABh

—
7ACh LCDDATA12
7ADh

—
7AEh

—
7AFh LCDDATA15
7B0h

—
7B1h

—
7B2h LCDDATA18
7B3h

—
7B4h

—
7B5h LCDDATA21
7B6h

—
7B7h

—
7B8h

7EFh

Unimplemented

Read as ‘0’

Bank 31

F80h

F8Bh

Core Registers

(Ta bl e 3 -2 )

F8Ch

FE3h

Unimplemented

Read as ‘0’

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

FF0h

Common RAM

(Accesses
70h – 7Fh)

FFFh

PIC16LF1902/3

 2011 Microchip Technology Inc. Preliminary DS41455B-page 23

PIC16LF1902/3

3.2.6 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3 -4 can be
addressed from any Bank.

TABLE 3-4: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Value on

POR, BOR

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Value on all

other Resets

DS41455B-page 24 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

00Fh

— Unimplemented — —

010h PORTE

011h PIR1 TMR1GIF ADIF

012h PIR2

013h

— Unimplemented — —

014h

— Unimplemented — —

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

01Ah

— Unimplemented — —

to

01Fh

— — — —RE3— — — ---- x--- ---- u---

— — — —TMR1IF00-- ---0 0000 ---0

— — — — — LCDIF — — ---- -0-- ---- -0--

—TMR1ON0000 00-0 uuuu uu-u

T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

DONE

Value on

POR, BOR

Bank 1

08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111

08Fh

— Unimplemented — —

090h TRISE

091h PIE1 TMR1GIE ADIE

092h PIE2

093h

— Unimplemented — —

094h

— Unimplemented — —

095h

OPTION_REG

096h PCON STKOVF STKUNF

097h WDTCON

098h

— Unimplemented — —

099h OSCCON

09Ah OSCSTAT T1OSCR
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0

09Fh

— Unimplemented — —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — —

— — — — —TMR1IE00-- ---0 0000 ---0

— — — — —LCDIE— — ---- -0-- ---- -0--

WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

—RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu

— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110

— IRCF3 IRCF2 IRCF1 IRCF0 — SCS1 SCS0 -011 1-00 -011 1-00

—OSTSHFIOFR— — LFIOFR HFIOFS 0-q0 --00 q-qq --0q

— CHS4 CHS3 CHS2 CHS1 CHS0

(2)

— — ADPREF1 ADPREF0 0000 ---- 0000 ----

— — — ---- 1--- ---- 1---

GO/DONE

ADON -000 0000 -000 0000

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41455B-page 25

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2
10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu
10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu
10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu

10Fh

to

— Unimplemented — —

115 h

116h BORCON SBOREN BORFS

117h FVRCON FVREN FVRRDY TSEN TSRNG

118 h

to

— Unimplemented — —

11Fh

— — — — — BORRDY 10-- ---q uu-- ---u

— — ADFVR1 ADFVR0 0q00 --00 0q00 --00

Value on

POR, BOR

Bank 3

18Ch ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --11 1111

18Dh ANSELB

18Eh

— Unimplemented — —

18Fh

— Unimplemented — —

190h

— Unimplemented — —

191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000

192h PMADRH
193h PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h PMDATH

195h PMCON1
196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000

197h

to

— Unimplemented — —

19Fh

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

— Program Memory Address Register High Byte 1000 0000 1000 0000

— — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

(2)

—

CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000

Bank 4

20Ch — Unimplemented — —
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

20Eh

— Unimplemented — —

20Fh

— Unimplemented — —

210h WPUE

211h

to

— Unimplemented — —

21Fh

— — — — WPUE3 — — — ---- 1--- ---- 1---

Bank 5

28Ch

— Unimplemented — —
—
29Fh

Bank 6

30Ch

— Unimplemented — —
—
31Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

Value on all

other

Resets

DS41455B-page 26 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 7

38Ch

— Unimplemented — —
—
393h

394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000
395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000
396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000

397h

— Unimplemented — —
—
39Fh

Bank 8-14

x0Ch

or

x8Ch

— Unimplemented — —

to

x1Fh

or

x9Fh

Bank 15

78Ch

— Unimplemented — —
—
790h

791h LCDCON LCDEN SLPEN WERR
792h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 0000 0000

793h LCDREF LCDIRE

794h LCDCST

795h LCDRL LRLAP1 LRLAP0 LRLBP1 LRLBP0

796h

— Unimplemented — —

797h

— Unimplemented — —
798h LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
799h LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu

79Ah

— Unimplemented — —

79Bh LCDSE3

79Dh

— Unimplemented — —
—
79Fh

7A0h LCDDATA0 SEG7

7A1h LCDDATA1 SEG15

7A2h

— Unimplemented — —

7A3h LCDDATA3 SEG7

7A4h LCDDATA4 SEG15

7A5h

— Unimplemented — —

7A6h LCDDATA6 SEG7

7A7h LCDDATA7 SEG15

7A8h

— Unimplemented — —

7A9h LCDDATA9 SEG7

7AAh LCDDATA10 SEG15

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — — LCDCST2 LCDCST1 LCDCST0 ---- -000 ---- -000

— — — — — SE26 SE25 SE24 ---- -000 ---- -uuu

COM0

COM0

COM1

COM1

COM2

COM2

COM3

COM3

— LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 0-0- 000- 0-0- 000-

SEG6

COM0

SEG14

COM0

SEG6

COM1

SEG14

COM1

SEG6

COM2

SEG14

COM2

SEG6

COM3

SEG14

COM3

SEG5

COM0

SEG13

COM0

SEG5

COM1

SEG13

COM1

SEG5

COM2

SEG13

COM2

SEG5

COM3

SEG13

COM3

— CS1 CS0 LMUX1 LMUX0 000- 0011 000- 0011

— LRLAT2 LRLAT1 LRLAT0 0000 -000 0000 -000

SEG4

COM0

SEG12

COM0

SEG4

COM1

SEG12

COM1

SEG4

COM2

SEG12

COM2

SEG4

COM3

SEG12

COM3

SEG3

COM0

SEG11
COM0

SEG3

COM1

SEG11
COM1

SEG3

COM2

SEG11
COM2

SEG3

COM3

SEG11
COM3

SEG2

COM0

SEG10

COM0

SEG2

COM1

SEG10

COM1

SEG2

COM2

SEG10

COM2

SEG2

COM3

SEG10

COM3

SEG1

COM0

SEG9

COM0

SEG1

COM1

SEG9

COM1

SEG1

COM2

SEG9

COM2

SEG1

COM3

SEG9

COM3

SEG0

COM0

SEG8

COM0

SEG0

COM1

SEG8

COM1

SEG0

COM2

SEG8

COM2

SEG0

COM3

SEG8

COM3

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41455B-page 27

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 15 (Continued)

7ABh — Unimplemented — —

7ACh

LCDDATA12

7ADh

— Unimplemented — —

7AEh

— Unimplemented — —

7AFh

LCDDATA15

7B0h

— Unimplemented — —

7B1h

— Unimplemented — —

7B2h

LCDDATA18

— Unimplemented — —

7B3h

7B4h

— Unimplemented — —

7B5h

LCDDATA21

7B6h

— Unimplemented — —
—
7EFh

— — — — — SEG26

— — — — — SEG26

— — — — — SEG26

— — — — — SEG26

COM0

COM1

COM2

COM3

SEG25

COM0

SEG25

COM1

SEG25

COM2

SEG25

COM3

SEG24

COM0

SEG24

COM1

SEG24

COM2

SEG24

COM3

---- -xxx ---- -uuu

---- -xxx ---- -uuu

---- -xxx ---- -uuu

---- -xxx ---- -uuu

Bank 16-30

x0Ch

or

x8Ch

— Unimplemented — —

to

x1Fh

or

x9Fh

Bank 31

F8Ch

— Unimplemented — —
—
FE3h

FE4h STATUS_SHAD
FE5h WREG_SHAD Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

FE6h BSR_SHAD

FE7h PCLATH_SHAD
FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

FECh

— Unimplemented — —

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu

— — — Bank Select Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu
— Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx uuuu uuuu

— — — Current Stack Pointer ---1 1111 ---1 1111

Top of Stack Low byte xxxx xxxx uuuu uuuu

— Top of Stack High byte -xxx xxxx -uuu uuuu

Value on all

other

Resets

DS41455B-page 28 Preliminary  2011 Microchip Technology Inc.

PIC16LF1902/3

PCLPCH

0

14

PC

06

7

ALU Result

8

PCLATH

PCLPCH

0

14

PC

06

4

OPCODE <10:0>

11

PCLATH

PCLPCH

0

14

PC

06

7

W

8

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH

0

14

PC

PC + W

15

BRW

PCLPCH

0

14

PC

PC + OPCODE <8:0>

15

BRA

3.3 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN

DIFFERENT SITUATIONS

3.3.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by com­bining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.

3.3.4 BRANCHING

The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.

If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.

3.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program Coun­ter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values con­tained in the PCLATH register and those being written
to the PCL register.

3.3.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PC L). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, “Implementing a T able Read” (DS00556).

 2011 Microchip Technology Inc. Preliminary DS41455B-page 29

PIC16LF1902/3

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled
(STVREN = 0)

Stack Reset Enabled
(STVREN = 1)

TOSH:TOSL

TOSH:TOSL

3.4 Stack

All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-3 and 3-3). The stack space is
not part of either program or data space. The PC is
PUSHed onto the stack when CALL or CALLW instruc­tions are executed or an interrupt causes a branch. The
stack is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Word 2). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over­flow/Underflow, regardless of whether the Reset is
enabled.

Note: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the

CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to an

interrupt address.

3.4.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement the
STKPTR.

Reference Figure 3-5 through Figure 3-8 for examples
of accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

DS41455B-page 30 Preliminary  2011 Microchip Technology Inc.