Datasheet PIC 16LF1783 Datasheet

PIC16(L)F1782/3

28-Pin 8-Bit Advanced Analog Flash Microcontroller

High-Performance RISC CPU:

• Only 49 Instructions

• Operating Speed:

- DC – 32 MHz clock input

- DC – 125 ns instruction cycle

• Interrupt Capability with Automatic Context
Saving

• 16-Level Deep Hardware Stack with optional
Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

• Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Memory Features:

• Up to 4 KW Flash Program Memory:

- Self-programmable under software control

- Programmable code protection

- Programmable write protection

• 256 Bytes of Data EEPROM

• Up to 512 Bytes of RAM

High Performance PWM Controller:

• Two Programmable Switch Mode Controller
(PSMC) modules:

- Digital and/or analog feedback control of

PWM frequency and pulse begin/end times

- 16-bit Period, Duty Cycle and Phase

- 16 ns clock resolution

- Supports Single PWM, Complementary,

Push-Pull and 3-phase modes of operation

- Dead-band control with 8-bit counter

- Auto-shutdown and restart

- Leading and falling edge blanking

-Burst mode

Extreme Low-Power Management PIC16LF1782/3 with XLP:

• Sleep mode: 50 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Secondary Oscillator: 500 nA @ 32 kHz

• Operating Current:

-8A @ 32 kHz, 1.8V, typical

-32A/MHz @ 1.8V, typical

Analog Peripheral Features:

• Analog-to-Digital Converter (ADC):

- Fully differential 12-bit converter

- Up to 75 ksps conversion rate

- 11 single-ended channels

- 5 differential channels

- Positive and negative reference selection

• 8-bit Digital-to-Analog Converter (DAC):

- Output available externally

- Positive and negative reference selection

- Internal connections to comparators, op
amps, Fixed Voltage Reference (FVR) and
ADC

• Three High-Speed Comparators:

- 50 ns response time @ V

- Rail-to-rail inputs

- Software selectable hysteresis

- Internal connection to op amps, FVR and
DAC

• Two Operational Amplifiers:

- Rail-to-rail inputs/outputs

- High/Low selectable Gain Bandwidth Product

- Internal connection to DAC and FVR

• Fixed Voltage Reference (FVR):

- 1.024V, 2.048V and 4.096V output levels

- Internal connection to ADC, comparators and
DAC

DD = 5V

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 1

PIC16(L)F1782/3

Digital Peripheral Features:

• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated low-power 32 kHz oscillator driver

• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler

• Two Capture/Compare/PWM modules (CCP):

- 16-bit capture, maximum resolution 12.5 ns

- 16-bit compare, max resolution 31.25 ns

- 10-bit PWM, max frequency 32 kHz

• Master Synchronous Serial Port (SSP) with SPI

2

and I

CTM with:

- 7-bit address masking

- SMBus/PMBus

• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART):

- RS-232, RS-485 and LIN compatible

- Auto-baud detect

- Auto-wake-up on start

TM

compatibility

General Microcontroller Features:

• Power-Saving Sleep mode

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• Brown-out Reset (BOR) with Selectable Trip Point

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming

• In-Circuit Debug (ICD)

• Enhanced Low-Voltage Programming (LVP)

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1782/3)

- 2.3V to 5.5V (PIC16F1782/3)

TM

(ICSPTM)

Oscillator Features:

• Operate up to 32 MHz from Precision Internal
Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range from

32 MHz to 31 kHz

• 31 kHz Low-Power Internal Oscillator

• 32.768 kHz Timer1 Oscillator:

- Available as system clock

- Low-power RTC

• External Oscillator Block with:

- 4 crystal/resonator modes up to 32 MHz

using 4x PLL

- 3 external clock modes up to 32 MHz

• 4x Phase-Locked Loop (PLL)

• Fail-Safe Clock Monitor:

- Detect and recover from external oscillator

failure

• Two-Speed Start-up:

- Minimize latency between code execution

and external oscillator start-up

DS41579D-page 2 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F178X Family Types

PIC16(L)F1782/3

C™/SPI)

2

MSSP (I

(1)

Debug

(bytes)

Data SRAM

(2)

Mode Controllers

(PSMC)

CCP

EUSART

I/O’s

12-bit ADC (ch)

Comparators

Amplifiers

Operational

Timers

DAC (8/5-bit)

(8/16-bit)

Programmable Switch

Device

(bytes)

Flash (words)

Data Sheet Index

Program Memory

PIC16(L)F1782 (1) 2048 256 256 25 11 3 2 1/0 2/1 2 2 1 1 I Y
PIC16(L)F1783 (1) 4096 256 512 25 11 3 2 1/0 2/1 2 2 1 1 I Y
PIC16(L)F1784 (2) 4096 256 512 36 14 4 3 1/0 2/1 3 3 1 1 I Y
PIC16(L)F1786 (2) 8192 256 1024 25 11 4 2 1/0 2/1 3 3 1 1 I Y
PIC16(L)F1787 (2) 8192 256 1024 36 14 4 3 1/0 2/1 3 3 1 1 I Y
PIC16(L)F1788 (3) 16384 256 2048 25 11 4 2 1/3 2/1 4 3 1 1 I Y
PIC16(L)F1789 (3) 16384 256 2048 36 14 4 3 1/3 2/1 4 3 1 1 I Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS41579 PIC16(L)F1782/3 Data Sheet, 28-Pin Flash, 8-bit Advanced Analog MCUs.
2: DS41637 PIC16(L)F1784/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs.
3: Future Release PIC16(L)F1788/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs.

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

Data EEPROM

XLP

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 3

PIC16(L)F1782/3

SPDIP, SOIC, SSOP

1
2
3
4
5
6
7

8
9

10

VPP/MCLR/RE3

RA0

RA1
RA2
RA3
RA4

RA5

RB6/ICSPCLK
RB5

RB4
RB3
RB2
RB1

RB0
VDD
VSS

11
12

13
14

15

16

17

18

19

20

28
27
26
25
24
23

22

21

V

SS

RA7

RA6
RC0
RC1
RC2
RC3

RC5
RC4

RC7
RC6

RB7/ICSPDAT

Note: See Table 1 for the location of all peripheral functions.

PIC16(L)F1782/3

2
3

6

1

18

19

20

21

15

7

16

17

RC0

5

4

RB7/ICSPDAT

RB6/ICSPCLK

RB5

RB4

RB3
RB2

RB1
RB0
V

DD

VSS
RC7

RC6

RC5

RC4

RE3/MCLR/VPP

RA0

RA1

RA2
RA3
RA4

RA5

VSS
RA7
RA6

RC1

RC2

RC3

9

10

13814

12

11

27

26

232822

24

25

PIC16(L)F1782/3

QFN, UQFN

Note: See Ta bl e 1 for the location of all peripheral functions.

FIGURE 1: 28-PIN DIAGRAM FOR PIC16(L)F1782/3

FIGURE 2: 28-PIN DIAGRAM FOR PIC16(L)F1782/3

DS41579D-page 4 Preliminary  2011-2012 Microchip Technology Inc.

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1782/3)

PIC16(L)F1782/3

I/O

ADC

28-Pin QFN, UQFN

ADC Reference

Comparator

Operation Amplifiers

8-bit DAC

Timers

PSMC

CCP

EUSART

MSSP

Pull-up

Interrupt

28-Pin SPDIP, SOIC, SSOP

RA0 2 27 AN0 — C1IN0-

C2IN0­C3IN0-

RA1 3 28 AN1 — C1IN1-

C2IN1­C3IN1-

RA2 4 1 AN2 VREF- C1IN0+

C2IN0+

— — — — — — — IOC Y —

OPA1OUT — — — — — — IOC Y —

— DACOUT1

REF-

DACV

— — — — — IOC Y —

C3IN0+

RA3 5 2 AN3

V

C1IN1+ — DACV

REF+

REF+— — — — —IOCY —

RA4 6 3 — — C1OUT OPA1IN+ — T0CKI — — — — IOC Y —

RA5 7 4 AN4 — C2OUT OPA1IN- — — — — — SS

RA6 10 7 — — C2OUT

RA7 9 6 — — — — — —

RB0 21 18 AN12 — C2IN1+ — — —

(1)

— — — — — — — IOC Y OSC2/

PSMC1CLK
PSMC2CLK

PSMC1IN

———IOCYOSC1/

(1)

CCP1

— — INT/

PSMC2IN

RB1 22 19 AN10 — C1IN3-

C2IN3-

OPA2OUT — — — — — — IOC Y —

IOC Y —

CLKOUT

CLKIN

Y —

IOC

C3IN3-

RB2 23 20 AN8 — — OPA2IN- — — — — — — IOC Y CLKR

(1)

RB3 24 21 AN9 —

C1IN2-

OPA2IN+ — — — CCP2

——IOCY—

C2IN2­C3IN2-

RB4 25 22 AN11 — C3IN1+ — — — — — — — IOC Y —

SDI

SDA

SCK

SCL

(1)

IOC Y —

(1)

IOC Y ICSPCLK

(1)

(1)

IOC Y ICSPDAT

(1)

RB5 26 23 AN13 — C3OUT — — T1G — — — SDO

RB6 27 24 — — — — — — — — TX

RB7 28 25 — — — — DACOUT2 — — — RX

RC0 11 8 — — — — — T1OSO

PSMC1A — — — IOC Y —

CK

DT

(1)
(1)

(1)
(1)

T1CKI

RC1 12 9 — — — — — T1OSI PSMC1B CCP2 — — IOC Y —

RC2 13 10 — — — — — — PSMC1C CCP1 — — IOC Y —

RC3 14 11 — — — — — — PSMC1D — — SCK-

IOC Y —

SCL

RC4 15 12 — — — — — — PSMC1E — — SDI

SDA

IOC Y —

RC5 16 13 — — — — — — PSMC1F — — SDO IOC Y —

RC6 17 14 — — — — — — PSMC2A — TX

CK

RC7 18 15 — — — — — — PSMC2B — RX

— IOC Y —

—IOCY —

DT

RE3 1 26 — — — — — — — — — — IOC Y MCLR

PP

V

VDD 20 17 — — — — — — — — — — — — VDD

VSS 8,195, 16—— — — — — — —————VSS

Basic

/

Note 1: Alternate pin function selected with the APFCON1 (Register 13-1) register.

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 5

PIC16(L)F1782/3

Table of Contents

1.0 Device Overview ......................................................................................................................................................................... 9

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15

3.0 Memory Organization ................................................................................................................................................................. 19

4.0 Device Configuration.................................................................................................................................................................. 43

5.0 Resets ........................................................................................................................................................................................ 49

6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 57

7.0 Reference Clock Module ............................................................................................................................................................ 75

8.0 Interrupts .................................................................................................................................................................................... 79

9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 93

10.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 97

11.0 Watchdog Timer (WDT) ............................................................................................................................................................. 99

12.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 103

13.0 I/O Ports ................................................................................................................................................................................... 117

14.0 Interrupt-On-Change ................................................................................................................................................................ 139

15.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 143

16.0 Temperature Indicator Module ................................................................................................................................................. 147

17.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 151

18.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 167

19.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 171

20.0 Comparator Module.................................................................................................................................................................. 175

21.0 Timer0 Module ........................................................................................................................................................................ 185

22.0 Timer1 Module with Gate Control............................................................................................................................................. 189

23.0 Timer2 Module ......................................................................................................................................................................... 201

24.0 Programmable Switch Mode Control (PSMC).......................................................................................................................... 205

25.0 Capture/Compare/PWM Modules ............................................................................................................................................ 261

26.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 271

27.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 325

28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 355

29.0 Instruction Set Summary .......................................................................................................................................................... 357

30.0 Electrical Specifications............................................................................................................................................................ 371

31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 405

32.0 Development Support............................................................................................................................................................... 423

33.0 Packaging Information.............................................................................................................................................................. 427

The Microchip Web Site..................................................................................................................................................................... 449

Customer Change Notification Service .............................................................................................................................................. 449

Customer Support .............................................................................................................................................................................. 449

Reader Response .............................................................................................................................................................................. 450

Product Identification System............................................................................................................................................................. 451

DS41579D-page 6 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:

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 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 7

PIC16(L)F1782/3

NOTES:

DS41579D-page 8 Preliminary  2011-2012 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16(L)F1782/3 are described within this data
sheet. They are available in 28-pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1782/3 devices. Table 1-2 shows the pinout
descriptions.

Reference Ta bl e 1 -1 for peripherals available per
device.

PIC16(L)F1782/3

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1782

Analog-to-Digital Converter (ADC) ●●
Digital-to-Analog Converter (DAC) ●●
Fixed Voltage Reference (FVR) ●●
Reference Clock Module ●●
Temperature Indicator ●●
Capture/Compare/PWM (CCP/ECCP) Modules

CCP1 ●●
CCP2 ●●

Comparators

C1 ●●
C2 ●●
C3 ●●

Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)

EUSART ●●

Master Synchronous Serial Ports

MSSP ●●

Op Amp

Op Amp 1 ●●
Op Amp 2 ●●

Programmable Switch Mode Controller (PSMC)

PSMC1 ●●
PSMC2 ●●

Timers

Timer0 ●●
Timer1 ●●
Timer2 ●●

PIC16(L)F1783

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 9

PIC16(L)F1782/3

PORTA

PORTB

PORTC

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

LFINTOSC

Oscillator

MCLR

Figure 2-2

CLKIN

CLKOUT

ADC

12-Bit

FVR

Te mp .

Indicator

EUSART

Comparators

MSSPTimer2Timer1Timer0

DAC

CCPs

PSMCsOp Amps

PORTE

HFINTOSC/

FIGURE 1-1: PIC16(L)F1782/3 BLOCK DIAGRAM

DS41579D-page 10 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/C1IN0-/C2IN0-/C3IN0- RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

C1IN0-

C2IN0-

C3IN0-

RA1/AN1/C1IN1-/C2IN1-/
C3IN1-/OPA1OUT

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

C1IN1-

C2IN1-

C3IN1-

OPA1OUT

RA2/AN2/C1IN0+/C2IN0+/
C3IN0+/DACOUT1/V

REF-

DACV

REF-/

RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

C1IN0+

C2IN0+

C3IN0+

DACOUT — AN Digital-to-Analog Converter output.

V

REF- AN — A/D Negative Voltage Reference input.

REF- AN — Digital-to-Analog Converter negative reference.

DACV

RA3 TTL/ST CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

REF+ AN — A/D Voltage Reference input.

V

RA3/AN3/V
DACV

REF+

REF+

(1)

/C1IN1+/

C1IN1+

DACVREF+ AN — Digital-to-Analog Converter positive reference.

RA4/C1OUT/OPA1IN+/T0CKI RA4 TTL/ST CMOS General purpose I/O.

C1OUT

OPA1IN+

T0CKI ST — Timer0 clock input.

RA5/AN4/C2OUT
SS

/OP1INA-/

RA5 TTL/ST CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

(1)

C2OUT

OPA1IN-

SS

RA6/C2OUT/OSC2/CLKOUT RA6 TTL/ST CMOS General purpose I/O.

C2OUT

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

2: All pins have Interrupt-on-Change functionality.

Output

Typ e

Typ e

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

—AN

AN — Comparator C1 positive input.

AN — Comparator C2 positive input.

AN — Comparator C3 positive input.

AN — Comparator C1 positive input.

—

CMOS

AN —

—

CMOS

AN —

Operational Amplifier 1 output.

Comparator C1 output.

Operational Amplifier 1 non-inverting input.

Comparator C2 output.

Operational Amplifier 1 inverting input.

Description

ST — Slave Select input.

—

CMOS

Comparator C2 output.

OSC/4 output.

2

C™ = Schmitt Trigger input with I2C

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 11

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RA7/V
PSMC2CLK/OSC1/CLKIN

RB0/AN12/C2IN1+/PSMC1IN/
PSMC2IN/CCP1

RB1/AN10/C1IN3-/C2IN3-/
C3IN3-/OPA2OUT

RB2/AN8/OPA2IN-/CLKR RB2 TTL/ST CMOS General purpose I/O.

RB3/AN9/C1IN2-/C2IN2-/
C3IN2-/OPA2IN+/CCP2

RB4/AN11/C3IN1+ RB4 TTL/ST CMOS General purpose I/O.

RB5/AN13/C3OUT/T1G/SDO

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

(1)

REF+

/PSMC1CLK/

(1)

/INT

(1)

(1)

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

2: All pins have Interrupt-on-Change functionality.

RA7 TTL/ST CMOS General purpose I/O.

V

REF+ AN — A/D Voltage Reference input.

PSMC1CLK

PSMC2CLK ST — PSMC2 clock input.

OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKIN st — External clock input (EC mode).

RB0 TTL/ST CMOS General purpose I/O.

AN12 AN — A/D Channel 12 input.

C2IN1+

PSMC1IN ST — PSMC1 Event Trigger input.

PSMC2IN ST — PSMC2 Event Trigger input.

CCP1 ST CMOS Capture/Compare/PWM1.

INT ST — External interrupt.

RB1 TTL/ST CMOS General purpose I/O.

AN10 AN — A/D Channel 10 input.

C1IN3-

C2IN3-

C3IN3-

OPA2OUT

AN8 AN — A/D Channel 8 input.

OPA2IN-

CLKR

RB3 TTL/ST CMOS General purpose I/O.

AN9 AN — A/D Channel 9 input.

C1IN2-

C2IN2-

C3IN2-

OPA2IN+

CCP2 ST CMOS Capture/Compare/PWM2.

AN11 AN — A/D Channel 11 input.

C3IN1+

RB5 TTL/ST CMOS General purpose I/O.

AN13 AN — A/D Channel 13 input.

C3OUT — CMOS Comparator C3 output.

T1G ST — Timer1 gate input.

SDO — CMOS SPI data output.

Output

Typ e

Typ e

ST — PSMC1 clock input.

AN — Comparator C2 positive input.

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

—AN

AN —

—CMOS

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

AN —

AN — Comparator C3 positive input.

Operational Amplifier 2 output.

Operational Amplifier 2 inverting input.

Clock output.

Operational Amplifier 2 non-inverting input.

Description

2

C™ = Schmitt Trigger input with I2C

DS41579D-page 12 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

(1)

(1)

(1)

RB6/TX
ICSPCLK

/CK

/SDI

/SDA

(1)

/

RB6 TTL/ST CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

SDI ST — SPI data input.

SDA I

ICSPCLK ST — Serial Programming Clock.

RB7/DACOUT2/RX

(1)

/SCL

(1)

/ICSPDAT

SCK

/

RB7 TTL/ST CMOS General purpose I/O.

DACOUT2 — AN Voltage Reference output.

(1)

(1)

/DT

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

SCK ST CMOS SPI clock.

SCL I

ICSPDAT ST CMOS ICSP™ Data I/O.

RC0/T1OSO/T1CKI/PSMC1A RC0 TTL/ST CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

PSMC1A — CMOS PSMC1 output A.

RC1/T1OSI/PSMC1B/CCP2

(1)

RC1 TTL/ST CMOS General purpose I/O.

T1OSI XTAL XTAL Timer1 oscillator connection.

PSMC1B — CMOS PSMC1 output B.

CCP2 ST CMOS Capture/Compare/PWM2.

RC2/PSMC1C/CCP1

(1)

RC2 TTL/ST CMOS General purpose I/O.

PSMC1C — CMOS PSMC1 output C.

CCP1 ST CMOS Capture/Compare/PWM1.

RC3/PSMC1D/SCK

/SCL

RC3 TTL/ST CMOS General purpose I/O.

(1)

(1)

PSMC1D — CMOS PSMC1 output D.

SCK ST CMOS SPI clock.

SCL I

(1)

RC4/PSMC1E/SDI

/SDA

(1)

RC4 TTL/ST CMOS General purpose I/O.

PSMC1E — CMOS PSMC1 output E.

SDI ST — SPI data input.

SDA I

RC5/PSMC1F/SDO

(1)

RC5 TTL/ST CMOS General purpose I/O.

PSMC1F — CMOS PSMC1 output F.

SDO — CMOS SPI data output.

RC6/PSMC2A/TX

/CK

RC6 TTL/ST CMOS General purpose I/O.

(1)

(1)

PSMC2A — CMOS PSMC2 output A.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC7/PSMC2B/RX

/DT

RC7 TTL/ST CMOS General purpose I/O.

(1)

(1)

PSMC2B — CMOS PSMC2 output B.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

2: All pins have Interrupt-on-Change functionality.

Output

Typ e

Typ e

2

CODI2C™ data input/output.

2

CODI2C™ clock.

2

CODI2C™ clock.

2

CODI2C™ data input/output.

Description

2

C™ = Schmitt Trigger input with I2C

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 13

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RE3/MCLR

DD VDD Power — Positive supply.

V

V

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

/VPP

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

2: All pins have Interrupt-on-Change functionality.

RE3 TTL/ST — General purpose input.

MCLR

PP HV — Programming voltage.

V

Output

Typ e

Typ e

ST — Master Clear with internal pull-up.

Description

2

C™ = Schmitt Trigger input with I2C

DS41579D-page 14 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

V

DD

8

8

Brown-out

Reset

12

3

VSS

Internal

Oscillator

Block

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

15

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

8

8

3

VSS

Internal

Oscillator

Block

RAM

FSR regFSR reg

FSR1 Reg

15

15

MUX

15

Program Memory

Read (PMR)

12

FSR regFSR reg

BSR Reg

5

ConfigurationConfigurationConfiguration

Flash

Program

Memory

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and

FIGURE 2-1: CORE BLOCK DIAGRAM

Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 15

PIC16(L)F1782/3

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See 8.5 “Automatic Context Saving”, for more
information.

2.2 16-level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under­flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft­ware Reset. See Section 3.5 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary” for more

details.

DS41579D-page 16 Preliminary  2011-2012 Microchip Technology Inc.

FIGURE 2-2: CORE BLOCK DIAGRAM

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

V

DD

8

8

Brown-out

Reset

12

3

VSS

Internal

Oscillator

Block

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

15

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

RAM

FSR regFSR reg

FSR1 Reg

15

15

MUX

15

Program Memory

Read (PMR)

12

FSR regFSR reg

BSR Reg

5

ConfigurationConfigurationConfiguration

Flash

Program

Memory

PIC16(L)F1782/3

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 17

PIC16(L)F1782/3

NOTES:

DS41579D-page 18 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

• Data EEPROM memory

Note 1: The Data EEPROM Memory and the

method to access Flash memory through
the EECON registers is described in

Section 12.0 “Data EEPROM and Flash
Program Memory Control”.

(1)

The following features are associated with access and
control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1782/3 family. Accessing
a location above these boundaries will cause a
wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1, and 3-2).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1782 2,048 07FFh
PIC16(L)F1783 4,096 0FFFh

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 19

PIC16(L)F1782/3

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip
Program
Memory

Page 0

07FFh

Wraps to Page 0

Wraps to Page 0

Wraps to Page 0

0800h

CALL, CALLW
RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

Rollover to Page 0

7FFFh

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh
1000h

7FFFh

Page 1

Rollover to Page 0

Interrupt, RETFIE

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR
PIC16(L)F1782

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR
PIC16(L)F1783

DS41579D-page 20 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

constants

BRW ;Add Index in W to

;program counter to

;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower 8 bits of the addressed word in the W
register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.

The high directive will set bit<7> if a label points to a
location in program memory.

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 21

PIC16(L)F1782/3

Addresses BANKx

x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR

x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper 7 bits
of the address define the Bank address and the lower
5 bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta b l e 3 - 2 . For detailed
information, see Tab le 3 -7 .

TABLE 3-2: CORE REGISTERS

DS41579D-page 22 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”).

Note: The C and DC bits operate as Borrow and

Digit Borrow
subtraction.

out bits, respectively, in

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —TOPD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

(1)

(1)

C

bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand.

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(1)

(1)

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 23

PIC16(L)F1782/3

0Bh
0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.3.1 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

3.3.3 COMMON RAM

There are 16 bytes of common RAM accessible from all
banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

DS41579D-page 24 Preliminary  2011-2012 Microchip Technology Inc.

3.3.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown
in Table 3-3.

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 25

TABLE 3-3: PIC16(L)F1782/3 MEMORY MAP (BANKS 0-7)

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 - 2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh
00Fh
010h PORTE 090h TRISE 110h
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h
013h
014h PIR4 094h PIE4 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h
015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON 295h
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSPCON3 297h
018h T1CON 098h OSCTUNE 118h DACCON0 198h
019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h
01Ah TMR2 09Ah OSCSTAT 11Ah
01Bh PR2 09Bh ADRESL 11Bh
01Ch T2CON 09Ch ADRESH 11Ch
01Dh
01Eh
01Fh
020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—093h— 113h CM2CON0 193h EEDATL 213h SSPMSK 293h CCPR1CON 313h — 393h IOCAF

— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh IOCEP
— 09Eh ADCON1 11Eh CM3CON0 19Eh TXSTA 21Eh —29Eh—31Eh—39EhIOCEN
— 09Fh ADCON2 11Fh CM3CON1 19Fh BAUDCON 21Fh —29Fh—31Fh—39FhIOCEF

General
Purpose
Register
80 Bytes

Common RAM

70h – 7Fh

080h

0A0h

0F0h

Core Registers

(Ta bl e 3 - 2)

General
Purpose
Register
80 Bytes

Accesses

70h – 7Fh

100h

120h

13Fh
140h

170h

Core Registers

(Table 3-2)

—190h— 210h WPUE 290h — 310h — 390h INLVLE

— 19Ah TXREG 21Ah — 29Ah CCPR2CON 31Ah —39Ah—
— 19Bh SPBRG 21Bh —29Bh—31Bh—39Bh—
— 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

180h

1A0h

1F0h

Core Registers

(Table 3-2)

— 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC

—218h— 298h CCPR2L 318h — 398h IOCCN

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

200h

Core Registers

(Table 3-2)

— 299h CCPR2H 319h — 399h IOCCF

220h

General
Purpose

(1)

270h

Register

80 Bytes

Accesses

70h – 7Fh

280h

Core Registers

(Table 3-2)

— 314h — 394h IOCBP
— 315h — 395h IOCBN
— 316h — 396h IOCBF
— 317h — 397h IOCCP

2A0h

General
Purpose

(1)

2F0h

Register

80 Bytes

Accesses
70h – 7Fh

300h

Core Registers

(Table 3-2)

320h

General Purpose

Register
33Fh
340h

(1)

36Fh 3EFh
370h

32 Bytes

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

380h

— 391h IOCAP
— 392h IOCAN

3A0h

(1)

3F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

PIC16(L)F1782/3

DS41579D-page 26 Preliminary  2011-2012 Microchip Technology Inc.

Legend: = Unimplemented data memory locations, read as ‘0’

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

40Bh

Core Registers

(Ta bl e 3 - 2)

480h

48Bh

Core Registers

(Ta bl e 3 - 2)

500h

50Bh

Core Registers

(Ta bl e 3 - 2)

580h

58Bh

Core Registers

(Ta bl e 3 - 2)

600h

60Bh

Core Registers

(Ta bl e 3 - 2)

680h

68Bh

Core Registers

(Ta bl e 3 - 2)

700h

70Bh

Core Registers

(Ta bl e 3 - 2)

780h

78Bh

Core Registers

(Ta bl e 3 - 2)

40Ch

Unimplemented

Read as ‘0’

48Ch

Unimplemented

Read as ‘0’

50Ch

Unimplemented

Read as ‘0’

58Ch

Unimplemented

Read as ‘0’

60Ch

Unimplemented

Read as ‘0’

68Ch

Unimplemented

Read as ‘0’

70Ch

Unimplemented

Read as ‘0’

78Ch

Unimplemented

Read as ‘0’

510h
511h

OPA1CON

512h

—

513h

OPA2CON

514h

Unimplemented

Read as ‘0’

519h
51Ah

CLKRCON

51Bh

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h

Common RAM

(Accesses

70h – 7Fh)

4F0h

Common RAM

(Accesses

70h – 7Fh)

570h

Common RAM

(Accesses

70h – 7Fh)

5F0h

Common RAM

(Accesses

70h – 7Fh)

670h

Common RAM

(Accesses
70h – 7Fh)

6F0h

Common RAM

(Accesses
70h – 7Fh)

770h

Common RAM

(Accesses

70h – 7Fh)

7F0h

Common RAM

(Accesses
70h – 7Fh)

47Fh

4FFh 57Fh

5FFh 67Fh 6FFh 77Fh 7FFh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

80Bh

Core Registers

(Ta bl e 3 - 2)

880h

88Bh

Core Registers

(Ta bl e 3 - 2)

900h

90Bh

Core Registers

(Ta bl e 3 - 2)

980h

98Bh

Core Registers

(Ta bl e 3 - 2)

A00h

A0Bh

Core Registers

(Ta bl e 3 - 2)

A80h

A8Bh

Core Registers

(Ta bl e 3 - 2)

B00h

B0Bh

Core Registers

(Ta bl e 3 - 2)

B80h

B8Bh

Core Registers

(Ta bl e 3 - 2)

80Ch

See Ta bl e 3 - 5

88Ch

Unimplemented

Read as ‘0’

90Ch

Unimplemented

Read as ‘0’

98Ch

Unimplemented

Read as ‘0’

A0Ch

Unimplemented

Read as ‘0’

A8Ch

Unimplemented

Read as ‘0’

B0Ch

Unimplemented

Read as ‘0’

B8Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh

9EFh

A6Fh

AEFh

B6Fh

BEFh

870h

Common RAM

(Accesses

70h – 7Fh)

8F0h

Common RAM

(Accesses

70h – 7Fh)

970h

Common RAM

(Accesses

70h – 7Fh)

9F0h

Common RAM

(Accesses

70h – 7Fh)

A70h

Common RAM

(Accesses
70h – 7Fh)

AF0h

Common RAM

(Accesses
70h – 7Fh)

B70h

Common RAM

(Accesses

70h – 7Fh)

BF0h

Common RAM

(Accesses
70h – 7Fh)

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3 - 2)

C80h

C8Bh

Core Registers

(Ta bl e 3 - 2)

D00h

D0Bh

Core Registers

(Ta bl e 3 - 2)

D80h

D8Bh

Core Registers

(Ta bl e 3 - 2)

E00h

E0Bh

Core Registers

(Ta bl e 3 - 2)

E80h

E8Bh

Core Registers

(Ta bl e 3 - 2)

F00h

F0Bh

Core Registers

(Ta bl e 3 - 2)

F80h

F8Bh

Core Registers

(Ta bl e 3 - 2)

C0Ch

C6Fh

Unimplemented

Read as ‘0’

C8Ch

CEFh

Unimplemented

Read as ‘0’

D0Ch

D6Fh

Unimplemented

Read as ‘0’

D8Ch

DEFh

Unimplemented

Read as ‘0’

E0Ch

E6Fh

Unimplemented

Read as ‘0’

E8Ch

EEFh

Unimplemented

Read as ‘0’

F0Ch

F6Fh

Unimplemented

Read as ‘0’

F8Ch

FEFh

See Ta bl e 3 -6

C70h

Common RAM

(Accesses

70h – 7Fh)

CF0h

Common RAM

(Accesses

70h – 7Fh)

D70h

Common RAM

(Accesses

70h – 7Fh)

DF0h

Common RAM

(Accesses

70h – 7Fh)

E70h

Common RAM

(Accesses
70h – 7Fh)

EF0h

Common RAM

(Accesses
70h – 7Fh)

F70h

Common RAM

(Accesses

70h – 7Fh)

FF0h

Common RAM

(Accesses
70h – 7Fh)

C7Fh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-4: PIC16(L)F1782/3 MEMORY MAP (BANKS 8-31)

PIC16(L)F1782/3

PIC16(L)F1782/3

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 16 BANK 16

811h

PSMC1CON

831h

PSMC2CON

812h

PSMC1MDL

832h

PSMC2MDL

813h

PSMC1SYNC

833h

PSMC2SYNC

814h

PSMC1CLK

834h

PSMC2CLK

815h

PSMC1OEN

835h

PSMC2OEN

816h

PSMC1POL

836h

PSMC2POL

817h

PSMC1BLNK

837h

PSMC2BLNK

818h

PSMC1REBS

838h

PSMC2REBS

819h

PSMC1FEBS

839h

PSMC2FEBS

81Ah

PSMC1PHS

83Ah

PSMC2PHS

81Bh

PSMC1DCS

83Bh

PSMC2DCS

81Ch

PSMC1PRS

83Ch

PSMC2PRS

81Dh

PSMC1ASDC

83Dh

PSMC2ASDC

81Eh

PSMC1ASDD

83Eh

PSMC2ASDD

81Fh

PSMC1ASDS

83Fh

PSMC2ASDS

820h

PSMC1INT

840h

PSMC2INT

821h

PSMC1PHL

841h

PSMC2PHL

822h

PSMC1PHH

842h

PSMC2PHH

823h

PSMC1DCL

843h

PSMC2DCL

824h

PSMC1DCH

844h

PSMC2DCH

825h

PSMC1PRL

845h

PSMC2PRL

826h

PSMC1PRH

846h

PSMC2PRH

827h

PSMC1TMRL

847h

PSMC2TMRL

828h

PSMC1TMRH

848h

PSMC2TMRH

829h

PSMC1DBR

849h

PSMC2DBR

82Ah

PSMC1DBF

84Ah

PSMC2DBF

82Bh

PSMC1BLKR

84Bh

PSMC2BLKR

82Ch

PSMC1BLKF

84Ch

PSMC2BLKF

82Dh

PSMC1FFA

84Dh

PSMC1FFA

82Eh

PSMC1STR0

84Eh

PSMC2STR0

82Fh

PSMC1STR1

84Fh

PSMC2STR1

830h

—

840h

86Fh

Unimplemented

Read as ‘0’

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 31

F8Ch

Unimplemented

Read as ‘0’

FE3h
FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

TABLE 3-5: PIC16(L)F1782/3 MEMORY

MAP (BANK 16 DETAILS)

TABLE 3-6: PIC16(L)F1782/3 MEMORY

MAP (BANK 31 DETAILS)

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 27

PIC16(L)F1782/3

3.3.5 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3- 7 can be
addressed from any Bank.

TABLE 3-7: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Value on all

other Resets

DS41579D-page 28 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu

00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

00Fh

— Unimplemented — —

010h PORTE

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF

013h

— Unimplemented — —

014h PIR4

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

016h TMR2 Holding Register for the Least Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu

017h PR2 Holding Register for the Most Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu

018h T2CON

01Dh

to

— Unimplemented — —

01Fh

Bank 1

08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111

08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111

08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111

08Fh

— Unimplemented — —

090h TRISE

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE

093h

— Unimplemented — —

094h PIE4

095h

OPTION_REG

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0

09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR

09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu

09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0 ADRMD CHS4 CHS3 CHS2 CHS1 CHS0

09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0

09Fh ADCON2 TRIGSEL3 TRIGSEL2 TRIGSEL1 TRIGSEL0 CHSN3 CHSN2 CHSN1 CHSN0 000- -000 000- -000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — —RE3— — — ---- x--- ---- u---

— C3IF CCP2IF 0000 0-00 0000 0-00

— — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF --00 --00 --00 --00

—TMR1ON0000 00-0 uuuu uu-u

DONE

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

— — — — —

— — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC2SIE --00 --00 --00 --00

WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu

— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000

(2)

HFIOFL MFIOFR LFIOFR HFIOFS 00q0 --00 qqqq --0q

— ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000

T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

— — — ---- 1--- ---- 1---

— C3IE CCP2IE 0000 0-00 0000 0-00

— SCS1 SCS0 0011 1-00 0011 1-00

GO/DONE

ADON 0000 0000 0000 0000

Val ue o n

POR, BOR

Valu e o n

all other

Resets

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 29

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu

10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu

10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu

10Fh

— Unimplemented — —

110h

— Unimplemented — —

111h

CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100

112h

CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000

113h

CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100

114h

CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000

115h

CMOUT — — — — — MC3OUT MC2OUT MC1OUT ---- -000 ---- -000

116h BORCON SBOREN BORFS

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

118h DACCON0 DACEN

119h DACCON1 DACR<7:0> 0000 0000 0000 0000

11A h

to

— Unimplemented — —

11C h

11Dh APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 0000 0000 0000 0000

11Eh

CM3CON0 C3ON C3OUT C3OE C3POL C3ZLF C3SP C3HYS C3SYNC 0000 0100 0000 0100

11Fh

CM3CON1 C3INTP C3INTN C3PCH<2:0> C3NCH<2:0> 0000 0000 0000 0000

Bank 3

18Ch

ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1-11 1111 1-11 1111

18Dh ANSELB

18Eh

to

— Unimplemented — —

190h

191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000

192h EEADRH

193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h EEDATH

195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000

196h EECON2 EEPROM / Program Memory Control Register 2 0000 0000 0000 0000

197h VREGCON

198h

— Unimplemented — —

199h RCREG USART Receive Data Register 0000 0000 0000 0000

19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000

19Bh SPBRG BRG<7:0> 0000 0000 0000 0000

19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

(2)

—

— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— — — — — —VREGPMReserved ---- --01 ---- --01

--- DACOE1 DACOE2 DACPSS<1:0> --- DACNSS 0-00 00-0 0-00 00-0

EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000

— — — — — BORRDY 1x-- ---q uu-- ---u

— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

Value on

POR, BOR

Valu e o n
all other

Resets

DS41579D-page 30 Preliminary  2011-2012 Microchip Technology Inc.