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PIC16LF1508
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Datasheet PIC16F1508, PIC16F1509, PIC16LF1508, PIC16LF1509 Datasheet

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PIC16(L)F1508/9
Data Sheet
20-Pin Flash, 8-Bit Microcontrollers
with nanoWatt XLP Technology
2011 Microchip Technology Inc. Preliminary DS41609A
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC
logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-726-3
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS41609A-page 2 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9
20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture
• Only 49 Instructions
• Up to 14 Kbytes Linear Program Memory Addressing
• Up to 512 bytes Linear Data Memory Addressing
• Operating Speed:
- DC – 20 MHz clock input
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator Block:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• Three External Clock modes up to 20 MHz

Special Microcontroller Features:

• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1508/9)
- 2.3V to 5.5V (PIC16F1508/9)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-Out Reset (LPBOR)
• Extended Watchdog Timer (WDT):
- Programmable period from 1 ms to 256s
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• Enhanced Low-Voltage Programming (LVP)
• In-Circuit Debug (ICD) via two pins
• Power-Saving Sleep mode:
- Low-Power Sleep mode
- Low-Power BOR (LPBOR)
• Integrated Temperature Indicator
• 128 Bytes High-Endurance Flash
- 100,000 write Flash endurance (minimum)

Extreme Low-Power Management with nanoWatt XLP (PIC16LF1508/9):

• Standby Current:
- 25 nA @ 1.8V, typical
• Watchdog Timer Current:
- 300 nA @ 1.8V, typical
• Operating Current:
-30 A/MHz @ 1.8V, typical
• Timer1 Oscillator Current:
- 600 nA @ 32 kHz, 1.8V, typical

Peripheral Features:

• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- 12 external channels
- 3 internal channels:
- Fixed Voltage Reference
- Digital-to-Analog Converter
- Temperature Indicator channel
- Auto acquisition capability
- Conversion available during Sleep
• 2 Comparators:
- Rail-to-rail inputs
- Power mode control
- Software controllable hysteresis
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- Up to 1 rail-to-rail resistive 5-bit DAC with positive reference selection
• 18 I/O Pins (1 Input-only Pin):
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable interrupt-on-change (IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler
• Four 10-bit PWM modules
• Master Synchronous Serial Port (MSSP) with SPI
2
C™ with:
and I
- 7-bit address masking
- SMBus/PMBus™ compatibility
2011 Microchip Technology Inc. Preliminary DS41609A-page 3
PIC16(L)F1508/9

Peripheral Features (Continued):

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
- Auto-wake-up on Start
• 4 Configurable Logic Cell (CLC) modules:
- 16 selectable input source signals
- Four inputs per module
- Software control of combinational/sequential
logic/state/clock functions
- AND/OR/XOR/D Flop/D Latch/SR/JK
- External or internal inputs/outputs
- Operation while in Sleep
• Numerically Controlled Oscillator (NCO):
- 20-bit accumulator
- 16-bit increment
- True linear frequency control
- High-speed clock input
- Selectable Output modes
- Fixed Duty Cycle (FDC) mode
- Pulse Frequency (PF) mode
• Complementary Waveform Generator (CWG):
- 8 selectable signal sources
- Selectable falling and rising edge dead-band control
- Polarity control
- 4 auto-shutdown sources
- Multiple input sources: PWM, CLC, NCO

PIC12(L)F1501/PIC16(F)L150X Family Types

C/SPI)
2
CLC
EUSART
CWG
MSSP (I
(bytes)
Data SRAM
(2)
I/O’s
10-bit ADC (ch)
DAC
Timers
Comparators
PWM
(8/16-bit)
Device
Data Sheet Index
PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 — — 1 2 1 H — PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 — 1 1 2 1 H — PIC16(L)F1507 (3) 2048 128 18 12 — — 2/1 4 — — 1 2 1 H — PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y PIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: Future Product 2: DS41607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers. 3: DS41586 4: DS41609 PIC16(L)F1508/1509 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.
Flash (words)
Program Memory
PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.
PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.
(1)
NCO
Debug
XLP
DS41609A-page 4 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9
PIC16F1508/9
PIC16LF1508/9
1
2 3 4
14
13
12
11
5 6
7
10
9
8
VDD
RA5 RA4
MCLR/VPP/RA3
RC5
RC4
V
SS
RA0/ICSPDAT
RA1/ICSPCLK RA2
RC0
RC1 RC2
RC3
PDIP, SOIC, SSOP
Note: See Tab le 1 for location of all peripheral functions.
18 17
16
15
20 19
RC6
RC7
RB7
RB4
RB5 RB6
PIC16F1508/9 PIC16LF1508/9
QFN 4x4
Note: See Tab le 1 for location of all peripheral functions.
15
RA1/ICSPCLK
RA2
RC0
RC1
RC2
11
12
13
14
6
7
RC7
RB7
RB4
RB5
RB6
8
9
10
2
3
1
18
1920
16
17
5
4
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
RC3
RC6
VSS
RA0/ICSPDAT
FIGURE 1: 20-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1508/9
FIGURE 2: 20-PIN QFN PACKAGE DIAGRAM FOR PIC16(L)F1508/9
2011 Microchip Technology Inc. Preliminary DS41609A-page 5
PIC16(L)F1508/9
TABLE 1: 20-PIN ALLOCATION TABLE (PIC16(L)F1508/9)
I/O
20-Pin PDIP/SOIC/SSOP
RA0 19 16 AN0 DACOUT1 C1IN+ — —
RA1 18 15 AN1 VREF+ C1IN0-
RA2 17 14 AN2 DACOUT2 C1OUT T0CKI
RA3 4 1 — — — T1G
RA4 3 20 AN3 — — SOSCO
RA5 2 19 — — — SOSCI
RB4 13 10 AN10 — — — — SDA/SDI — — CLC3IN0 — IOC Y —
RB5 12 9 AN11 — — —RX/DT— — — CLC4IN0 — IOC Y —
RB6 11 8 — — — — — SCL/SCK — — — — IOC Y —
RB7 10 7 — — — —TX/CK— — — CLC3 — IOC Y —
RC0 16 13 AN4 — C2IN+ — — — — — CLC2 — — — —
RC1 15 12 AN5 — C1IN1-
RC2 14 11 AN6 — C1IN2-
RC3 7 4 AN7 — C1IN3- ——— — — CLC2IN0 PWM2 — — —
RC4 6 3 — — C2OUT — — — CWG1B — CLC4
RC5 5 2 — — — ———CWG1A — CLC1
RC6 8 5 AN8 — — — — SS
RC7 9 6 AN9 — — ——SDO — — CLC1IN1 — — — —
VDD 1 18 — — — — — — — — — — — — VDD
VSS 2017—— — ——— — — — ———VSS
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
A/D
20-Pin QFN
Reference
Comparator
C2IN0-
C2IN1-
C2IN2-
Timers
——— — — CLC4IN1 — IOC Y ICSPCLK
(2)
(1)
T1G
T1CKI
——— — NCO1
— — — — — — — — — —
EUSART
— —
—SS
— — — — — — IOC Y CLKOUT
—— — NCO1CLK — — IOC Y CLKIN
MSSP
—
(2)
(1)
CWG
— — — — IOC Y ICSPDAT
CWG1FLT — CLC1
— — CLC1IN0 — IOC Y MCLR
— NCO1
NCO
(1)
(2)
CLC
(1)
— PWM4 — — —
CLC2IN1
(2)
CLC3IN1 — — — —
PWM
PWM3 INT/
IOC
— — — —
PWM1 — — —
Interrupt
Pull-up
ICDDAT
ICDCLK
Y —
OSC2
OSC1
Basic
VPP
DS41609A-page 6 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15
3.0 Memory Organization................................................................................................................................................................. 17
4.0 Device Configuration.................................................................................................................................................................. 43
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 49
6.0 Resets ........................................................................................................................................................................................ 65
7.0 Interrupts .................................................................................................................................................................................... 73
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 87
9.0 Watchdog Timer......................................................................................................................................................................... 91
10.0 Flash Program Memory Control ................................................................................................................................................. 95
11.0 I/O Ports ................................................................................................................................................................................... 111
12.0 Interrupt-On-Change ................................................................................................................................................................ 125
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 131
14.0 Temperature Indicator Module ................................................................................................................................................. 133
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 135
16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 149
17.0 Comparator Module.................................................................................................................................................................. 153
18.0 Timer0 Module ......................................................................................................................................................................... 163
19.0 Timer1 Module with Gate Control............................................................................................................................................. 167
20.0 Timer2 Module ......................................................................................................................................................................... 179
21.0 Master Synchronous Serial Port Module.................................................................................................................................. 183
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237
23.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 265
24.0 Configurable Logic Cell (CLC).................................................................................................................................................. 271
25.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 287
26.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 297
27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 313
28.0 Instruction Set Summary.......................................................................................................................................................... 315
29.0 Electrical Specifications............................................................................................................................................................ 329
30.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 357
31.0 Development Support............................................................................................................................................................... 359
32.0 Packaging Information.............................................................................................................................................................. 363
Appendix A: Data Sheet Revision History.......................................................................................................................................... 373
Index .................................................................................................................................................................................................. 375
The Microchip Web Site..................................................................................................................................................................... 381
Customer Change Notification Service .............................................................................................................................................. 381
Customer Support .............................................................................................................................................................................. 381
Reader Response .............................................................................................................................................................................. 382
Product Identification System ............................................................................................................................................................ 383
2011 Microchip Technology Inc. Preliminary DS41609A-page 7
PIC16(L)F1508/9
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.

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Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS41609A-page 8 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9

1.0 DEVICE OVERVIEW

The PIC16(L)F1508/9 are described within this data sheet. They are available in 14-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1508/9 devices. Tables 1-2 shows the pinout descriptions.
Reference Ta bl e 1 -1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral
PIC16F1501
Analog-to-Digital Converter (ADC) ● ● ● ● ● ●●● Complementary Wave Generator (CWG) Digital-to-Analog Converter (DAC) ● ● ● ● ●● Enhanced Universal
Synchronous/Asynchronous Receiver/Transmitter (EUSART)
Fixed Voltage Reference (FVR) ● ● ● ● ● ●●● Numerically Controlled Oscillator (NCO) Temperature Indicator ● ● ● ● ● ●●● Comparators
Configurable Logic Cell (CLC)
CLC1 ● ● ● ● ● ●●● CLC2 ● ● ● ● ● ●●● CLC3 ●● CLC4
Master Synchronous Serial Ports
MSSP1 ● ● ●●
PWM Modules
PWM1 ● ● ● ● ● ●●● PWM2 ● ● ● ● ● ●●● PWM3 PWM4 ● ● ● ● ● ●●●
Timers
Timer0 ● ● ● ● ● ●●● Timer1 ● ● ● ● ● ●●● Timer2 ● ● ● ● ● ●●●
● ● ● ● ● ●●●
● ● ● ● ● ●●●
C1 ● ● ● ● ●● C2 ● ● ●●
● ● ● ● ● ●●●
PIC16F1503
PIC16LF1501
PIC16F1507
PIC16LF1503
PIC16LF1507
●●
●●
PIC16F1508/9
PIC16LF1508/9
2011 Microchip Technology Inc. Preliminary DS41609A-page 9
PIC16(L)F1508/9
PORTC
Note 1: See applicable chapters for more information on peripherals.
2: See Tab l e 1 - 1 for peripherals available on specific devices.
CPU
Program
Flash Memory
RAM
Timi ng
Generation
INTRC
Oscillator
MCLR
(Figure 2-1)
NCO1
PWM4
Timer2Timer1Timer0
CLC4
PWM1 PWM2
PWM3
PORTA
CWG1
CLC3
ADC
10-Bit
FVR
Te mp .
Indicator
OSC1/CLKIN
OSC2/CLKOUT
MSSP1
C2C1
DAC
PORTB
CLC2CLC1
EUSART

FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM

DS41609A-page 10 Preliminary 2011 Microchip Technology Inc.

TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION

Input
Name Function
Typ e
Output
Typ e
PIC16(L)F1508/9
Description
RA0/AN0/C1IN+/DACOUT1/ ICSPDAT/ICDDAT
RA1/AN1/CLC4IN1/V C1IN0-/C2IN0-/ICSPCLK/ ICDCLK
RA2/AN2/C1OUT/DACOUT2/ T0CKI/INT/PWM3/CLC1 CWG1FLT
RA3/CLC1IN0/V MCLR
RA4/AN3/SOSCO/ CLKOUT/T1G
RA5/CLKIN/T1CKI/NCO1CLK/ SOSCI
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
REF+/
PP/T1G
(1)
/
(2)
(2)
/SS
RA0 TTL CMOS General purpose I/O.
AN0 AN — A/D Channel input.
C1IN+ AN — Comparator positive input.
DACOUT1 — AN Digital-to-Analog Converter output.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST CMOS In-Circuit Debug data.
RA1 TTL CMOS General purpose I/O.
AN1 AN — A/D Channel input.
CLC4IN1 ST — Configurable Logic Cell source input.
REF+ AN — A/D Positive Voltage Reference input.
V
C1IN0- AN — Comparator negative input.
C2IN0- AN — Comparator negative input.
ICSPCLK ST — ICSP Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
RA2 ST CMOS General purpose I/O.
AN2 AN — A/D Channel input.
C1OUT — CMOS Comparator output.
DACOUT2 — AN Digital-to-Analog Converter output.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt.
PWM3 — CMOS PWM output.
CLC1 — CMOS Configurable Logic Cell source output.
CWG1FLT
/
RA3 TTL — General purpose input with IOC and WPU.
CLC1IN0 ST — Configurable Logic Cell source input.
PP HV — Programming voltage.
V
T1G ST — Timer1 Gate input.
SS
MCLR
RA4 TTL CMOS General purpose I/O.
AN3 AN — A/D Channel input.
SOSCO XTAL XTAL Secondary Oscillator Connection.
CLKOUT — CMOS F
T1G ST — Timer1 Gate input.
RA5 TTL CMOS General purpose I/O.
CLKIN CMOS — External clock input (EC mode).
T1CKI ST — Timer1 clock input.
NCO1CLK ST — Numerically Controlled Oscillator Clock source input.
SOSCI XTAL XTAL Secondary Oscillator Connection.
ST — Complementary Waveform Generator Fault input.
ST — Slave Select input.
ST — Master Clear with internal pull-up.
OSC/4 output.
2
C™ = Schmitt Trigger input with I2C
2011 Microchip Technology Inc. Preliminary DS41609A-page 11
PIC16(L)F1508/9
TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RB4/AN10/CLC3IN0/SDA/SDI RB4 TTL CMOS General purpose I/O.
AN10 AN — A/D Channel input.
CLC3IN0 ST — Configurable Logic Cell source input.
SDA I
SDI CMOS — SPI data input.
RB5/AN11/CLC4IN0/RX/DT RB5 TTL CMOS General purpose I/O.
AN11 AN — A/D Channel input.
CLC4IN0 ST — Configurable Logic Cell source input.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.
SCL I
SCK ST CMOS SPI clock.
RB7/CLC3/TX/CK RB7 TTL CMOS General purpose I/O.
CLC3 — CMOS Configurable Logic Cell source output.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RC0/AN4/CLC2/C2IN+ RC0 TTL CMOS General purpose I/O.
AN4 AN — A/D Channel input.
CLC2 — CMOS Configurable Logic Cell source output.
C2IN+ AN — Comparator positive input.
RC1/AN5/C1IN1-/C2IN1-/PWM4/
(1)
NCO1
RC2/AN6/C1IN2-/C2IN2- RC2 TTL CMOS General purpose I/O.
RC3/AN7/C1IN3-/PWM2/ CLC2IN0
RC4/C2OUT/CLC2IN1/CLC4/ CWG1B
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
HV = High Voltage XTAL = Crystal levels
2: Alternate location for peripheral pin function selected by the APFCON register.
RC1 TTL CMOS General purpose I/O.
AN5 AN — A/D Channel input.
C1IN1- AN — Comparator negative input.
C2IN1- AN — Comparator negative input.
PWM4 — CMOS PWM output.
NCO1 — CMOS Numerically Controlled Oscillator is source output.
AN6 AN — A/D Channel input.
C1IN2- AN — Comparator negative input.
C2IN2- AN — Comparator negative input.
RC3 TTL CMOS General purpose I/O.
AN7 AN — A/D Channel input.
C1IN3- AN — Comparator negative input.
PWM2 — CMOS PWM output.
CLC2IN0 ST — Configurable Logic Cell source input.
RC4 TTL CMOS General purpose I/O.
C2OUT — CMOS Comparator output.
CLC2IN1 ST — Configurable Logic Cell source input.
CLC4 — CMOS Configurable Logic Cell source output.
CWG1B — CMOS CWG complementary output.
Output
Typ e
Typ e
2
CODI2C data input/output.
2
CODI2C™ clock.
Description
2
C™ = Schmitt Trigger input with I2C
DS41609A-page 12 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9
TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RC5/PWM1/CLC1 CWG1A
RC6/AN8/NCO1
(1)
SS
RC7/AN9/CLC1IN1/SDO RC7 TTL CMOS General purpose I/O.
DD VDD Power — Positive supply.
V
SS VSS Power — Ground reference.
V
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
(2)
/
(2)
/CLC3IN1/
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels
RC5 TTL CMOS General purpose I/O.
PWM1 — CMOS PWM output.
CLC1 — CMOS Configurable Logic Cell source output.
CWG1A — CMOS CWG primary output.
RC6 TTL CMOS General purpose I/O.
AN8 AN — A/D Channel input.
NCO1 — CMOS Numerically Controlled Oscillator source output.
CLC3IN1 ST — Configurable Logic Cell source input.
SS
AN9 AN — A/D Channel input.
CLC1IN1 ST — Configurable Logic Cell source input.
SDO — CMOS SPI data output.
Output
Typ e
Typ e
ST — Slave Select input.
Description
2
C™ = Schmitt Trigger input with I2C
2011 Microchip Technology Inc. Preliminary DS41609A-page 13
PIC16(L)F1508/9
NOTES:
DS41609A-page 14 Preliminary 2011 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in Shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information.
PIC16(L)F1508/9

2.2 16-Level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under­flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft­ware Reset. See section Section 3.4 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See
Section 28.0 “Instruction Set Summary” for more
details.
2011 Microchip Technology Inc. Preliminary DS41609A-page 15
PIC16(L)F1508/9
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Instruction Decode &
Control
Timing
Generation
CLKIN
CLKOUT
8
8
12
3
Internal
Oscillator
Block
Configuration
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W Reg
Instruction Decode &
Control
Timing
Generation
8
8
3
Internal
Oscillator
Block
Configuration
15
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr
7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
8
8
3
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
Power-up
Timer
Power-on
Reset
Watchdog
Timer
V
DD
Brown-out
Reset
VSSVDD VSSVDD VSS

FIGURE 2-1: CORE BLOCK DIAGRAM

DS41609A-page 16 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
-User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (See
Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device
PIC16F1508 PIC16LF1508
PIC16F1509 PIC16LF1509
Note 1: High-endurance Flash applies to low byte of each address in the range.
Program Memory
Space (Words)
4,096 0FFFh 0F80h-0FFFh
8,192 1FFFh 1F80h-1FFFh
Last Program Memory
Address
High-Endurance Flash
Memory Address Range
(1)
2011 Microchip Technology Inc. Preliminary DS41609A-page 17
PIC16(L)F1508/9
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
CALL, CALLW
RETURN, RETLW
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh 1000h
7FFFh
Page 1
Rollover to Page 1
Interrupt, RETFIE
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh 1000h
7FFFh
Page 1
Rollover to Page 3
Page 2
Page 3
17FFh 1800h
1FFFh 2000h
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR PIC16(L)F1508
FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR PIC16(L)F1509
DS41609A-page 18 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9
constants
BRW ;Add Index in W to
;program counter to
;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3
my_function
;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W
constants
RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3
my_function
;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in pro­gram memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.
3.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by set­ting bit 7 of the FSRxH register and reading the match­ing INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the pro­gram memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates access­ing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
The BRW instruction makes this type of table very sim­ple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.
2011 Microchip Technology Inc. Preliminary DS41609A-page 19
PIC16(L)F1508/9
Addresses BANKx
x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR
x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper 7-bits of the address define the Bank address and the lower 5-bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta b l e 3 -2 . For detailed information, see Tab le 3 -8 .
TABLE 3-2: CORE REGISTERS
DS41609A-page 20 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 28.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in subtraction.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TO
PD ZDC
(1)
(1)
C
bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
bit 0 C: Carry/Borrow
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred
: Power-Down bit
1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
(1)
(1)
2011 Microchip Technology Inc. Preliminary DS41609A-page 21
PIC16(L)F1508/9
0Bh
0Ch
1Fh
20h
6Fh 70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appro­priate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all banks.
FIGURE 3-3: BANKED MEMORY
PARTITIONING
DS41609A-page 22 Preliminary 2011 Microchip Technology Inc.

3.2.5 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1508/9 are as shown in Table 3-5 and Tab le 3 - 6.
2011 Microchip Technology Inc. Preliminary DS41609A-page 23
TABLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 1-7
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta bl e 3 -2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 00Fh 010h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h 013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh— —090h—110h—190h—210h—290h
—094h— 114h CM2CON1 194h PMDATH 214h
TMR1L 096h PCON 116h BORCON 196h PMCON2 216h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h T1CON 098h
T1GCON 099h OSCCON 119h
TMR2 09Ah OSCSTAT 11Ah
PR2 09BhADRESL11Bh
T2CON 09Ch ADRESH 11Ch
— 09Dh ADCON0 11Dh APFCON 19Dh — —
080h
Core Registers
(Ta bl e 3 -2 )
—118h
09Eh ADCON1 11Eh 09Fh ADCON2 11Fh
0A0h
100h
120h
Core Registers
(Table 3-2)
DACCON0 DACCON1
—19Ah —19Bh — 19Ch
— —19Fh
180h
Core Registers
(Table 3-2)
198h —218h 199h
19Eh
1A0h
RCREG
TXREG SPBRG
SPBRGH
RCSTA TXSTA
BAUDCON
200h
Core Registers
(Table 3-2)
SSP1BUF SSP1ADD SSP1MSK
SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3
219h 21Ah —29Ah—31Ah—39Ah— 21Bh —29Bh—31Bh 21Ch — 29Ch — 31Ch 21Dh 21Eh 21Fh
220h
280h
Core Registers
(Table 3-2)
— 30Ch — 38Ch —
—28Eh—30Eh—38Eh—
291h 292h 293h 294h 295h 296h
297h — —299h— 319h — 399h —
— — —
298h
29Dh
29Eh
29Fh
2A0h
— 30Dh — 38Dh —
— — — — — — — 316h — 396h IOCBF — 317h — 397h — — 318h — 398h —
— — —
300h
310h 311h 312h 313h 314h 315h
31Dh 31Eh 31Fh
320h
Core Registers
(Table 3-2)
— 390h — — — — — —
— — — — —
380h
Core Registers
(Table 3-2)
391h IOCAP 392h IOCAN 393h 394h IOCBP 395h IOCBN
39Bh 39Ch 39Dh 39Eh 39Fh
3A0h
IOCAF
— — — — —
General Purpose Register
80 Bytes
06Fh 070h
Common RAM
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
0EFh 0F0h
General Purpose Register
80 Bytes
Common RAM
(Accesses 70h – 7Fh)
General Purpose Register
80 Bytes
16Fh 1EFh 26Fh 2EFh 170h
Common RAM
(Accesses
70h – 7Fh)
1F0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
270h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
2F0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
Unimplemented
Read as ‘0’
36Fh 3EFh 370h
Common RAM
(Accesses 70h – 7Fh)
3F0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
PIC16(L)F1508/9
DS41609A-page 24 Preliminary 2011 Microchip Technology Inc.
TABLE 3-4: PIC16(L)F1509 MEMORY MAP, BANK 1-7
PIC16(L)F1508/9
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta bl e 3 -2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 00Fh 010h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h 013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh
020h
06Fh 070h
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh— —090h—110h—190h—210h—290h
—094h— 114h CM2CON1 194h PMDATH 214h
TMR1L 096h PCON 116h BORCON 196h PMCON2 216h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h T1CON 098h
T1GCON 099h OSCCON 119h
TMR2 09Ah OSCSTAT 11Ah
PR2 09BhADRESL11Bh
T2CON 09Ch ADRESH 11Ch
— 09Dh ADCON0 11Dh APFCON 19Dh — —
General Purpose Register
80 Bytes
Common RAM
080h
Core Registers
(Ta bl e 3 -2 )
—118h
09Eh ADCON1 11Eh 09Fh ADCON2 11Fh 0A0h
General Purpose Register 80 Bytes
0EFh 0F0h
Common RAM
(Accesses 70h – 7Fh)
100h
120h
16Fh 1EFh 26Fh 2EFh 170h
Core Registers
(Table 3-2)
DACCON0 DACCON1
—19Ah —19Bh — 19Ch
— —19Fh
General Purpose Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
180h
Core Registers
(Table 3-2)
198h —218h 199h
19Eh
1A0h
1F0h
RCREG
TXREG SPBRG
SPBRGH
RCSTA TXSTA
BAUDCON
General Purpose Register 80 Bytes
Common RAM
(Accesses 70h – 7Fh)
200h
Core Registers
(Table 3-2)
SSP1BUF SSP1ADD SSP1MSK
SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3
219h 21Ah —29Ah—31Ah—39Ah— 21Bh —29Bh—31Bh 21Ch — 29Ch — 31Ch 21Dh 21Eh 21Fh
220h
270h
General Purpose Register 80 Bytes
Common RAM
(Accesses 70h – 7Fh)
280h
Core Registers
(Table 3-2)
— 30Ch — 38Ch —
—28Eh—30Eh—38Eh—
291h 292h 293h 294h 295h 296h
297h — —299h— 319h — 399h —
— — —
298h
29Dh
29Eh
29Fh
2A0h
2F0h
— 30Dh — 38Dh —
— — — — — — — 316h — 396h IOCBF — 317h — 397h — — 318h — 398h —
— — —
General Purpose Register
80 Bytes
Common RAM
(Accesses 70h – 7Fh)
300h
Core Registers
(Table 3-2)
310h 311h 312h 313h 314h 315h
31Dh 31Eh 31Fh 320h General Purpose
36Fh 3EFh 370h
— 390h — — — — — —
— — — — —
Register 16Bytes 3A0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
380h
391h IOCAP 392h IOCAN 393h 394h IOCBP 395h IOCBN
39Bh 39Ch 39Dh 39Eh 39Fh
3F0h
Core Registers
(Table 3-2)
IOCAF
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
— — — — —
2011 Microchip Technology Inc. Preliminary DS41609A-page 25
TABLE 3-5: PIC16(L)F1508/9 MEMORY MAP, BANK 8-23
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh
420h
Core Registers
(Ta bl e 3 -2 )
— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh— —48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh— —490h—510h—590h—610h—690h— 710h — 790h — —491h—511h—591h— 611h PWM1DCL 691h CWG1DBR 711h — 791h — —492h—512h—592h— 612h PWM1DCH 692h CWG1DBF 712h — 792h — —493h—513h—593h— 613h PWM1CON 693h CWG1CON0 713h — 793h — —494h—514h—594h— 614h PWM2DCL 694h CWG1CON1 714h — 794h — —495h—515h—595h— 615h PWM2DCH 695h CWG1CON2 715h — 795h — —496h—516h—596h— 616h PWM2CON 696h — 716h — 796h — —497h—517h—597h— 617h PWM3DCL 697h — 717h — 797h — — 498h NCO1ACCL 518h —598h— 618h PWM3DCH 698h — 718h — 798h — — 499h NCO1ACCH 519h —599h— 619h PWM3CON 699h — 719h — 799h — — 49Ah NCO1ACCU 51Ah —59Ah— 61Ah PWM4DCL 69Ah —71Ah—79Ah— — 49Bh NCO1INCL 51Bh —59Bh— 61Bh PWM4DCH 69Bh —71Bh—79Bh— — 49Ch NCO1INCH 51Ch — 59Ch — 61Ch PWM4CON 69Ch — 71Ch — 79Ch — — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh — — 49Eh NCO1CON 51Eh —59Eh—61Eh—69Eh—71Eh—79Eh— — 49Fh NCO1CLK 51Fh —59Fh—61Fh—69Fh—71Fh—79Fh—
480h
48Bh
4A0h
Core Registers
(Ta bl e 3 -2 )
500h
50Bh
520h
Core Registers
(Table 3-2)
580h
58Bh
5A0h
Core Registers
(Table 3-2)
600h
60Bh
620h
Core Registers
(Table 3-2)
680h
68Bh
6A0h
Core Registers
(Table 3-2)
700h
70Bh
720h
Core Registers
(Table 3-2)
780h
78Bh
7A0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 64Fh 6EFh 76Fh 7EFh 470h
Common RAM
(Accesses
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
70h – 7Fh)
4F0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
570h
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
5F0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
650h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
6F0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
770h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
7F0h
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
Core Registers
(Ta bl e 3 -2 ) 80Bh 80Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 870h
Common RAM
(Accesses
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
70h – 7Fh)
880h
88Bh 88Ch
8F0h
Core Registers
(Ta bl e 3 -2 )
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
900h
90Bh 90Ch
970h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
980h
98Bh 98Ch
9EFh 9F0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
A00h
A0Bh A0Ch
A6Fh A70h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
A80h
A8Bh
A8Ch
AEFh AF0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
B00h
B0Bh B0Ch
B6Fh B70h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
B80h
B8Bh B8Ch
BEFh BF0h
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
PIC16(L)F1508/9
DS41609A-page 26 Preliminary 2011 Microchip Technology Inc.
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta bl e 3 -2 )
C80h
C8Bh
Core Registers
(Ta bl e 3 -2 )
D00h
D0Bh
Core Registers
(Ta bl e 3 -2 )
D80h
D8Bh
Core Registers
(Ta bl e 3 -2 )
E00h
E0Bh
Core Registers
(Ta bl e 3 -2 )
E80h
E8Bh
Core Registers
(Ta bl e 3 -2 )
F00h
F0Bh
Core Registers
(Ta bl e 3 -2 )
F80h
F8Bh
Core Registers
(Ta bl e 3 -2 )
C0Ch
—C8Ch—D0Ch—D8Ch—E0Ch—E8Ch—F0Ch
See Tab l e 3 - 7 for register mapping
details
F8Ch
See Tab l e 3 - 7 for register mapping
details
C0Dh
—C8Dh—D0Dh—D8Dh—E0Dh—E8Dh— F0Dh F8Dh
C0Eh
—C8Eh—D0Eh—D8Eh—E0Eh—E8Eh— F0Eh F8Eh
C0Fh
—C8Fh—D0Fh—D8Fh—E0Fh—E8Fh— F0Fh F8Fh
C10h
—C90h—D10h—D90h—E10h—E90h— F10h F90h
C11h
—C91h—D11h—D91h—E11h—E91h— F11h F91h
C12h
—C92h—D12h—D92h—E12h—E92h— F12h F92h
C13h
—C93h—D13h—D93h—E13h—E93h— F13h F93h
C14h
—C94h—D14h—D94h—E14h—E94h— F14h F94h
C15h
—C95h—D15h—D95h—E15h—E95h— F15h F95h
C16h
—C96h—D16h—D96h—E16h—E96h— F16h F96h
C17h
—C97h—D17h—D97h—E17h—E97h— F17h F97h
C18h
—C98h—D18h—D98h—E18h—E98h— F18h F98h
C19h
—C99h—D19h—D99h—E19h—E99h— F19h F99h
C1Ah
—C9Ah—D1Ah—D9Ah—E1Ah—E9Ah— F1Ah F9Ah
C1Bh
—C9Bh—D1Bh—D9Bh—E1Bh—E9Bh— F1Bh F9Bh
C1Ch
—C9Ch—D1Ch—D9Ch—E1Ch—E9Ch— F1Ch F9Ch
C1Dh
—C9Dh—D1Dh—D9Dh—E1Dh—E9Dh— F1Dh F9Dh
C1Eh
—C9Eh—D1Eh—D9Eh—E1Eh—E9Eh— F1Eh F9Eh
C1Fh
—C9Fh—D1Fh—D9Fh—E1Fh—E9Fh— F1Fh F9Fh
C20h
Unimplemented
Read as ‘0’
CA0h
Unimplemented
Read as ‘0’
D20h
Unimplemented
Read as ‘0’
DA0h
Unimplemented
Read as ‘0’
E20h
Unimplemented
Read as ‘0’
EA0h
Unimplemented
Read as ‘0’
F20h FA0h
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h
Common RAM
(Accesses
70h – 7Fh)
CF0h
Common RAM
(Accesses 70h – 7Fh)
D70h
Common RAM
(Accesses
70h – 7Fh)
DF0h
Common RAM
(Accesses 70h – 7Fh)
E70h
Common RAM
(Accesses
70h – 7Fh)
EF0h
Common RAM
(Accesses 70h – 7Fh)
F70h
Common RAM
(Accesses 70h – 7Fh)
FF0h
Common RAM
(Accesses 70h – 7Fh)
CFFh
CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
TABLE 3-6: PIC16(L)F1508/9 MEMORY MAP, BANK 24-31
PIC16(L)F1508/9
TABLE 3-7: PIC16(L)F1508/9 MEMORY MAP, BANK 30-31
Bank 30
F0Ch
—
F0Dh
—
F0Eh
—
F0Fh
CLCDATA
F10h
CLC1CON
F11h
CLC1POL
F12h
CLC1SEL0
F13h
CLC1SEL1
F14h
CLC1GLS0
F15h
CLC1GLS1
F16h
CLC1GLS2
F17h
CLC1GLS3
F18h
CLC2CON
F19h
CLC2POL
F1Ah
CLC2SEL0
F1Bh
CLC2SEL1
F1Ch
CLC2GLS0
F1Dh
CLC2GLS1
F1Eh
CLC2GLS2
F1Fh
CLC2GLS3
F20h
CLC3CON
F21h
CLC3POL
F22h
CLC3SEL0
F23h
CLC3SEL1
F24h
CLC3GLS0
F25h
CLC3GLS1
F26h
CLC3GLS2
F27h
CLC3GLS3
F2Ah
CLC4CON
F2Bh
CLC4POL
F2Ch
CLC4SEL0
F2Dh
CLC4SEL1
F2Eh
CLC4GLS0
F2Fh
CLC4GLS1
F31h
CLC4GLS2
F31h
CLC4GLS3
F32h
Unimplemented
Read as ‘0’
F6Fh
Bank 31
F8Ch
FE3h
Unimplemented
Read as ‘0’
FE4h
STATUS_SHAD
FE5h
WREG_SHAD
FE6h
BSR_SHAD
FE7h
PCLATH_SHAD
FE8h
FSR0L_SHAD
FE9h
FSR0H_SHAD
FEAh
FSR1L_SHAD
FEBh
FSR1H_SHAD
FECh
—
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Legend: = Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1508/9
2011 Microchip Technology Inc. Preliminary DS41609A-page 27
PIC16(L)F1508/9

3.2.6 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3 -8 can be addressed from any Bank.
TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0-31
x00h or
INDF0
x80h
x01h or
INDF1
x81h
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)
— — —TOPD ZDCC---1 1000 ---q quuu
— — —BSR<4:0>---0 0000 ---0 0000
— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
Shaded locations are unimplemented, read as ‘0’.
Val ue o n
POR, BOR
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on all
other Resets
DS41609A-page 28 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1508/9
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Bank 0
00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx
00Dh PORTB RB7 RB6 RB5 RB4
00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx
00Fh
010h
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF
012h PIR2 OSFIF C2IF C1IF
013h PIR3
014h
015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON
01Dh
01Eh
01Fh
— Unimplemented — —
— Unimplemented — —
— BCL1IF NCO1IF — — 000- -0-- 000- -0--
— — — — CLC4IF CLC3IF CLC2IF CLC1IF ---- 0000 ---- 0000
— Unimplemented — —
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— — — — xxxx ---- xxxx ----
— TMR2IF TMR1IF 0000 0-00 0000 0-00
—TMR1ON0000 00-0 uuuu uu-u
DONE
T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
Bank 1
08Ch TRISA — — TRISA5 TRISA4 —
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4
08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
08Fh
090h
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE
092h PIE2 OSFIE C2IE C1IE
093h PIE3
094h
095h
096h PCON STKOVF STKUNF
097h WDTCON
098h
099h OSCCON
09Ah OSCSTAT SOSCR
09Bh ADRESL xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0
09Eh ADCON1 ADFM ADCS<2:0>
09Fh ADCON2 TRIGSEL<3:0>
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F1508/9 only.
— Unimplemented — —
— Unimplemented — —
— BCL1IE NCO1IE — — 000- 00-- 000- 00--
— — — — CLC4IE CLC3IE CLC2IE CLC1IE ---- 0000 ---- 0000
— Unimplemented — —
OPTION_REG
— Unimplemented — —
2: Unimplemented, read as ‘1’.
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
—RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu
— — WDTPS<4:0> SWDTEN --01 0110 --01 0110
— IRCF<3:0> —SCS<1:0>-011 1-00 -011 1-00
—OSTSHFIOFR— — LFIOFR HFIOFS 0-q0 --00 q-qq --qq
— CHS<4:0>
(2)
TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
— — — — 1111 ---- 1111 ----
— TMR2IE TMR1IE 0000 0-00 0000 0-00
GO/DONE
— —
— — — — 0000 ---- 0000 ----
ADPREF<1:0>
ADON -000 0000 -000 0000
0000 --00 0000 --00
Value on all
other
Resets
2011 Microchip Technology Inc. Preliminary DS41609A-page 29
PIC16(L)F1508/9
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Bank 2
10Ch LATA — —LATA5LATA4— L ATA2 L ATA1 L ATA0 --xx -xxx --uu -uuu
10Dh LATB LATB7 LATB6 LATB5 LATB4
10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh
110h
111h CM1CON0 C1ON C1OUT C1OE C1POL
112h CM1CON1 C1INTP C1INTN C1PCH<1:0>
113h CM2CON0 C2ON C2OUT C2OE C2POL
114h CM2CON1 C2INTP C2INTN C2PCH<1:0>
115h CMOUT
116h BORCON SBOREN BORFS
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN
119h DACCON1
11Dh APFCON
11Eh
11Fh
— Unimplemented — —
— Unimplemented — —
— — — — — —MC2OUT MC1OUT---- --00 ---- --00
— — — — — BORRDY 10-- ---q uu-- ---u
— DACOE1 DACOE2 — DACPSS — — 0-00 -0-- 0-00 -0--
— — DACR<4:0> ---0 0000 ---0 0000
11A h
to
— Unimplemented — —
11C h
— — — SSSEL T1GSEL — CLC1SEL NCO1SEL ---0 0-00 ---0 0-00
— Unimplemented — —
— Unimplemented — —
— — — — xxxx ---- uuuu ----
— C1SP C1HYS C1SYNC 0000 -100 0000 -100
— C1NCH<2:0> 0000 -000 0000 -000
— C2SP C2HYS C2SYNC 0000 -100 0000 -100
— C2NCH<2:0> 0000 -000 0000 -000
Bank 3
18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
18Dh ANSELB
18Eh ANSELC ANSC7 ANSC6
18Fh
190h
191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH
193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH
195h PMCON1
196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON
198h
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F1508/9 only.
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
2: Unimplemented, read as ‘1’.
— — ANSB5 ANSB4 — — — — --11 ---- --11 ----
— — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
— Flash Program Memory Address Register High Byte -000 0000 -000 0000
— — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
(2)
—
(1)
——————VREGPMReserved ---- --01 ---- --01
CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Value on all
other
Resets
DS41609A-page 30 Preliminary 2011 Microchip Technology Inc.
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