Datasheet PIC16LF1454, PIC16LF1455, PIC16LF1459, PIC16F1454, PIC16F1455 Datasheet

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PIC16(L)F1454/5/9

Data Sheet

14/20-Pin Flash, 8-Bit USB Microcontrollers

with XLP Technology

 2012 Microchip Technology Inc. Preliminary DS41639A

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC

logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

QUALITY MANAGEMENT S

DS41639A-page 2 Preliminary  2012 Microchip Technology Inc.

ISBN: 9781620763476

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

PIC16(L)F1454/5/9

14/20-Pin, 8-Bit Flash USB Microcontroller with

XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• 14 Kbytes Linear Program Memory Addressing

• 1024 Bytes Linear Data Memory Addressing

• Operating Speed:

- DC – 48 MHz clock input

- DC – 83 ns instruction cycle

- Selectable 3x or 4x PLL for specific frequencies

• Interrupt Capability with Automatic Context Saving

• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

capable of accessing both data or program memory

- FSRs can read program and data memory

Special Microcontroller Features:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF145X)

- 2.3V to 5.5V (PIC16F145X)

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Programmable Brown-Out Reset (BOR)

• Low-Power BOR (LPBOR)

• Extended Watchdog Timer (WDT):

- Programmable period from 1 ms to 256s

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

• Enhanced Low-Voltage Programming (LVP)

• Power-Saving Sleep mode:

Universal Serial Bus (USB) Features:

• Self-Tuning from USB Host (eliminates need for external crystal)

• USB V2.0 Compliant SIE

• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)

• Supports Control, Interrupt, Isochronous and Bulk Transfers

• Supports up to Eight Bidirectional Endpoints

• 512-Byte Dual Access RAM for USB

• Interrupt-on-Change (IOC) on D+/D- for USB Host Detection

• Configurable Internal Pull-up Resistors for use with USB

Extreme Low-Power Management PIC16LF145X with XLP:

• Sleep mode: 25 nA @ 1.8V, typical

• Watchdog Timer Current: 290 nA @ 1.8V, typical

• Timer1 Oscillator: 600 nA @ 32 kHz, typical

• Operating Current: 25 A/MHz @ 1.8V, typical

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator Block:

- Factory calibrated to ±0.25%, typical

- Software selectable frequency range from 16 MHz to 31 kHz

- Tunable to 0.25% across temperature range

- 48 MHz with 3x PLL

• 31 kHz Low-Power Internal Oscillator

• Clock Switching with run from:

- Primary Oscillator

- Secondary Oscillator (SOSC)

- Internal Oscillator

• Clock Reference Output:

- Clock Prescaler

-CLKOUT

Analog Features

• Analog-to-Digital Converter (ADC):

- 10-bit resolution

- Up to nine external channels

- Two internal channels:

- Fixed Voltage Reference channel

- DAC output channel

- Auto acquisition capability

- Conversion available during Sleep

• Two Comparators:

- Rail-to-rail inputs

- Power mode control

- Software controllable hysteresis

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

• Up to One Rail-to-Rail Resistive 5-Bit DAC with Positive Reference Selection

Note 1: Analog features are not available on

PIC16(L)F1454 devices.

(1)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 3

PIC16(L)F145X

Peripheral Features:

• Up to 14 I/O Pins and Three Input-only Pins:

- High current sink/source 25 mA/25 mA

- Individually programmable weak pull-ups

- Individually programmable Interrupt-On-Change (IOC) pins

• Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

• Two 10-bit PWM modules

• Complementary Waveform Generator (CWG)

- Up to four selectable signal sources

- Selectable falling and rising edge dead-band

control

- Polarity control

- Up to four auto-shutdown sources

- Multiple input sources: PWM, Comparators

• Master Synchronous Serial Port (MSSP) with SPI

C™ with:

and I

- 7-bit address masking

- SMBus/PMBus™ compatibility

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART):

- RS-232, RS-485 and LIN compatible

- Auto-baud detect

- Auto-wake-up on Start

(1)

Note 1: Not available on PIC16(L)F1454 devices.

PIC16(L)F145X Family Types

(1)

Debug

Clock Reference

(bytes)

Data SRAM

(2)

Comparators

DAC

Timers

I/Os

10-bit ADC (ch)

PWM

(8/16-bit)

Device

Program Memory

Flash (words)

Data Sheet Index

PIC16(L)F1454 (1) 8192 1024 11 — — — 2/1 2 1 1 — 1 1 I/H Y PIC16(L)F1455 (1) 8192 1024 11 5 2 1 2/1 2 1 1 1 1 1 I/H Y PIC16(L)F1459 (1) 8192 1024 17 9 2 1 2/1 2 1 1 1 1 1 I/H Y Note 1: I - Debugging, Integrated on Chip; H - Debugging, Available using Debug Header;

E - Emulation, Available using Emulation Header.

2: Three pins are input-only.

Data Sheet Index:

1: DS41639 PIC16(L)F1454/1455/1459 Data Sheet, 14/20-Pin Flash, 8-Bit USB Microcontrollers.

Note: For other small form-factor package availability and marking information, please visit

www.microchip.com/packaging or contact your local sales office.

C™/SPI)

EUSART

MSSP (I

USB

CWG

XLP

DS41639A-page 4 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F145X

PDIP, SOIC, TSSOP

PIC16(L)F1454

PIC16(L)F1455

2 3 4

14 13

5 6

VDD RA5 RA4

MCLR

/VPP/RA3

RC5

RC4

RC3

RA0/D+/ICSPDAT

(1)

RA1/D-/ICSPCLK

(1)

VUSB3V3

RC0/ICSPDAT

RC1/ICSPCLK RC2

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Ta bl e 1 and Tab l e 2 for location of all peripheral functions.

13141516

RA5

RA4

MCLR/VPP/RA3

RC4

RC3

ICSPCLK/RC1

RC2

RC0/ICSPDAT

RA0/D+/ICSPDAT

(1)

VUSB3V3

RA1/D-/ICSPCLK

(1)

Vss

VDD

RC5

QFN (4x4)

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Tab le 1 and Ta bl e 2 for location of all peripheral functions.

PIC16(L)F1454 PIC16(L)F1455

FIGURE 1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1454/1455

FIGURE 2: 16-PIN QFN DIAGRAM FOR PIC16(L)F1454/1455

 2012 Microchip Technology Inc. Preliminary DS41639A-page 5

PIC16(L)F145X

PIC16(L)F1459

2 3 4

5 6

VDD

RA5 RA4

MCLR

/VPP/RA3

RC5

RC4

RA0/D+/ICSPDAT

(1)

RA1/D-/ICSPCLK

(1)

VUSB3V3

RC0/ICSPDAT

RC1/ICSPCLK RC2

RC3

PDIP, SOIC, SSOP

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Ta bl e 3 for location of all peripheral functions.

18 17

20 19

RC6

RC7

RB7

RB4

RB5 RB6

2 3

17181920

MCLR/VPP/RA3

RC5 RC4 RC3 RC6

RC7

RB7

RB4

RB5

RB6

RC1/ICSPCLK

RC0/ICSPDAT

USB3V3

RA1/D-/ICSPCLK

(1)

RA0/D+/ICSPDAT

(1)

Vss

RA4

RA5

RC2

QFN (4x4)

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Table 3 for location of all peripheral functions.

PIC16(L)F1459

FIGURE 3: 20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1459

FIGURE 4: 20-PIN QFN DIAGRAM FOR PIC16(L)F1459

DS41639A-page 6 Preliminary  2012 Microchip Technology Inc.

TABLE 1: 14-PIN ALLOCATION TABLE (PIC16(L)F1454)

PIC16(L)F145X

I/O

14-Pin PDIP/SOIC/TSSOP

RA0 13 12 — — — — — D+ — — — IOC ICSPDAT

RA1 12 11 — — — — — D- — — — IOC ICSPCLK

RA2 — — — — — — — — — — — — —

RA3 4 3 — — — T1G

RA4 3 2 — — — SOSCO

RA5 2 1 — — — SOSCI

RC0 10 9 — — — — — — — — SCL

RC1 9 8 — — — — — — — — SDA

RC2 8 7 — — — — — — — — SDO

RC3 7 6 — — — — — — — PWM2

RC4 6 5 — — — — — — TK

RC5 5 4 — — — T0CKI — — RXDTPWM1 — — —

VDD 1 16 — — — — — — — — — — VDD

VSS 14 13 — — — — — — — — — — VSS

VUSB3V3 11 10 — — — — — VUSB3V3 — — — — —

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

ADC

16-Pin QFN

Reference

Comparator

T1G

T1CKI

Timer

(2)

(1)

CWG

— — — — SS

— — — — SDO

— — — PWM2

USB

EUSART

PWM

(2)

(1)

— — — —

MSSP

(2)

— IOC CLKIN

SCK

SDI

(1)

Interrupt

IOC MCLR

IOC CLKOUT

— ICSPDAT

INT ICSPCLK

— —

— CLKR

VPP

OSC2

CLKR

OSC1

Basic

(3)

(1)

(2)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 7

PIC16(L)F145X

TABLE 2: 14-PIN ALLOCATION TABLE (PIC16(L)F1455)

I/O

14-Pin PDIP/SOIC/TSSOP

RA0 13 12 — — — — — D+ — — — IOC ICSPDAT

RA1 12 11 — — — — — D- — — — IOC ICSPCLK

RA2 — — — — — — — — — — — — —

RA3 4 3 — — — T1G

RA4 3 2 AN3 — — SOSCO

RA5 2 1 — — — SOSCI

RC0 10 9 AN4 VREF+ C1IN+

RC1 9 8 AN5 — C1IN1-

RC2 8 7 AN6 DACOUT1 C1IN2-

RC3 7 6 AN7 DACOUT2 C1IN3-

RC4 6 5 — — C1OUT

RC5 5 4 — — — T0CKI CWG1A — RXDTPWM1 — — —

VDD 1 16 — — — — — — — — — — VDD

VSS 14 13 — — — — — — — — — — VSS

VUSB3V3 11 10 — — — — — VUSB3V3 — — — — —

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

ADC

16-Pin QFN

Reference

Comparator

C2IN+

C2IN1-

C2IN2-

C2IN3-

C2OUT

Timer

(2)

(1)

T1G

T1CKI

— — — — — SCL

— CWGFLT — — — SDA

— — — — — SDO

— — — — PWM2

— CWG1B — TK

CWG

— — — — SS

— — — — SDO

— — — PWM2

USB

EUSART

PWM

(2)

(1)

— — — —

MSSP

(2)

— IOC CLKIN

SCK

SDI

(1)

Interrupt

IOC MCLR

IOC CLKOUT

— ICSPDAT

INT ICSPCLK

— —

— CLKR

VPP

OSC2

CLKR

OSC1

Basic

(3)

(1)

(2)

DS41639A-page 8 Preliminary  2012 Microchip Technology Inc.

TABLE 3: 20-PIN ALLOCATION TABLE (PIC16(L)F1459)

PIC16(L)F145X

I/O

20-Pin PDIP/SOIC/SSOP

RA0 19 16 — — — — — D+ — — — IOC ICSPDAT

RA1 18 15 — — — — — D- — — — IOC ICSPCLK

RA2 — — — — — — — — — — — — —

RA3 4 1 — — — T1G

RA4 3 20 AN3 — — SOSCO

RA5 2 19 — — — SOSCI

RB4 13 10 AN10 — — — — — — — SDA

RB5 12 9 AN11 — — — — — RX

RB6 11 8 — — — — — — — — SCL

RB7 10 7 — — — — — — TX

RC0 16 13 AN4 VREF+ C1IN+

RC1 15 12 AN5 — C1IN1-

RC2 14 11 AN6 DACOUT1 C1IN2-

RC3 7 4 AN7 DACOUT2 C1IN3-

RC4 6 3 — — C1OUT

RC5 5 2 — — — T0CKI CWG1A

RC6 8 5 AN8 — — — — — — PWM2 SS

RC7 9 6 AN9 — — — — — — — SDO — —

VDD 1 18 — — — — — — — — — — VDD

VSS 20 17 — — — — — — — — — — VSS

VUSB3V3 17 14 — — — — — VUSB3V3 — — — — —

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

ADC

20-Pin QFN

Reference

Comparator

C2IN+

C2IN1-

C2IN2-

C2IN3-

C2OUT

Timer

(2)

(1)

T1G

T1CKI

— — — — — — — ICSPDAT

— CWGFLT — — — — INT ICSPCLK

— — — — — — — —

— ——— — — — CLKR

— CWG1B — — — — — —

CWG

— — — — SS

— — — — — IOC OSC2

— — — — — IOC OSC1

USB

EUSART

— PWM1 — — —

—

PWM

— — IOC —

MSSP

(2)

SDI

SCK

(1)

Interrupt

IOC MCLR

VPP

CLKOUT

CLKR

CLKIN

IOC —

— —

Basic

(3)

(1)

(2)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 9

PIC16(L)F145X

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 21

3.0 Memory Organization ................................................................................................................................................................. 23

4.0 Device Configuration.................................................................................................................................................................. 51

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 57

6.0 Resets ........................................................................................................................................................................................ 79

7.0 Reference Clock Module ............................................................................................................................................................ 87

8.0 Interrupts .................................................................................................................................................................................... 91

9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 103

10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 107

11.0 Flash Program Memory Control ............................................................................................................................................... 112

12.0 I/O Ports ................................................................................................................................................................................... 129

13.0 Interrupt-On-Change ................................................................................................................................................................ 143

14.0 Fixed Voltage Reference (FVR) (PIC16(L)F1455/9 only)......................................................................................................... 149

15.0 Temperature Indicator Module (PIC16(L)F1455/9 only)........................................................................................................... 151

16.0 Analog-to-Digital Converter (ADC) Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 153

17.0 Digital-to-Analog Converter (DAC) Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 169

18.0 Comparator Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 173

19.0 Timer0 Module ......................................................................................................................................................................... 183

20.0 Timer1 Module with Gate Control............................................................................................................................................. 187

21.0 Timer2 Module ......................................................................................................................................................................... 199

22.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 203

23.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 257

24.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 287

25.0 Complementary Waveform Generator (CWG) Module (PIC16(L)F1455/9 only)293

26.0 Universal Serial Bus (USB) ...................................................................................................................................................... 309

27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 337

28.0 Instruction Set Summary .......................................................................................................................................................... 339

29.0 Electrical Specifications............................................................................................................................................................ 353

30.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 383

31.0 Development Support............................................................................................................................................................... 385

32.0 Packaging Information.............................................................................................................................................................. 389

Appendix A: Data Sheet Revision History .......................................................................................................................................... 407

Index .................................................................................................................................................................................................. 409

The Microchip Web Site..................................................................................................................................................................... 415

Customer Change Notification Service .............................................................................................................................................. 415

Customer Support .............................................................................................................................................................................. 415

Reader Response .............................................................................................................................................................................. 416

Product Identification System............................................................................................................................................................. 417

DS41639A-page 10 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F145X

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2012 Microchip Technology Inc. Preliminary DS41639A-page 11

PIC16(L)F145X

NOTES:

DS41639A-page 12 Preliminary  2012 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16(L)F1454/5/9 are described within this data sheet. They are available in 14/20-pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1454/5/9 devices. Tables 1-2, 1-3 and 1-4 show the pinout descriptions.

Reference Ta bl e 1 -1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral

PIC16(L)F1454/5/9

PIC16F1454

PIC16LF1454

Analog-to-Digital Converter (ADC) ●● Clock Reference ●●● Complementary Wave Generator (CWG) ●● Digital-to-Analog Converter (DAC) ●● Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter

(EUSART) Fixed Voltage Reference (FVR) ●● Temperature Indicator ●● Universal Serial Bus (USB) ●●● Comparators

C1 ●● C2 ●●

Master Synchronous Serial Ports

MSSP1 ●●●

PWM Modules

PWM1 ●●● PWM2 ●●●

Timers

Timer0 ●●● Timer1 ●●● Timer2 ●●●

●●●

PIC16F1455

PIC16LF1455

PIC16F1459

PIC16LF1459

 2012 Microchip Technology Inc. Preliminary DS41639A-page 13

PIC16(L)F1454/5/9

PORTC

Note 1: PIC16(L)F1455/9 only.

2: PIC16(L)F1459 only.

CPU

Program

Flash Memory

RAM

Timi ng

Generation

INTRC

Oscillator

MCLR

(Figure 2-1)

Timer2Timer1Timer0

PWM1 PWM2

PORTA

CWG1

(1)

ADC

10-Bit

(1)

FVR

(1)

Te mp .

Indicator

(1)

OSC1/CLKIN

OSC2/CLKOUT

MSSP1

(1)

DAC

(1)

PORTB

(2)

EUSART

CLKRUSB

FIGURE 1-1: PIC16(L)F1454/5/9 BLOCK DIAGRAM

DS41639A-page 14 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION

Input

Name Function

RA0/D+/ICSPDAT

(3)

RA0 TTL CMOS General purpose I/O.

D+ XTAL XTAL USB differential plus line.

ICSPDAT ST CMOS ICSP™ Data I/O.

RA1/D-/ICSPCLK

(3)

RA1 TTL CMOS General purpose I/O.

D- XTAL XTAL USB differential minus line.

ICSPCLK ST — ICSP Programming Clock.

(2)

RA3/V

PP/T1G

(2)

/SS

/MCLR RA3 TTL — General purpose input with IOC and WPU.

PP HV — Programming voltage.

T1G ST — Timer1 Gate input.

MCLR

RA4/SOSCO/CLKOUT/

(1)

T1G

/SDO

(2)

/CLKR

(1)

/OSC2

RA4 TTL CMOS General purpose I/O.

SOSCO XTAL XTAL Secondary Oscillator Connection.

CLKOUT — CMOS F

T1G ST — Timer1 Gate input.

SDO — CMOS SPI data output.

CLKR — CMOS Clock reference output.

OSC2 XTAL XTAL Primary Oscillator connection.

RA5/CLKIN/SOSCI/T1CKI/

(2)

PWM2

/OSC1

RA5 TTL CMOS General purpose I/O.

CLKIN CMOS — External clock input (EC mode).

SOSCI XTAL XTAL Secondary Oscillator Connection.

T1CKI ST — Timer1 clock input.

PWM2 — CMOS PWM output.

OSC1 XTAL XTAL Primary Oscillator Connection.

RC0/SCL/SCK/ICSPDAT RC0 TTL CMOS General purpose I/O.

SCL I

SCK ST CMOS SPI clock.

ICSPDAT ST CMOS ICSP™ Data I/O.

RC1/SDA/SDI/INT/ICSPCLK RC1 TTL CMOS General purpose I/O.

SDA I

SDI CMOS — SPI data input.

INT ST — External input.

ICSPCLK ST — ICSP Programming Clock.

RC2/SDO

(1)

RC2 TTL CMOS General purpose I/O.

SDO — CMOS SPI data output.

RC3/PWM2

/SS

(1)

/CLKR

(2)

RC3 TTL CMOS General purpose I/O.

(1)

PWM2 — CMOS PWM output.

CLKR — CMOS Clock reference output.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

Typ e

Output

Typ e

Description

ST — Slave Select input.

ST — Master Clear with internal pull-up.

OSC/4 output.

CODI2C™ clock.

CODI2C data input/output.

ST — Slave Select input.

C™ = Schmitt Trigger input with I2C

 2012 Microchip Technology Inc. Preliminary DS41639A-page 15

PIC16(L)F1454/5/9

TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RC4/TX/CK RC4 TTL CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC5/T0CKI/RX/DT/PWM1 RC5 TTL CMOS General purpose I/O.

T0CKI ST — Timer0 clock input.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

PWM1 — CMOS PWM output.

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

USB3V3 VUSB3V3 Power — Positive supply for USB transceiver.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

Typ e

Output

Typ e

Description

C™ = Schmitt Trigger input with I2C

DS41639A-page 16 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 1-3: PIC16(L)F1455 PINOUT DESCRIPTION

Input

Name Function

RA0/D+/ICSPDAT

(3)

RA0 TTL CMOS General purpose I/O.

D+ XTAL XTAL USB differential plus line.

ICSPDAT ST CMOS ICSP™ Data I/O.

RA1/D-/ICSPCLK

(3)

RA1 TTL CMOS General purpose I/O.

D- XTAL XTAL USB differential minus line.

ICSPCLK ST — ICSP Programming Clock.

(2)

RA3/V

PP/T1G

(2)

/SS

/MCLR RA3 TTL — General purpose input with IOC and WPU.

PP HV — Programming voltage.

T1G ST — Timer1 Gate input.

MCLR

RA4/AN3/SOSCO/CLKOUT/

(1)

T1G

/SDO

(2)

/CLKR

(1)

/OSC2

RA4 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

CLKOUT — CMOS F

T1G ST — Timer1 Gate input.

SDO — CMOS SPI data output.

CLKR — CMOS Clock reference output.

OSC2 XTAL XTAL Primary Oscillator connection.

RA5/CLKIN/SOSCI/T1CKI/

(2)

PWM2

/OSC1

RA5 TTL CMOS General purpose I/O.

CLKIN CMOS — External clock input (EC mode).

SOSCI XTAL XTAL Secondary Oscillator Connection.

T1CKI ST — Timer1 clock input.

PWM2 — CMOS PWM output.

OSC1 XTAL XTAL Primary Oscillator Connection.

RC0/AN4/V

REF+/C1IN+/C2IN+/

SCL/SCK/ICSPDAT

RC0 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel input.

REF+ AN — Positive Voltage Reference input.

C1IN+ AN — Comparator positive input.

C2IN+ AN — Comparator positive input.

SCL I

SCK ST CMOS SPI clock.

ICSPDAT ST CMOS ICSP™ Data I/O.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

Typ e

Output

Typ e

Description

ST — Slave Select input.

ST — Master Clear with internal pull-up.

OSC/4 output.

CODI2C™ clock.

C™ = Schmitt Trigger input with I2C

 2012 Microchip Technology Inc. Preliminary DS41639A-page 17

PIC16(L)F1454/5/9

TABLE 1-3: PIC16(L)F1455 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RC1/AN5/C1IN1-/ C2IN1-/CWGFLT SDI/INT/ICSPCLK

RC2/AN6/DACOUT1/ C1IN2-/C2IN2-/SDO

RC3/AN7/DACOUT2/ C1IN3-/C2IN3-/PWM2

(1)

/CLKR

RC4/C1OUT/C2OUT/ CWG1B/TX/CK

RC5/T0CKI/CWG1A/RX/DT/ PWM1

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

USB3V3 VUSB3V3 Power — Positive supply for USB transceiver.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

/SDA/

(1)

(2)

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

RC1 TTL CMOS General purpose I/O.

AN5 AN — A/D Channel input.

C1IN1- AN — Comparator negative input.

C2IN1- AN — Comparator negative input.

CWGFLT

SDA I

SDI CMOS — SPI data input.

INT ST — External input.

ICSPCLK ST — ICSP™ Programming Clock.

RC2 TTL CMOS General purpose I/O.

AN6 AN — A/D Channel input.

DACOUT1 — AN Digital-to-Analog Converter output.

C1IN2- AN — Comparator negative input.

C2IN2- AN — Comparator negative input.

SDO — CMOS SPI data output.

RC3 TTL CMOS General purpose I/O.

AN7 AN — A/D Channel input.

DACOUT2 — AN Digital-to-Analog Converter output.

C1IN3- AN — Comparator negative input.

C2IN3- AN — Comparator negative input.

PWM2 — CMOS PWM output.

CLC2IN0 ST — Configurable Logic Cell source input.

CLKR — CMOS Clock reference output.

RC4 TTL CMOS General purpose I/O.

C1OUT — CMOS Comparator output.

C2OUT — CMOS Comparator output.

CWG1B — CMOS CWG complementary output.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC5 TTL CMOS General purpose I/O.

T0CKI ST — Timer0 clock input.

CWG1A — CMOS CWG complementary output.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

PWM1 — CMOS PWM output.

Output

Typ e

ST — Complementary Waveform Generator Fault input.

CODI2C™ data input/output.

Description

C™ = Schmitt Trigger input with I2C

DS41639A-page 18 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 1-4: PIC16(L)F1459 PINOUT DESCRIPTION

Input

Name Function

RA0/D+/ICSPDAT

(3)

RA0 TTL CMOS General purpose I/O.

D+ XTAL XTAL USB differential plus line.

ICSPDAT ST CMOS ICSP™ Data I/O.

RA1/D-/ICSPCLK

(3)

RA1 TTL CMOS General purpose I/O.

D- XTAL XTAL USB differential minus line.

ICSPCLK ST — ICSP Programming Clock.

(2)

RA3/V

PP/T1G

(2)

/SS

/MCLR RA3 TTL — General purpose input with IOC and WPU.

PP HV — Programming voltage.

T1G ST — Timer1 Gate input.

MCLR

RA4/AN3/SOSCO/CLKOUT/ T1G

(1)

/CLKR

(1)

/OSC2

RA4 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

CLKOUT — CMOS F

T1G ST — Timer1 Gate input.

CLKR — CMOS Clock reference output.

OSC2 XTAL XTAL Primary Oscillator connection.

RA5/CLKIN/SOSCI/T1CKI/ OSC1

RA5 TTL CMOS General purpose I/O.

CLKIN CMOS — External clock input (EC mode).

SOSCI XTAL XTAL Secondary Oscillator Connection.

T1CKI ST — Timer1 clock input.

OSC1 XTAL XTAL Primary Oscillator Connection.

RB4/AN10/SDA/SDI RB4 TTL CMOS General purpose I/O.

AN10 AN — A/D Channel input.

SDA I

SDI CMOS — SPI data input.

RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O.

AN11 AN — A/D Channel input.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.

SCL I

SCK ST CMOS SPI clock.

RB7/TX/CK RB7 TTL CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

Typ e

Output

Typ e

Description

ST — Slave Select input.

ST — Master Clear with internal pull-up.

OSC/4 output.

CODI2C data input/output.

CODI2C™ clock.

C™ = Schmitt Trigger input with I2C

 2012 Microchip Technology Inc. Preliminary DS41639A-page 19

PIC16(L)F1454/5/9

TABLE 1-4: PIC16(L)F1459 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RC0/AN4/V ICSPDAT

RC1/AN5/C1IN1-/C2IN1-/ CWGFLT

RC2/AN6/DACOUT1/ C1IN2-/C2IN2-

RC3/AN7/DACOUT2/ C1IN3-/C2IN3-/CLKR

RC4/C1OUT/C2OUT/ CWG1B

RC5/T0CKI/CWG1A/PWM1 RC5 TTL CMOS General purpose I/O.

RC6/AN8/SS

RC7/AN9/SDO RC7 TTL CMOS General purpose I/O.

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

USB3V3 VUSB3V3 Power — Positive supply for USB transceiver.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

REF+/C1IN+/C2IN+/

/INT/ICSPCLK

(2)

(1)

/PWM2 RC6 TTL CMOS General purpose I/O.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: Alternate location for peripheral pin function selected by the APFCON register. 3: LVP support for PIC18(L)F1XK50 legacy designs.

RC0 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel input.

REF+ AN — Positive Voltage Reference input.

C1IN+ AN — Comparator positive input.

C2IN+ AN — Comparator positive input.

ICSPDAT ST CMOS ICSP™ Data I/O.

RC1 TTL CMOS General purpose I/O.

AN5 AN — A/D Channel input.

C1IN1- AN — Comparator negative input.

C2IN1- AN — Comparator negative input.

CWGFLT

INT ST — External input.

ICSPCLK ST — ICSP Programming Clock.

RC2 TTL CMOS General purpose I/O.

AN6 AN — A/D Channel input.

DACOUT1 — AN Digital-to-Analog Converter output.

C1IN2- AN — Comparator negative input.

C2IN2- AN — Comparator negative input.

RC3 TTL CMOS General purpose I/O.

AN7 AN — A/D Channel input.

DACOUT2 — AN Digital-to-Analog Converter output.

C1IN3- AN — Comparator negative input.

C2IN3- AN — Comparator negative input.

CLKR — CMOS Clock reference output.

RC4 TTL CMOS General purpose I/O.

C1OUT — CMOS Comparator output.

C2OUT — CMOS Comparator output.

CWG1B — CMOS CWG complementary output.

T0CKI ST — Timer0 clock input.

CWG1A — CMOS CWG complementary output.

PWM1 — CMOS PWM output.

AN8 AN — A/D Channel input.

PWM2 — CMOS PWM output.

AN9 AN — A/D Channel input.

SDO — CMOS SPI data output.

Output

Typ e

ST — Complementary Waveform Generator Fault input.

ST — Slave Select input.

Description

C™ = Schmitt Trigger input with I2C

DS41639A-page 20 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Instruction Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Internal

Oscillator

Block

Configuration

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction Decode &

Control

Timing

Generation

Internal

Oscillator

Block

Configuration

Data Bus

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

Internal

Oscillator

Block

Configuration

Flash

Program

Memory

RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

Power-up

Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VSSVDD VSSVDD VSS

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and

FIGURE 2-1: CORE BLOCK DIAGRAM

Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

 2012 Microchip Technology Inc. Preliminary DS41639A-page 21

PIC16(L)F1454/5/9

2.1 Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 “Automatic Context Saving”, for more information.

2.2 16-Level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See section Section 3.5 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See

Section 28.0 “Instruction Set Summary” for more

details.

DS41639A-page 22 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- Dual-Port General Purpose RAM

- General Purpose RAM

- Common RAM

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (See

Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device

PIC16F1454 PIC16LF1454

PIC16F1455 PIC16LF1455

PIC16F1459 PIC16LF1459

Note 1: High-endurance Flash applies to low byte of each address in the range.

Program Memory

Space (Words)

8,192 1FFFh 1F80h-1FFFh

Last Program Memory

Address

High-Endurance Flash

Memory Address Range

(1)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 23

PIC16(L)F1454/5/9

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh 1000h

7FFFh

Page 1

Rollover to Page 3

Page 2

Page 3

17FFh 1800h

1FFFh 2000h

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

constants

BRW ;Add Index in W to

;program counter to

;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1454/5/9

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.

DS41639A-page 24 Preliminary  2012 Microchip Technology Inc.

3.1.1.2 Indirect Read with FSR

constants

RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.

The High directive will set bit<7> if a label points to a location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

PIC16(L)F1454/5/9

 2012 Microchip Technology Inc. Preliminary DS41639A-page 25

PIC16(L)F1454/5/9

Addresses BANKx

x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR

x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• Up to 80 bytes of Dual-Port General Purpose RAM (DPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper 7-bits of the address define the Bank address and the lower 5-bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta b l e 3 -2 . For detailed information, see Tab le 3 -11 .

TABLE 3-2: CORE REGISTERS

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PIC16(L)F1454/5/9

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 28.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in subtraction.

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

PD ZDC

(1)

bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 27

PIC16(L)F1454/5/9

3.3.1 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

Refer to Table 3-3 for Dual Port and USB addressing information.

TABLE 3-3: DUAL PORT RAM ADDRESSING

Port 0 Port 1

3.3.3 DUAL-PORT RAM

Part of the data memory is mapped to a special dual access RAM. When the USB module is disabled, the GPRs in these banks are used like any other GPR in the data memory space.

When the USB module is enabled, the memory in these banks is allocated as buffer RAM for USB operation. This area is shared between the microcontroller core and the USB Serial Interface Engine (SIE) and is used to transfer data directly between the two.

It is theoretically possible to use the areas of USB RAM that are not allocated as USB buffers for normal scratchpad memory or other variable storage. In practice, the dynamic nature of buffer allocation makes this risky at best. Additional information on USB RAM and buffer operation is provided in Section 26.0 “Universal Serial

Bus (USB)”.

3.3.4 COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

CPU Banked Address CPU Linear Address USB Banked Address USB Linear Address

020 - 06F 2000 - 204F 020 - 06F 2000 - 204F 0A0 - 0EF 2050 - 209F 0A0 - 0EF 2050 - 209F 120 - 16F 20A0 - 20EF 120 - 16F 20A0 - 20EF 1A0 - 1EF 20F0 - 213F 1A0 - 1EF 20F0 - 213F 220 - 26F 2140 - 218F 220 - 26F 2140 - 218F 2A0 - 2EF 2190 - 21DF 2A0 - 2EF 2190 - 21DF 320 - 32F 21E0 - 21EF 320 - 32F 21E0 - 21EF 370 - 37F (1) 370 - 37F (1)

Note 1: Accessible from banked memory only.

DS41639A-page 28 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

0Bh 0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

Dual Port RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

(1)

General Purpose RAM

(80 bytes maximum)

Note 1: If the USB module is disabled, data

memory is GPR. If enabled, data memory can be DPR. Refer to Memory Map for RAM type details.

FIGURE 3-2: BANKED MEMORY

PARTITIONING

3.3.5 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1454/5/9 are as shown in Tab le 3 -8 and Table 3-9.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 29

DS41639A-page 30 Preliminary  2012 Microchip Technology Inc.

TABLE 3-4: PIC16(L)F1454 MEMORY MAP, BANK 0-7

PIC16(L)F1454/5/9

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3- 2 )

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch 00Dh 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh 00Fh 010h 011h PIR1 091h PIE1 111h 012h PIR2 092h PIE2 112h 013h 014h 015h TMR0 095h OPTION_REG 115h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h

06Fh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

— 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh —

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh— —090h—110h—190h—210h—290h

—093h—113h —094h—114h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h TMR1H 097h WDTCON 117h T1CON 098h OSCTUNE 118h

T1GCON 099h OSCCON 119h

TMR2 09Ah OSCSTAT 11Ah

PR2 09Bh

T2CON 09Ch

— 09Dh — —

Dual-Port

General

Purpose Register

80 Bytes

Dual-Port

Common RAM

080h

09Eh

09Fh

0A0h

0EFh

0F0h

Core Registers

(Ta bl e 3- 2 )

—11Bh—19Bh — 11Ch — 19Ch — — —

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

100h

Core Registers

(Table 3-2)

— — — — —

— 197h VREGCON 217h —198h—218h —199h —19Ah

11Dh APFCON 19Dh 11Eh 11Fh

120h

16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

170h

— —19Fh

Dual-Port

General Purpose Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

180h

Core Registers

(Table 3-2)

— 20Ch WPUA 28Ch — 30Ch — 38Ch —

—20Eh—28Eh—30Eh—38Eh—

191h PMADRL 211h 192h PMADRH 212h 193h PMDATL 213h 194h PMDATH 214h 195h PMCON1 215h

RCREG

TXREG SPBRG

SPBRGH

RCSTA

19Eh

1A0h

1F0h

TXSTA

BAUDCON

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

200h

219h —299h— 319h — 399h — 21Ah —29Ah—31Ah—39Ah 21Bh —29Bh—31Bh 21Ch — 29Ch — 31Ch 21Dh 21Eh 21Fh

220h

270h

Core Registers

(Table 3-2)

SSP1BUF SSP1ADD SSP1MSK

SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3

—

— — —

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

280h

Core Registers

(Table 3-2)

— 291h 292h 293h 294h 295h

296h 297h — 317h — 397h — 298h

29Dh 29Eh 29Fh

2A0h

2F0h

—

— 316h — 396h

— 318h — 398h —

—

Dual-Port

General Purpose Register

80 Bytes

Common RAM

(Accesses 70h – 7Fh)

300h

310h 311h 312h 313h 314h 315h

31Dh 31Eh 31Fh

320h

32Fh 330h

370h

Core Registers

(Table 3-2)

— 390h — — — — — —

— — — — —

Dual-Port

General Purpose Register 16Bytes

General Purpose Register

64 Bytes

Common RAM

(Accesses 70h – 7Fh)

380h

391h IOCAP 392h IOCAN 393h 394h 395h

39Bh CRCON 39Ch 39Dh 39Eh 39Fh

3A0h

3F0h

Core Registers

(Table 3-2)

IOCAF

CLKRCON

General Purpose Register

80 Bytes

Common RAM

(Accesses 70h – 7Fh)

— — —

— — — —

 2012 Microchip Technology Inc. Preliminary DS41639A-page 31

TABLE 3-5: PIC16(L)F1455 MEMORY MAP, BANK 0-7

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3- 2 )

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 00Dh 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 00Fh 010h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h 013h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h

06Fh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

— 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh —

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh— —090h—110h—190h—210h—290h

—093h— 113h CM2CON0 193h PMDATL 213h —094h— 114h CM2CON1 194h PMDATH 214h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h T1CON 098h OSCTUNE 118h

T1GCON 099h OSCCON 119h

TMR2 09Ah OSCSTAT 11Ah

PR2 09BhADRESL11Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON 19Dh — —

Dual-Port

General Purpose Register

80 Bytes

Dual-Port

Common RAM

080h

Core Registers

(Ta bl e 3- 2 )

09Eh ADCON1 11Eh

09Fh ADCON2 11Fh

0A0h

Dual-Port

General Purpose Register 80 Bytes

0EFh

0F0h

Common RAM

(Accesses 70h – 7Fh)

100h

120h

16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

170h

Core Registers

(Table 3-2)

DACCON0 DACCON1

—19Ah —19Bh — 19Ch

— —19Fh

Dual-Port

General Purpose Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

180h

198h 199h

19Eh

1A0h

1F0h

Core Registers

(Table 3-2)

—218h

RCREG

TXREG SPBRG

SPBRGH

RCSTA TXSTA

BAUDCON

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

200h

Core Registers

(Table 3-2)

—28Eh—30Eh—38Eh—

SSP1BUF SSP1ADD SSP1MSK

SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3

— 219h 21Ah —29Ah—31Ah—39Ah 21Bh —29Bh—31Bh 21Ch — 29Ch — 31Ch

21Dh 21Eh 21Fh

220h

270h

—299h— 319h — 399h —

—

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

280h

291h 292h 293h 294h 295h 296h 297h 298h

29Dh 29Eh 29Fh

2A0h

2F0h

Core Registers

(Table 3-2)

— 30Ch — 38Ch —

— — — — — — — 316h — 396h — 317h — 397h — — 318h — 398h —

— — —

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

300h

310h 311h 312h 313h 314h 315h

31Dh 31Eh 31Fh

320h

32Fh 330h

370h

Core Registers

(Table 3-2)

— 390h — — — — — —

— — — — —

Dual-Port

General Purpose Register

16Bytes

General Purpose Register 64 Bytes

Common RAM

(Accesses 70h – 7Fh)

380h

Core Registers

(Table 3-2)

391h IOCAP 392h IOCAN 393h 394h 395h

39Bh CRCON 39Ch 39Dh 39Eh 39Fh

3A0h

3F0h

IOCAF

— — —

CLKRCON

— — — —

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

PIC16(L)F1454/5/9

DS41639A-page 32 Preliminary  2012 Microchip Technology Inc.

TABLE 3-6: PIC16(L)F1459 MEMORY MAP, BANK 0-7

PIC16(L)F1454/5/9

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3- 2 )

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 00Fh 010h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h 013h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h

06Fh 0EFh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh— —090h—110h—190h—210h—290h

—093h— 113h CM2CON0 193h PMDATL 213h —094h— 114h CM2CON1 194h PMDATH 214h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h T1CON 098h OSCTUNE 118h

T1GCON 099h OSCCON 119h

TMR2 09Ah OSCSTAT 11Ah

PR2 09BhADRESL11Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON 19Dh — —

Dual-Port

General Purpose Register

80 Bytes

Dual-Port

Common RAM

080h

Core Registers

(Ta bl e 3- 2 )

09Eh ADCON1 11Eh

09Fh ADCON2 11Fh

0A0h

Dual-Port

General Purpose Register 80 Bytes

0F0h

Common RAM

(Accesses 70h – 7Fh)

100h

120h

16Fh 1EFh 26Fh 2EFh 36Fh

170h

Core Registers

(Table 3-2)

DACCON0 DACCON1

—19Ah —19Bh — 19Ch

— —19Fh

Dual-Port

General Purpose Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

180h

198h 199h

19Eh

1A0h

1F0h

Core Registers

(Table 3-2)

—218h

RCREG

TXREG SPBRG

SPBRGH

RCSTA TXSTA

BAUDCON

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

200h

Core Registers

(Table 3-2)

—28Eh—30Eh—38Eh—

SSP1BUF SSP1ADD SSP1MSK

SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3

— 219h 21Ah —29Ah—31Ah—39Ah 21Bh —29Bh—31Bh 21Ch — 29Ch — 31Ch

21Dh 21Eh 21Fh

220h

270h

—299h— 319h — 399h —

—

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

280h

291h 292h 293h 294h 295h 296h 297h 298h

29Dh 29Eh 29Fh

2A0h

2F0h

Core Registers

(Table 3-2)

— 30Ch — 38Ch — — 30Dh — 38Dh —

— — — — — — — 316h — 396h IOCBF — 317h — 397h — — 318h — 398h —

— — —

Dual-Port

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

300h

310h 311h 312h 313h 314h 315h

31Dh 31Eh 31Fh

320h

32Fh 330h

370h

Core Registers

(Table 3-2)

— 390h — — — — — —

— — — — —

Dual-Port

General Purpose Register

16Bytes

General Purpose Register 64 Bytes

Common RAM

(Accesses 70h – 7Fh)

380h

391h IOCAP 392h IOCAN 393h 394h IOCBP 395h IOCBN

39Bh CRCON 39Ch 39Dh 39Eh 39Fh

3A0h

3EFh

3F0h

Core Registers

(Table 3-2)

CLKRCON

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

IOCAF

— — — —

 2012 Microchip Technology Inc. Preliminary DS41639A-page 33

TABLE 3-7: PIC16(L)F1454 MEMORY MAP, BANK 8-23

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

Core Registers

(Ta bl e 3- 2 )

40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh

420h

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh— —48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh— —490h—510h—590h—610h—690h— 710h — 790h — —491h—511h—591h— 611h PWM1DCL 691h —711h— 791h — —492h—512h—592h— 612h PWM1DCH 692h — 712h — 792h — —493h—513h—593h— 613h PWM1CON 693h — 713h — 793h — —494h—514h—594h— 614h PWM2DCL 694h — 714h — 794h — —495h—515h—595h— 615h PWM2DCH 695h — 715h — 795h — —496h—516h—596h— 616h PWM2CON 696h — 716h — 796h — —497h—517h—597h—617h—697h— 717h — 797h — —498h—518h—598h—618h—698h— 718h — 798h — —499h—519h—599h—619h—699h— 719h — 799h — —49Ah—51Ah—59Ah—61Ah—69Ah—71Ah—79Ah— —49Bh—51Bh—59Bh—61Bh—69Bh—71Bh—79Bh— — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch — — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh — —49Eh—51Eh—59Eh—61Eh—69Eh—71Eh—79Eh— —49Fh—51Fh—59Fh—61Fh—69Fh—71Fh—79Fh—

General Purpose Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

480h

48Bh

4A0h

4F0h

Core Registers

(Ta bl e 3- 2 )

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

500h

50Bh

520h

570h

Core Registers

(Table 3-2)

General Purpose Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

580h

58Bh

5A0h

5F0h

Core Registers

(Table 3-2)

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

600h

60Bh

620h

64Fh 650h

670h

Core Registers

(Table 3-2)

General Purpose Register 48 Bytes

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

680h

68Bh

6A0h

6F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

700h

70Bh

720h

770h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

780h

78Bh

7A0h

7F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

PIC16(L)F1454/5/9

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

Core Registers

(Ta bl e 3- 2 ) 80Bh 80Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh 870h

Common RAM

(Accesses

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

70h – 7Fh)

880h

88Bh 88Ch

8F0h

Core Registers

(Ta bl e 3- 2 )

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

900h

90Bh 90Ch

970h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

980h

98Bh 98Ch

9EFh 9F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

A00h

A0Bh A0Ch

A6Fh A70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

A80h

A8Bh

A8Ch

AEFh AF0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

B00h

B0Bh B0Ch

B6Fh B70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

B80h

B8Bh B8Ch

BEFh BF0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

DS41639A-page 34 Preliminary  2012 Microchip Technology Inc.

TABLE 3-8: PIC16(L)F1455/9 MEMORY MAP, BANK 8-23

PIC16(L)F1454/5/9

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

Core Registers

(Ta bl e 3- 2 )

40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh

420h

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh— —48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh— —490h—510h—590h—610h—690h— 710h — 790h — —491h—511h—591h— 611h PWM1DCL 691h CWG1DBR 711h — 791h — —492h—512h—592h— 612h PWM1DCH 692h CWG1DBF 712h — 792h — —493h—513h—593h— 613h PWM1CON 693h CWG1CON0 713h — 793h — —494h—514h—594h— 614h PWM2DCL 694h CWG1CON1 714h — 794h — —495h—515h—595h— 615h PWM2DCH 695h CWG1CON2 715h — 795h — —496h—516h—596h— 616h PWM2CON 696h — 716h — 796h — —497h—517h—597h—617h—697h— 717h — 797h — —498h—518h—598h—618h—698h— 718h — 798h — —499h—519h—599h—619h—699h— 719h — 799h — —49Ah—51Ah—59Ah—61Ah—69Ah—71Ah—79Ah— —49Bh—51Bh—59Bh—61Bh—69Bh—71Bh—79Bh— — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch — — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh — —49Eh—51Eh—59Eh—61Eh—69Eh—71Eh—79Eh— —49Fh—51Fh—59Fh—61Fh—69Fh—71Fh—79Fh—

General Purpose Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

480h

48Bh

4A0h

4F0h

Core Registers

(Ta bl e 3- 2 )

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

500h

50Bh

520h

570h

Core Registers

(Table 3-2)

General Purpose Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

580h

58Bh

5A0h

5F0h

Core Registers

(Table 3-2)

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

600h

60Bh

620h

64Fh 650h

670h

Core Registers

(Table 3-2)

General Purpose Register 48 Bytes

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

680h

68Bh

6A0h

6F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

700h

70Bh

720h

770h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

780h

78Bh

7A0h

7F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

Core Registers

(Ta bl e 3- 2 ) 80Bh 80Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh 870h

Common RAM

(Accesses

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

70h – 7Fh)

880h

88Bh 88Ch

8F0h

Core Registers

(Ta bl e 3- 2 )

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

900h

90Bh 90Ch

970h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

980h

98Bh 98Ch

9EFh 9F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

A00h

A0Bh A0Ch

A6Fh A70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

A80h

A8Bh A8Ch

AEFh AF0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

B00h

B0Bh B0Ch

B6Fh B70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

B80h

B8Bh B8Ch

BEFh BF0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 35

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3- 2 )

C80h

C8Bh

Core Registers

(Ta bl e 3- 2 )

D00h

D0Bh

Core Registers

(Ta bl e 3- 2 )

D80h

D8Bh

Core Registers

(Ta bl e 3- 2 )

E00h

E0Bh

Core Registers

(Ta bl e 3- 2 )

E80h

E8Bh

Core Registers

(Ta bl e 3- 2 )

F00h

F0Bh

Core Registers

(Ta bl e 3- 2 )

F80h

F8Bh

Core Registers

(Ta bl e 3- 2 )

C0Ch

—C8Ch—D0Ch—D8Ch—E0Ch—E8Ch—F0Ch—F8Ch

See Ta bl e 3- 1 0

for register map-

ping details

C0Dh

—C8Dh—D0Dh—D8Dh—E0Dh—E8Dh—F0Dh—F8Dh

C0Eh

—C8Eh—D0Eh—D8Eh—E0Eh— E8Eh UCON F0Eh —F8Eh

C0Fh

—C8Fh—D0Fh—D8Fh—E0Fh—E8FhUSTATF0Fh—F8Fh

C10h

—C90h—D10h—D90h—E10h— E90h UIR F10h —F90h

C11h

—C91h—D11h—D91h—E11h— E91h UCFG F11h —F91h

C12h

—C92h—D12h—D92h—E12h— E92h UIE F12h —F92h

C13h

—C93h—D13h—D93h—E13h—E93hUEIRF13h—F93h

C14h

—C94h—D14h—D94h—E14h— E94h UFRMH F14h —F94h

C15h

—C95h—D15h—D95h—E15h— E95h UFRML F15h —F95h

C16h

—C96h—D16h—D96h—E16h— E96h UADDR F16h —F96h

C17h

—C97h—D17h—D97h—E17h—E97hUEIEF17h—F97h

C18h

—C98h—D18h—D98h—E18h— E98h UEP0 F18h —F98h

C19h

—C99h—D19h—D99h—E19h— E99h UEP1 F19h —F99h

C1Ah

—C9Ah—D1Ah—D9Ah—E1Ah— E9Ah UEP2 F1Ah —F9Ah

C1Bh

—C9Bh—D1Bh—D9Bh—E1Bh— E9Bh UEP3 F1Bh —F9Bh

C1Ch

—C9Ch—D1Ch—D9Ch—E1Ch— E9Ch UEP4 F1Ch —F9Ch

C1Dh

—C9Dh—D1Dh—D9Dh—E1Dh— E9Dh UEP5 F1Dh —F9Dh

C1Eh

—C9Eh—D1Eh—D9Eh—E1Eh— E9Eh UEP6 F1Eh —F9Eh

C1Fh

—C9Fh—D1Fh—D9Fh—E1Fh— E9Fh UEP7 F1Fh —F9Fh

C20h

Unimplemented

Read as ‘0’

CA0h

Unimplemented

Read as ‘0’

D20h

Unimplemented

Read as ‘0’

DA0h

Unimplemented

Read as ‘0’

E20h

Unimplemented

Read as ‘0’

EA0h

Unimplemented

Read as ‘0’

F20h

Unimplemented

Read as ‘0’

FA0h

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh C70h

Common RAM

(Accesses

70h – 7Fh)

CF0h

Common RAM

(Accesses 70h – 7Fh)

D70h

Common RAM

(Accesses

70h – 7Fh)

DF0h

Common RAM

(Accesses 70h – 7Fh)

E70h

Common RAM

(Accesses

70h – 7Fh)

EF0h

Common RAM

(Accesses 70h – 7Fh)

F70h

Common RAM

(Accesses 70h – 7Fh)

FF0h

Common RAM

(Accesses 70h – 7Fh)

CFFh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-9: PIC16(L)F1454/5/9 MEMORY MAP, BANK 24-31

PIC16(L)F1454/5/9

Bank 31

F8Ch

FE3h

Unimplemented

Read as ‘0’

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

Legend: = Unimplemented data memory locations,

read as ‘0’.

TABLE 3-10: PIC16(L)F1454/5/9 MEMORY

MAP, BANK 30-31

DS41639A-page 36 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

3.3.6 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Tab l e 3- 11 can be addressed from any Bank.

TABLE 3-11: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — —BSR<4:0>---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

Value on all

other Resets

 2012 Microchip Technology Inc. Preliminary DS41639A-page 37

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY

Addres

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 0

00Ch PORTA — — RA5 RA4 RA3 —RA1RA0--xx x-xx --xx x-xx

00Dh PORTB

00Eh PORTC RC7

00Fh

010h

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF

012h PIR2 OSFIF C2IF C1IF

013h

014h

(1)

RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx ----

(1)

RC6

(1)

RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx

— Unimplemented — —

— TMR2IF TMR1IF 0000 0-00 0000 0-00

— BCL1IF USBIF ACTIF — 000- 000- 000- 000-

— Unimplemented — —

015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu

018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

—TMR1ON0000 00-0 uuuu uu-u

01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000

01Bh PR2 Timer2 Period Register 1111 1111 1111 1111

01Ch T2CON

01Dh

01Eh

01Fh

— Unimplemented — —

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

Bank 1

08Ch TRISA — — TRISA5 TRISA4 —

08Dh TRISB

08Eh TRISC TRISC7

08Fh

090h

(1)

TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----

(1)

TRISC6

(1)

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

— Unimplemented — —

(2)

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE

092h PIE2 OSFIE C2IE C1IE

093h

094h

095h

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

— Unimplemented — —

OPTION_REG

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111

—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu

— — WDTPS<4:0> SWDTEN --01 0110 --01 0110

— TUN<6:0> -000 0000 -uuu uuuu

—BCL1IEUSBIEACTIE — 000- 000- 000- 000-

— —

— TMR2IE TMR1IE 0000 0-00 0000 0-00

(2)

—

--11 ---- --11 ----

099h OSCCON SPLLEN SPLLMULT IRCF<3:0> SCS<1:0> 0011 1100 0011 1100

09Ah OSCSTAT SOSCR PLLRDY OSTS HFIOFR

09Bh ADRESL

09Ch ADRESH

09Dh ADCON0

09Eh ADCON1

09Fh ADCON2

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1459 only.

(2)

A/D Result Register Low xxxx xxxx uuuu uuuu

(2)

A/D Result Register High xxxx xxxx uuuu uuuu

(2)

— CHS<4:0>

ADFM ADCS<2:0> — —

— TRIGSEL<2:0> — — — — -000 ---- -000 ----

— — LFIOFR HFIOFS 00q0 --00 qqqq --qq

GO/DONE

ADPREF<1:0>

ADON -000 0000 -000 0000

0000 --00 0000 --00

2: PIC16(L)F1455/9 only. 3: Unimplemented, read as ‘1’.

Value on all

other

Resets

DS41639A-page 38 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addres

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 2

10Ch LATA — —LATA5LATA4— — — — --xx ---- --uu ----

10Dh LATB

10Eh LATC LATC7

10Fh

110h

111h CM1CON0

112h CM1CON1

113h CM2CON0

114h CM2CON1

115h CMOUT

116h BORCON SBOREN BORFS

117h FVRCON

118h DACCON0

119h DACCON1

(1)

LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ----

(1)

LATC6

(1)

LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu

— Unimplemented — —

(2)

C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100

(2)

C1INTP C1INTN C1PCH<1:0> — C1NCH<2:0> 0000 -000 0000 -000

(2)

C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100

(2)

C2INTP C2INTN C2PCH<1:0> — C2NCH<2:0> 0000 -000 0000 -000

(2)

— — — — — —MC2OUT MC1OUT---- --00 ---- --00

— — — — — BORRDY 10-- ---q uu-- ---u

(2)

FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

(2)

DACEN — DACOE1 DACOE2 DACPSS<1:0> — — 0-00 00-- 0-00 00--

(2)

— — — DACR<4:0> ---0 0000 ---0 0000

11Ah

— Unimplemented — —

11C h

11Dh APFCON CLKRSEL SDOSEL

11Eh

11Fh

— Unimplemented — —

(1)

SSSEL

—

T1GSEL P2SEL

(1)

— —

000- --00 000- --00

Bank 3

18Ch ANSELA

18Dh ANSELB

18Eh ANSELC

18Fh

190h

(2)

(1)

(2)

— — — ANSA4 — — — — ---1 ---- ---1 ----

— — ANSB5 ANSB4 — — — — --11 ---- --11 ----

ANSC7

(1)

ANSC6

(1)

— — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111

— Unimplemented — —

191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000

192h PMADRH

(2)

—

Flash Program Memory Address Register High Byte 1000 0000 1000 0000

193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h PMDATH

195h PMCON1

— — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

(2)

—

CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000

196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000

197h VREGCON

198h

— Unimplemented — —

(1)

——————VREGPMReserved ---- --01 ---- --01

199h RCREG USART Receive Data Register 0000 0000 0000 0000

19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000

19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000

19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1459 only.

— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

2: PIC16(L)F1455/9 only. 3: Unimplemented, read as ‘1’.

Value on all

other

Resets

 2012 Microchip Technology Inc. Preliminary DS41639A-page 39

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addres

Bank 4

20Ch WPUA — — WPUA5 WPUA4 WPUA3 — — — --11 1--- --11 1---

20Dh WPUB

20Eh

210h

211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

212h SSP1ADD ADD<7:0> 0000 0000 0000 0000

213h SSP1MSK MSK<7:0> 1111 1111 1111 1111

214h SSP1STAT SMP CKE D/A

215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

21Fh

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(1)

— Unimplemented — —

WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----

PSR/WUA BF 0000 0000 0000 0000

Value on

POR, BOR

Bank 5

28Ch

— Unimplemented — —

29Fh

Bank 6

30Ch

— Unimplemented — —

31Fh

Bank 7

38Ch

— Unimplemented — —

390h

391h IOCAP

392h IOCAN

393h IOCAF

394h IOCBP

395h IOCBN

396h IOCBF

397h

399h

39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000

39Bh ACTCON ACTEN ACTUD

39Ch

39Fh

(1)

— Unimplemented — —

— — IOCAP5 IOCAP4 IOCAP3 —

— — IOCAN5 IOCAN4 IOCAN3 —

— — IOCAF5 IOCAF4 IOCAF3 —

IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ----

IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ----

IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ----

— ACTSRC ACTLOCK —ACTORS — 00-0 0-0- 00-0 0-0-

IOCAP1 IOCAP0

IOCAN1 IOCAN0

IOCAF1 IOCAF0

--00 0-00 --00 0-00

Bank 8

40Ch

— Unimplemented — —

41Fh

Bank 9

48Ch

— Unimplemented — —

49Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only. 3: Unimplemented, read as ‘1’.

Value on all

other

Resets

DS41639A-page 40 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addres

Bank 10

50Ch

51Fh

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— Unimplemented — —

Value on

POR, BOR

Bank 11

58Ch

— Unimplemented — —

59Fh

Bank 12

60Ch

— Unimplemented — —

610h

611h PWM1DCL PWM1DCL<7:6>

612h PWM1DCH PWM1DCH<7:0> xxxx xxxx uuuu uuuu

613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL

614h PWM2DCL PWM2DCL<7:6>

615h PWM2DCH PWM2DCH<7:0> xxxx xxxx uuuu uuuu

616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL

617h

— Unimplemented — —

61Fh

— — — — — — 00-- ---- 00-- ----

— — — — 0000 ---- 0000 ----

— — — — — — 00-- ---- 00-- ----

— — — — 0000 ---- 0000 ----

Bank 13

68Ch

— Unimplemented — —

690h

691h CWG1DBR

692h CWG1DBF

693h CWG1CON0

694h CWG1CON1

695h CWG1CON2

696h

— Unimplemented — —

69Fh

(2)

— —CWG1DBR<5:0>--00 0000 --00 0000

— —CWG1DBF<5:0>--xx xxxx --xx xxxx

(2)

G1EN G1OEB G1OEA G1POLB G1POLA — —G1CS00000 0--0 0000 0--0

(2)

G1ASDLB<1:0> G1ASDLA<1:0> — — G1IS<1:0> 0000 --00 0000 --00

(2)

G1ASE G1ARSEN — — G1ASDC2 G1ASDC1 G1ASDSFLT — 00-- 0001 00-- 000-

Banks 14-28

x0Ch/ x8Ch — x1Fh/ x9Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1459 only.

— Unimplemented — —

2: PIC16(L)F1455/9 only. 3: Unimplemented, read as ‘1’.

Value on all

other

Resets

 2012 Microchip Technology Inc. Preliminary DS41639A-page 41

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addres

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 29

E8Ch — Unimplemented — —

E8Dh

E8Eh

E8Fh

E90h

E91h

E92h

E93h

E94h

E95h

E96h

E97h

E98h

E99h

E9Ah

E9Bh

E9Ch

E9Dh

E9Eh

E9Fh

— Unimplemented — —

UCON

USTAT

UIR

UCFG UTEYE

UIE

UEIR BTSEF

UFRMH

UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0

UADDR

UEIE BTSEE

UEP7

UEP6

UEP5

UEP4

UEP3

UEP2

UEP1

UEP0

—

PPBRST SE0 PKTDIS USBEN RESUME SUSPND

—

— — — — —

—

– – –

SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF

Reserved

SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE

— —

ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

— —

ENDP<3:0> DIR PPBI

—

UPUEN

BTOEF DFN8EF CRC16EF CRC5EF PIDEF

BTOEE DFN8EE CRC16EE CRC5EE PIDEE

EPHSHK

Reserved FSEN PPB<1:0>

FRM10 FRM9 FRM8

EPCONDIS

EPOUTEN EPINEN EPSTALL

— -0x0 000- -0u0 000-

— -xxx xxx- -uuu uuu-

-000 0000 -000 0000

00-0 -000 00-0 -000

-000 0000 -000 0000

0--0 -000 0--0 -000

---- -xxx ---- -uuu

xxxx xxxx uuuu uuuu

-000 0000 -000 0000

0--0 0000 0--0 0000

---0 0000 ---0 0000

Bank 30

F0Ch — F1Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1459 only.

— Unimplemented — —

2: PIC16(L)F1455/9 only. 3: Unimplemented, read as ‘1’.

Value on all

other

Resets

DS41639A-page 42 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addres

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 31

F8Ch — FE3h

FE4h STATUS_

FE5h WREG_

FE6h BSR_

FE7h PCLATH_

FE8h FSR0L_

FE9h FSR0H_

FEAh FSR1L_

FEBh FSR1H_

FECh

FEDh

FEEh

FEFh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1459 only.

— Unimplemented — —

— — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu

SHAD

Working Register Shadow xxxx xxxx uuuu uuuu

SHAD

— — — Bank Select Register Shadow ---x xxxx ---u uuuu

SHAD

— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

— Unimplemented — —

STKPTR

TOSL

TOSH

2: PIC16(L)F1455/9 only. 3: Unimplemented, read as ‘1’.

— — — Current Stack Pointer ---1 1111 ---1 1111

Top-of-Stack Low byte xxxx xxxx uuuu uuuu

— Top-of-Stack High byte -xxx xxxx -uuu uuuu

Value on all

other

Resets

 2012 Microchip Technology Inc. Preliminary DS41639A-page 43

PIC16(L)F1454/5/9

PCL

PCH

PCL

PCH

ALU Result

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

OPCODE <10:0>

PCLATH

PCL

PCH

PCLATH

CALLW

PCL

PCH

PC + W

BRW

PCLPCH

PC + OPCODE <8:0>

BRA

3.4 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC.

FIGURE 3-3: LOADING OF PC IN

DIFFERENT SITUATIONS

3.4.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

3.4.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).

3.4.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.

3.4.4 BRANCHING

The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction.

DS41639A-page 44 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled (STVREN = 0)

Stack Reset Enabled (STVREN = 1)

TOSH:TOSL

3.5 Stack

All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-4 through 3-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘(Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the

CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to

an interrupt address.

3.5.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR.

Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack.

FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1

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PIC16(L)F1454/5/9

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00

STKPTR = 0x00

This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack.

TOSH:TOSL

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3

DS41639A-page 46 Preliminary  2012 Microchip Technology Inc.

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten.

Return Address

TOSH:TOSL

PIC16(L)F1454/5/9

3.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register.

3.6 Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

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PIC16(L)F1454/5/9

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000

Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

FIGURE 3-8: INDIRECT ADDRESSING

DS41639A-page 48 Preliminary  2012 Microchip Technology Inc.

3.6.1 TRADITIONAL DATA MEMORY

Indirect AddressingDirect Addressing

Bank Select

Location Select

4BSR 6

From Opcode

FSRxL70

Bank Select

Location Select

00000 00001 00010 11111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

FSRxH70

0000

The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR, DPR and common registers.

FIGURE 3-9: TRADITIONAL DATA MEMORY MAP

PIC16(L)F1454/5/9

 2012 Microchip Technology Inc. Preliminary DS41639A-page 49

PIC16(L)F1454/5/9

Location Select

0x2000

FSRnH

FSRnL

0x020

Bank 0

0x06F 0x0A0

Bank 1 0x0EF 0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

Location Select

0x8000

FSRnH

FSRnL

0x0000

0x7FFF

0xFFFF

Program Flash Memory (low 8 bits)

3.6.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of DPR or GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the DPR or GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

FIGURE 3-10: LINEAR DATA MEMORY

MAP

3.6.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete.

FIGURE 3-11: PROGRAM FLASH

MEMORY MAP

DS41639A-page 50 Preliminary  2012 Microchip Technology Inc.

4.0 DEVICE CONFIGURATION

Device configuration consists of Configuration Words, Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Words is

managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.

PIC16(L)F1454/5/9

 2012 Microchip Technology Inc. Preliminary DS41639A-page 51

PIC16(L)F1454/5/9

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1

FCMEN IESO CLKOUTEN BOREN<1:0>

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

bit 12 IESO: Internal External Switchover bit

bit 11 CLKOUTEN

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

bit 8 Unimplemented: Read as ‘1’ bit 7 CP

bit 6 MCLRE: MCLR

bit 5 PWRTE

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bits

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled

1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled

: Clock Out Enable bit

1 = CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin 0 = CLKOUT function is enabled on the CLKOUT pin

(1)

11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled

: Code Protection bit

1 = Program memory code protection is disabled 0 = Program memory code protection is enabled

/VPP Pin Function Select bit

If LVP bit =

This bit is ignored.

If LVP bit = 0:

1 =MCLR 0 =MCLR

1 = PWRT disabled 0 = PWRT enabled

11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled

/VPP pin function is MCLR; Weak pull-up enabled. /VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUA register.

: Power-Up Timer Enable bit

(2)

—

DS41639A-page 52 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECH: External clock, High-Power mode: on CLKIN pin 110 = ECM: External clock, Medium-Power mode: on CLKIN pin 101 = ECL: External clock, Low-Power mode: on CLKIN pin 100 = INTOSC oscillator: I/O function on OSC1 pin 011 = EXTRC oscillator: RC function connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator on OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator on OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal on OSC1 and OSC2 pins

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: Once enabled (CP

= 0), code-protect can only be disabled by bulk erasing the device.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 53

PIC16(L)F1454/5/9

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

(3)

LVP

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1

PLLMULT USBLSCLK CPUDIV<1:0>

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

DEBUG

LPBOR BORV STVREN PLLEN

— —WRT<1:0>

bit 13 LVP: Low-Voltage Programming Enable bit

1 = Low-voltage programming enabled 0 = High-voltage on MCLR

bit 12 DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11

bit 10 BORV: Brown-out Reset Voltage Selection bit

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

bit 8 PLLEN: PLL Enable bit

bit 7 PLLMULT: PLL Multiplier Selection bit

bit 6 USBLSCLK: USB Low-Speed Clock Selection bit

bit 5-4 CPUDIV<1:0>: CPU System Clock Selection bits

bit 3-2 Unimplemented: Read as ‘1’

bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

: Low-Power BOR Enable bit

LPBOR

1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled

1 = Brown-out Reset voltage (Vbor), low trip point selected 0 = Brown-out Reset voltage (

1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset

1 = PLL is enabled 0 = PLL is disabled

1 = 3x PLL Output Frequency is selected 0 = 4x PLL Output Frequency is selected

1 = USB Clock divide-by 8 (48 MHz system input clock expected) 0 = USB Clock divide-by 4 (24 MHz system input clock expected)

11 = CPU system clock divided by 6 10 = CPU system clock divided by 3 01 = CPU system clock divided by 2 00 = No CPU system clock divide

8 kW Flash memory

11 = Write protection off 10 = 000h to 01FFh write-protected, 0200h to 1FFFh may be modified 01 = 000h to 0FFFh write-protected, 1000h to 1FFFh may be modified 00 = 000h to 1FFFh write-protected, no addresses may be modified

must be used for programming

Vbor, high trip point selected

(1)

(3)

(2)

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: See Vbor parameter for specific trip point voltages. 3: The DEBUG

debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.

DS41639A-page 54 Preliminary  2012 Microchip Technology Inc.

bit in Configuration Words is managed automatically by device development tools including

4.3 Code Protection

Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting.

4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP Words. When CP program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write

Protection” for more information.

= 0, external reads and writes of

bit in Configuration

4.4 Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected.

PIC16(L)F1454/5/9

4.5 User ID

Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these

memory locations. calculation, see the “PIC16(L)F1454/5/9 Memory

Programming Specification” (DS41620).

For more information on checksum

 2012 Microchip Technology Inc. Preliminary DS41639A-page 55

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Device DEVICEID<13:0> Values

PIC16F1454 11 0000 0010 0000 (3020h)

PIC16LF1454 11 0000 0010 0100 (3024h)

PIC16F1455 11 0000 0010 0001 (3021h)

PIC16LF1455 11 0000 0010 0101 (3025h)

PIC16F1459 11 0000 0010 0011 (3023h)

PIC16LF1459 11 0000 0010 0111 (3027h)

4.6 Device ID and Revision ID

The memory location 8005h and 8006h are where the Device ID and Revision ID are stored. See

Section 11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.

4.7 Register Definitions: Revision and Device

REGISTER 4-3: DEVID: DEVICE ID REGISTER

RRRRRR

DEV<13:8>

bit 13 bit 8

RRRRRRRR

DEV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 DEV<13:0>: Device ID bits

REGISTER 4-4: REVID: REVISION ID REGISTER

RRRRRR

REV<13:8>

bit 13 bit 8

RRRRRRRR

REV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 REV<13:0>: Revision ID bits

DS41639A-page 56 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.0 OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

5.1 Overview

The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

• Fast start-up oscillator allows internal circuits to

power up and stabilize before switching to the 16 MHz HFINTOSC

• 3x/4x selectable Phase Lock Frequency Multiplier

allows operation at 24, 32 or 48 MHz.

• USB with configurable Full/Low speed operation.

The oscillator module can be configured in one of eight clock modes.

1. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode (0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode (4 MHz to 20 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 16 MHz).

Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered.

The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency.

The INTOSC internal oscillator block produces a low and high-frequency clock source, designated LFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these two clock sources.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 57

PIC16(L)F1454/5/9

Primary

Oscillator

(OSC)

Secondary

Oscillator

(SOSC)

Postscaler

16 MHz

8 MHz 4 MHz 2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

62.5 kHz

31.25 kHz 31 kHz

to WDT, PWRT

and other Modules

Clock

Control

SCS<1:0>

FOSC<2:0>

CLKIN/ OSC1/ SOSCI/ T1CKI

CLKOUT / OSC2

SOSCO/ T1G

Primary Clock

Secondary Clock

INTOSC

IRCF<3:0>

Start-up

Control Logic

16 MHz

Internal OSC

31 kHz Source

Start-Up

OSC

3x/4x PLL

FOSC<2:0>

LFINTOSC

HFINTOSC

SPLLEN

PLLEN

Active Clock

Tuning

SOSC_clk

Sleep

PLLMULT

INTOSC

(16 or 8 MHz)

LFINTOSC

SPLLMULT

FOSC to CPU and Peripherals

CPU

Divider

CPUDIV<1:0>

USBLSCLK

USB

Divider

USB

Clock

Source

FSEN

48 MHz

6 MHz

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS41639A-page 58 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

OSC1/CLKIN

OSC2/CLKOUT

Clock from Ext. System

PIC

MCU

FOSC/4 or

I/O

(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

5.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.

Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 MHz High-Frequency Internal Oscillator and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3

“CPU Clock Divider” for additional information.

5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to:

- Secondary oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “CPU Clock Divider”for more infor- mation.

5.2.1.1 EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode.

EC mode has three power modes to select from through Configuration Words:

• High power, 4-20 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low power, 0-0.5 MHz (FOSC = 101)

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC

MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

5.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 59

PIC16(L)F1454/5/9

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M

 to 10 M.

Quartz

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M

 to 10 M.

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

Ceramic

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

(3)

Resonator

OSC2/CLKOUT

FIGURE 5-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC Devices” (DS00826)

• AN849, “Basic PIC (DS00849)

• AN943, “Practical PIC Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

and PIC®

Oscillator Design”

Oscillator

FIGURE 5-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

5.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended unless either FSCM or Two-Speed Start-Up are enabled. In this case, code will continue to execute at the selected INTOSC frequency while the OST is counting . The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module.

In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.6

“Two-Speed Clock Start-up Mode”).

DS41639A-page 60 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

32.768 kHz

SOSCI

To Internal Logic

PIC® MCU

Crystal

SOSCO

Quartz

5.2.1.4 3x PLL or 4x PLL

The oscillator module contains a PLL that can be used with both external and internal clock sources to provide a system clock source. By setting the SPLLMULT bit of the OSCCON register, 3x PLL is selected. By clearing the SPLLMULT bit of the OSCCON register, 4x PLL is selected. The input frequency for the PLL must fall within specifications. See the PLL Clock Timing Specifications in

Section 29.0 “Electrical Specifications”.

The PLL may be enabled for use by one of two methods:

1. Program the PLLEN bit in Configuration Words to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored.

PLL

HFINTOSC

(MHz)

ECH/HS

(MHz)

System

Clock (MHz)

4x 8 8 - 12 32 - 48 3x 16, 8 8 - 16 24 - 48

5.2.1.5 Secondary Oscillator

The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.

The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3

“CPU Clock Divider” for more information.

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

and PIC®

Devices” (DS00826)

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for Low-Power External Oscillators”

(DS01288)

FIGURE 5-5: QUARTZ CRYSTAL

OPERATION (SECONDARY OSCILLATOR)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 61

PIC16(L)F1454/5/9

OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k

  REXT  100 k, 3-5V

EXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

I/O

(1)

5.2.1.6 External RC Mode

The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required.

The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

bit in Configuration Words.

Figure 5-6 shows the external RC mode connections.

FIGURE 5-6: EXTERNAL RC MODES

5.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 “CPU

Clock Divider”for more information.

In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

The internal oscillator block has two independent oscillators that provides the internal system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at 16 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3).

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at 31 kHz.

bit in Configuration Words.

The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due to tolerance of the external RC components used.

DS41639A-page 62 Preliminary  2012 Microchip Technology Inc.

5.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The frequency derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See

Section 5.2.2.4 “Internal Oscillator Frequency Selection” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’.

A fast start-up oscillator allows internal circuits to power-up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running.

The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.

PIC16(L)F1454/5/9

5.2.2.2 Internal Oscillator Frequency Adjustment

The 16 MHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since all HFINTOSC clock sources are derived from the 16 MHz internal oscillator a change in the OSCTUNE register value will apply to all HFINTOSC frequencies.

The default value of the OSCTUNE register is ‘0’. The value is a 7-bit two’s complement number. A value of 3Fh will provide an adjustment to the maximum frequency. A value of 40h will provide an adjustment to the minimum frequency.

When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.

5.2.2.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.4 “Internal Oscillator

Frequency Selection” for more information. The

LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled:

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.

5.2.2.4 Internal Oscillator Frequency Selection

The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software:

•HFINTOSC

- 48 MHz (requires 3x PLL)

- 32 MHz (requires 4x PLL)

- 24 MHz (requires 3x PLL)

-16 MHz

-8 MHz

-4 MHz

-2 MHz

-1 MHz

- 500 kHz (Default after Reset)

-250 kHz

-125 kHz

-62.5 kHz

-31.25 kHz

•LFINTOSC

-31 kHz

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 63

PIC16(L)F1454/5/9

5.2.2.5 Internal Oscillator Frequency Selection Using the PLL

The Internal Oscillator Block can be used with the PLL associated with the External Oscillator Block to produce a 24 MHz, 32 MHz or 48 MHz internal system clock source. The following settings are required to use the PLL internal clock sources:

• The FOSC bits of the Configuration Words must

be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100).

• The SCS bits of the OSCCON register must be

cleared to use the clock determined by FOSC<2:0> in Configuration Words (SCS<1:0> = 00).

• For 24 MHz or 32 MHz, the IRCF bits of the

OSCCON register must be set to the 8 MHz HFINTOSC set to use (IRCF<3:0> = 1110).

• For 48 MHz, the IRCF bits of the OSCCON regis-

ter must be set to the 16 MHz HFINTOSC set to use (IRCF<3:0> = 1111).

• For 24 MHz or 48 MHz, the 3x PLL is required.

The SPLLMULT of the OSCCON register must be set to use (SPLLMULT = 1).

• For 32 MHz, the 4x PLL is required. The

SPLLMULT of the OSCCON register must be clear to use (SPLLMULT = 0).

• The SPLLEN bit of the OSCCON register must be

set to enable the PLL, or the PLLEN bit of the Configuration Words must be programmed to a '1'.

Note: When using the PLLEN bit of the

Configuration Words, the PLL cannot be disabled by software. The 8 MHz and 16 MHz HFINTOSC options will no longer be available.

5.2.2.6 Internal Oscillator Clock Switch Timing

When switching between the HFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-3.

Start-up delay specifications are located in the oscillator tables of Section 29.0 “Electrical

Specifications”.

The PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to '1x'. The SCS bits must be set to '00' to use the PLL with the internal oscillator.

DS41639A-page 64 Preliminary  2012 Microchip Technology Inc.

FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC

LFINTOSC

IRCF <3:0>

System Clock

0 0

Start-up Time

2-cycle Sync Running

HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC

IRCF <3:0>

System Clock

= 0  0

Start-up Time 2-cycle Sync

Running

LFINTOSC HFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

PIC16(L)F1454/5/9

 2012 Microchip Technology Inc. Preliminary DS41639A-page 65

PIC16(L)F1454/5/9

5.3 CPU Clock Divider

The CPU Clock divider allows the system clock to run at a slower speed than the Low/Full-Speed USB module clock, while sharing the same clock source. Only the oscillator defined by the settings of the FOSC bits of the Configuration Words may be used with the CPU clock divider. the CPU clock divider is controlled by the CPUDIV<1:0> bits of the Configuration Words.

Setting the CPUDIV bits will set the system clock to:

• Equal the clock speed of the USB module

• Half the clock speed of the USB module

• One third the clock speed of the USB Module

• One sixth clock speed of the USB module

For more information on the CPU Clock Divider, see

Figure 5-1 and Configuration Words.

5.4 USB Operation

The USB module is designed to operate in two different modes:

• Low Speed

• Full Speed

To achieve the timing requirements imposed by the USB specifications, the internal oscillator or the primary external oscillator are required for the USB module. The FOSC bits of the Configuration Words must be set to INTOSC, ECH or HS mode with a clock frequency of 6, 12, or 16 MHz.

5.4.1 LOW-SPEED OPERATION

For low-speed USB Operation, a 24 MHz clock is required for the USB module. To generate the 24 MHz clock, the following Oscillator modes are allowed:

• HFINTOSC with PLL

• ECH mode

•HS mode

Table 5-1 shows the recommended Clock mode for

low-speed operation.

5.4.2 HIGH-SPEED OPERATION

For full-speed USB operation, a 48 MHz clock is required for the USB module. To generate the 48 MHz clock, the following oscillator modes are allowed:

• HFINTOSC with PLL

• ECH mode

•HS mode

Table 5-1 shows the recommended Clock mode for

full-speed operation.

TABLE 5-1: LOW-SPEED USB CLOCK SETTINGS

Clock Mode

HFINTOSC

ECH or HS mode

Clock

Frequency

16 MHz 3x 1

8 MHz 3x 0

16 MHz 3x 1

12 MHz 4x 1

8 MHz 3x 0

PLL Value USBLSCLK CPUDIV<1:0>

11 10 01 00

System Clock

Frequency

(MHz)

8 16 24 48

8 12 24

8 16 24 48

8 12 24

DS41639A-page 66 Preliminary  2012 Microchip Technology Inc.

TABLE 5-2: HIGH-SPEED USB CLOCK SETTINGS

Clock Mode

HFINTOSC 16 MHz 3x 0

ECH or HS mode

Clock

Frequency

16 MHz 3x 0

12 MHz 4x 0

PLL Value USBLSCLK CPUDIV<1:0>

PIC16(L)F1454/5/9

System Clock

Frequency

(MHz)

11 10 01 00

8 16 24 48

 2012 Microchip Technology Inc. Preliminary DS41639A-page 67

PIC16(L)F1454/5/9

5.5 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits:

• Default system oscillator determined by FOSC bits in Configuration Words

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

5.5.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator.

• When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source.

5.5.3 SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.

The secondary oscillator is enabled using the T1OSCEN control bit in the T1CON register. See

Section 20.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

5.5.4 SECONDARY OSCILLATOR READY

(SOSCR) BIT

The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator.

When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-3.

5.5.2 OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator.

DS41639A-page 68 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.6 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT, or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.

If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.

5.6.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO (of the Configuration Words) = 1; Inter-

nal/External Switchover bit (Two-Speed Start-up mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

Note: When FSCM is enabled, Two-Speed

Start-Up will automatically be enabled.

TABLE 5-3: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay

Sleep/POR

Sleep/POR EC, RC DC – 20 MHz 2 cycles

LFINTOSC EC, RC DC – 20 MHz 1 cycle of each

Sleep/POR

Any clock source HFINTOSC

Any clock source LFINTOSC

Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST)

PLL Inactive PLL Active 24-48 MHz 2 ms (approx.)

Note 1: PLL inactive.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 69

LFINTOSC HFINTOSC

Secondary Oscillator, LP, XT, HS

(1)

31 kHz

31.25kHz-16MHz

32 kHz-20 MHz 1024 Clock Cycles (OST)

31.25kHz-16MHz 2s (approx.)

31 kHz 1 cycle of each

Oscillator Warm-up Delay (T

WARM)

PIC16(L)F1454/5/9

0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N

5.6.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 5-8: TWO-SPEED START-UP

5.6.3 CHECKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator.

DS41639A-page 70 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

External

LFINTOSC

÷ 64

31 kHz

(~32

s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

5.7 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator).

FIGURE 5-9: FSCM BLOCK DIAGRAM

5.7.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.

5.7.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware.

5.7.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed.

5.7.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation.

The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 71

PIC16(L)F1454/5/9

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te st

Test Test

Clock Monitor Output

FIGURE 5-10: FSCM TIMING DIAGRAM

DS41639A-page 72 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

ACTSRC

FSUSB_clk

SOSC_clk

ACTEN

Active

Clock

Tuning

ACT_clk

Enable

ACTEN

Write

OSCTUNE

ACTEN

ACTUD

16 MHz

Internal OSC

OSCTUNE<6:0>

ACT data

sfr data

5.8 Active Clock Tuning (ACT)

The Active Clock Tuning (ACT) continuously adjusts the 16 MHz Internal Oscillator, using an available external reference, to achieve ± 0.20% accuracy. This eliminates the need for a high-speed, high-accuracy external crystal when the system has an available lower speed, lower power, high-accuracy clock source available.

Systems implementing a Real-Time Clock Calendar (RTCC) or a full-speed USB application can take full advantage of the ACT.

5.8.1 ACTIVE CLOCK TUNING OPERATION

The ACT defaults to the disabled state after any Reset. When the ACT is disabled, the user can write to the TUN<6:0> bits in the OSCTUNE register to manually adjust the 16 MHz Internal Oscillator.

The ACT is enabled by setting the ACTEN bit of the ACTCON register. When enabled, the ACT takes control of the OSCTUNE register. The ACT uses the selected ACT reference clock to tune the 16 MHz Internal Oscillator to an accuracy of 16MHz ± 0.2%. The tuning automatically adjusts the OSCTUNE register every reference clock cycle.

Note 1: When the ACT is enabled, the

OSCTUNE register is only updated by the ACT. Writes to the OSCTUNE register by the user are inhibited, but reading the register is permitted.

2: After disabling the ACT, the user should

wait three instructions before writing to the OSCTUNE register.

5.8.2 ACTIVE CLOCK TUNING SOURCE SELECTION

The ACT reference clock is selected with the ACTSRC bit of the ACTCON register. The reference clock sources are provided by the:

• USB module in full-speed operation (ACT_clk)

• Secondary clock at 32.768 kHz (SOSC_clk)

5.8.3 ACT LOCK STATUS

The ACTLOCK bit will be set to '1', when the 16 MHz Internal Oscillator is successfully tuned. The bit will be cleared by the following conditions:

• Out of Lock condition

• Device Reset

• ACT is disabled

5.8.4 ACT OUT-OF-RANGE STATUS

If the ACT requires an OSCTUNE value outside the range to achieve ± 0.20% accuracy, then the ACT Out-of-Range (ACTOR) Status bit will be set to '1'.

An out-of-range status can occur:

• When the 16 MHz internal oscillator is tuned to its

lowest frequency and the next ACT_clk event requests a lower frequency.

• When the 16 MHz internal oscillator is tuned to its

highest frequency and the next ACT_clk event requests a higher frequency.

When the ACT out-of-range event occurs, the 16 MHz internal oscillator will continue to use the last written OSCTUNE value. When the OSCTUNE value moves back within the tunable range and ACTLOCK is established, the ACTOR bit is cleared to '0'.

FIGURE 5-11: ACTIVE CLOCK TUNING BLOCK DIAGRAM

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5.8.5 ACTIVE CLOCK TUNING UPDATE DISABLE

When the ACT is enabled, the OSCTUNE register is continuously updated every ACT_clk period. Setting the ACT Update Disable bit can be used to suspend updates to the OSCTUNE register, without disabling the ACT. If the 16 MHz internal oscillator drifts out of the accuracy range, the ACT Status bits will change and an interrupt can be generated to notify the application.

Clearing the ACTUD bit will engage the ACT updates to OSCTUNE and an interrupt can be generated to notify the application.

5.8.6 INTERRUPTS

The ACT will set the ACT Interrupt Flag, (ACTIF) when either of the ACT Status bits (ACTLOCK or ACTORS) change state, regardless if the interrupt is enabled, (ACTIE = 1). The ACTIF and ACTIE bits are in the PIRx and PIEx registers, respectively. When ACTIE = 1, an interrupt will be generated whenever the ACT Status bits change.

The ACTIF bit must be cleared in software, regardless of the interrupt enable setting.

5.8.7 OPERATION DURING SLEEP

This ACT does not run during Sleep and will not generate interrupts during Sleep.

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5.9 Register Definitions: Oscillator Control

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 SPLLEN SPLLMULT IRCF<3:0> SCS<1:0>

bit 7 bit 0

Legend:

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words =

1 = PLL is enabled 0 = PLL is disabled

bit 6 SPLLMULT: Software PLL Multiplier Select bit

1 = 3x PLL is enabled 0 = 4x PLL is enabled

bit 5-2 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz or 48 MHz HF (see Section 5.2.2.1 “HFINTOSC”) 1110 = 8 MHz or 24 MHz HF (3x PLL) or 32 MHz HF (4x PLL) (see Section 5.2.2.1 “HFINTOSC”) 1101 =4MHz 1100 =2MHz 1011 =1MHz 1010 =500kHz 1001 =250kHz 1000 =125kHz 0111 = 500 kHz (default upon Reset) 0110 =250kHz 0101 =125kHz 0100 =62.5kHz 001x =31.25kHz 000x =31kHz LF

bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words.

(1)

Note 1: Duplicate frequency derived from HFINTOSC.

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REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q R-0/q R-q/q R-0/q U-0 U-0 R-0/q R-0/q

SOSCR PLLRDY OSTS HFIOFR

bit 7 bit 0

Legend:

bit 7 SOSCR: Secondary Oscillator Ready bit

If T1OSCEN =

1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready

If T1OSCEN = 0: 1 = Timer1 clock source is always ready

bit 6 PLLRDY: PLL Ready bit

1 = PLL is ready 0 = PLL is not ready

bit 5 OSTS: Oscillator Start-up Timer Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready 0 = HFINTOSC is not ready

bit 3-2 Unimplemented: Read as ‘0’ bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready 0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC 0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC

— —

LFIOFR HFIOFS

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U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— TUN<6:0>

bit 7 bit 0

Legend:

bit 7 Unimplemented: Read as ‘0’ bit 6-0 TUN<6:0>: Frequency Tuning bits

1000000 = Minimum frequency

•

1111111 = 0000000 = Oscillator module is running at the factory-calibrated frequency. 0000001 =

•

0111110 = 0111111 = Maximum frequency

(1,2)

Note 1: When active clock tuning is enabled (ACTSEL = 1) the oscillator is tuned automatically, the user cannot

write to OSCTUNE.

2: Oscillator is tuned monotonically.

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REGISTER 5-4: ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER

R/W-0/0 R/W-0/0 U-0 R/W-0/0 R-0/0 U-0 R-0/0 U-0

ACTEN ACTUD

—ACTSRC

bit 7 bit 0

Legend:

bit 7 ACTEN: Active Clock Tuning Selection bit

1 = ACT is enabled, updates to OSCTUNE are exclusive to the ACT 0 = ACT is disabled

bit 6 ACTUD: Active Clock Tuning Update Disable bit

1 = Updates to the OSCTUNE register from ACT are disabled 0 = Updates to the OSCTUNE register from ACT are enabled

bit 5 Unimplemented: Read as ‘0’ bit 4 ACTSRC: Active Clock Tuning Source Selection bit

1 = The HFINTOSC oscillator is tuned using Fll-speed USB events 0 = The HFINTOSC oscillator is tuned using the 32.768 kHz oscillator (SOSC) clock source

bit 3 ACTLOCK: Active Clock Tuning Lock Status bit

1 = Locked; 16 MHz internal oscillator is within ± 0.20%.Locked 0 = Not locked; 16 MHz internal oscillator tuning has not stabilized within ± 0.20%

bit 2 Unimplemented: Read as ‘0’ bit 1 ACTORS: Active Clock Tuning Out-of-Range Status bit

1 = Out-of-range; oscillator frequency is outside of the OSCTUNE range 0 = In-range; oscillator frequency is within the OSCTUNE range

bit 0 Unimplemented: Read as ‘0’

(1)

ACTLOCK —ACTORS—

Note 1: The ACTSRC bit should only be changed when ACTEN = 0.

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ACTCON

OSCCON SPLLEN SPLLMULT IRCF<3:0> SCS<1:0> 75

OSCSTAT SOSCR PLLRDY OSTS HFIOFR

OSCTUNE

PIR2

PIE2

T1CON

Legend: — = unimplemented location, read as ‘

ACTEN ACTUD

— TUNE<6:0> 77

OSFIF

OSFIE

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON

C2IF C1IF — BCL1IF USBIF ACTIF —

C2IE C1IE — BCL1IE USBIE ACTIE —

— ACTSRC ACTLOCK —ACTORS—

— — LFIOFR HFIOFS 76

0’. Shaded cells are not used by clock sources.

100

195

TABLE 5-5: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

DS41639A-page 78 Preliminary  2012 Microchip Technology Inc.

13:8

7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

— — FCMEN IESO CLKOUTEN BOREN<1:0>

—

PIC16(L)F1454/5/9

Note 1: See Table 6-1 for BOR active conditions.

Device

Reset

Power-on

Reset

WDT

Time-out

Brown-out

Reset

LPBOR

Reset

RESET Instruction

MCLRE

Sleep

BOR

Active

(1)

PWRT

Done

PWRTE

LFINTOSC

VDD

ICSP™ Programming Mode Exit

Stack

Pointer

MCLR

6.0 RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

•MCLR Reset

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event.

A simplified block diagram of the on-chip Reset circuit is shown in Figure 6-1.

FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

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6.1 Power-On Reset (POR)

The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising V performance may require greater than minimum V The PWRT, BOR or MCLR extend the start-up period until all device operation conditions have been met.

6.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the V rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607).

DD, fast operating speeds or analog

DD.

features can be used to

DD to

6.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 6 -1 for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words.

DD noise rejection filter prevents the BOR from trig-

A V gering on small events. If V duration greater than parameter T will reset. See Figure 6-2 for more information.

DD falls below VBOR for a

BORDC, the device

TABLE 6-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

11 X X Active Waits for BOR ready

10 X

0 X Disabled Begins immediately

00 X XDisabled

Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits.

Awake Active Waits for BOR ready

Sleep Disabled

Active Waits for BOR ready

Instruction Execution upon:

Release of POR or Wake-up from Sleep

(1)

(BORRDY = 1)

(1)

(BORRDY = 1)

(BORRDY = x)

6.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

6.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready

DD is higher than the BOR threshold.

and V

DS41639A-page 80 Preliminary  2012 Microchip Technology Inc.

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

6.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or

DD level.

the V

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

FIGURE 6-2: BROWN-OUT SITUATIONS

TPWRT

(1)

VBOR

Internal

Reset

VBOR

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

PIC16(L)F1454/5/9

6.3 Register Definitions: BOR Control

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN BORFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Word

1 = BOR Enabled 0 = BOR Disabled

If BOREN <1:0> in Configuration Words SBOREN is read/write, but has no effect on the BOR.

bit 6 BORFS: Brown-out Reset Fast Start bit

If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect.

bit 5-1 Unimplemented: Read as ‘0’

bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive

— — — — —BORRDY

s = 01:

 00:

(1)

Note 1: BOREN<1:0> bits are located in Configuration Words.

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6.4 Low-Power Brown-out Reset

(LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to

Figure 6-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2.

DD pin.

6.4.1 ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled.

6.4.1.1 LPBOR Module Output

The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR the PCON register and to the power control block.

signal which goes to

6.5 MCLR

The MCLR is an optional external input that can reset the device. The MCLR MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2).

TABLE 6-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled 10Enabled x1Enabled

6.5.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR V

DD through an internal weak pull-up.

The device has a noise filter in the MCLR The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR

6.5.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.3 “PORTA Regis-

ters” for more information.

function is controlled by the

pin is connected to

Reset path.

pin low.

6.6 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer (WDT)” for more information.

and PD bits in the STATUS register are

6.7 RESET Instruction

A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Ta b le 6 - 4 for default conditions after a RESET instruction has occurred.

6.8 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 3.5.2 “Overflow/Underflow

Reset” for more information.

6.9 Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

6.10 Power-Up Timer

The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running.

The Power-up Timer is controlled by the PWRTE Configuration Words.

bit of

6.11 Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. M

CLR must be released (if enabled).

The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 6.0 “Active Clock Tuning (ACT) Module” for more information.

The Power-up Timer runs independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will expire. Upon bringing MCLR will begin execution immediately (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel.

high, the device

DS41639A-page 82 Preliminary  2012 Microchip Technology Inc.

FIGURE 6-3: RESET START-UP SEQUENCE

TMCLR

TPWRT

VDD

Internal POR

Power-Up Timer

MCLR

Internal RESET

Internal Oscillator

Oscillator

OSC

External Clock (EC)

CLKIN

OSC

PIC16(L)F1454/5/9

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6.12 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Tab le 6 - 3 and Ta bl e 6 -4 show the Reset conditions of these registers.

TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition

0 0 1 1 10 x11Power-on Reset

0 0 1 1 10 x0xIllegal, TO

0 0 1 1 10 xx0Illegal, PD is set on POR

0 0 u 1 1u 011Brown-out Reset

u u 0 u uu u0uWDT Reset

u u u u uu u00WDT Wake-up from Sleep

u u u u uu u10Interrupt Wake-up from Sleep

u u u 0 uu uuuMCLR

u u u 0 uu u10MCLR

u u u u 0 u u u u RESET Instruction Executed

1 u u u uu uuuStack Overflow Reset (STVREN = 1)

u 1 u u uu uuuStack Underflow Reset (STVREN = 1)

is set on POR

Reset during normal operation

Reset during Sleep

(1)

(2)

STATUS

---1 0uuu uu-- uuuu

PCON

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-- 110x

MCLR

Reset during normal operation 0000h ---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu

WDT Reset 0000h ---0 uuuu uu-- uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu

Brown-out Reset 0000h ---1 1uuu 00-- 11u0

Interrupt Wake-up from Sleep PC + 1

RESET Instruction Executed 0000h ---u uuuu uu-- u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is

pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program Counter

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6.13 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI

•MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in Register 6-2.

6.14 Register Definitions: Power Control

REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF —

bit 7 bit 0

)

WDT RMCLR RI POR BOR

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware

bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT

bit 3 RMCLR

bit 2 RI: RESET Instruction Flag bit

bit 1 POR

bit 0 BOR

: Watchdog Timer Reset Flag bit

1 = A Watchdog Timer Reset has not occurred or set by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware)

: MCLR Reset Flag bit

1 = A MCLR Reset has not occurred or set by firmware 0 = A MCLR

1 = A RESET instruction has not been executed or set by firmware 0 = A RESET instruction has been executed (cleared by hardware)

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

Reset has occurred (cleared by hardware)

: Brown-out Reset Status bit

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TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

on Page

BORCON SBOREN BORFS

PCON STKOVF STKUNF

STATUS

WDTCON

— — —TOPD Z DC C 27

— — WDTPS<4:0> SWDTEN 110

— — — — — BORRDY 81

—RWDTRMCLR RI POR BOR 85

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR

Reset and Watchdog Timer Reset during normal operation.

TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

CONFIG2

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

13:8

7:0

13:8

7:0

— —

CP MCLRE PWRTE WDTE<1:0>

— — LVP DEBUG LPBOR BORV STVREN

PLLMULT USBLSCLK CPUDIV<1:0>

FCMEN IESO

CLKOUTEN BOREN<1:0> —

FOSC<2:0>

— — WRT<1:0>

PLLEN

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7.0 REFERENCE CLOCK MODULE

The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR). This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. The reference clock module includes the following features:

• System clock is the source

• Available in all oscillator configurations

• Programmable clock divider

• Output enable to a port pin

• Selectable duty cycle

• Slew rate control

The reference clock module is controlled by the CLKRCON register (Register 7-1) and is enabled when setting the CLKREN bit. To output the divided clock signal to the CLKR port pin, the CLKROE bit must be set. The CLKRDIV<2:0> bits enable the selection of eight different clock divider options. The CLKRDC<1:0> bits can be used to modify the duty cycle of the output

(1)

. The CLKRSLR bit controls slew rate limiting.

clock

Note 1: If the base clock rate is selected without

a divider, the output clock will always have a duty cycle equal to that of the source clock, unless a 0% duty cycle is selected. If the clock divider is set to base clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock.

7.3 Conflicts with the CLKR Pin

There are two cases when the reference clock output signal cannot be output to the CLKR pin, if:

• LP, XT or HS Oscillator mode is selected.

• CLKOUT function is enabled.

7.3.1 OSCILLATOR MODES

If LP, XT or HS Oscillator modes are selected, the OSC2/CLKR pin must be used as an oscillator input pin and the CLKR output cannot be enabled. See

Section 5.2 “Clock Source Types” for more informa-

tion on different oscillator modes.

7.3.2 CLKOUT FUNCTION

The CLKOUT function has a higher priority than the reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configuration Words, F Reference Section 4.0 “Device Configuration” for more information.

OSC/4 will always be output on the port pin.

7.4 Operation During Sleep

As the reference clock module relies on the system clock as its source, and the system clock is disabled in Sleep, the module does not function in Sleep, even if an external clock source or the Timer1 clock source is configured as the system clock. The module outputs will remain in their current state until the device exits Sleep.

7.1 Slew Rate

The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the CLKRSLR bit in the CLKRCON register.

7.2 Effects of a Reset

Upon any device Reset, the reference clock module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 87

PIC16(L)F1454/5/9

7.5 Register Definition: Reference Clock Control

REGISTER 7-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0>

bit 7 bit 0

Legend:

bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference clock module is enabled 0 = Reference clock module is disabled

bit 6 CLKROE: Reference Clock Output Enable bit

1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin

bit 5 CLKRSLR: Reference Clock Slew Rate Control limiting enable bit

1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled

bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits

11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0%

bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits

111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2 000 = Base clock value

(2)

(1)

(3)

Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.

2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%

is selected.

3: To route CLKR to pin, CLKOUTEN

Words = 0 will result in F

DS41639A-page 88 Preliminary  2012 Microchip Technology Inc.

OSC/4. See Section 7.3 “Conflicts with the CLKR Pin” for details.

of Configuration Words = 1 is required. CLKOUTEN of Configuration

PIC16(L)F1454/5/9

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0>

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

CLKRDIV<2:0>

TABLE 7-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

13:8

7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

— — FCMEN IESO CLKOUTEN BOREN<1:0> CPD

on Page

 2012 Microchip Technology Inc. Preliminary DS41639A-page 89

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 90 Preliminary  2012 Microchip Technology Inc.

8.0 INTERRUPTS

TMR0IF TMR0IE

INTF

INTE

IOCIF

IOCIE

Interrupt to CPU

Wake-up (If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7> PIEn<7>

PEIE

Peripheral Interrupts

(TMR1IF) PIR1<0>

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.

This chapter contains the following information for Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 8-1.

FIGURE 8-1: INTERRUPT LOGIC

PIC16(L)F1454/5/9

 2012 Microchip Technology Inc. Preliminary DS41639A-page 91

PIC16(L)F1454/5/9

8.1 Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the PIE1 and PIE2 registers)

The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See “Section 8.5 “Automatic

Context Saving”.”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

8.2 Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 8-2 and Figure 8.3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

DS41639A-page 92 Preliminary  2012 Microchip Technology Inc.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Fosc

CLKR

PC 0004h 0005h

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC )

Interrupt Sam pled during Q1

Inst(PC)

PC-1 PC+1

NOP

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(0005h)

Execute

PIC16(L)F1454/5/9

FIGURE 8-2: INTERRUPT LATENCY

 2012 Microchip Technology Inc. Preliminary DS41639A-page 93

PIC16(L)F1454/5/9

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

Instruction Fetched

Instruction Executed

Interrupt Latency

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Forced NOP

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Forced NOP

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”

INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

FIGURE 8-3: INT PIN INTERRUPT TIMING

DS41639A-page 94 Preliminary  2012 Microchip Technology Inc.

8.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 9.0 “Power-

Down Mode (Sleep)” for more details.

8.4 INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.

PIC16(L)F1454/5/9

8.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.

and PD)

 2012 Microchip Technology Inc. Preliminary DS41639A-page 95

PIC16(L)F1454/5/9

8.6 Register Definitions: Interrupt Control

REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

bit 7 bit 0

Legend:

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt 0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed 0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state

(1)

Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register

Note: Interrupt flag bits are set when an interrupt

DS41639A-page 96 Preliminary  2012 Microchip Technology Inc.

have been cleared by software.

condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PIC16(L)F1454/5/9

REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

TMR1GIE ADIE

bit 7 bit 0

Legend:

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt

bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

(1)

RCIE TXIE SSP1IE — TMR2IE TMR1IE

Note 1: PIC16(L)F1455/9 only.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2012 Microchip Technology Inc. Preliminary DS41639A-page 97

PIC16(L)F1454/5/9

REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0

OSFIE C2IE C1IE

bit 7 bit 0

Legend:

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt

bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt

bit 2 USBIE: USB Interrupt Enable bit

1 = Enables the USB interrupt 0 = Disables the USB interrupt

bit 1 ACTIE: Active Clock Tuning Interrupt Enable bit

1 = Enables the Active Clock Tuning interrupt 0 = Disables the Active Clock Tuning interrupt

bit 0 Unimplemented: Read as ‘0’

— BCL1IE USBIE ACTIE —

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS41639A-page 98 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

TMR1GIF ADIF

bit 7 bit 0

Legend:

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

(1)

RCIF TXIF SSP1IF — TMR2IF TMR1IF

Note 1: PIC16(L)F1455/9 only.

Note: Interrupt flag bits are set when an interrupt

 2012 Microchip Technology Inc. Preliminary DS41639A-page 99

PIC16(L)F1454/5/9

REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0

OSFIF C2IF C1IF

bit 7 bit 0

Legend:

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 C2IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 C1IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2 USBIF: USB Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 1 ACTIF: Active Clock Tuning Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 Unimplemented: Read as ‘0’

— BCL1IF USBIF ACTIF —

Note: Interrupt flag bits are set when an interrupt

DS41639A-page 100 Preliminary  2012 Microchip Technology Inc.

Datasheet PIC16LF1454, PIC16LF1455, PIC16LF1459, PIC16F1454, PIC16F1455 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance RISC CPU:

Special Microcontroller Features:

Universal Serial Bus (USB) Features:

Extreme Low-Power Management PIC16LF145X with XLP:

Flexible Oscillator Structure:

Peripheral Features:

PIC16(L)F145X Family Types

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

FIGURE 1-1: PIC16(L)F1454/5/9 BLOCK DIAGRAM

TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION

TABLE 1-3: PIC16(L)F1455 PINOUT DESCRIPTION

TABLE 1-4: PIC16(L)F1459 PINOUT DESCRIPTION

2.0 ENHANCED MID-RANGE CPU

FIGURE 2-1: CORE BLOCK DIAGRAM

2.3 File Select Registers

2.4 Instruction Set

3.0 MEMORY ORGANIZATION

3.1 Program Memory Organization

TABLE 3-1: DEVICE SIZES AND ADDRESSES

3.1.1 READING PROGRAM MEMORY AS DATA

EXAMPLE 3-1: RETLW INSTRUCTION

3.2 Data Memory Organization

3.2.1 CORE REGISTERS

TABLE 3-2: CORE REGISTERS

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

3.3.1 SPECIAL FUNCTION REGISTER

3.3.2 GENERAL PURPOSE RAM

TABLE 3-3: DUAL PORT RAM ADDRESSING

3.3.3 DUAL-PORT RAM

3.3.4 COMMON RAM

3.3.5 DEVICE MEMORY MAPS

TABLE 3-4: PIC16(L)F1454 MEMORY MAP, BANK 0-7

TABLE 3-5: PIC16(L)F1455 MEMORY MAP, BANK 0-7

TABLE 3-6: PIC16(L)F1459 MEMORY MAP, BANK 0-7

TABLE 3-7: PIC16(L)F1454 MEMORY MAP, BANK 8-23

TABLE 3-8: PIC16(L)F1455/9 MEMORY MAP, BANK 8-23

TABLE 3-9: PIC16(L)F1454/5/9 MEMORY MAP, BANK 24-31

3.3.6 CORE FUNCTION REGISTERS SUMMARY

TABLE 3-11: CORE FUNCTION REGISTERS SUMMARY

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY

3.4 PCL and PCLATH

3.4.1 MODIFYING PCL

3.4.2 COMPUTED GOTO

3.4.3 COMPUTED FUNCTION CALLS

3.4.4 BRANCHING

3.5 Stack

3.5.1 ACCESSING THE STACK

FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4

3.5.2 OVERFLOW/UNDERFLOW RESET

3.6 Indirect Addressing

FIGURE 3-8: INDIRECT ADDRESSING

3.6.1 TRADITIONAL DATA MEMORY

FIGURE 3-9: TRADITIONAL DATA MEMORY MAP

3.6.2 LINEAR DATA MEMORY

3.6.3 PROGRAM FLASH MEMORY

4.0 DEVICE CONFIGURATION

4.1 Configuration Words

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

4.3 Code Protection

4.3.1 PROGRAM MEMORY PROTECTION

4.4 Write Protection

4.5 User ID

4.6 Device ID and Revision ID

4.7 Register Definitions: Revision and Device

REGISTER 4-3: DEVID: DEVICE ID REGISTER