Datasheet PIC16F707, PIC16LF707 Datasheet

PIC16F707/PIC16LF707

Data Sheet

40/44-Pin, Flash Microcontrollers

with nanoWatt XLP and

mTouch™ Technology

 2010 Microchip Technology Inc. Preliminary DS41418A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-60932-148-2

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41418A-page 2 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

40/44-Pin, Flash Microcontrollers with

nanoWatt XLP and mTouch™ Technology

Devices included in this data sheet:

•PIC16F707

• PIC16LF707

High-Performance RISC CPU:

• Only 35 Single-Word Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 20 MHz clock input

- DC – 200 ns instruction cycle

• 8K x 14 Words of Flash Program Memory

• 363 Bytes of Data Memory (SRAM)

• Interrupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Read Access to Program Memory

• Pinout Compatible to other 40-pin PIC16CXXX
and PIC16FXXX Microcontrollers

Special Microcontroller Features:

• Precision Internal Oscillator:

- 16 MHz or 500 kHz operation

- Factory calibrated to ±1%, typical

- Software selectable ÷1, ÷2, ÷4 or ÷8 divider

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- 3 crystal/resonator modes up to 20 MHz

- 3 external clock modes up to 20 MHz

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Oscillator Start-Up Timer (OST)

• Brown-out Reset (BOR):

- Selectable between two trip points

- Disabled in Sleep option

• Watchdog Timer (WDT)

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via two
pins

• In-Circuit Debug (ICD) via Two Pins

• Multiplexed Master Clear with Pull-up/Input Pin

• Industrial and Extended Temperature Range

• High-Endurance Flash Cell:

- 1,000 Write Flash Endurance (typical)

- Flash Retention: >40 years

- Power-Saving Sleep mode

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF707)

• 1.8V to 5.5V (PIC16F707)

Extreme Low-Power Management PIC16LF707 with nanoWatt XLP:

• Sleep mode: 20 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Timer1 Oscillator: 600 nA @ 1.8V, typical
@ 32 kHz

mTouch™ Technology Features:

• Up to 32 Channels

• Two Capacitive Sensing modules:

- Acquire 2 samples simultaneously

• Multiple Power modes:

- Operation during Sleep

- Proximity sensing with ultra low µA current

• Adjustable Waveform Min. and Max. for Optimal
Noise Performance

• 1.8V to 5.5V Operation (3.6V max. for
PIC16LF707)

Analog Features:

• A/D Converter:

- 8-bit resolution and up to 14 channels

- Conversion available during Sleep

- Selectable 1.024V/2.048V/4.096V voltage

reference

• On-chip 3.2V Regulator (PIC16F707 device only)

Peripheral Highlights:

• Up to 35 I/O Pins and 1 Input-only Pin:

- High current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• Timer0/A/B: 8-Bit Timer/Counter with 8-Bit
Prescaler

• Enhanced Timer1/3:

- Dedicated low-power 32 kHz oscillator driver

- 16-bit timer/counter with prescaler

- External Gate Input mode with toggle and

single shot modes

- Interrupt-on-gate completion

• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler

• Two Capture, Compare, PWM modules (CCP):

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)

 2010 Microchip Technology Inc. Preliminary DS41418A-page 3

PIC16F707/PIC16LF707

40-PIN PDIP

PIC16F707/PIC16LF707

1

2

3

4

5

6

7

8

9

10

VPP/MCLR/RE3

V

CAP

(3)

/SS

(2)

/AN0/RA0

CPSA0

/AN1/RA1

DACOUT/CPSA1/AN2/RA2

CPSA2/V

REF/AN3/RA3

TACKI/T0CKI/CPSA3/RA4

V

CAP

(3)

/SS

(2)

/CPSA4/AN4/RA5

CPSA5/AN5/RE0

CPSA6/AN6/RE1

CPSA7/AN7/RE2

RB6/CPSB14/ICSPCLK

RB5/AN13/CPSB13/T1G/T3CKI

RB4/AN11/CPSB12

RB3/AN9/CPSB11/CCP2

(1)

RB2/AN8/CPSB10

RB1/AN10/CPSB9

RB0/AN12/CPSB8/INT

V

DD

VSS

RD2/CPSB7

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

V

DD

VSS

CLKIN/OSC1/CPSB0/RA7

V

CAP

(3)

/CLKOUT/OSC2/CPSB1/RA6

T1CKI/T1OSO/CPSB2/RC0

CCP2

(1)

/T1OSI/CPSB3/RC1

TBCKI/CCP1/CPSB4/RC2

SCL/SCK/RC3

T3G/CPSB5/RD0

CPSB6/RD1

RC5/CPSA9/SDO

RC4/SDI/SDA

RD3/CPSA8

RD4/CPSA12

RC7/CPSA11/RX/DT

RC6/CPSA10/TX/CK

RD7/CPSA15

RD6/CPSA14

RD5/CPSA13

RB7/CPSB15/ICSPDAT

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS

pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

• Synchronous Serial Port (SSP):

- SPI (Master/Slave)

-I2C™ (Slave) with Address Mask

• Voltage Reference module:

- Fixed voltage reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive
reference selection

Device

PIC16F707 8192 363 36 32 14 Yes 2 4/2

PIC16LF707 8192 363 36 32 14 Yes 2 4/2

Pin Diagrams

Memory Flash

Program

(words)

SRAM
(bytes)

Capacitive Touch

I/Os

Channels

8-bit A/D

(ch)

AUSART CCP

Timers

8/16-bit

DS41418A-page 4 Preliminary  2010 Microchip Technology Inc.

Pin Diagrams

10
11

2
3
4
5
6

1

181920

21

22

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

CPSA2/V

REF/AN3/RA3

DACOUT/CPSA1/AN2/RA2

CPSA0/AN1/RA1

V

CAP

(3)

/SS

(2)

/AN0/RA0

VPP/MCLR/RE3

CCP2

(1)

/CPSB11/AN9/RB3

ICSPDAT/CPSB15/RB7

ICSPCLK/CPSB14/RB6

T3CKI/T1G/CPSB13/AN13/RB5

CPSB12/AN11/RB4

NC

RC6/CPSA10/TX/CK

RC5/CPSA9/SDO

RC4/SDI/SDA

RD3/CPSA8

RD2/CPSB7

RD1/CPSB6

RD0/CPSB5/T3G

RC3/SCK/SCL

RC2/CPSB4/CCP1/TBCKI

RC1/CPSB3/T1OSI/CCP2

(1)

RC0/CPSB2/T1OSO/T1CKI

RA6/OSC2/CLKOUT/CPSB1/VCAP

(3)

RA7/OSC1/CLKIN/CPSB0
V

SS

VSS
NC
V

DD

RE2/AN7/CPSA7
RE1/AN6/CPSA6
RE0/AN5/CPSA5
RA5/AN4/CPSA4/SS

(2)

/VCAP

(3)

RA4/CPSA3/T0CKI/TACKI

DT/RX/CPSA11/RC7

CPSA12/RD4
CPSA13/RD5
CPSA14/RD6
CPSA15/RD7

V

SS

VDD
VDD

INT/CPSB8/AN12/RB0

CPSB9/AN10/RB1
CPSB10/AN8/RB2

44-PIN QFN (8x8x0.9)

PIC16F707

PIC16LF707

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS

pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 5

PIC16F707/PIC16LF707

10
11

2
3

6

1

1819202122

121314

15

38

8

7

44

43

42

414039

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

VREF/CPSA2/AN3/RA3

DACOUT/CPSA1/AN2/RA2

CPSA0/AN1/RA1

V

CAP

(3)

/SS

(2)

/AN0/RA0

V

PP/MCLR/RE3

NC

ICSPDAT/CPSB15/RB7

ICSPCLK/CPSB14/RB6

T1G/CPSB13/AN13/RB5

CPSB12/AN11/RB4

NC

RC6/CPSA10/TX/CK

RC5/CPSA9/SDO

RC4/SDI/SDA

RD3/CPSA8

RD2/CPSB7

RD1/CPSB6

RD0CPSB5/T3G

RC3//SCK/SCL

RC2CPSB4/CCP1/TBCKI

RC1/CPSB3/T1OSI/CCP2

(1)

NC

NC
RC0/T1OSO/T1CKI/CPSB2
RA6/OSC2/CLKOUT/CPSB1/V

CAP

(3)

RA7/OSC1/CLKIN/CPSB0
V

SS

VDD
RE2/AN7/CPSA7
RE1/AN6/CPSA6
RE0/AN5/CPSA5
RA5/AN4/CPSA4/SS

(2)

/VCAP

(3)

RA4/CPSA3/T0CKI/TACKI

DT/RX/CPSA11/RC7

CPSA12/RD4
CPSA13/RD5
CPSA14/RD6

V

SS

VDD

INT/CPSB8/AN12/RB0

CPSB9/AN10/RB1
CPSB10/AN8/RB2

CCP2

(1)

/CPSB11/AN9/RB3

CPSA15/RD7

5

4

PIC16F707

PIC16LF707

44-PIN TQFP

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS

pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

Pin Diagrams

DS41418A-page 6 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707

I/O

44-Pin TQFP

44-Pin QFN

CAP functionality is selectable by the VCAPEN bits in Configuration Word 2.

40-Pin PDIP

RA0 2 19 19 Y AN0 — — — —

RA1 3 20 20 Y AN1 — CPSA0 — — — — — — —

RA2 4 21 21 Y AN2 DACOUT CPSA1 — — — — — — —

RA3 5 22 22 Y AN3/

RA4 6 23 23 Y — — CPSA3 T0CKI/

RA5 7 24 24 Y AN4 — CPSA4 — — — SS

RA6 14 31 33 Y — — CPSB1 — — — — — — OSC2/

RA7 13 30 32 Y — — CPSB0 — — — — — — OSC1/

RB0 33 8 9 Y AN12 — CPSB8 — — — — IOC/INT Y —

RB1 34 9 10 Y AN10 — CPSB9 — — — — IOC Y —

RB2 35 10 11 Y AN8 — CPSB10 — — — — IOC Y —

RB3 36 11 12 Y AN9 — CPSB11 — CCP2

RB4 37 14 14 Y AN11 — CPSB12 — — — — IOC Y —

RB5 38 15 15 Y AN13 — CPSB13 T1G/

RB6 39 16 16 Y — — CPSB14 — — — — IOC Y ICSPCLK/

RB7 40 17 17 Y — — CPSB15 — — — — IOC Y ICSPDAT/

RC0 15 32 34 Y — — CPSB2 T1OSO/

RC1 16 35 35 Y — — CPSB3 T1OSI CCP2

RC2 17 36 36 Y — — CPSB4 TBCKI CCP1 — — — — —

RC3 18 37 37 — — — — — — — SCK/SCL — — —

RC4 23 42 42 — — — — — — — SDI/SDA — — —

RC5 24 43 43 Y — — CPSA9 — — — SDO — — —

RC6 25 44 44 Y — — CPSA10 — — TX/CK — — — —

RC7 26 1 1 Y — — CPSA11 — — RX/DT — — — —

RD0 19 38 38 Y — — CPSB5 T3G — — — — — —

RD1 20 39 39 Y — — CPSB6 — — — — — — —

RD2 21 40 40 Y — — CPSB7 — — — — — — —

RD3 22 41 41 Y — — CPSA8 — — — — — — —

RD4 27 2 2 Y — — CPSA12 — — — — — — —

RD5 28 3 3 Y — — CPSA13 — — — — — — —

RD6 29 4 4 Y — — CPSA14 — — — — — — —

RD7 30 5 5 Y — — CPSA15 — — — — — — —

RE0 8 25 25 Y AN5 — CPSA5 — — — — — — —

RE1 9 26 26 Y AN6 — CPSA6 — — — — — — —

RE2 10 27 27 Y AN7 — CPSA7 — — — — — — —

RE3 1 18 18 — — — — — — — — — Y

VDD 11 , 32 7, 28 7,8,28 — — — — — — — — — VDD

Vss 12, 31 6, 29 6, 30, 31 — — — — — — — — — VSS

Note 1: Pull-up activated only with external MCLR configuration.

2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.

3: RA5 is the default pin location for SS

4: PIC16F707 only. V

ANSEL

V

A/D

REF

DAC

Cap Sensor

VREF CPSA2 — — — — — — —

. RA0 may be selected by changing the SSSEL bit in the APFCON register.

Timers

TAC KI

T3CKI

T1CKI

CCP

— — — — — —

— — — IOC Y —

— — — — — —

AUSART

(2)

— — IOC Y —

(2)

—— ———

SS

SSP

(3)

(3)

— — VCAP

——VCAP

Basic

Pull-up

Interrupt

(4)

(4)

CLKOUT/

(4)

V

CAP

CLKIN

ICDCLK

ICDDAT

(1)

MCLR/

PP

V

 2010 Microchip Technology Inc. Preliminary DS41418A-page 7

PIC16F707/PIC16LF707

Table of Contents

1.0 Device Overview ....................................................................................................................................................................... 11

2.0 Memory Organization ................................................................................................................................................................ 17

3.0 Resets ....................................................................................................................................................................................... 29

4.0 Interrupts ................................................................................................................................................................................... 39

5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 49

6.0 I/O Ports .................................................................................................................................................................................... 51

7.0 Oscillator Module....................................................................................................................................................................... 69

8.0 Device Configuration................................................................................................................................................................. 75

9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 79

10.0 Fixed Voltage Reference ........................................................................................................................................................... 89

11.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................... 91

12.0 Timer0 Module .......................................................................................................................................................................... 95

13.0 Timer1/3 Modules with Gate Control......................................................................................................................................... 99

14.0 TimerA/B Modules................................................................................................................................................................... 111

15.0 Timer2 Module ........................................................................................................................................................................ 115

16.0 Capacitive Sensing Module ..................................................................................................................................................... 117

17.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 127

18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .......................................................... 137

19.0 SSP Module Overview ............................................................................................................................................................ 157

20.0 Program Memory Read........................................................................................................................................................... 179

21.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 183

22.0 In-Circuit Serial Programming™ (ICSP™) .............................................................................................................................. 185

23.0 Instruction Set Summary ......................................................................................................................................................... 187

24.0 Development Support.............................................................................................................................................................. 197

25.0 Electrical Specifications........................................................................................................................................................... 201

26.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 231

27.0 Packaging Information............................................................................................................................................................. 267

Appendix A: Data Sheet Revision History ......................................................................................................................................... 273

Appendix B: Migrating From Other PIC® Devices ............................................................................................................................ 273

The Microchip Web Site.................................................................................................................................................................... 281

Customer Change Notification Service ............................................................................................................................................. 281

Customer Support ............................................................................................................................................................................. 281

Reader Response ............................................................................................................................................................................. 282

Product Identification System............................................................................................................................................................. 283

DS41418A-page 8 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TO OUR VALUED CUSTOMERS

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 2010 Microchip Technology Inc. Preliminary DS41418A-page 9

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 10 Preliminary  2010 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16F707/PIC16LF707 devices are covered by
this data sheet. They are available in 40/44-pin
packages. Figure 1-1 shows a block diagram of the
PIC16F707/PIC16LF707 devices. Table 1-1 shows the
pinout descriptions.

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 11

PIC16F707/PIC16LF707

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

RAM Addr

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

PORTA

PORTB

PORTC

PORTD

PORTE

RA4
RA5

RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7

RE0

RE1

RE2

8

8

Timer0

RA3

RA1

RA0

8

3

RA6
RA7

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

RB0
RB1
RB2

RB3
RB4
RB5

RB7

AN6

AN0 AN1

AN2

AN3 AN4

AN5

AN7

Synchronous

SDA

SCL

SSSDO

Serial Port

SDI/

SCK/

TX/CK

RX/DT

Internal

Oscillator

Block

Configuration

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

PORTB

PORTC

PORTD

PORTE

RC1

8

8

8

3

Synchronous

SDA

SCL

SSSDO

Serial Port

SDI/

SCK/

Internal

Oscillator

Block

Configuration

13

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

8 Level Stack

(13-bit)

7

Addr MUX

FSR Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

PORTB

PORTC

PORTD

PORTE

RC1

8

8

8

3

Analog-To-Digital Converter

RB6

Synchronous

SDA

SCL

SSSDO

Serial Port

SDI/

SCK/

Internal

Oscillator

Block

Configuration

RE3

CCP2

CCP2

CCP1

CCP1

VREF

RA2

AN9AN8

AN10

AN11

AN12 AN13

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR

VDD

Brown-out

Reset

VSS

T0CKI

T1G

T1CKI

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR

VDD

Brown-out

Reset

VSS

T0CKI

MCLR

VDD VSS

T0CKI

Timer1

32 kHz

Oscillator

T1OSI

T1OSO

LDO

Regulator

Capacitive Sensing Module A

CPSA6CPSA0 CPSA1 CPSA2 CPSA3 CPSA4

CPSA7

CPSA8 CPSA9 CPSA10 CPSA11 CPSA12 CPSA13 CPSA14 CPSA15

CPSA5

Flash

Program

Memory

RAM

T3G

T3CKI

Timer1 Timer2 Timer3

TimerA Timer B

AUSART

TACKI

TBCKI

CPSB6CPSB0 CPSB1 CPSB2 CPSB3 CPSB4

CPSB7

CPSB8 CPSB9 CPSB10 CPSB11 CPSB12 CPSB13 CPSB14 CPSB15

CPSB5

Capacitive Sensing Module B

Digital-To-Analog

DACOUT

Converter

FIGURE 1-1: PIC16F707/PIC16LF707 BLOCK DIAGRAM

DS41418A-page 12 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION

Input

Name Function

Typ e

Output

Typ e

Description

RA0/AN0/SS

RA1/AN1/CPSA0 RA1 TTL CMOS General purpose I/O.

RA2/AN2/CPSA1/DACOUT RA2 TTL CMOS General purpose I/O.

RA3/AN3/V

RA4/CPSA3/T0CKI/TACKI RA4 TTL CMOS General purpose I/O.

RA5/AN4/CPSA4/SS/

RA6/OSC2/CLKOUT/V
CPSB1

RA7/OSC1/CLKIN/CPSB0 RA7 TTL CMOS General purpose I/O.

RB0/AN12/CPSB8/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

RB1/AN10/CPSB9 RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

/VCAP RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

SS

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).

V

AN1 AN — A/D Channel 1 input.

CPSA0 AN — Capacitive sensing A input 0.

AN2 AN — A/D Channel 2 input.

CPSA1 AN — Capacitive sensing A input 1.

DACOUT — AN Voltage Reference Output.

REF/CPSA2 RA3 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

REF AN — A/D Voltage Reference input.

V

CPSA2 AN — Capacitive sensing A input 2.

CPSA3 AN — Capacitive sensing A input 3.

T0CKI ST — Timer0 clock input.

TACKI ST — TimerA clock input.

VCAP RA5 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

CPSA4 AN — Capacitive sensing A input 4.

SS

V

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).

CAP/

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

CAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).

V

CPSB1 AN — Capacitive sensing B input 1.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN CMOS — External clock input (EC mode).

CLKIN ST — RC oscillator connection (RC mode).

CPSB0 AN — Capacitive sensing B input 0.

AN12 AN — A/D Channel 12 input.

CPSB8 AN — Capacitive sensing B input 8.

INT ST — External interrupt.

AN10 AN — A/D Channel 10 input.

CPSB9 AN — Capacitive sensing B input 9.

ST — Slave Select input.

ST — Slave Select input.

OSC/4 output.

Individually enabled pull-up.

Individually enabled pull-up.

2

C™ = Schmitt Trigger input with I2C

 2010 Microchip Technology Inc. Preliminary DS41418A-page 13

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB2/AN8/CPSB10 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN8 AN — A/D Channel 8 input.

CPSB10 AN — Capacitive sensing B input 10.

RB3/AN9/CPSB11/CCP2 RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN9 AN — A/D Channel 9 input.

CPSB11 AN — Capacitive sensing B input 11.

CCP2 ST CMOS Capture/Compare/PWM2.

RB4/AN11/CPSB12 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN11 AN — A/D Channel 11 input.

CPSB12 AN — Capacitive sensing B input 12.

RB5/AN13/CPSB13/T1G/T3CKI RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN13 AN — A/D Channel 13 input.

CPSB13 AN — Capacitive sensing B input 13.

T1G ST — Timer1 gate input.

T3CKI ST — Timer3 clock input.

RB6/ICSPCLK/ICDCLK/CPSB14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

ICSPCLK ST — Serial Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

CPSB14 AN — Capacitive sensing B input 14.

RB7/ICSPDAT/ICDDAT/CPSB15 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST — In-Circuit Data I/O.

CPSB15 AN — Capacitive sensing B input 15.

RC0/T1OSO/T1CKI/CPSB2 RC0 ST CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

CPSB2 AN — Capacitive sensing B input 2.

RC1/T1OSI/CCP2/CPSB3 RC1 ST CMOS General purpose I/O.

T1OSI XTAL XTAL Timer1 oscillator connection.

CCP2 ST CMOS Capture/Compare/PWM2.

CPSB3 AN — Capacitive sensing B input 3.

RC2/CCP1/CPSB4/TBCKI RC2 ST CMOS General purpose I/O.

CCP1 ST CMOS Capture/Compare/PWM1.

CPSB4 AN — Capacitive sensing B input 4.

TBCKI ST — TimerB clock input.

RC3/SCK/SCL RC3 ST CMOS General purpose I/O.

SCK ST CMOS SPI clock.

SCL I

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Output

Typ e

2

Typ e

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

Individually enabled pull-up.

C™ OD I2C™ clock.

Description

2

C™ = Schmitt Trigger input with I2C

DS41418A-page 14 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RC4/SDI/SDA RC4 ST CMOS General purpose I/O.

SDI ST — SPI data input.

SDA I

RC5/SDO/CPSA9 RC5 ST CMOS General purpose I/O.

SDO — CMOS SPI data output.

CPSA9 AN — Capacitive sensing A input 9.

RC6/TX/CK/CPSA10 RC6 ST CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

CPSA10 AN — Capacitive sensing A input 10.

RC7/RX/DT/CPSA11 RC7 ST CMOS General purpose I/O.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

CPSA11 AN — Capacitive sensing A input 11.

RD0/CPSB5/T3G RD0 ST CMOS General purpose I/O.

CPSB5 AN — Capacitive sensing B input 5.

T3G ST — Timer3 Gate input.

RD1/CPSB6 RD1 ST CMOS General purpose I/O.

CPSB6 AN — Capacitive sensing B input 6.

RD2/CPSB7 RD2 ST CMOS General purpose I/O.

CPSB7 AN — Capacitive sensing B input 7.

RD3/CPSA8 RD3 ST CMOS General purpose I/O.

CPSA8 AN — Capacitive sensing A input 8.

RD4/CPSA12

RD5/CPSA13

RD6/CPSA14

RD7/CPSA15

RE0/AN5/CPSA5 RE0 ST CMOS General purpose I/O.

RE1/AN6/CPSA6 RE1 ST CMOS General purpose I/O.

RE2/AN7/CPSA7 RE2 ST CMOS General purpose I/O.

RE3/MCLR

V

DD VDD Power — Positive supply.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

/VPP RE3 TTL — General purpose input.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

RD4 ST

CPSA12 AN — Capacitive sensing A input 12.

RD5 ST

CPSA13 AN — Capacitive sensing A input 13.

RD6 ST

CPSA14 AN — Capacitive sensing A input 14.

RD7 ST

CPSA15 AN — Capacitive sensing A input 15.

AN5 AN — A/D Channel 5 input.

CPSA5 AN — Capacitive sensing A input 5.

AN6 AN — A/D Channel 6 input.

CPSA6 AN — Capacitive sensing A input 6.

AN7 AN — A/D Channel 7 input.

CPSA7 AN — Capacitive sensing A input 7.

MCLR

PP HV — Programming voltage.

V

Output

Typ e

2

Typ e

C™ OD I2C™ data input/output.

CMOS

CMOS

CMOS

CMOS

ST — Master Clear with internal pull-up.

General purpose I/O.

General purpose I/O.

General purpose I/O.

General purpose I/O.

Description

2

C™ = Schmitt Trigger input with I2C

 2010 Microchip Technology Inc. Preliminary DS41418A-page 15

PIC16F707/PIC16LF707

TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

V

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note: The PIC16F707 devices have an internal low dropout voltage regulator. An external capacitor must be

connected to one of the available V
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF707 devices do not have the voltage
regulator and therefore no external capacitor is required.

Output

Typ e

Typ e

CAP pins to stabilize the regulator. For more information, see

Description

2

C™ = Schmitt Trigger input with I2C

DS41418A-page 16 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

PC<12:0>

13

0000h

0004h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN
RETFIE, RETLW

Stack Level 2

0005h

On-chip

1FFFh

Program

Memory

Page 0

Page 1

07FFh
0800h

0FFFh
1000h

Page 2

Page 3

17FFh
1800h

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F707/PIC16LF707 has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The Reset vector is at 0000h and the
interrupt vector is at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16F707/PIC16LF707

2.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.

RP1

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.

2.2.1 GENERAL PURPOSE REGISTER

The register file is organized as 363 x 8 bits. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing, INDF and FSR Registers”).

RP0

00 Bank 0 is selected
01 Bank 1 is selected
10 Bank 2 is selected
11 Bank 3 is selected

FILE

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (refer to Table 2-2).
These registers are static RAM.

The Special Function Registers can be classified into

 2010 Microchip Technology Inc. Preliminary DS41418A-page 17

two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.

PIC16F707/PIC16LF707

Legend: = Unimplemented data memory locations, read as ‘0’,

* = Not a physical register

File Address

Indirect addr.

(*)

00h Indirect addr.

(*)

80h Indirect addr.

(*)

100h Indirect addr.

(*)

180h

TMR0 01h OPTION 81h TMR0 101h OPTION 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h TACON 105h

ANSELA

185h

PORTB 06h TRISB 86h

CPSBCON0

106h

ANSELB

186h

PORTC 07h TRISC 87h

CPSBCON1

107h ANSELC 187h

PORTD 08h TRISD 88h

CPSACON0

108h

ANSELD

188h

PORTE 09h TRISE 89h

CPSACON1

109h

ANSELE

189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch

PIR2 0Dh PIE2 8Dh PMADRL 10Dh

Reserved 18Dh

TMR1L 0Eh PCON 8Eh PMDATH 10Eh

Reserved 18Eh

TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh

Reserved 18Fh

T1CON 10h OSCCON 90h TMRA 110h

General
Purpose
Register

16 Bytes

190h

TMR2 11h OSCTUNE 91h TBCON 111h 191h

T2CON 12h PR2 92h TMRB 112h 192h

SSPBUF 13h SSPADD/SSPMSK 93h DACCON0 113h 193h

SSPCON 14h SSPSTAT 94h DACCON1 114h 194h

CCPR1L 15h WPUB 95h

General
Purpose
Register
11 Bytes

115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h T3CON 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah TMR3L 9Ah 11Ah 19Ah

CCPR2L 1Bh TMR3H 9Bh 11Bh 19Bh

CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch

CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh

ADRES

1Eh T3GCON 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General
Purpose
Register
96 Bytes

20h

7Fh

General
Purpose
Register
80 Bytes

A0h

EFh

General
Purpose
Register

80 Bytes

120h

16Fh

General
Purpose
Register

80 Bytes

1A0h

1EFh

Accesses

70h – 7Fh

F0h

FFh

Accesses

70h – 7Fh

170h

17Fh

Accesses

70h – 7Fh

1F0h

1FFh

BANK 0 BANK 1 BANK 2 BANK 3

TABLE 2-1: DATA MEMORY MAP FOR PIC16F707/PIC16LF707

DS41418A-page 18 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

(2)

00h

01h TMR0 Timer0 Module Register 0000 0000 0000 0000

02h

03h

04h

05h PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h PORTE

0Ah

0Bh

0Ch PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

11h TMR2 Timer2 Module Register 0000 0000 0000 0000

12h T2CON

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transmit Data Register 0000 0000 0000 0000

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

1Dh CCP2CON

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

— — — — RE3 RE2 RE1 RE0 ---- xxxx ---- uuuu

— — — CCP2IF 0000 ---0 0000 ---0

—TMR1ON0000 00-0 uuuu uu-u

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

Val ue o n:

POR, BOR

Value on all

other

resets

 2010 Microchip Technology Inc. Preliminary DS41418A-page 19

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(2)

80h

81h OPTION_REG RBPU

82h

83h

84h

85h TRISA PORTA Data Direction Register 1111 1111 1111 1111

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h TRISD PORTD Data Direction Register 1111 1111 1111 1111

89h TRISE

8Ah

8Bh

8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE

8Eh PCON

8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

90h OSCCON

91h OSCTUNE

92h PR2 Timer2 Period Register 1111 1111 1111 1111

93h SSPADD Synchronous Serial Port (I

93h

94h SSPSTAT SMP CKE D/A

95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000

97h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0

98h TXSTA CSRC TX9 TXEN SYNC

99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

9Ah TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu

9Bh TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu

9Ch APFCON

9Dh FVRCON FVRRDY FVREN

9Eh T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/

9Fh ADCON1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

(3)

SSPMSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— — — — ‘1’ TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111

— — — CCP2IE 0000 ---0 0000 ---0

— — — — — —PORBOR ---- --qq ---- --uu

DONE

— — IRCF1 IRCF0 ICSL ICSS — — --10 00-- --10 uu--

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000

2

C mode) Address Register 0000 0000 0000 0000

PSR/WUA BF 0000 0000 0000 0000

— T3SYNC —TMR3ON0000 -0-0 uuuu -u-u

— BRGH TRMT TX9D 0000 -010 0000 -010

— — — — — — SSSEL CCP2SEL ---- --00 ---- --00

— — CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 x000 0000 x000 0000

DONE

— ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 -000 --00 -000 --00

T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

T3GVAL T3GSS1 T3GSS0 0000 0x00 uuuu uxuu

Val ue o n:

POR, BOR

Value on all

other

resets

DS41418A-page 20 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

(2)

100h

101h TMR0 Timer0 Module Register 0000 0000 0000 0000

102h

103h

104h

105h TACON TMRAON

106h CPSBCON0 CPSBON CPSBRM

107h CPSBCON1

108h CPSACON0 CPSAON CPSARM

109h CPSACON1

10Ah

10Bh

10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

10Dh PMADRL Program Memory Read Address Register Low Byte xxxx xxxx uuuu uuuu

10Eh PMDATH

10Fh PMADRH

110h TMRA TimerA Module Register 0000 0000 0000 0000

111h TBCON TMRBON

112h TMRB TimerB Module Register 0000 0000 0000 0000

113h DACCON0 DACEN DACLPS DACOE

114h DACCON1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

— TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000

— — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

— — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

— — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 0--- 0000 0--- 0000

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

— — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

— — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— — — Program Memory Read Address Register High Byte ---x xxxx ---u uuuu

— TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000

— DACPSS1 DACPSS0 — — 000- 00-- 000- 00--

— — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000

Val ue o n:

POR, BOR

Value on all

other

resets

 2010 Microchip Technology Inc. Preliminary DS41418A-page 21

PIC16F707/PIC16LF707

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

(2)

180h

181h OPTION_REG RB

182h

183h

184h

185h ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111

186h ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111

187h ANSELC ANSC7 ANSC6 ANSC5

188h ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111

189h ANSELE

18Ah

18Bh

18Ch PMCON1

18Dh — Reserved — —

18Eh — Reserved — —

18Fh — Reserved — —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

Shaded locations are unimplemented, read as ‘0’.

upper byte of the program counter.

2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.

PU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— — ANSC2 ANSC1 ANSC0 111- -111 111- -111

— — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

— — — — — — —RD1--- ---0 1--- ---0

Val ue o n:

POR, BOR

Value on all

other

resets

DS41418A-page 22 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 23.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow and

Digit Borrow
subtraction.

out bits, respectively, in

REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

(1)

C

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(1)

(1)

Note 1: For Borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 23

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

PIC16F707/PIC16LF707

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Bit Value Timer0 Rate WDT Rate

2.2.2.2 OPTION register

The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:

• Timer0/WDT prescaler

• External RB0/INT interrupt

•Timer0

• Weak pull-ups on PORTB

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by
setting PSA bit of the OPTION register to
‘1’. Refer to Section 13.3 “Timer1/3
Prescaler”.

bit 7 R

BPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual bits in the WPUB register

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 5 TMR0CS: Timer0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (F

OSC/4)

bit 4 TMR0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

DS41418A-page 24 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2.2.2.3 PCON Register

The Power Control (PCON) register contains flag bits
(refer to Table 3-4) to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

The PCON register bits are shown in Register 2-3.

REGISTER 2-3: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

)

: Power-on Reset Status bit

: Brown-out Reset Status bit

occurs)

 2010 Microchip Technology Inc. Preliminary DS41418A-page 25

PIC16F707/PIC16LF707

PC

12 8 7 0

5

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE<10:0>

8

PC

12 11 10 0

11

PCLATH<4:3>

PCH PCL

87

2

PCLATH

PCH PCL

PCL as

Destination

ORG 500h
PAGESEL SUB_P1 ;Select page 1

;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 900h ;page 1 (800h-FFFh)

SUB1_P1

: ;called subroutine

;page 1 (800h-FFFh)
:
RETURN ;return to

;Call subroutine

;in page 0

;(000h-7FFh)

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from
PCLATH. On any Reset, the PC is cleared. Figure 2-2
shows the two situations for the loading of the PC. The
upper example in Figure 2-2 shows how the PC is
loaded on a write to PCL (PCLATH<4:0>  PCH).
The lower example in Figure 2-2 shows how the PC is
loaded during a CALL or GOTO instruction
(PCLATH<4:3>  PCH).

FIGURE 2-2: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When
performing a table read using a computed GOTO
method, care should be exercised if the table location
crosses a PCL memory boundary (each 256-byte
block). Refer to Application Note AN556,
“Implementing a Table Read” (DS00556).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc­tions or the vectoring to an interrupt
address.

2.4 Program Memory Paging

All devices are capable of addressing a continuous 8K
word block of program memory. The CALL and GOTO
instructions provide only 11 bits of address to allow
branching within any 2K program memory page. When
doing a CALL or GOTO instruction, the upper 2 bits of
the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is POPed off the stack. Therefore,
manipulation of the PCLATH<4:3> bits is not required
for the RETURN instructions (which POPs the address
from the stack).

Note: The contents of the PCLATH register are

unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis­ter for any subsequent subroutine calls or
GOTO instructions.

Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine

EXAMPLE 2-1: CALL OF A SUBROUTINE

(if interrupts are used).

IN PAGE 1 FROM PAGE 0

2.3.2 STACK

All devices have an 8-level x 13-bit wide hardware
stack (refer to Figure 2-1). The stack space is not part
of either program or data space and the Stack Pointer
is not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an
interrupt causes a branch. The stack is POPed in the
event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.

The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).

DS41418A-page 26 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

MOVLW 020h ;initialize pointer
MOVWF FSR ;to RAM
BANKISEL 020h

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next

CONTINUE ;yes continue

Note: For memory map detail, refer to Table 2-2.

Data
Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1 RP0 6

0

From Opcode

IRP File Select Register

7

0

Bank Select

Location Select

00 01 10 11

180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-3.

A simple program to clear RAM location 020h-02Fh
using indirect addressing is shown in Example 2-2.

FIGURE 2-3: DIRECT/INDIRECT ADDRESSING

EXAMPLE 2-2: INDIRECT ADDRESSING

 2010 Microchip Technology Inc. Preliminary DS41418A-page 27

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 28 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

MCLR/VPP

VDD

OSC1/

WDT

Module

POR

OST/PWRT

WDTOSC

WDT
Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

11-bit Ripple Counter

Reset

Enable OST

Enable PWRT

Sleep

Brown-out

(1)

Reset

BOREN

CLKIN

Note 1: Refer to the Configuration Word Register 1 (Register 8-1).

MCLRE

3.0 RESETS

Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal

The PIC16F707/PIC16LF707 differentiates between
various kinds of Reset:

a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR
e) MCLR

Reset during normal operation
Reset during Sleep

f) Brown-out Reset (BOR)

operation. TO

and PD bits are set or cleared differently
in different Reset situations, as indicated in Table 3-3.
These bits are used in software to determine the nature
of the Reset.

A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.

The MCLR

Reset path has a noise filter to detect and

ignore small pulses. See Section 25.0 “Electrical
Specifications” for pulse width specifications.

Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:

• Power-on Reset (POR)

•MCLR

•MCLR

Reset
Reset during Sleep

•WDT Reset

• Brown-out Reset (BOR)

FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

 2010 Microchip Technology Inc. Preliminary DS41418A-page 29

PIC16F707/PIC16LF707

TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE

POR BOR TO PD Condition

0x11Power-on Reset or LDO Reset

0x0xIllegal, TO

0xx0Illegal, PD is set on POR

1011Brown-out Reset

1101WDT Reset

1100WDT Wake-up

11uuMCLR

1110MCLR

is set on POR

Reset during normal operation

Reset during Sleep or interrupt wake-up from Sleep

(1)

(2)

STATUS

Register

uuu1 0uuu ---- --uu

PCON

Register

TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 0000h 000u uuuu ---- --uu

Reset during Sleep 0000h 0001 0uuu ---- --uu

MCLR

WDT Reset 0000h 0000 1uuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 0000h 0001 1uuu ---- --u0

Interrupt Wake-up from Sleep PC + 1

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program
Counter

DS41418A-page 30 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

VDD

PIC® MCU

MCLR

R1
10 k

C1

0.1 F

3.1 MCLR

The PIC16F707/PIC16LF707 has a noise filter in the

Reset path. The filter will detect and ignore

MCLR
small pulses.

It should be noted that a Reset does not drive the

pin low.

MCLR

Voltages applied to the pin that exceed its specification
can result in both MCLR
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.

An internal MCLR
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RE3/MCLR
becomes an external Reset input. In this mode, the
RE3/MCLR pin has a weak pull-up to VDD. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.

FIGURE 3-2: RECOMMENDED MCLR

Resets and excessive current

option is enabled by clearing the

pin

CIRCUIT

3.3 Power-up Timer (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
oscillator. For more information, see Section 7.3
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the

DD to rise to an acceptable level. A Configuration bit,

V
PWRTE
grammed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.

The Power-up Timer delay will vary from chip-to-chip
and vary due to:

•V

• Temperature variation

• Process variation

See DC parameters for details (Section 25.0
“Electrical Specifications”).

, can disable (if set) or enable (if cleared or pro-

DD variation

Note: The Power-up Timer is enabled by the

PWRTE

bit in the Configuration Word 1.

3.4 Watchdog Timer (WDT)

3.2 Power-on Reset (POR)

The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for V
Section 25.0 “Electrical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until V
“Brown-Out Reset (BOR)”).

When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.

For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).

DD reaches VBOR (see Section 3.5

DD is required. See

The WDT has the following features:

• Shares an 8-bit prescaler with Timer0

• Time-out period is from 17 ms to 2.2 seconds,

nominal

• Enabled by a Configuration bit

WDT is cleared under certain conditions described in
Table 3-3.

3.4.1 WDT OSCILLATOR

The WDT derives its time base from 31 kHz internal
oscillator.

Note: When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).

 2010 Microchip Technology Inc. Preliminary DS41418A-page 31

PIC16F707/PIC16LF707

From TMR0

Postscaler

8

PS<2:0>

PSA

TO TMR0

1

10

0

Clock Source

To T x G

Divide by

512

WDTE

TMRxGE

TxGSS = 11

WDTE

WDT Reset

Low-Power

WDT OSC

3.4.2 WDT CONTROL

The WDTE bit is located in the Configuration Word
Register 1. When set, the WDT runs continuously.

The PSA and PS<2:0> bits of the OPTION register
control the WDT period. See Section 12.0 “Timer0

Module” for more information.

FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 3-3: WDT STATUS

Conditions WDT

WDTE = 0 Cleared

CLRWDT Command

Exit Sleep + System Clock = EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

DS41418A-page 32 Preliminary  2010 Microchip Technology Inc.

3.5 Brown-Out Reset (BOR)

64 ms

(1)

VBOR

V

DD

Internal

Reset

VBOR

V

DD

Internal

Reset

64 ms

(1)

< 64 ms

64 ms

(1)

VBOR

V

DD

Internal

Reset

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

Brown-out Reset is enabled by programming the
BOREN<1:0> bits in the Configuration register. The
brown-out trip point is selectable from two trip points
via the BORV bit in the Configuration register.

Between the POR and BOR, complete voltage range
coverage for execution protection can be imple­mented.

Two bits are used to enable the BOR. When
BOREN = 11, the BOR is always enabled. When
BOREN = 10, the BOR is enabled, but disabled during
Sleep. When BOREN = 0X, the BOR is disabled.

FIGURE 3-4: BROWN-OUT SITUATIONS

PIC16F707/PIC16LF707

DD falls below VBOR for greater than parameter

If V

BOR) (see Section 25.0 “Electrical Specifica-

(T
tions”), the brown-out situation will reset the device.
This will occur regardless of VDD slew rate. A Reset is
not ensured to occur if V
than parameter (T

DD drops below VBOR while the Power-up Timer is

If V
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once V
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.

Note: When erasing Flash program memory, the

BOR is forced to enabled at the minimum
BOR setting to ensure that any code
protection circuitry is operating properly.

DD falls below VBOR for more

BOR).

DD

 2010 Microchip Technology Inc. Preliminary DS41418A-page 33

PIC16F707/PIC16LF707

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

3.6 Time-out Sequence

On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configu­ration and PWRTE
with PWRTE
time-out at all. Figure 3-5, Figure 3-6 and Figure 3-7
depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR
(see Figure 3-6). This is useful for testing purposes or
to synchronize more than one PIC16F707/
PIC16LF707 device operating in parallel.

Table 3-2 shows the Reset conditions for some special
registers.

bit status. For example, in EC mode

bit = 1 (PWRT disabled), there will be no

high will begin execution immediately

3.7 Power Control (PCON) Register

The Power Control (PCON) register has two Status bits
to indicate what type of Reset that last occurred.

Bit 0 is BOR
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word register).

Bit 1 is POR
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR
Power-on Reset has occurred (i.e., V
gone too low).

For more information, see Section 3.5 “Brown-Out
Reset (BOR)”.

(Brown-out Reset). BOR is unknown on

(Power-on Reset). It is a ‘0’ on Power-on

is ‘0’, it will indicate that a

DD may have

TABLE 3-4: TIME-OUT IN VARIOUS SITUATIONS

Oscillator Configuration

XT, HS, LP

RC, EC, INTOSC TPWRT —TPWRT ——

PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1

T

PWRT + 1024 •

Power-up Brown-out Reset

1024 • TOSC TPWRT + 1024 •

T

OSC

T

OSC

1024 • TOSC 1024 • TOSC

Wake-up from

Sleep

FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

DS41418A-page 34 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

T

PWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR

WITH VDD): CASE 3

 2010 Microchip Technology Inc. Preliminary DS41418A-page 35

PIC16F707/PIC16LF707

TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS

Register Address

Power-on Reset/

Brown-out Reset

(1)

MCLR Reset/

WDT Reset

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h/80h/

xxxx xxxx xxxx xxxx uuuu uuuu

100h/180h

TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h/82h/

0000 0000 0000 0000 PC + 1

102h/182h

STATUS 03h/83h/

0001 1xxx 000q quuu

(4)

103h/183h

FSR 04h/84h/

xxxx xxxx uuuu uuuu uuuu uuuu

104h/184h

PORTA 05h xxxx xxxx xxxx xxxx uuuu uuuu

PORTB 06h xxxx xxxx xxxx xxxx uuuu uuuu

PORTC 07h xxxx xxxx xxxx xxxx uuuu uuuu

PORTD 08h xxxx xxxx xxxx xxxx uuuu uuuu

PORTE 09h ---- xxxx ---- xxxx ---- uuuu

PCLATH 0Ah/8Ah/

---0 0000 ---0 0000 ---u uuuu

10Ah/18Ah

INTCON 0Bh/8Bh/

0000 000x 0000 000x uuuu uuuu

10Bh/18Bh

PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu

PIR2 0Dh 0000 ---0 0000 ---0 uuuu ---u

TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 10h 0000 00-0 uuuu uu-u uuuu uu-u

TMR2 11h 0000 0000 0000 0000 uuuu uuuu

T2CON 12h -000 0000 -000 0000 -uuu uuuu

SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu

SSPCON 14h 0000 0000 0000 0000 uuuu uuuu

CCPR1L 15h xxxx xxxx xxxx xxxx uuuu uuuu

CCPR1H 16h xxxx xxxx xxxx xxxx uuuu uuuu

CCP1CON 17h --00 0000 --00 0000 --uu uuuu

RCSTA 18h 0000 000x 0000 000x uuuu uuuu

TXREG 19h 0000 0000 0000 0000 uuuu uuuu

RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu

CCPR2L 1Bh xxxx xxxx xxxx xxxx uuuu uuuu

CCPR2H 1Ch xxxx xxxx xxxx xxxx uuuu uuuu

CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu

ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu

Legend: u = unchanged, x = unknown,
Note 1: If V

DD goes too low, Power-on Reset will be activated and registers will be affected differently.

- = unimplemented bit, reads as ‘0’, q = value depends on condition.

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 3-2 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

Wake-up from Sleep through

Interrupt/Time-out

(3)

uuuq quuu

(4)

(2)

(2)

(2)

DS41418A-page 36 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Register Address

ADCON0 1Fh --00 0000 --00 0000 --uu uuuu

OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h 1111 1111 1111 1111 uuuu uuuu

TRISB 86h 1111 1111 1111 1111 uuuu uuuu

TRISC 87h 1111 1111 1111 1111 uuuu uuuu

TRISD 88h 1111 1111 1111 1111 uuuu uuuu

TRISE 89h ---- 1111 ---- 1111 ---- uuuu

PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu

PIE2 8Dh 0000 ---0 0000 ---0 uuuu ---u

PCON 8Eh ---- --qq ---- --uu

T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu

OSCCON 90h --10 qq-- --10 qq-- --uu qq--

OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu

PR2 92h 1111 1111 1111 1111 uuuu uuuu

SSPADD 93h 0000 0000 0000 0000 uuuu uuuu

SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu

SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu

WPUB 95h 1111 1111 1111 1111 uuuu uuuu

IOCB 96h 0000 0000 0000 0000 uuuu uuuu

T3CON 97h 0000 -0-0 0000 -0-0 uuuu -u-u

TXSTA 98h 0000 -010 0000 -010 uuuu -uuu

SPBRG 99h 0000 0000 0000 0000 uuuu uuuu

TMR3L 9Ah xxxx xxxx uuuu uuuu uuuu uuuu

TMR3H 9Bh xxxx xxxx uuuu uuuu uuuu uuuu

APFCON 9Ch ---- --00 ---- --00 ---- --uu

FVRCON 9Dh q000 0000 q000 0000 q000 0000

ADCON1 9Fh -000 --00 -000 --00 -uuu --uu

TACO N 10 5h 0-00 0000 0-00 0000 u-uu uuuu

CPSBCON0 106h 00-- 0000 00-- 0000 uu-- uuuu

CPSBCON1 107h ---- 0000 ---- 0000 ---- uuuu

CPSACON0 108h 00-- 0000 00-- 0000 uu-- uuuu

CPSACON1 109h ---- 0000 ---- 0000 ---- uuuu

PMDATL 10Ch xxxx xxxx xxxx xxxx uuuu uuuu

PMADRL 10Dh xxxx xxxx xxxx xxxx uuuu uuuu

PMDATH 10Eh --xx xxxx --xx xxxx --uu uuuu

PMADRH 10Fh ---x xxxx ---x xxxx ---u uuuu

TMRA 110h 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown,
Note 1: If V

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

4: See Table 3-2 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

DD goes too low, Power-on Reset will be activated and registers will be affected differently.

vector (0004h).

Power-on Reset/

Brown-out Reset

- = unimplemented bit, reads as ‘0’, q = value depends on condition.

(1)

MCLR Reset/

WDT Reset

(1,5)

Wake-up from Sleep through

Interrupt/Time-out

---- --uu

 2010 Microchip Technology Inc. Preliminary DS41418A-page 37

PIC16F707/PIC16LF707

TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Register Address

TBC ON 111 h 0-00 0000 0-00 0000 u-uu uuuu

TMRB 112h 0000 0000 0000 0000 uuuu uuuu

DACCON0 113h 000- 00-- 000- 00-- uuu- uu--

DACCON1 114h ---0 0000 ---0 0000 ---u uuuu

ANSELA 185h 1111 1111 1111 1111 uuuu uuuu

ANSELB 186h 1111 1111 1111 1111 uuuu uuuu

ANSELC 187h 1111 1111 1111 1111 uuuu uuuu

ANSELD 188h 1111 1111 1111 1111 uuuu uuuu

ANSELE 189h ---- -111 ---- -111 ---- -uuu

PMCON1 18Ch 1--- ---0 1--- ---0 u--- ---u

Legend: u = unchanged, x = unknown,
Note 1: If V

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

4: See Table 3-2 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

DD goes too low, Power-on Reset will be activated and registers will be affected differently.

vector (0004h).

Power-on Reset/

Brown-out Reset

- = unimplemented bit, reads as ‘0’, q = value depends on condition.

(1)

MCLR Reset/

WDT Reset

Wake-up from Sleep through

Interrupt/Time-out

TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

PCON

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are

Note 1: Other (non Power-up) Resets include MCLR

— — — — — —PORBOR ---- --qq ---- --uu

not used by Resets.

Reset and Watchdog Timer Reset during normal operation.

Value on

POR, BOR

Value on

all other

(1)

Resets

DS41418A-page 38 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TMR0IF
TMR0IE

INTF
INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in Sleep mode)

(1)

Interrupt to CPU

TMR1GIE

TMR1GIF

ADIF
ADIE

IOC-RB0

IOCB0

IOC-RB1

IOCB1

IOC-RB2

IOCB2

IOC-RB3

IOCB3

CCP1IF
CCP1IE

IOC-RB4

IOCB4

IOC-RB5

IOCB5

IOC-RB6

IOCB6

IOC-RB7

IOCB7

RCIF
RCIE

TMR2IE

TMR2IF

SSPIE

SSPIF

TXIE

TXIF

TMR1IE

TMR1IF

Note 1: Some peripherals depend upon the

system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 21.1
“Wake-up from Sleep”.

CCP2IF
CCP2IE

TMRAIF
TMRAIE

TMR3IF
TMR3IE

TMR3GIF
TMR3GIE

TMRBIF
TMRBIE

4.0 INTERRUPTS

The PIC16F707/PIC16LF707 device family features an
interruptible core, allowing certain events to preempt
normal program flow. An Interrupt Service Routine
(ISR) is used to determine the source of the interrupt
and act accordingly. Some interrupts can be configured
to wake the MCU from Sleep mode.

The PIC16F707 family has 16 interrupt sources,
differentiated by corresponding interrupt enable and
flag bits:

• Timer0 Overflow Interrupt

• External Edge Detect on INT Pin Interrupt

• PORTB Change Interrupt

• Timer1 Gate Interrupt

• A/D Conversion Complete Interrupt

FIGURE 4-1: INTERRUPT LOGIC

• AUSART Receive Interrupt

• AUSART Transmit Interrupt

• SSP Event Interrupt

• CCP1 Event Interrupt

• Timer2 Match with PR2 Interrupt

• Timer1 Overflow Interrupt

• CCP2 Event Interrupt

• TimerA Overflow Interrupt

• TimerB Overflow Interrupt

• Timer3 Overflow Interrupt

• Timer3 Gate Interrupt

A block diagram of the interrupt logic is shown in
Figure 4-1.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 39

PIC16F707/PIC16LF707

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF flag
(INTCON<1>)

GIE bit
(INTCON<7>)

INSTRUCTION FLOW

PC

Instruction
Fetched

Instruction
Executed

Interrupt Latency

PC

PC + 1

PC + 1 0004h 0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 T

CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

4.1 Operation

Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt enable bit(s) for the specific interrupt
event(s)

• PEIE bit of the INTCON register (if the interrupt
enable bit of the interrupt event is contained in the
PIE1 and PIE2 registers)

The INTCON, PIR1 and PIR2 registers record individ­ual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual Interrupt Enable bits.

The following events happen when an interrupt event
occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the
stack

• PC is loaded with the interrupt vector 0004h

The ISR determines the source of the interrupt by
polling the interrupt flag bits. The interrupt flag bits must
be cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the
previous address from the stack and setting the GIE bit.

For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other
enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

4.2 Interrupt Latency

Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 instruction cycles. For asynchronous
interrupts, the latency is 3 to 4 instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.

FIGURE 4-2: INT PIN INTERRUPT TIMING

DS41418A-page 40 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

MOVWF W_TEMP ;Copy W to W_TEMP register
SWAPF STATUS,W ;Swap status to be saved into W

;Swaps are used because they do not affect the status bits
BANKSEL STATUS_TEMP ;Select regardless of current bank
MOVWF STATUS_TEMP ;Copy status to bank zero STATUS_TEMP register
MOVF PCLATH,W ;Copy PCLATH to W register
MOVWF PCLATH_TEMP ;Copy W register to PCLATH_TEMP
:
:(ISR) ;Insert user code here
:
BANKSEL STATUS_TEMP ;Select regardless of current bank
MOVF PCLATH_TEMP,W ;
MOVWF PCLATH ;Restore PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W

4.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate interrupt enable bit(s) set
prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 21.0 “Power-

Down Mode (Sleep)” for more details.

4.4 INT Pin

The external interrupt, INT pin, causes an
asynchronous, edge-triggered interrupt. The INTEDG bit
of the OPTION register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the INTCON register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector. This interrupt is
disabled by clearing the INTE bit of the INTCON register.

4.5 Context Saving

When an interrupt occurs, only the return PC value is
saved to the stack. If the ISR modifies or uses an
instruction that modifies key registers, their values
must be saved at the beginning of the ISR and restored
when the ISR completes. This prevents instructions

following the ISR from using invalid data. Examples of
key registers include the W, STATUS, FSR and
PCLATH registers.

Note: The microcontroller does not normally

require saving the PCLATH register.
However, if computed GOTO’s are used,
the PCLATH register must be saved at the
beginning of the ISR and restored when
the ISR is complete to ensure correct
program flow.

The code shown in Example 4-1 can be used to do the
following.

• Save the W register

• Save the STATUS register

• Save the PCLATH register

• Execute the ISR program

• Restore the PCLATH register

• Restore the STATUS register

• Restore the W register

Since most instructions modify the W register, it must
be saved immediately upon entering the ISR. The
SWAPF instruction is used when saving and restoring
the W and STATUS registers because it will not affect
any bits in the STATUS register. It is useful to place
W_TEMP in shared memory because the ISR cannot
predict which bank will be selected when the interrupt
occurs.

The processor will branch to the interrupt vector by
loading the PC with 0004h. The PCLATH register will
remain unchanged. This requires the ISR to ensure
that the PCLATH register is set properly before using
an instruction that causes PCLATH to be loaded into
the PC. See Section 2.3 “PCL and PCLATH” for
details on PC operation.

EXAMPLE 4-1: SAVING W, STATUS AND PCLATH REGISTERS IN RAM

 2010 Microchip Technology Inc. Preliminary DS41418A-page 41

PIC16F707/PIC16LF707

4.5.1 INTCON REGISTER

The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTB change and
external RB0/INT/SEG0 pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the appropri­ate interrupt flag bits are clear prior to
enabling an interrupt.

REGISTER 4-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE TMR0IE INTE RBIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3 RBIE: PORTB Change Interrupt Enable bit

1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: PORTB Change Interrupt Flag bit

1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in

software)

0 = None of the PORTB general purpose I/O pins have changed state

(1)

(2)

(1)

TMR0IF

(2)

INTF RBIF

Note 1: The appropriate bits in the IOCB register must also be set.

2: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing TMR0IF bit.

DS41418A-page 42 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

4.5.2 PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as
shown in Register 4-2.

REGISTER 4-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enable the Timer1 gate acquisition complete interrupt
0 = Disable the Timer1 gate acquisition complete interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt
0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit

1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 43

PIC16F707/PIC16LF707

4.5.3 PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.

REGISTER 4-3: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0

TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other

‘1’ = Bit is set ‘0’ = Bit is cleared

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

Resets

bit 7 TMR3GIE: Timer3 Gate Interrupt Flag bit

1 = Enable the Timer3 gate acquisition complete interrupt
0 = Disable the Timer3 gate acquisition complete interrupt

bit 6 TMR3IE: Timer3 Overflow Interrupt Enable bit

1 = Enables the Timer3 overflow interrupt
0 = Disables the Timer3 overflow interrupt

bit 5 TMRBIE: TimerB Overflow Interrupt Enable bit

1 = Enables the TimerB interrupt
0 = Disables the TimerB interrupt

bit 4 TMRAIE: TimerA Overflow Interrupt Enable bit

1 = Enables the TimerA interrupt
0 = Disables the TimerA interrupt

bit 3-1 Unimplemented: Read as '0'

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

DS41418A-page 44 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

4.5.4 PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as
shown in Register 4-4.

REGISTER 4-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Timer1 gate is inactive
0 = Timer1 gate is active

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full

bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode

1 = A Timer1 register capture occurred (must be cleared in software)
0 = No Timer1 register capture occurred

Compare mode

1 = A Timer1 register compare match occurred (must be cleared in software)
0 = No Timer1 register compare match occurred

PWM mode:
Unused in this mode

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = The Timer1 register overflowed (must be cleared in software)
0 = The Timer1 register did not overflow

:

:

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 45

PIC16F707/PIC16LF707

4.5.5 PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.

REGISTER 4-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0

TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR3GIF: Timer3 Gate Interrupt Flag bit

1 = Timer3 gate is inactive
0 = Timer3 gate is active

bit 6 TMR3IF: Timer3 Overflow Interrupt Flag bit

1 = Timer3 register overflowed (must be cleared in software)
0 = Timer3 register did not overflow

bit 5 TMRBIF: TimerB Overflow Interrupt Flag bit

1 = TimerB register has overflowed (must be cleared in software)
0 = TimerB register did not overflow

bit 4 TMRAIF: TimerA Overflow Interrupt Flag bit

1 = TimerA register has overflowed (must be cleared in software)
0 = TimerA register did not overflow

bit 3-1 Unimplemented: Read as ‘0’

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A Timer1 register capture occurred (must be cleared in software)
0 = No Timer1 register capture occurred

Compare Mode

1 = A Timer1 register compare match occurred (must be cleared in software)
0 = No Timer1 register compare match occurred

PWM Mode
Unused in this mode

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

DS41418A-page 46 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF

OPTION_REG RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000

PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000

PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by interrupts.

Value on

POR, BOR

0000 000x

Val ue o n
all other

Resets

0000 000x

1111 1111

0000 0000

0000 ---0

0000 0000

0000 ---0

 2010 Microchip Technology Inc. Preliminary DS41418A-page 47

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 48 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR

The PIC16F707 has an internal Low Dropout Regulator
(LDO) which provides operation above 3.6V. The LDO
regulates a voltage for the internal device logic while
permitting the V
voltage. There is no user enable/disable control
available for the LDO, it is always active. The
PIC16LF707 operates at a maximum V
does not incorporate an LDO.

A device I/O pin may be configured as the LDO voltage
output, identified as the V
required, an external low-ESR capacitor may be
connected to the VCAP pin for additional regulator
stability.

The VCAPEN<1:0> bits of Configuration Word 2
determines which pin is assigned as the V
Refer to Table 5-1.

TABLE 5-1: VCAPEN<1:0> SELECT BITS

VCAPEN<1:0> Pin

DD and I/O pins to operate at a higher

DD of 3.6V and

CAP pin. Although not

CAP pin.

00 RA0

01 RA5

10 RA6

11 No VCAP

On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on recommended capacitor values and the
constant current rate, refer to the LDO Regulator
Characteristics Table in Section 25.0 “Electrical

Specifications”.

TABLE 5-2: SUMMARY OF CONFIGURATION WORD WITH LDO

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG2

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
Note 1: PIC16F707 only.

13:8

7:0

— — — — — — — —

— —

VCAPEN1

(1)

VCAPEN0

(1)

— — — —

Register
on Page

76

 2010 Microchip Technology Inc. Preliminary DS41418A-page 49

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 50 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

QD

CK

Data Register

I/O pin

Read PORTx

Write PORT x

TRISx

Data Bus

To peripherals

ANSELx

VDD

VSS

6.0 I/O PORTS

There are thirty-five general purpose I/O pins available.
Depending on which peripherals are enabled, some or
all of the pins may not be available as general purpose
I/O. In general, when a peripheral is enabled, the
associated pin may not be used as a general purpose
I/O pin.

Each port has two registers for its operation. These
registers are:

• TRISx registers (data direction register)

• PORTx registers (port read/write register)

Ports with analog functions also have an ANSELx
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure 6-1.

FIGURE 6-1: GENERIC I/O PORT

OPERATION

6.1 Alternate Pin Function

The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 6-1. For this device family, the
following functions can be moved between different
pins.

(Slave Select)

•SS

• CCP2

REGISTER 6-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — SSSEL CCP2SEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’.

bit 1 SSSEL: SS

0 =SS function is on RA5/AN4/CPS7/SS/VCAP
1 =SS function is on RA0/AN0/SS/VCAP

bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit

0 = CCP2 function is on RC1/T1OSI/CCP2
1 = CCP2 function is on RB3/CCP2

 2010 Microchip Technology Inc. Preliminary DS41418A-page 51

Input Pin Selection bit

PIC16F707/PIC16LF707

BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ;and set RA<7:4,1:0>

;as outputs

6.2 PORTA and TRISA Registers

PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 6-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 6-1 shows how to
initialize PORTA.

Reading the PORTA register (Register 6-2) reads the

The TRISA register (Register 6-3) controls the PORTA
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISA register are maintained set when using them as
analog inputs. I/O pins configured as analog input
always read ‘0’.

Note: The ANSELA register must be initialized to

configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.

EXAMPLE 6-1: INITIALIZING PORTA

status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch.

REGISTER 6-2: PORTA: PORTA REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RA<7:0>: PORTA I/O Pin bits

1 = Port pin is > V
0 = Port pin is < VIL

IH

REGISTER 6-3: TRISA: PORTA TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

DS41418A-page 52 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

6.2.1 ANSELA REGISTER

The ANSELA register (Register 6-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.

The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.

REGISTER 6-4: ANSELA: PORTA ANALOG SELECT REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit ‘0’ = Bit is cleared

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown

bit 7-0 ANSA<7:0>: Analog Select between Analog or Digital Function on pins RA<7:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.2.2 PIN DESCRIPTIONS

Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the A/D Converter (ADC), refer to the
appropriate section in this data sheet.

(1)

. Digital Input buffer disabled.

6.2.2.2 RA1/AN1/CPSA0

The RA1 pin is configurable to function as one of the
following:

• General purpose I/O

• Analog input for the A/D

• Capacitive sensing input

6.2.2.1 RA0/AN0/VCAP

The RA0 pin is configurable to function as one of the
following:

• General purpose I/O

• Analog input for the A/D

• Slave Select input for the SSP

• Voltage Regulator Capacitor pin (PIC16F707

only)

Note 1: SS pin location may be selected as RA5

or RA0.

(1)

6.2.2.3 RA2/AN2/CPSA1/DACOUT

The RA2 pin is configurable to function as one of the
following:

• General purpose I/O

• Analog input for the A/D

• Capacitive sensing input

• DAC Output

 2010 Microchip Technology Inc. Preliminary DS41418A-page 53

PIC16F707/PIC16LF707

6.2.2.4 RA3/AN3/VREF+/CPSA2

The RA3 pin is configurable to function as one of the
following:

• General purpose I/O

• Analog input for the A/D

• Voltage Reference input for the A/D

• Capacitive sensing input

6.2.2.7 RA6/CPSB1/OSC2/CLKOUT/VCAP

The RA6 pin is configurable to function as one of the
following:

• General purpose I/O

• Crystal/resonator connection

• Clock Output

• Voltage Regulator Capacitor pin (PIC16F707
only)

6.2.2.5 RA4/CPSA3/T0CKI/TACKI

• Capacitive sensing input

The RA4 pin is configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

• Clock input for Timer0

• Clock input for TimerA

The Timer0 clock input function works independently
of any TRIS register setting. Effectively, if TRISA4 = 0,

6.2.2.8 RA7/CPSB0/OSC1/CLKIN

The RA7 pin is configurable to function as one of the
following:

• General purpose I/O

• Crystal/resonator connection

• Clock Input

• Capacitive sensing input.

the PORTA4 register bit will output to the pad and
clock Timer0 at the same time.

6.2.2.6 RA5/AN4/CPSA4/SS/VCAP

The RA5 pin is configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

• Analog input for the A/D

• Slave Select input for the SSP

(1)

• Voltage Regulator Capacitor pin (PIC16F707
only)

Note 1: SS pin location may be selected as RA5

or RA0.

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADCON0

ADCON1

ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111

APFCON

CPSACON0 CPSAON CPSARM

CPSACON1

CPSBCON0 CPSBON CPSBRM

CPSBCON1

CONFIG2

OPTION_REG

PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx

SSPCON

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TAC ON TM RAO N

DACCON0 DACEN DACLPS DACOE

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: PIC16F707 only.

(1)

— — CHS3 CHS2 CHS1 CHS0

— ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 -000 --00 -000 --00

— — — — — — SSSEL CCP2SEL ---- --00 ---- --00

— — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000

— — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

— — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

— — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

— —

RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

VCAPEN1 VCAPEN0

— TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000

— DACPSS1 DACPSS0 — — 000- 00-- 000- 00--

— — — —

GO/DONE

ADON --00 0000 --00 0000

Val ue o n

POR, BOR

——

Val ue o n

all other

Resets

DS41418A-page 54 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

BANKSEL PORTB ;
CLRF PORTB ;Init PORTB
BANKSEL ANSELB
CLRF ANSELB ;Make RB<7:0> digital
BANKSEL TRISB ;
MOVLW B’11110000’ ;Set RB<7:4> as inputs

;and RB<3:0> as outputs

MOVWF TRISB ;

6.3 PORTB and TRISB Registers

PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 6-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-2 shows how to initialize PORTB.

Reading the PORTB register (Register 6-5) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.

The TRISB register (Register 6-6) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’. Example 6-2 shows how to initialize PORTB.

EXAMPLE 6-2: INITIALIZING PORTB

Note: The ANSELB register must be initialized to

configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.

6.3.1 ANSELB REGISTER

The ANSELB register (Register 6-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.

The state of the ANSELB bits has no affect on digital
output functions. A pin with TRIS clear and ANSELB
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write
instructions on the affected port.

6.3.2 WEAK PULL-UPS

Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:0> enable or
disable each pull-up (see Register 6-7). Each weak pull­up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RBPU

bit of the OPTION register.

6.3.3 INTERRUPT-ON-CHANGE

All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:0> enable
or disable the interrupt function for each pin. Refer to
Register 6-8. The interrupt-on-change feature is
disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the present value
is compared with the old value latched on the last read
of PORTB to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTB
Change Interrupt Flag bit (RBIF) in the INTCON
register.

This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear the flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared. The latch
holding the last read value is not affected by a MCLR
Brown-out Reset. After these Resets, the RBIF flag will
continue to be set if a mismatch is present.

nor

 2010 Microchip Technology Inc. Preliminary DS41418A-page 55

Note: When a pin change occurs at the same

time as a read operation on PORTB, the
RBIF flag will always be set. If multiple
PORTB pins are configured for the
interrupt-on-change, the user may not be
able to identify which pin changed state.

PIC16F707/PIC16LF707

REGISTER 6-5: PORTB: PORTB REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RB<7:0>: PORTB I/O Pin bit

1 = Port pin is > V
0 = Port pin is < VIL

REGISTER 6-6: TRISB: PORTB TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

bit 7 bit 0

IH

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output

REGISTER 6-7: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 WPUB<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled
0 = Pull-up disabled

Note 1: Global RBPU

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

bit of the OPTION register must be cleared for individual pull-ups to be enabled.

DS41418A-page 56 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 6-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bits

1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled

REGISTER 6-9: ANSELB: PORTB ANALOG SELECT REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANSB<7:0>: Analog Select between Analog or Digital Function on Pins RB<7:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.3.4 PIN DESCRIPTIONS

Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I
section in this data sheet.

2

C or interrupts, refer to the appropriate

(1)

. Digital input buffer disabled.

6.3.4.2 RB1/AN10/CPSB9

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

6.3.4.1 RB0/AN12/CPSB8/INT

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

• External edge triggered interrupt

6.3.4.3 RB2/AN8/CPSB10

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

 2010 Microchip Technology Inc. Preliminary DS41418A-page 57

PIC16F707/PIC16LF707

6.3.4.4 RB3/AN9/CPSB11/CCP2

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

• Capture 2 input, Compare 2 output, and PWM2
output

Note: CCP2 pin location may be selected as

RB3 or RC1.

6.3.4.5 RB4/AN11/CPSB12

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

6.3.4.6 RB5/AN13/CPSB13/T1G/T3CKI

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

• Timer1 gate input

• Timer3 clock input

6.3.4.7 RB6/ICSPCLK/CPSB14

These pins are configurable to function as one of the
following:

• General purpose I/O

• In-Circuit Serial Programming clock

• Capacitive sensing input

6.3.4.8 RB7/ICSPDAT/CPSB15

These pins are configurable to function as one of the
following:

• General purpose I/O

• In-Circuit Serial Programming data

• Capacitive sensing input

TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADCON0

ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111

APFCON

CCP2CON

CPSBCON0 CPSBON CPSBRM

CPSBCON1

INTCON

IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000

OPTION_REG RBPU

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx

T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0

T1GCON TMR1GE

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

— — — — — — SSSEL CCP2SEL ---- --00 ---- --00

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

— — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

— — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000X

INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— T3SYNC —TMR3ON0000 -0-0 0000 -0-0

T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

Valu e o n

POR, BOR

Value on all

other

Resets

DS41418A-page 58 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

BANKSEL PORTC ;
CLRF PORTC ;Init PORTC
BANKSEL TRISC ;
MOVLW B‘00001100’ ;Set RC<3:2> as inputs
MOVWF TRISC ;and set RC<7:4,1:0>

;as outputs

6.4 PORTC and TRISC Registers

PORTC is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC
(Register 6-11). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-3 shows how to initialize PORTC.

Reading the PORTC register (Register 6-10) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.

The TRISC register (Register 6-11) controls the PORTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.

EXAMPLE 6-3: INITIALIZING PORTC

The location of the CCP2 function is controlled by the
CCP2SEL bit in the APFCON register (see Register 6-1).

REGISTER 6-10: PORTC: PORTC REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits

1 = Port pin is > V
0 = Port pin is < VIL

IH

REGISTER 6-11: TRISC: PORTC TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output

 2010 Microchip Technology Inc. Preliminary DS41418A-page 59

PIC16F707/PIC16LF707

6.4.1 ANSELC REGISTER

The ANSELC register (Register 6-12) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.

The state of the ANSELC bits has no affect on digital
output functions. A pin with TRIS clear and ANSELC
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write instruc­tions on the affected port.

Note: The ANSELC register must be initialized

to configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.

REGISTER 6-12: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1

ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 ANSC<7:5>: Analog Select between Analog or Digital Function on Pins RC<7:5>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input

bit 4-3 Unimplemented: Read as ‘0’

bit 2-0 ANSC<2:0>: Analog Select between Analog or Digital Function on Pins RC<2:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.4.2 PIN DESCRIPTIONS

Each PORTC pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I
section in this data sheet.

2

C or interrupts, refer to the appropriate

6.4.2.1 RC0/T1OSO/T1CKI/CPSB2

These pins are configurable to function as one of the
following:

• General purpose I/O

• Timer1 oscillator output

• Timer1 clock input

• Capacitive sensing input

(1)

. Digital input buffer disabled.

(1)

. Digital input buffer disabled.

6.4.2.2 RC1/T1OSi/CCP2/CPSB3

These pins are configurable to function as one of the
following:

• General purpose I/O

• Timer1 oscillator input

• Capture 2 input, Compare 2 output, and PWM2
output

• Capacitive sensing input

Note: CCP2 pin location may be selected as

RB3 or RC1.

DS41418A-page 60 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

6.4.2.3 RC2/CCP1/CPSB4/TBCKI

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capture 1 input, Compare 1 output, and PWM1
output

• Capacitive sensing input

• TimerB Clock input

6.4.2.4 RC3/SCK/SCL

These pins are configurable to function as one of the
following:

• General purpose I/O

• SPI clock

2

•I

C™ clock

6.4.2.5 RC4/SDI/SDA

These pins are configurable to function as one of the
following:

• General purpose I/O

• SPI data input

2

C data I/O

•I

6.4.2.6 RC5/SDO/CPSA9

These pins are configurable to function as one of the
following:

• General purpose I/O

• SPI data output

• Capacitive sensing input

6.4.2.7 RC6/TX/CK/CPSA10

These pins are configurable to function as one of the
following:

• General purpose I/O

• Asynchronous serial output

• Synchronous clock I/O

• Capacitive sensing input

6.4.2.8 RC7/RX/DT/CPSA11

These pins are configurable to function as one of the
following:

• General purpose I/O

• Asynchronous serial input

• Synchronous serial data I/O

• Capacitive sensing input

TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELC ANSC7 ANSC6 ANSC5

APFCON

CCP1CON

CCP2CON

CPSACON0 CPSAON CPSARM

CPSACON1

CPSBCON0 CPSBON CPSBRM

CPSBCON1

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SSPCON

SSPSTAT SMP

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TBCON TMRBON

TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

— — — — — — SSSEL CCP2SEL ---- --00 ---- --00

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

— — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000

— — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

— — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

— — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

CKE D/A P S R/W UA BF 0000 0000 0000 0000

— TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0

— — ANSC2 ANSC1 ANSC0 111- -111 111- -111

—

TMR1ON 0000 00-0 uuuu uu-u

Value on

POR, BOR

0-00 0000 0-00 0000

Value on all

other

Resets

 2010 Microchip Technology Inc. Preliminary DS41418A-page 61

PIC16F707/PIC16LF707

BANKSEL PORTD ;
CLRF PORTD ;Init PORTD
BANKSEL ANSELD
CLRF ANSELD ;Make PORTD digital
BANKSEL TRISD ;
MOVLW B‘00001100’ ;Set RD<3:2> as inputs
MOVWF TRISD ;and set RD<7:4,1:0>

;as outputs

6.5 PORTD and TRISD Registers

PORTD is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISD
(Register 6-14). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-4 shows how to initialize PORTD.

Reading the PORTD register (Register 6-13) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.

The TRISD register (Register 6-14) controls the
PORTD pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISD register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.

EXAMPLE 6-4: INITIALIZING PORTD

6.5.1 ANSELD REGISTER

The ANSELD register (Register 6-15) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELD bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.

The state of the ANSELD bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.

Note: The ANSELD register must be initialized

to configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.

REGISTER 6-13: PORTD: PORTD REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits

1 = Port pin is > V
0 = Port pin is < VIL

IH

DS41418A-page 62 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 6-14: TRISD: PORTD TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits

1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output

REGISTER 6-15: ANSELD: PORTD ANALOG SELECT REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.5.2 PIN DESCRIPTIONS

Each PORTD pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I
section in this data sheet.

2

C or interrupts, refer to the appropriate

6.5.2.1 RD0/CPSB5/T3G

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

• Timer3 Gate input

6.5.2.2 RD1/CPSB6

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

(1)

. Digital input buffer disabled.

6.5.2.3 RD2/CPSB7

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

6.5.2.4 RD3/CPSA8

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

6.5.2.5 RD4/CPSA12

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

 2010 Microchip Technology Inc. Preliminary DS41418A-page 63

PIC16F707/PIC16LF707

6.5.2.6 RD5/CPSA13

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

6.5.2.8 RD7/CPSA15

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

6.5.2.7 RD6/CPSA14

These pins are configurable to function as one of the
following:

• General purpose I/O

• Capacitive sensing input

TABLE 6-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111

CPSACON0 CPSAON CPSARM

CPSACON1

CPSBCON0 CPSBON CPSBRM

CPSBCON1

T3GCON TMR3GE

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx xxxx xxxx

TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.

— — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

— — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

T3GPOL T3GTM T3GSPM T3GGO/

— — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000

— — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

T3GVAL T3GSS1 T3GSS0 0000 0x00 uuuu uxuu

DONE

Value on

POR, BOR

Value on
all other

Resets

DS41418A-page 64 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

BANKSEL PORTE ;
CLRF PORTE ;Init PORTE
BANKSEL ANSELE ;
CLRF ANSELE ;digital I/O
BANKSEL TRISE ;
MOVLW B‘00001100’ ;Set RE<2> as an input
MOVWF TRISE ;and set RE<1:0>

;as outputs

6.6 PORTE and TRISE Registers

PORTE is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 6-5 shows how to initialize PORTE.

Reading the PORTE register (Register 6-16) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. RE3 reads ‘0’ when
MCLRE = 1.

The TRISE register (Register 6-17) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.

Note: The ANSELE register must be initialized to

configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.

EXAMPLE 6-5: INITIALIZING PORTE

6.6.1 ANSELE REGISTER

The ANSELE register (Register 6-18) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.

The state of the ANSELE bits has no affect on digital
output functions. A pin with TRIS clear and ANSELE
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write
instructions on the affected port.

REGISTER 6-16: PORTE: PORTE REGISTER

U-0 U-0 U-0 U-0 R-x R/W-x R/W-x R/W-x

— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 RE<3:0>: PORTE I/O Pin bits

1 = Port pin is > V
0 = Port pin is < VIL

 2010 Microchip Technology Inc. Preliminary DS41418A-page 65

RE3 RE2 RE1 RE0

IH

PIC16F707/PIC16LF707

REGISTER 6-17: TRISE: PORTE TRI-STATE REGISTER

U-0 U-0 U-0 U-0 R-1 R/W-1 R/W-1 R/W-1

— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3 TRISE3: RE3 Port Tri-state Control bit

This bit is always ‘1’ as RE3 is an input only

bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits

1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output

REGISTER 6-18: ANSELE: PORTE ANALOG SELECT REGISTER

TRISE3 TRISE2 TRISE1 TRISE0

(1)

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

— — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.6.2 PIN DESCRIPTIONS

Each PORTE pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I
section in this data sheet.

2

C or interrupts, refer to the appropriate

6.6.2.1 RE0/AN5/CPSA5

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

(1)

. Digital input buffer disabled.

6.6.2.2 RE1/AN6/CPSA6

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

6.6.2.3 RE2/AN7/CPSA7

These pins are configurable to function as one of the
following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

ANSE2 ANSE1 ANSE0

DS41418A-page 66 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

6.6.2.4 RE3/MCLR/VPP

These pins are configurable to function as one of the
following:

• General purpose input

• Master Clear Reset with weak pull-up

• Programming voltage reference input

TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADCON0

ANSELE

CPSACON0 CPSAON CPSARM

CPSACON1

PORTE

TRISE

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: This bit is always ‘1’ as RE3 is input only.

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

— — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

— — CPSARNG1 CPSARNG0 CPSAOUT TAXCS

— — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0

— — — — RE3 RE2 RE1 RE0 ---- xxxx ---- xxxx

— — — —TRISE3

(1)

TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111

Valu e o n

POR, BOR

00-- 0000 00-- 0000

---- 0000 ---- 0000

Valu e o n
all other

Resets

 2010 Microchip Technology Inc. Preliminary DS41418A-page 67

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 68 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

(CPU and Peripherals)

OSC1

OSC2

Sleep

External Oscillator

LP, XT, HS, RC, EC

System Clock

Postscaler

MUX

MUX

16 MHz/500 kHz

8 MHz/250 kHz

4 MHz/125 kHz

2 MHz/62.5 kHz

IRCF<1:0>

11

10

01

00

FOSC<2:0>

(Configuration Word 1)

Internal Oscillator

(OSCCON Register)

500 kHz

INTOSC

32x

MUX

0

1

PLL

PLLEN

(Configuration Word 1)

7.0 OSCILLATOR MODULE

Clock source modes are configured by the FOSC bits
in Configuration Word 1 (CONFIG1). The oscillator

7.1 Overview

The oscillator module has a wide variety of clock sources
and selection features that allow it to be used in a wide
range of applications while maximizing performance and
minimizing power consumption. Figure 7-1 illustrates a
block diagram of the oscillator module.

Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system can be configured to use an internal calibrated
high-frequency oscillator as clock source, with a choice
of selectable speeds via software.

module can be configured for one of eight modes of
operation.

1. RC – External Resistor-Capacitor (RC) with

OSC/4 output on OSC2/CLKOUT.

F

2. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.

3. INTOSC – Internal oscillator with F
on OSC2 and I/O on OSC1/CLKIN.

4. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.

5. EC – External clock with I/O on OSC2/CLKOUT.

6. HS – High Gain Crystal or Ceramic Resonator
mode.

7. XT – Medium Gain Crystal or Ceramic
Resonator Oscillator mode.

8. LP – Low-Power Crystal mode.

FIGURE 7-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

OSC/4 output

 2010 Microchip Technology Inc. Preliminary DS41418A-page 69

PIC16F707/PIC16LF707

7.2 Clock Source Modes

Clock source modes can be classified as external or
internal.

• Internal clock source (INTOSC) is contained
within the oscillator module and derived from a
500 kHz high precision oscillator. The oscillator
module has eight selectable output frequencies,
with a maximum internal frequency of 16 MHz.

• External clock modes rely on external circuitry for
the clock source. Examples are: oscillator mod­ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.

The system clock can be selected between external or
internal clock sources via the FOSC bits of the
Configuration Word 1.

7.3 Internal Clock Modes

The oscillator module has eight output frequencies
derived from a 500 kHz high precision oscillator. The
IRCF bits of the OSCCON register select the
postscaler applied to the clock source dividing the
frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the
Configuration Word 1 locks the internal clock source to
16 MHz before the postscaler is selected by the IRCF
bits. The PLLEN bit must be set or cleared at the time
of programming; therefore, only the upper or low four
clock source frequencies are selectable in software.

7.3.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is programmed using the oscillator selection
or the FOSC<2:0> bits in the CONFIG1 register. See
Section 8.0 “Device Configuration” for more
information.

In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/
CLKOUT are available for general purpose I/O.

7.3.2 FREQUENCY SELECT BITS (IRCF)

The output of the 500 kHz INTOSC and 16 MHz
INTOSC, with Phase Locked Loop enabled, connect to
a postscaler and multiplexer (see Figure 7-1). The
Internal Oscillator Frequency Select bits (IRCF) of the
OSCCON register select the frequency output of the
internal oscillator. Depending upon the PLLEN bit, one
of four frequencies of two frequency sets can be
selected via software:

If PLLEN = 1, frequency selection is as follows:

•16 MHz

• 8 MHz (Default after Reset)

•4 MHz

•2 MHz

If PLLEN = 0, frequency selection is as follows:

•500 kHz

• 250 kHz (Default after Reset)

•125 kHz

•62.5 kHz

Note: Following any Reset, the IRCF<1:0> bits of

the OSCCON register are set to ‘10’ and
the frequency selection is set to 8 MHz or
250 kHz. The user can modify the IRCF
bits to select a different frequency.

There is no start-up delay before a new frequency
selected in the IRCF bits takes effect. This is because
the old and new frequencies are derived from INTOSC
via the postscaler and multiplexer.

Start-up delay specifications are located in the
Table 25-4 in Section 25.0 “Electrical
Specifications”.

DS41418A-page 70 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

7.4 Oscillator Control

The Oscillator Control (OSCCON) register (Figure 7-1)
displays the status and allows frequency selection of the
internal oscillator (INTOSC) system clock. The
OSCCON register contains the following bits:

• Frequency selection bits (IRCF)

• Status Locked bits (ICSL)

• Status Stable bits (ICSS)

REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 U-0 R/W-1 R/W-0 R-q R-q U-0 U-0

— — IRCF1 IRCF0 ICSL ICSS — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits

When PLLEN = 1 (16 MHz INTOSC)

11 =16MHz
10 = 8 MHz (POR value)
01 =4MHz
00 =2MHz

When PLLEN =

11 = 500 kHz
10 = 250 kHz (POR value)
01 = 125 kHz
00 = 62.5 kHz

bit 3 ICSL: Internal Clock Oscillator Status Locked bit (2% Stable)

1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) is in lock.
0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet locked.

bit 2 ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable)

1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy
0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy

bit 1-0 Unimplemented: Read as ‘0’

0 (500 kHz INTOSC)

 2010 Microchip Technology Inc. Preliminary DS41418A-page 71

PIC16F707/PIC16LF707

7.5 Oscillator Tuning

The INTOSC is factory calibrated but can be adjusted
in software by writing to the OSCTUNE register
(Register 7-2).

The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number.

When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.

REGISTER 7-2: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: Frequency Tuning bits

01 1111 = Maximum frequency
01 1110 =

•

•

•

00 0001 =
00 0000 = Oscillator module is running at the factory-calibrated frequency.
11 1111 =

•

•

•
10 0000 = Minimum frequency

DS41418A-page 72 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

OSC1/CLKIN

OSC2/CLKOUT

(1)

I/O

Clock from
Ext. System

PIC

®

MCU

Note 1: Alternate pin functions are described in

Section 6.1 “Alternate Pin Function”.

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected.

C1

C2

Quartz

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

Crystal

OSC2/CLKOUT

7.6 External Clock Modes

7.6.1 OSCILLATOR START-UP TIMER (OST)

If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations on the OSC1 pin before the device is
released from Reset. This occurs following a Power-on
Reset (POR) and when the Power-up Timer (PWRT)
has expired (if configured), or a wake-up from Sleep.
During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.

7.6.2 EC MODE

The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 7-2 shows the pin
connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

®

MCU design is fully

XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.

HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.

Figure 7-3 and Figure 7-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.

FIGURE 7-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR
HS MODE)

FIGURE 7-2: EXTERNAL CLOCK (EC)

MODE OPERATION

7.6.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 7-3). The mode selects a low,
medium or high gain setting of the internal inverter­amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is best suited
to drive resonators with a low drive level specification, for
example, tuning fork type crystals.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 73

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

®

and PIC®

Devices” (DS00826)

®

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

®

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”
(DS00949)

PIC16F707/PIC16LF707

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected.

3: An additional parallel feedback resistor (R

P)

may be required for proper ceramic resonator
operation.

C1

C2

Ceramic

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

RP

(3)

Resonator

OSC2/CLKOUT

OSC2/CLKOUT

(1)

CEXT

REXT

PIC® MCU

OSC1/CLKIN

F

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  R

EXT  100 k, 3-5V

C

EXT > 20 pF, 2-5V

Note 1: Alternate pin functions are described in

Section 6.1 “Alternate Pin Function”.

2: Output depends upon RC or RCIO clock mode.

I/O

(2)

FIGURE 7-4: CERAMIC RESONATOR

OPERATION
(XT OR HS MODE)

7.6.4 EXTERNAL RC MODES

The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 7-5 shows the
external RC mode connections.

FIGURE 7-5: EXTERNAL RC MODES

In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due
to tolerance of external RC components used.

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CONFIG1

OSCCON

OSCTUNE

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: See Configuration Word 1 (Register 8-1) for operation of all bits.

DS41418A-page 74 Preliminary  2010 Microchip Technology Inc.

(1)

— CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

— — IRCF1 IRCF0 ICSL ICSS — — --10 qq-- --10 qq--

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --uu uuuu

Value on

POR, BOR

Value on

all other

(1)

Resets

PIC16F707/PIC16LF707

8.0 DEVICE CONFIGURATION

Device Configuration consists of Configuration Word 1
and Configuration Word 2 registers, Code Protection
and Device ID.

8.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1
register at 2007h and Configuration Word 2 register at
2008h. These registers are only accessible during
programming.

REGISTER 8-1: CONFIG1: CONFIGURATION WORD REGISTER 1

R/P-1 R/P-1 U-1

— —DEBUGPLLEN — BORV BOREN1 BOREN0

bit 15 bit 8

(4)

U-1

—CPMCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

bit 7 bit 0

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13 DEBUG

bit 12 PLLEN: INTOSC PLL Enable bit

bit 11 Unimplemented: Read as ‘1’

bit 10 BORV: Brown-out Reset Voltage Selection bit

bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits

bit 7 Unimplemented: Read as ‘1’

bit 6 CP

bit 5 MCLRE: RE3/MCLR

bit 4 PWRTE: Power-up Timer Enable bit

bit 3 WDTE: Watchdog Timer Enable bit

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger

0 = INTOSC Frequency is 500 kHz
1 = INTOSC Frequency is 16 MHz (32x)

0 = Brown-out Reset Voltage (V
1 = Brown-out Reset Voltage (V

0x = BOR disabled (Preconditioned State)
10 = BOR enabled during operation and disabled in Sleep
11 = BOR enabled

: Code Protection bit

1 = Program memory code protection is disabled
0 = Program memory code protection is enabled

Pin Function Select bit

1 = RE3/MCLR pin function is MCLR
0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD

1 = PWRT disabled
0 = PWRT enabled

1 = WDT enabled
0 = WDT disabled

BOR) set to 2.5 V nominal
BOR) set to 1.9 V nominal

(1)

(2)

(3)

(4)

R/P-1 R/P-1 R/P-1

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire program memory will be erased when the code protection is turned off.
3: When MCLR
4: MPLAB

 2010 Microchip Technology Inc. Preliminary DS41418A-page 75

is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

®

IDE masks unimplemented Configuration bits to ‘0’.

PIC16F707/PIC16LF707

REGISTER 8-1: CONFIG1: CONFIGURATION WORD REGISTER 1 (CONTINUED)

bit 2-0 FOSC<2:0>: Oscillator Selection bits

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire program memory will be erased when the code protection is turned off.
3: When MCLR
4: MPLAB

111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

®

IDE masks unimplemented Configuration bits to ‘0’.

REGISTER 8-2: CONFIG2: CONFIGURATION WORD REGISTER 2

(1)

U-1

— — — — — — — —

bit 15 bit 8

(1)

U-1

— —

bit 7 bit 0

U-1

U-1

(1)

(1)

U-1

(1)

U-1

(1)

R/P-1 R/P-1 U-1

VCAPEN1 VCAPEN0

U-1

(1)

(1)

U-1

U-1

(1)

(1)

U-1

U-1

(1)

(1)

— — — —

U-1

U-1

(1)

(1)

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘1’

bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits

For the PIC16LF707
These bits are ignored. All V
For the PIC16F707

00 =V
01 =V
10 =V
11 = All V

CAP functionality is enabled on RA0
CAP functionality is enabled on RA5
CAP functionality is enabled on RA6

CAP functions are disabled (not recommended)

:

CAP pin functions are disabled.

:

bit 3-0 Unimplemented: Read as ‘1’

®

Note 1: MPLAB

IDE masks unimplemented Configuration bits to ‘0’.

DS41418A-page 76 Preliminary  2010 Microchip Technology Inc.

8.2 Code Protection

If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.

Note: The entire Flash program memory will be

erased when the code protection is turned
off. See the “PIC16F707/PIC16LF707

Memory Programming Specification”

(DS41332) for more information.

8.3 User ID

Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read­able and writable during Program/Verify mode. Only
the Least Significant 7 bits of the ID locations are
reported when using MPLAB IDE. See the
“PIC16F707/PIC16LF707 Memory Programming
Specification” (DS41332) for more information.

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 77

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 78 Preliminary  2010 Microchip Technology Inc.

9.0 ANALOG-TO-DIGITAL

AN0

AN1

AN2

AN4

AVDD

VREF+

ADON

GO/DONE

ADREF = 10

ADREF = 0x

CHS<3:0>

VSS

AN5

AN6

AN7

AN3

AN8

AN9

AN10

AN11

AN12

AN13

Reserved

FV

REF

0000

0001

0010

0011

0100

0101

0111

0110

1000

1001

1010

1011

1100

1101

1110

1111

8

ADC

ADRES

ADREF = 11

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 8-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 8-bit binary result via successive
approximation and stores the conversion result into the
ADC result register (ADRES). Figure 9-1 shows the
block diagram of the ADC.

The ADC voltage reference is software selectable to be
either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.

FIGURE 9-1: ADC BLOCK DIAGRAM

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 79

PIC16F707/PIC16LF707

9.1 ADC Configuration

When configuring and using the ADC the following
functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Results formatting

9.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to Section 6.0

“I/O Ports” for more information.

Note: Analog voltages on any pin that is defined

as a digital input may cause the input
buffer to conduct excess current.

9.1.2 CHANNEL SELECTION

The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.

When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.

9.1.3 ADC VOLTAGE REFERENCE

The ADREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be either V

DD, an external

voltage source or the internal Fixed Voltage Reference.
The negative voltage reference is always connected to
the ground reference. See Section 10.0 “Fixed
Voltage Reference” for more details on the Fixed
Voltage Reference.

9.1.4 CONVERSION CLOCK

The source of the conversion clock is software select­able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:

OSC/2

•F

•F

OSC/4

•FOSC/8

•FOSC/16

•F

OSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

AD. One full 8-bit conversion requires 10 TAD periods

T
as shown in Figure 9-2.

For correct conversion, the appropriate T
specification must be met. Refer to the A/D conversion
requirements in Section 25.0 “Electrical
Specifications” for more information. Table 9-1 gives
examples of appropriate ADC clock selections.

AD

Note: Unless using the FRC, any changes in the

system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.

TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD) Device Frequency (FOSC)

ADC

Clock Source

Fosc/2 000

Fosc/4 100 200 ns

Fosc/8 001 400 ns

Fosc/16 101 800 ns 1.0 s2.0 s4.0 s 16.0 s
Fosc/32 010 1.6 s2.0 s4.0 s 8.0 s
Fosc/64 110 3.2 s4.0 s 8.0 s

FRC x11 1.0-6.0 s

Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required T
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz

100 ns

(2)

(2)

(2)

(1,4)

1.0-6.0 s

125 ns

250 ns

0.5 s

AD time.

(2)

(2)

(2)

(1,4)

250 ns

500 ns

(2)

(2)

(2)

500 ns

1.0 s4.0 s

1.0 s2.0 s 8.0 s

(3)

1.0-6.0 s

(3)

(1,4)

1.0-6.0 s

16.0 s

(3)

(1,4)

2.0 s

32.0 s

64.0 s

1.0-6.0 s

(3)

(3)

(3)

(3)

(1,4)

DS41418A-page 80 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

b7 b6 b5 b4 b3 b2 b1 b0

Tcy to TAD

Conversion Starts

ADRES register is loaded,
GO/DONE bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input

TAD0

FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

9.1.5 INTERRUPTS

The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC Interrupt Enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether
or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the F

This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc­tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu­tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.

Please refer to Section 9.1.5 “Interrupts” for more
information.

RC oscillator is selected.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 81

PIC16F707/PIC16LF707

9.2 ADC Operation

9.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.

Note: The GO/DONE bit should not be set in the

same instruction that turns on the ADC.
Refer to Section 9.2.6 “A/D Conversion
Procedure”.

9.2.2 COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE

• Set the ADIF interrupt flag bit

• Update the ADRES register with new conversion
result

9.2.3 TERMINATING A CONVERSION

If a conversion must be terminated before completion,
the GO/DONE
ADRES register will be updated with the partially com­plete Analog-to-Digital conversion sample. Incomplete
bits will match the last bit converted.

Note: A device Reset forces all registers to their

Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.

9.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the F
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.

When the ADC clock source is something other than

RC, a SLEEP instruction causes the present conver-

F
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.

bit

bit can be cleared in software. The

RC

9.2.5 SPECIAL EVENT TRIGGER

The Special Event Trigger of the CCP module allows
periodic ADC measurements without software inter­vention. When this trigger occurs, the GO/DONE
set by hardware and the Timer1 counter resets to zero.

Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.

Refer to Section 17.0 “Capture/Compare/PWM
(CCP) Module” for more information.

bit is

9.2.6 A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:

1. Configure Port:

• Disable pin output driver (Refer to the TRIS
register)

• Configure pin as analog (Refer to the ANSEL
register)

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt

4. Wait the required acquisition time

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of
the following:

• Polling the GO/DONE

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt
is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.

2: Refer to Section 9.3 “A/D Acquisition

Requirements”.

(1)

bit

(2)

.

DS41418A-page 82 Preliminary  2010 Microchip Technology Inc.

EXAMPLE 9-1: A/D CONVERSION

;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL ADCON1 ;
MOVLW B’01110000’ ;ADC Frc clock,

;V

DD reference

MOVWF ADCON1 ;
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSELA ;
BSF ANSELA,0 ;Set RA0 to analog
BANKSEL ADCON0 ;
MOVLW B’00000001’;AN0, On
MOVWF ADCON0 ;
CALL SampleTime ;Acquisiton delay
BSF ADCON0,GO ;Start conversion
BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRES ;
MOVF ADRES,W ;Read result
MOVWF RESULT ;store in GPR space

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 83

PIC16F707/PIC16LF707

9.2.7 ADC REGISTER DEFINITIONS

The following registers are used to control the
operation of the ADC.

REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 =AN0
0001 =AN1
0010 =AN2
0011 =AN3
0100 =AN4
0101 =AN5
0110 =AN6
0111 =AN7
1000 =AN8
1001 =AN9
1010 =AN10
1011 =AN11
1100 =AN12
1101 =AN13
1110 =Reserved
1111 = Fixed Voltage Reference (FV

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

REF)

DS41418A-page 84 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

—

ADCS2 ADCS1 ADCS0

— —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits

000 =F
001 =F
010 =F
011 =F
100 =F
101 =F
110 =F
111 =F

OSC/2
OSC/8
OSC/32
RC (clock supplied from a dedicated RC oscillator)
OSC/4
OSC/16
OSC/64
RC (clock supplied from a dedicated RC oscillator)

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 ADREF<1:0>: Voltage Reference Configuration bits

0x =VREF is connected to VDD
10 =VREF is connected to external VREF (RA3/AN3)

REF is connected to internal Fixed Voltage Reference

11 =V

REGISTER 9-3: ADRES: ADC RESULT REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0

bit 7 bit 0

ADREF1 ADREF0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<7:0>: ADC Result Register bits

8-bit conversion result.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 85

PIC16F707/PIC16LF707

TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=

T

AMP TC TCOFF++=

2µs T

C Temperature - 25°C0.05µs/°C++=

TC CHOLD R IC RSS RS++ ln(1/511)–=

10pF 1k



7k10k



++– ln(0.001957)=

1.12

= µs

T

ACQ 2 µs 1.12µs 50°C- 25°C0.05µs/°C++=

4.42µs=

VAPPLIED 1e

Tc–

RC

---------

–







VAPPLIED 1

1

2

n1+

1–

--------------------------–





=

VAPPLIED 1

1

2

n1+

1–

--------------------------

–





VCHOLD=

VAPPLIED 1e

TC–

RC

----------

–







VCHOLD=

;[1] VCHOLD charged to within 1/2 lsb

;[2] V

CHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for T

C can be approximated with the following equations:

Solving for T

C:

Therefore:

Temperature 50°C and external impedance of 10k



5.0V VDD=

Assumptions:

Note: Where n = number of bits of the ADC.

9.3 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the input channel voltage level. The analog
input model is shown in Figure 9-3. The source
impedance (R
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (V
to Figure 9-3. The maximum recommended

impedance for analog sources is 10 k. As the

EQUATION 9-1: ACQUISITION TIME EXAMPLE

HOLD) must be allowed to fully

S) and the internal sampling switch (RSS)

DD), refer

source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 9-1 may be
used. This equation assumes that 1/2 LSb error is used
(256 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (C
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

HOLD) is not discharged after each conversion.

DS41418A-page 86 Preliminary  2010 Microchip Technology Inc.

FIGURE 9-3: ANALOG INPUT MODEL

CPIN

VA

Rs

ANx

5 pF

V

DD

VT  0.6V

V

T  0.6V

I

LEAKAGE

(1)

RIC  1k

Sampling
Switch

SS

Rss

C

HOLD = 10 pF

V

SS/VREF-

6V

Sampling Switch

5V
4V
3V
2V

567891011

(k)

V

DD

Legend:

C

PIN

VT

I LEAKAGE

RIC

SS

C

HOLD

= Input Capacitance

= Threshold Voltage

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

RSS

Note 1: Refer to Section 25.0 “Electrical Specifications”.

RSS = Resistance of Sampling Switch

FFh

FEh

ADC Output Code

FDh

FCh

04h

03h

02h

01h

00h

Full-Scale

FBh

1 LSB ideal

VSS

Zero-Scale
Transition

V

REF

Transition

1 LSB ideal

Full-Scale Range

Analog Input Voltage

PIC16F707/PIC16LF707

FIGURE 9-4: ADC TRANSFER FUNCTION

 2010 Microchip Technology Inc. Preliminary DS41418A-page 87

PIC16F707/PIC16LF707

TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADCON0

ADCON1

ANSELA

ANSELB

ANSELE

ADRES A/D Result Register Byte xxxx xxxx uuuu uuuu

CCP2CON

FVRCON FVRRDY FVREN

INTCON GIE PEIE

PIE1

PIR1

TRISA

TRISB

TRISE

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’,

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

— ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 -000 --00 -000 --00

ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111

ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111

— — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

— — CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000

TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x

TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

— — — — TRISE3 TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111

q = value depends on condition. Shaded cells are not used for ADC

module.

Valu e o n

POR, BOR

Valu e o n
all other

Resets

DS41418A-page 88 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

ADFVR<1:0>

CDAFVR<1:0>

X1
X2
X4

X1
X2
X4

2

2

FVR BUFFER1

(To ADC Module)

FVR BUFFER2

(To Cap Sense, DAC)

+

_

FVREN

FVRRDY

1.024V Fixed
Reference

10.0 FIXED VOLTAGE REFERENCE

The Fixed Voltage Reference, or FVR, is a stable
voltage reference independent of V

2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:

• ADC input channel

• ADC positive reference

• Digital-to-Analog Converter (DAC)

• Capacitive Sensing Modules (CSM)

The FVR can be enabled by setting the FVREN bit of
the FVRCON register.

DD with 1.024V,

10.1 Independent Gain Amplifiers

The output of the FVR supplied to the ADC and
CSM/DAC modules is routed through the two
independent programmable gain amplifiers. Each
amplifier can be configured to amplify the reference
voltage by 1x, 2x or 4x.

The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer­ence Section 9.0 “Analog-to-Digital Converter
(ADC) Module” for additional information on selecting
the appropriate input channel.

The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the capacitive sensing and
digital-to-analog converter modules. Reference

Section 16.0 “Capacitive Sensing Module” and
Section 11.0 “Digital-to-Analog Converter (DAC)
Module” for additional information.

10.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for
use, the FVRRDY bit of the FVRCON register will be set.
See Section 25.0 “Electrical Specifications” for the
minimum delay requirement.

FIGURE 10-1: VOLTAGE REFERENCE BLOCK DIAGRAM

 2010 Microchip Technology Inc. Preliminary DS41418A-page 89

PIC16F707/PIC16LF707

REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER

R-q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

FVRRDY

(1)

FVREN — — CDAFVR1

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

(2)

CDAFVR0

(2)

ADFVR1

(2)

ADFVR0

(2)

bit 7 FVRRDY: Fixed Voltage Reference Ready Flag bit

(1)

0 = Fixed Voltage Reference output is not active or stable
1 = Fixed Voltage Reference output is ready for use

bit 6 FVREN: Fixed Voltage Reference Enable bit

0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled

bit 5-4 Reserved: Read as ‘0’. Maintain these bits clear

bit 3-2 CDAFVR<1:0>: Cap Sense and D/A Converter Fixed Voltage Reference Selection bit

00 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is off.
01 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)
11 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)

bit 1-0 ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bit

(2)

00 = A/D Converter Fixed Voltage Reference Peripheral output is off.
01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)
11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)

Note 1: FVRRDY is always ‘1’ on PIC16F707 devices.

2: Fixed Voltage Reference output cannot exceed V

DD.

TABLE 10-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FVRCON FVRRDY FVREN

Legend: Shaded cells are not used by the voltage reference module.

Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000

Value on

POR, BOR

(2)

Value on

all other

Resets

DS41418A-page 90 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

VOUT VSOURCE VSOURCE – x

DACR[4:0]

2

5

------------- ------------ ----







VSOURCE+=

-

IF DACEN = 1

IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111

VOUT VSOURCE =

+

IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000

VOUT VSOURCE =

-

VSOURCE+ = VDD, VREF, or FVR BUFFER 2

V

SOURCE- = VSS

+

-

11.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE

The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with V
selectable output levels. The output of the DAC can be
configured to supply a reference voltage to the
following:

• DACOUT device pin

• Capacitive sensing modules

The Digital-to-Analog Converter (DAC) can be enabled
by setting the DACEN bit of the DACCON0 register.

EQUATION 11-1:

DD, with 32

11.1 Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels
are set with the DACR<4:0> bits of the DACCON1
register.

The DAC output voltage is determined by the following
equation:

11.2 Output Clamped to VSS

The DAC output voltage can be set to VSS with no
power consumption by setting the DACEN bit of the
DACCON0 register to ‘0’.

11.3 Output Ratiometric to VDD

The DAC is VDD derived and therefore, the DAC output
changes with fluctuations in V
accuracy of the DAC can be found in Section 25.0
“Electrical Specifications”.

DD. The tested absolute

11.4 Voltage Reference Output

The DAC can be output to the device DACOUT pin by
setting the DACOE bit of the DACCON0 register to ‘1’.
Selecting the reference voltage for output on the
DACOUT pin automatically overrides the digital output
buffer and digital input threshold detector functions of
that pin. Reading the DACOUT pin when it has been
configured for reference voltage output will always
return a ‘0’.

Due to the limited current drive capability, a buffer must
be used on the voltage reference output for external
connections to DACOUT. Example 11-1 shows an
example buffering technique.

11.5 Operation During Sleep

When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.

11.6 Effects of a Reset

A device Reset affects the following:

• Voltage reference is disabled

• Fixed voltage reference is disabled

• DAC is removed from the DACOUT pin

• The DACR<4:0> range select bits are cleared

 2010 Microchip Technology Inc. Preliminary DS41418A-page 91

PIC16F707/PIC16LF707

16-to-1 MUX

DACR<4:0>

R

DACEN

V

DD

VREF

DACPSS[1:0] = 00

R

R

R

R

R

R

32 Steps

DAC

FVR

DACPSS[1:0] = 01

DACPSS[1:0] = 10

DACOUT pin

DACOE

DACLPS

DACEN

DACLPS

BUFFER 2

(To Capacitive

Sensing Module)

R

Buffered DAC Output

+
–

DAC

Module

Voltage

Reference

Output

Impedance

R

DACOUT

PIC16F707/
PIC16LF707

FIGURE 11-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

EXAMPLE 11-1: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

DS41418A-page 92 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 11-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0

DACEN DACLPS DACOE — DACPSS1 DACPSS0 — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 DACEN: Digital-to-Analog Converter Enable bit

0 = Digital-to-Analog Converter is disabled
1 = Digital-to-Analog Converter is enabled

bit 6 DACLPS: DAC Low-Power Voltage State Select bit

DAC = DAC negative reference source selected

0 =V

DAC = DAC positive reference source selected

1 =V

bit 5 DACOE: DAC Voltage Output Enable bit

0 = DAC voltage level is output on the DACOUT pin
1 = DAC voltage level is disconnected from the DACOUT pin

bit 4 Unimplemented: Read as ‘0’

bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits

DD

00 =V
01 =VREF
10 = FVR Buffer 2 output
11 = Reserved, do not use

bit 1-0 Unimplemented: Read as ‘0’

REGISTER 11-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — DACR4 DACR3 DACR2 DACR1 DACR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 DACR<4:0>: DAC Voltage Output Select bits

 2010 Microchip Technology Inc. Preliminary DS41418A-page 93

PIC16F707/PIC16LF707

TABLE 11-1: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FVRCON FVRRDY FVREN

DACCON0 DACEN DACLPS DACOE

DACCON1

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the DAC module.

— — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000

Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000

— DACPSS1 DACPSS0 — — 000- 00-- 000- 00--

Val ue o n

POR, BOR

Value on
all other

Resets

DS41418A-page 94 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

T0CKI

TMR0SE

TMR0

WDT

Time-out

PS<2:0>

WDTE

Data Bus

Set Flag bit TMR0IF

on Overflow

TMR0CS

0

1

0

1

0

1

8

8

8-bit

Prescaler

0

1

FOSC/4

PSA

PSA

PSA

Sync

2 T

CY

Divide by

512

TMR1GE

T1GSS = 11

pin

Note 1: TMR0SE, TMR0CS, PSA, PS<2:0> are bits in the OPTION register.

2: WDTE bit is in Configuration Word 1.

3: T1GSS and TMR1GE are in the T1GCON register.

12.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the
following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

Figure 12-1 is a block diagram of the Timer0 module.

FIGURE 12-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

 2010 Microchip Technology Inc. Preliminary DS41418A-page 95

PIC16F707/PIC16LF707

12.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.

12.1.1 8-BIT TIMER MODE

The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the OPTION
register.

When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.

Note: The value written to the TMR0 register can

be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.

12.1.2 8-BIT COUNTER MODE

In 8-bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin. 8-bit
Counter mode using the T0CKI pin is selected by setting
the TMR0CS bit of the OPTION register to ‘1’.

The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION register.

12.1.3 SOFTWARE PROGRAMMABLE PRESCALER

A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.

There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.

The prescaler is not readable or writable. When the
prescaler is enabled or assigned to the Timer0 module,
all instructions writing to the TMR0 register will clear the
prescaler.

Note: When the prescaler is assigned to WDT, a

CLRWDT instruction will clear the prescaler
along with the WDT.

12.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The
Timer0 interrupt enable is the TMR0IE bit of the
INTCON register.

Note: The Timer0 interrupt cannot wake the

processor from Sleep since the timer is
frozen during Sleep.

12.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements as
shown in Section 25.0 “Electrical Specifications”.

12.1.6 TIMER ENABLE

Operation of Timer0 is always enabled and the module
will operate according to the settings of the OPTION
register.

12.1.7 OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.

DS41418A-page 96 Preliminary  2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

000

001

010

011

100

101

110

111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

BIT VALUE TMR0 RATE WDT RATE

REGISTER 12-1: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU

: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin

bit 5 TMR0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)

bit 4 TMR0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE

OPTION_REG

TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

TRISA

Legend: – = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.

 2010 Microchip Technology Inc. Preliminary DS41418A-page 97

RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Val ue o n

POR, BOR

INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x

Value on

all other

Resets

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 98 Preliminary  2010 Microchip Technology Inc.

13.0 TIMER1/3 MODULES WITH GATE CONTROL

The Timer1 and Timer3 modules are 16-bit timers/
counters with the following features:

• 16-bit timer/counter register pair (TMRxH:TMRxL)

• Programmable internal or external clock source

• 3-bit prescaler

• Dedicated LP oscillator circuit (Timer1 only)

• Synchronous or asynchronous operation

• Multiple Timer1/3 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

(Timer1 only)

• Special Event Trigger with CCP (Timer1 only)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gate Single-pulse mode

• Gate Value Status

• Gate Event Interrupt

Figure 13-1 is a block diagram of the Timer1/3
modules.

PIC16F707/PIC16LF707

 2010 Microchip Technology Inc. Preliminary DS41418A-page 99

TMRxH TMRxL

T

xSYNC

TxCKPS<1:0>

Prescaler

1, 2, 4, 8

0

1

Synchronized

clock input

2

Set flag bit
TMRxIF on
Overflow

TMRx

(2)

TMRxON

Note 1: ST Buffer is high speed type when using TxCKI.

2: Timer1/3 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: Timer1 gate source is TimerA. Timer3 gate source is TimerB. Refer to Table 13-1.
5: Timer1 clock source is CPSAOSC. Timer3 clock source is CPSBOSC. Refer to Table 13-1.
6: Timer3 does not have a T3OSC circuit. There is no T3OSCEN bit. Timer3 can operate from T1OSC.

TxG

T1OSC

F

OSC

Internal

Clock

T1OSO/T1CKI

T1OSI

T1OSCEN

1

0

TxCKI

TMRxCS<1:0>

(1)

Synchronize

(3)

det

Sleep input

TMRxGE

0

1

00

01

10

11

From TimerA/B

From Timer2

TxGPOL

D

Q

CK

Q

0

1

TxGVAL

TxGTM

Single Pulse

Acq. Control

TxGSPM

TxGGO/DONE

TxGSS<1:0>

EN

OUT

11

10

00

00

FOSC/4

Internal

Clock

From WDT
Overflow

Match PR2

Overflow

(4)

R

DENQ

Q1

RD

TXGCON

Data Bus

det

Interrupt

TMRxGIF

Set

TxCLK

FOSC/2

Internal

Clock

D

EN

Q

TxG_IN

(6)

Cap. Sense

(5)

Oscillator A/B

PIC16F707/PIC16LF707

FIGURE 13-1: TIMER1/TIMER3 BLOCK DIAGRAM

TABLE 13-1: CPSOSC/TIMER

ASSOCIATION

Period

Measurement

Timer1 CPS A TimerA

Timer3 CPS B TimerB

Cap Sense

Oscillator

Divider Timer

(Gate Source)

DS41418A-page 100 Preliminary  2010 Microchip Technology Inc.