PIC16F631/677/685/687/689/690
20-Pin Flash-Based, 8-Bit CMOS Micr ocontrollers
High-Performance RISC CPU
• Only 35 Instructions to Le arn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
Special Microcontroller Features
• Precision Internal Oscillator:
- Factory calibrated to ± 1%
- Software selectable frequency range of
8 MHz to 32 kHz
- Software tunable
- Two-Speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for
power savings
• Power-Saving Sleep mode
• Wide Operating Voltage Range (2.0V-5.5V)
• Industrial and Extend ed Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRTE) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR) with Software Control
Option
• Enhanced Low-Current Watchdog Timer (WDT)
with On-Chip Oscillator (Sof t wa re sel ec t ab le
nominal 268 Seconds with Full Prescaler) with
Software Enable
• Multiplexed Master Clear/Input Pin
• Programmable Code Protection
• High Endurance Flash/EEPROM Cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
• Enhanced USART Module:
- Supports RS-485, RS-232 and LIN 2.0
- Auto-Baud Detect
- Auto-wake-up on Start bit
Low-Power Features
• Standby Current:
- 50 nA @ 2.0V, typical
• Operating Current:
-11A @ 32 kHz, 2.0V, typical
-220A @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
-<1A @ 2.0V, typical
Peripheral Features
• 17 I/O Pins and 1 Input-Only Pin:
- High current source/sink for direct LED drive
- Interrupt-on-Change pin
- Individually programmable weak pull-ups
- Ultra Low-Power Wake-up (ULPWU)
• Analog Compar ator Module with:
- Two analog comparators
- Programmable on-chip voltage reference
REF) module (% of VDD)
(CV
- Comparator inputs and outputs externally
accessible
- SR Latch mode
- Timer 1 Gate Sync Latch
- Fixed 0.6V V
• A/D Converter:
- 10-bit resolution and 12 channels
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode
selected
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Enhanced Capture, Compare, PWM+ Module:
- 16-bit Capture, max resolution 12.5 ns
- Compare, max resolution 200 ns
- 10-bit PWM with 1, 2 or 4 output channels,
programmable “dead time”, max frequency
20 kHz
- PWM output steering control
• Synchronous Serial Port (SSP):
- SPI mode (Master and Slave)
2
C™ (Master/Slave modes):
•I
2
C™ address mask
-I
• In-Circuit Serial Prog ram ming
Pins
REF
TM
(ICSPTM) via Two
2005-2015 Microchip Technology Inc. DS40001262F-page 1
PIC16F631/677/685/687/689/690
20-pin PDIP, SOIC, SSOP
PIC16F631
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G
/OSC2/CLKOUT
RA3/MCLR
/VPP
RC5
RC4/C2OUT
RC3/C12IN3-
RC6
RC7
RB7
VSS
RA0/C1IN+/ICSPDAT/ULPWU
RA1/C12IN0-/ICSPCLK
RA2/T0CKI/INT/C1OUT
RC0/C2IN+
RC1/C12IN1RC2/C12IN2RB4
RB5
RB6
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
Program
Memory
Device
Flash
(words)
Data Memory
SRAM
EEPROM
(bytes)
(bytes)
I/O
10-bit A/D
(ch)
Comparators
Timers
8/16-bit
SSP ECCP+ EUSART
PIC16F631 1024 64 128 18 — 2 1/1 No No No
PIC16F677 2048 128 256 18 12 2 1/1 Yes No No
PIC16F685 4096 256 256 18 12 2 2/1 No Yes No
PIC16F687 2048 128 256 18 12 2 1/1 Yes No Yes
PIC16F689 4096 256 256 18 12 2 1/1 Yes No Yes
PIC16F690 4096 256 256 18 12 2 2/1 Yes Yes Yes
PIC16F631 Pin Diagram
TABLE 1: PIC16F631 PIN SUMMARY
I/O Pin Analog Comparators Timers Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — IOC Y ICSPDAT
RA1 18 AN1 C12IN0- — IOC Y ICSPCLK
RA2 17 — C1OUT T0CKI IOC/INT Y —
RA3 4 — — — IOC Y
RA4 3 — — T1G IOC Y OSC2/CLKOUT
RA5 2 — — T1CKI IOC Y OSC1/CLKIN
RB4 13 — — — IOC Y —
RB5 12 — — — IOC Y —
RB6 11 — — — IOC Y —
RB7 10 — — — IOC Y —
RC0 16 AN4 C2IN+ — — — —
RC1 15 AN5 C12IN1- — — — —
RC2 14 AN6 C12IN2- — — — —
RC3 7 AN7 C12IN3- — — — —
RC4 6 — C2OUT — — — —
RC55— ———— —
RC6 8 — — — — — —
RC79— ———— —
— 1 — — — — — VDD
—20— ———— VSS
Note 1: Pull-up enabled only with external MCLR configuration.
DS40001262F-page 2 2005-2015 Microchip Technology Inc.
(1)
MCLR/VPP
PIC16F631/677/685/687/689/690
20-pin PDIP, SOIC, SSOP
PIC16F677
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR
/VPP
RC5
RC4/C2OUT
RC3/AN7C12IN3-
RC6/AN8/SS
RC7/AN9/SDO
RB7
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/V
REF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1RC2/AN6/C12IN2RB4/AN10/SDI/SDA
RB5/AN11
RB6/SCK/SCL
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
PIC16F677 Pin Diagram
TABLE 2: PIC16F631 PIN SUMMARY
I/O Pin Analog Comparators Timers Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — IOC Y ICSPDAT
RA1 18 AN1 C12IN0- — IOC Y ICSPCLK
RA2 17 — C1OUT T0CKI IOC/INT Y —
RA3 4 — — — IOC Y
RA4 3 — — T1G IOC Y OSC2/CLKOUT
RA5 2 — — T1CKI IOC Y OSC1/CLKIN
RB4 13 — — — IOC Y —
RB5 12 — — — IOC Y —
RB6 11 — — — IOC Y —
RB7 10 — — — IOC Y —
RC0 16 AN4 C2IN+ — — — —
RC1 15 AN5 C12IN1- — — — —
RC2 14 AN6 C12IN2- — — — —
RC3 7 AN7 C12IN3- — — — —
RC4 6 — C2OUT — — — —
RC55— ———— —
RC6 8 — — — — — —
RC79— ———— —
— 1 — — — — — VDD
—20— ———— VSS
Note 1: Pull-up enabled only with external MCLR configuration.
(1)
MCLR/VPP
2005-2015 Microchip Technology Inc. DS40001262F-page 3
PIC16F631/677/685/687/689/690
20-pin PDIP, SOIC, SSOP
PIC16F685
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR
/VPP
RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C
RC6/AN8
RC7/AN9
RB7
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/V
REF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1RC2/AN6/C12IN2-/P1D
RB4/AN10
RB5/AN11
RB6
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
PIC16F685 Pin Diagram
TABLE 3: PIC16F685 PIN SUMMARY
I/O Pin Analog Comparators Timers ECCP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT
RA1 18 AN1/VREF C12IN0- — — IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI — IOC/INT Y —
RA3 4 — — — — IOC Y
RA4 3 AN3 —
T1G
— IOC Y OSC2/CLKOUT
RA5 2 — — T1CKI — IOC Y OSC1/CLKIN
RB4 13 AN10 — — — IOC Y —
RB5 12 AN11 — — — IOC Y —
RB6 11 — — — — IOC Y —
RB7 10 — — — — IOC Y —
RC0 16 AN4 C2IN+ — — — — —
RC1 15 AN5 C12IN1- — — — — —
RC2 14 AN6 C12IN2- — P1D — — —
RC3 7 AN7 C12IN3- — P1C — — —
RC4 6 — C2OUT — P1B — — —
RC5 5 — — — CCP1/P1A — — —
RC6 8 AN8 — — — — — —
RC7 9 AN9 — — — — — —
— 1 — — — — — — VDD
—20 — — — — — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
(1)
MCLR/VPP
DS40001262F-page 4 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
20-pin PDIP, SOIC, SSOP
PIC16F687/689
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR
/VPP
RC5
RC4/C2OUT
RC3/AN7/C12IN3-
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/V
REF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1RC2/AN6/C12IN2RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
PIC16F687/689 Pin Diagram
T ABLE 4: PIC16F687/689 PIN SUMMARY
I/O Pin Analog Comparators Timers EUSART SSP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — — — IOC Y ICSPDAT
RA1 18 AN1/VREF C12IN0- — — — IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI — — IOC/INT Y
RA3 4 — — — — — IOC Y
RA4 3 AN3 —
T1G
— — IOC Y OSC2/CLKOUT
RA5 2 — — T1CKI — — IOC Y OSC1/CLKIN
RB4 13 AN10 — — — SDI/SDA IOC Y —
RB5 12 AN11 — — RX/DT — IOC Y —
RB6 11 — — — — SCL/SCK IOC Y —
RB7 10 — — — TX/CK — IOC Y —
RC0 16 AN4 C2IN+ — — — — — —
RC1 15 AN5 C12IN1- — — — — — —
RC2 14 AN6 C12IN2- — — — — — —
RC3 7 AN7 C12IN3- — — — — — —
RC4 6 — C2OUT — — — — — —
RC5 5 — — — — — — — —
RC6 8 AN8 — — —
SS
— — —
RC7 9 AN9 — — — SDO — — —
— 1 — — — — — — — VDD
—20 — — — — — — — VSS
Note1: Pull-up activated only with external MCLR configuration.
(1)
MCLR/VPP
2005-2015 Microchip Technology Inc. DS40001262F-page 5
PIC16F631/677/685/687/689/690
20-pin PDIP, SOIC, SSOP
PIC16F690
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR
/VPP
RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/V
REF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1RC2/AN6/C12IN2-/P1D
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
PIC16F690 Pin Diagram (PDIP, SOIC, SSOP)
TABLE 5: PIC16F690 PIN SUMMARY
I/O Pin Analog Comparators Timers ECCP EUSART SSP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — — — — IOC Y ICSPDAT
RA1 18 AN1/V
RA2 17 AN2 C1OUT T0CKI — — — IOC/INT Y
RA3 4 — — — — — — IOC Y
RA4 3 AN3 —
RA5 2 — — T1CKI — — — IOC Y OSC1/CLKIN
RB4 13 AN10 — — — — SDI/SDA IOC Y —
RB5 12 AN11 — — — RX/DT — IOC Y —
RB6 11 — — — — SCL/SCK IOC Y —
RB7 10 — — — — TX/CK — IOC Y —
RC0 16 AN4 C2IN+ — — — — — — —
RC1 15 AN5 C12IN1- — — — — — — —
RC2 14 AN6 C12IN2- — P1D — — — — —
RC3 7 AN7 C12IN3- — P1C — — — — —
RC4 6 — C2OUT — P1B — — — — —
RC5 5 — — — CCP1/P1A — — — — —
RC6 8 AN8 — — — —
RC7 9 AN9 — — — — SDO — — —
— 1 — — — — — — — — VDD
—20 — — — — — — — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
REF C12IN0- — — — — IOC Y ICSPCLK
T1G
(1)
— — — IOC Y OSC2/CLKOUT
SS
— — —
MCLR/VPP
DS40001262F-page 6 2005-2015 Microchip Technology Inc.
20-pin QFN
RA4/AN3/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
V
DD
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RC7/AN9/SDO
(2)
RB7/TX/CK
(3)
RB6/SCK/SCL
(2)
RB5/AN11/RX/DT
(3)
RB4/AN10/SDI/SDA
(2)
RA3/MCLR/VPP
RC5/CCP1/P1A
(1)
RC4/C2OUT/P1B
(1)
RC3/AN7/C12IN3-/P1C
(1)
RC6/AN8/SS
(2)
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1RC2/AN6/C12IN2-/P1D
(1)
PIC16F631/677/
685/687/689/690
20
19
18
17
16
6
7
8
9
10
15
14
13
12
11
1
2
3
4
5
Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only.
2: SS
, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F690 only.
PIC16F631/677/685/687/689/690
PIC16F631/677/685/687/689/690 Pin Diagram (QFN)
2005-2015 Microchip Technology Inc. DS40001262F-page 7
PIC16F631/677/685/687/689/690
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Memory Organization................................................................................................................................................................. 24
3.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................45
4.0 I/O Ports ............................................. .................................................... .................................................................................... 57
5.0 Timer0 Module ........................................................................................................................................................................... 79
6.0 Timer1 Module with Gate Control............................................................................................................................................... 82
7.0 Timer2 Module ........................................................................................................................................................................... 89
8.0 Comparator Module......................................................... .... .... ......... .... .... .... ......... .... .... .............................................................91
9.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 105
10.0 Data EEPROM and Flash Program Memory Control........ ...... ................. ................. ........ ................. ...................................... 117
11.0 Enhanced Capture/Compare/PWM Module ....................................... .. .... .... ......... .... .. .... ......... .... .. .... . ..................................... 125
12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 148
13.0 SSP Module Overview ............................................................................................................................................................. 175
14.0 Special Features of th e CPU...................................................... ....................................... ....................................................... 193
15.0 Instruction Set Summary.......................................................................................................................................................... 212
16.0 Development Support............................................................................................................................................................... 221
17.0 Electrical Specifications............................................................................................................................................................225
18.0 DC and AC Characteristics Graphs and Tables............................................................................... ........................................258
19.0 Packaging Information........................................... ....................................... ............................................................................285
The Microchip Web Site.................. ........................................ ........................................................................................................... 295
Customer Change Notification Service .............................................................................................................................................. 295
Customer Support..............................................................................................................................................................................295
Product Identification System.............................................................................................................................................................296
TO OUR VALUED CUSTOMERS
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DS40001262F-page 8 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
8
8
8
3
8-Level Stack (13-bit)
64 bytes
1K x 14
VDD
INT
Configuration
Internal
Oscillator
MCLR
Block
VSS
2
Timer0 Timer1
Analog Comparators
C1IN- C1IN+ C1OUT
and Reference
8
C2IN- C2IN+ C2OUT
T1G T1CKIT0CKI
Data
EEPROM
128 Bytes
EEDAT
EEADR
RB4
RB5
RB6
RB7
PORTA
RA0
RA1
RA2
RA3
RA4
RA5
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
Ultra Low-Power
Wake-up
ULPWU
1.0 DEVICE OVERVIEW
The PIC16F631/677/685/687/689/690 devices are
covered by this dat a sheet. The y are availab le in 20-pin
PDIP, SOIC, TSSOP and QFN packages.
FIGURE 1-1: PIC16F631 BLOCK DIAGRAM
Block Diagrams and pinout descriptions of the devices
are as follows:
• PIC16F631 (Figure 1-1, Table 1-1)
• PIC16F677 (Figure 1-2, Table 1-2)
• PIC16F685 (Figure 1-3, Table 1-3)
• PIC16F687/PIC16F689 (Figure 1-4, Table 1-4)
• PIC16F690 (Figure 1-5, Table 1-5)
2005-2015 Microchip Technology Inc. DS40001262F-page 9
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit)
128 bytes
2K x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
2
Timer0 Timer1
Analog Comparators
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
8
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G T1CKIT0CKI
Data
EEPROM
256 Bytes
EEDAT
EEADR
SDO
SDI/ SCK/
SS
Synchronous
Serial Port
SDA SCL
Ultra Low-Power
Wake-up
ULPWU
PIC16F631/677/685/687/689/690
FIGURE 1-2: PIC16F677 BLOCK DIAGRAM
DS40001262F-page 10 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit)
256 bytes
4K x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
8
ECCP+
CCP1/
P1B P1C P1DP1A
Data
EEPROM
256 Bytes
EEDAT
EEADR
2
Timer0 Timer1
Analog Comparators
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G
T1CKIT0CKI
Timer2
Ultra Low-Power
Wake-up
ULPWU
FIGURE 1-3: PIC16F685 BLOCK DIAGRAM
2005-2015 Microchip Technology Inc. DS40001262F-page 11
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit)
2K
(1)
/4K x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
8
SDO
SDI/ SCK/
SS
Synchronous
Serial Por t
SDA SCL
Data
EEPROM
256 Bytes
EEDAT
EEADR
RAM
File
Registers
128
(1)
/256 bytes
Note 1: PIC16F687 only.
2
Timer0 Timer1
Analog Comparators
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G T1CKIT0CKI
EUSART
TX/CK
Ultra Low-Power
Wake-up
ULPWU
RX/DT
PIC16F631/677/685/687/689/690
FIGURE 1-4: PIC16F687/PIC16F689 BLOCK DIAGRAM
DS40001262F-page 12 2005-2015 Microchip Technology Inc.
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit)
256 bytes
4k x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
8
ECCP+
CCP1/
P1B P1C P1D
EUSART
P1A
TX/CK RX/DT
SDO
SDI/ SCK/
SS
Synchronous
Serial Port
SDA SCL
Data
EEPROM
256 Bytes
EEDAT
EEADR
2
Timer0
Timer1
Analog Comparators
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G T1CKI
T0CKI
Ultra Low-Power
Wake-up
ULPWU
Timer2
PIC16F631/677/685/687/689/690
FIGURE 1-5: PIC16F690 BLOCK DIAGRAM
2005-2015 Microchip Technology Inc. DS40001262F-page 13
PIC16F631/677/685/687/689/690
TABLE 1-1: PINOUT DESCRIPTION – PIC16F631
Input
Name Function
RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
C1IN+ AN — Comparator C1 non-inverting input.
ICSPDAT ST CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/C12IN0-/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
C12IN0- AN — Comparator C1 or C2 inverting input.
ICSPCLK ST — ICSP™ clock.
RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt pin.
C1OUT — CMOS Com parator C1 output.
RA3/MCLR
RA4/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMO S General purpose I/O. Individually controlled interrupt-on-change.
RB4 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB5 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB6 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/C2IN+ RC0 ST CMOS General purpose I/O.
RC1/C12IN1- RC1 ST CMOS General purpose I/O.
RC2/C12IN2- RC2 ST CMOS General purpose I/O.
RC3/C12IN3- RC3 ST CMOS General purpose I/O.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
RC5 RC5 ST CMOS General purpose I/O.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
MCLR
PP HV — Programming voltage.
V
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
T1G
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMO S F
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — External clock input/RC oscillator connection.
C2IN+ AN — Comparator C2 non-inverting input.
C12IN1- AN — Comparator C1 or C2 inverting input.
C12IN2- AN — Comparator C1 or C2 inverting input.
C12IN3- AN — Comparator C1 or C2 inverting input.
C2OUT — CMOS Com parator C2 output.
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
Output
Type
Type
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
change.
ST — Master Clear with internal pull-up.
Individually enabled pull-up.
ST — Timer1 gate input.
OSC/4 output.
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
Description
DS40001262F-page 14 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 (CONTINUED)
Input
Name Function
RC6 RC6 ST CMOS General purpose I/O.
RC7 RC7 ST CMOS General purpose I/O.
SS VSS Power — Ground reference.
V
DD VDD Power — Positive supply.
V
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
Type
Output
Type
Description
2005-2015 Microchip Technology Inc. DS40001262F-page 15
PIC16F631/677/685/687/689/690
TABLE 1-2: PINOUT DESCRIPTION – PIC16F677
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/
ULPWU
RA1/AN1/C12IN0-/V
ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMO S General purpose I/O. Individually controlled interrupt-on-change.
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB5/AN11 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
REF/
/OSC2/CLKOUT RA4 T TL CM O S General purpose I/O. Individually controlled interrupt-on-change.
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 non-inverting input.
ICSPDAT ST CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 inverting input.
REF AN — External Voltage Reference for A/D.
V
ICSPCLK ST — ICSP™ clock.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt pin.
C1OUT — CMOS Com parator C1 output.
MCLR
PP HV — Programming voltage.
V
AN3 AN — A/D Channel 3 input.
T1G
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMO S F
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — External clock input/RC oscillator connection.
AN10 AN — A/D Channel 10 input.
SDI ST — SPI data input.
SDA ST OD I
AN11 AN — A/D Channel 11 input.
SCK ST CMOS SPI clock.
SCL ST OD I
Output
Type
Type
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
change.
ST — Master Clear with internal pull-up.
Individually enabled pull-up.
ST — Timer1 gate input.
OSC/4 output.
Individually enabled pull-up.
Individually enabled pull-up.
2
C™ data input/output.
Individually enabled pull-up.
Individually enabled pull-up.
2
C™ clock.
Description
DS40001262F-page 16 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 (CONTINUED)
Input
Name Function
RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
C2IN+ AN — Comparator C2 non-inverting input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 inverting input.
RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O.
AN6 AN — A/D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 inverting input.
RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O.
AN7 AN — A/D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 inverting input.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Com parator C2 output.
RC5 RC5 ST CMOS General purpose I/O.
RC6/AN8/SS
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
SS VSS Power — Ground reference.
V
DD VDD Power — Positive supply.
V
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
SS
AN9 AN — A/D Channel 9 input.
SDO — CMOS SPI data output.
Output
Type
Type
Individually enabled pull-up.
ST — Slave Select input.
Description
2005-2015 Microchip Technology Inc. DS40001262F-page 17
PIC16F631/677/685/687/689/690
TABLE 1-3: PINOUT DESCRIPTION – PIC16F685
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/
ULPWU
RA1/AN1/C12IN0-/V
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB4/AN10 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB5/AN11 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB6 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 negative input.
REF AN — External Voltage Reference for A/D.
V
ICSPCLK S T — ICSP™ clock.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT ST —
C1OUT — CMOS Comparator C1 output.
MCLR
V
PP HV — Programming voltage.
AN3 AN — A/D Channel 3 input.
T1G
OSC2 — XTAL Cry stal/Resonator.
CLKOUT — CMOS F
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — External clock input/RC oscillator connection.
AN10 AN — A/D Channel 10 input.
AN11 AN — A/D Channel 11 input.
AN4 AN — A/D Channel 4 input.
C2IN+ AN — Comparator C2 positive input.
Type
Output
Type
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
Description
External interrupt pin.
change.
ST — Master Clear with internal pull-up.
change. Individually enabled pull-up.
ST — Timer1 gate input.
OSC/4 output.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
DS40001262F-page 18 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 (CONTINUED)
Input
Name Function
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 negative input.
RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O.
AN6 AN — A/D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 negative input.
P1D — CMOS PWM output.
RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O.
AN7 AN — A/D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 negative input.
P1C — CMOS PWM output.
RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
P1B — CMOS PWM output.
RC5/CCP1/P1A RC5 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare input.
P1A ST CMOS PWM output.
RC6/AN8 RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
RC7/AN9 RC7 ST CMOS General purpose I/O.
AN9 AN — A/D Channel 9 input.
SS VSS Power — Ground reference.
V
V
DD VDD Pow er — Positive supply.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
Type
Output
Type
Description
2005-2015 Microchip Technology Inc. DS40001262F-page 19
PIC16F631/677/685/687/689/690
TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/
ULPWU
RA1/AN1/C12IN0-/V
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
/VPP RA3 TTL — General purpose input. Individually controlled
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 negative input.
REF AN — External Voltage Reference for A/D.
V
ICSPCLK S T — ICSP™ clock.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT ST — External Interrupt.
C1OUT — CMOS Comparator C1 output.
MCLR
PP HV — Programming voltage.
V
AN3 AN — A/D Channel 3 input.
T1G
OSC2 — XTAL Cry stal/Resonator.
CLKOUT — CMOS F
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — External clock input/RC oscillator connection.
AN10 AN — A/D Channel 10 input.
SDI ST — SPI data input.
SDA ST OD I
AN11 AN — A/D Channel 11 input.
RX ST — EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
Output
Type
Type
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
interrupt-on-change.
ST — Master Clear with internal pull-up.
change. Individually enabled pull-up.
ST — Timer1 gate input.
OSC/4 output.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
2
C™ data input/output.
change. Individually enabled pull-up.
Description
DS40001262F-page 20 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 (CONTINUED)
Input
Name Function
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
SCK ST C M OS SPI clock.
SCL ST OD I
RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
TX — CMOS EUSART asynchronous output.
CK ST CMOS EUSART synchronous clock.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
C2IN+ AN — Comparator C2 positive input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 negative input.
RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O.
AN6 AN — A/D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 negative input.
RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O.
AN7 AN — A/D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 negative input.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
RC5 RC5 ST CMOS General purpose I/O.
RC6/AN8/SS
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
SS VSS Power — Ground reference.
V
DD VDD Pow er — Positive supply.
V
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
SS
AN9 AN — A/D Channel 9 input.
SDO — CMOS SPI data output.
Output
Type
Type
change. Individually enabled pull-up.
2
C™ clock.
change. Individually enabled pull-up.
ST — Slave Select input.
Description
2005-2015 Microchip Technology Inc. DS40001262F-page 21
PIC16F631/677/685/687/689/690
TABLE 1-5: PINOUT DESCRIPTION – PIC16F690
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/
ULPWU
RA1/AN1/C12IN0-/V
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 negative input.
REF AN — External Voltage Reference for A/D.
V
ICSPCLK S T — ICSP™ clock.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT ST — External interru p t.
C1OUT — CMOS Comparator C1 output.
MCLR
PP HV — Programming voltage.
V
AN3 AN — A/D Channel 3 input.
T1G
OSC2 — XTAL Cry stal/Resonator.
CLKOUT — CMOS F
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — External clock input/RC oscillator connection.
AN10 AN — A/D Channel 10 input.
SDI ST — SPI data input.
SDA ST OD I
AN11 AN — A/D Channel 11 input.
RX ST — EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
Output
Type
Type
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change.
ST — Master Clear with internal pull-up.
change. Individually enabled pull-up.
ST — Timer1 gate input.
OSC/4 output.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
2
C™ data input/output.
change. Individually enabled pull-up.
Description
DS40001262F-page 22 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 (CONTINUED)
Input
Name Function
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
SCK ST C M OS SPI clock.
SCL ST OD I
RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
TX — CMOS EUSART asynchronous output.
CK ST CMOS EUSART synchronous clock.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
C2IN+ AN — Comparator C2 positive input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 negative input.
RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O.
AN6 AN — A/D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 negative input.
P1D — CMOS PWM output.
RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O.
AN7 AN — A/D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 negative input.
P1C — CMOS PWM output.
RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
P1B — CMOS PWM output.
RC5/CCP1/P1A RC5 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare input.
P1A ST CMOS PWM output.
RC6/AN8/SS
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
SS VSS Power — Ground reference.
V
DD VDD Pow er — Positive supply.
V
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL= Crys tal
RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
SS
AN9 AN — A/D Channel 9 input.
SDO — CMOS SPI data output.
Output
Type
Type
change. Individually enabled pull-up.
2
C™ clock.
change. Individually enabled pull-up.
ST — Slave Select input.
Description
2005-2015 Microchip Technology Inc. DS40001262F-page 23
PIC16F631/677/685/687/689/690
PC<12:0>
13
0000h
0004h
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Access 0-3FFh
0005h
03FFh
Page 0
On-Chip
Memory
PC<12:0>
13
0000h
0004h
1000h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Access 0-FFFh
0005h
07FFh
0800h
Page 0
Page 1
0FFFh
On-Chip
Program
Memory
PC<12:0>
13
0000h
0004h
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Access 0-7FFh
0005h
07FFh
Page 0
On-Chip
Memory
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16F631/677/685/687/689/690 has a 13-bit
program counter capable of addressing an 8K x 14
program memory sp ac e. Onl y th e fi rst 1 Kx 14 (0000h03FFh) is physically implemented for the PIC16F631,
the first 2K x 14 (0000h-07FFh) for the PIC16F677/
PIC16F687, and the first 4K x 14 (0000h-0FFFh) for
the PIC16F685/PIC16F689/PIC16F690. Accessing a
location above these boundaries will cause a wraparound. The Reset vector is at 0000h and the interrupt
vector is at 0004h (see Figures 2-1 through 2-3).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F631
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F685/689/690
FIGURE 2-3: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F677/PIC16F687
DS40001262F-page 24 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
2.2 Data Memory Organization
The data memory (see Figures 2-6 through 2-8) is
partitioned into four banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). The Special Function Registers are
located in the first 32 locations of each bank. The
General Purpose Registers, implemented as static
RAM, are located in the l ast 96 locat ion s of ea ch Bank .
Register locations F0h-FFh in Bank 1, 170h-17Fh in
Bank 2 and 1F0h-1FFh in Bank 3 point to addresses
70h-7Fh in Bank 0. The actual number of General
Purpose Resisters (GPR) in eac h Bank depends on the
device. Details are shown in Figures 2-4 through 2-8.
All other RAM is unimplemented and returns ‘0’ when
read. RP<1:0> of the STATUS register are the bank
select bits:
RP1
RP0
00 Bank 0 is selected
01 Bank 1 is selected
10 Bank 2 is selected
11 Bank 3 is selected
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file is organized as 128 x 8 in the
PIC16F687 and 256 x 8 in the PIC16F685/PIC16F689/
PIC16F690. Each register is accessed, either directly or
indirectly, through the File Select Register (FSR) (see
Section 2.4 “Indirect Addressing, INDF and FSR
Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1
through 2-4). These re g is t e rs ar e s tatic RAM.
The special re gisters can be classifi ed into two sets:
core and peripheral. The Special Function Registers
associated with the “c ore” are des cribed in this sectio n.
Registers related to the operati on of peripheral features
are described in the section of that peri phe ral feature .
2005-2015 Microchip Technology Inc. DS40001262F-page 25
PIC16F631/677/685/687/689/690
File File File File
Address Address Address Address
Indirect addr.
(1)
00h Indirect addr.
(1)
80h Indirect addr.
(1)
100h Indirect addr.
(1)
180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2
(1)
18Dh
TMR1L 0Eh PCON 8Eh
10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh
10Fh 18Fh
T1CON 10h OSCTUNE 90h
110h 190h
11h 91h 111h 191h
12h 92h 112h 192h
13h 93h 113h 193h
14h 94h 114h 194h
15h WPUA 95h WPUB 115h 195h
16h IOCA 96h IOCB 116h 196h
17h WDTCON 97h 117h 197h
18h 98h VRCON 118h 198h
19h 99h CM1CON0 119h 199h
1Ah 9Ah CM2CON0 11Ah 19Ah
1Bh 9Bh CM2CON1 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh 9Dh 11Dh 19Dh
1Eh 9Eh ANSEL 11Eh SRCON 19Eh
1Fh 9Fh 11Fh 19Fh
20h
3Fh
A0h 120h 1A0h
General
Purpose
Registers
64 Bytes
40h
6Fh EFh 16Fh 1EFh
70h accesses
70h-7Fh
F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
FIGURE 2-4: PI C16F63 1 SPECIAL FUNCTION REGISTERS
DS40001262F-page 26 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
File File File File
Address Address Address Address
Indirect addr.
(1)
00h Indirect addr.
(1)
80h Indirect addr.
(1)
100h Indirect addr.
(1)
180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2
(1)
18Dh
TMR1L 0Eh PCON 8Eh
10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh
10Fh 18Fh
T1CON 10h OSCTUNE 90h
110h 190h
11h 91h 111h 191h
12h 92h 112h 192h
SSPBUF 13h SSPADD
(2)
93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
15h WPUA 95h WPUB 115h 195h
16h IOCA 96h IOCB 116h 196h
17h WDTCON 97h 117h 197h
18h 98h VRCON 118h 198h
19h 99h CM1CON0 119h 199h
1Ah 9Ah CM2CON0 11Ah 19Ah
1Bh 9Bh CM2CON1 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh
19Fh
General
Purpose
Register
96 Bytes
20h General
Purpose
Register
32 Bytes
A0h
BFh
120h 1A0h
C0h
EFh 16Fh 1EFh
accesses
70h-7Fh
F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.
See Registers 13-2 and 13-3 for more details.
FIGURE 2-5: PI C16F67 7 SPECIAL FUNCTION REGISTERS
2005-2015 Microchip Technology Inc. DS40001262F-page 27
PIC16F631/677/685/687/689/690
File File File File
Address Address Address Address
Indirect addr.
(1)
00h Indirect addr.
(1)
80h Indirect addr.
(1)
100h Indirect addr.
(1)
180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2
(1)
18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh
18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h 91h 111h 191h
T2CON 12h PR2 92h
112h 192h
13h 93h 113h 193h
14h 94h 114h 194h
CCPR1L 15h WPUA 95h WPUB 115h
195h
CCPR1H 16h IOCA 96h IOCB 116h 196h
CCP1CON 17h WDTCON 97h 117h 197h
18h 98h VRCON 118h 198h
19h 99h CM1CON0 119h 199h
1Ah 9Ah CM2CON0 11Ah 19Ah
1Bh 9Bh CM2CON1 11Bh 19Bh
PWM1CON 1Ch 9Ch 11Ch 19Ch
ECCPAS 1Dh 9Dh 11Dh PSTRCON 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh
19Fh
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
80 Bytes
A0h
General
Purpose
Register
80 Bytes
120h
1A0h
EFh 16Fh
accesses
70h-7Fh
F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
FIGURE 2-6: PI C16F68 5 SPECIAL FUNCTION REGISTERS
DS40001262F-page 28 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
File File File File
Address Address Address Address
Indirect addr.
(1)
00h Indirect addr.
(1)
80h Indirect addr.
(1)
100h Indirect addr.
(1)
180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2
(1)
18Dh
TMR1L 0Eh PCON 8Eh EEDATH
(3)
10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH
(3)
10Fh 18Fh
T1CON 10h OSCTUNE 90h
110h 190h
11h 91h 111h 191h
12h 92h 112h 192h
SSPBUF 13h SSPADD
(2)
93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
15h WPUA 95h WPUB 115h 195h
16h IOCA 96h IOCB 116h 196h
17h WDTCON 97h 117h 197h
RCSTA 18h TXSTA 98h VRCON 118h
198h
TXREG 19h SPBRG 99h CM1CON0 119h 199h
RCREG 1Ah SPBRGH 9Ah CM2CON0 11Ah 19Ah
1Bh BAUDCTL 9Bh CM2CON1 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh
19Fh
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
32 Bytes
A0h
BFh
General
Purpose
Register
80 Bytes
(PIC16F689
only)
120h
1A0h
48 Bytes
(PIC16F689
only)
C0h
EFh
accesses
70h-7Fh
F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.
See Registers 13-2 and 13-3 for more details.
3: PIC16F689 only.
FIGURE 2-7: PIC16F687/PIC16F689 SPECIAL FUNCTION REGISTERS
2005-2015 Microchip Technology Inc. DS40001262F-page 29
PIC16F631/677/685/687/689/690
File File File File
Address Address Address Address
Indirect addr.
(1)
00h Indirect addr.
(1)
80h Indirect addr.
(1)
100h Indirect addr.
(1)
180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORT A 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2
(1)
18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh
18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh
18Fh
T1CON 10h OSCTUNE 90h
110h 190h
TMR2 11h
91h 111h 191h
T2CON 12h PR2 92h
112h 192h
SSPBUF 13h SSPADD
(2)
93h 113h 193h
SSPCON 14h SSPSTAT 94h
114h 194h
CCPR1L 15h WPUA 95h WPUB 115h 195h
CCPR1H 16h IOCA 96h IOCB 116h 196h
CCP1CON 17h WDTCON 97h
117h 197h
RCSTA 18h TXSTA 98h VRCON 118h 198h
TXREG 19h SPBRG 99h CM1CON0 119h 199h
RCREG 1Ah SPBRGH 9Ah CM2CON0 11Ah
19Ah
1Bh BAUDCTL 9Bh CM2CON1 11Bh 19Bh
PWM1CON 1Ch 9Ch 11Ch 19Ch
ECCPAS 1Dh
9Dh 1 1Dh PSTRCON 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh
19Fh
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
80 Bytes
A0h
General
Purpose
Register
80 Bytes
120h
1A0h
EFh 16Fh
accesses
70h-7Fh
F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.
See Registers 13-2 and 13-3 for more details.
FIGURE 2-8: PI C16F69 0 SPECIA L FUNCTION REGISTERS
DS40001262F-page 30 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
T ABLE 2-1: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
01h TMR0 Timer0 Module Register xxxx xxxx 79,200
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
03h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 35,200
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
05h PORTA
06h PORTB
07h PORTC
(7)
(7)
(7)
— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 57,200
RB7 RB6 RB5 RB4 — — — — xxxx ---- 67,200
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 74,200
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 43,200
0Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF
0Ch PIR1
0Dh PIR2
—ADIF
(4)
OSFIF C2IF C1IF EEIF — — — — 0000 ---- 41,200
RCIF
(2)
TXIF
(2)
SSPIF
(5)
CCP1IF
(3)
TMR2IF
(3)
TMR1IF -000 0000 40,200
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 85,200
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 85,200
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
11h TMR2
12h T2CON
13h SSPBUF
14h SSPCON
15h CCPR1L
16h CCPR1H
17h CCP1CON
18h RCSTA
19h TXREG
1Ah RCREG
(3)
Timer2 Module Register 0000 0000 89,200
(3)
(5)
(5, 6)
(3)
(3)
(2)
(2)
(2)
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 90,200
Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 178,200
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 177,200
Capture/Compare/PW M Regi st er 1 (LSB ) xxxx xxxx 126,200
Capture/Compare/PW M Regi st er 1 (MSB ) xxxx xxxx 126,200
(3)
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 125,200
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 158,200
EUSART Transmit Data Register 0000 0000 150
EUSART Receive Data Register 0000 0000 155
TMR1CS TMR1ON 0000 0000 87,200
1Bh — Unimplemented — —
PWM1CON
1Ch
ECCPAS
1Dh
1Eh ADRESH
1Fh ADCON0
(3)
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 143,200
(3)
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 140,200
(4)
A/D Result Register High Byte xxxx xxxx 113,200
(4)
ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 111,200
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR
and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F687/PIC16F689/PIC16F690 only.
3: PIC16F685/PIC16F690 only.
4: P IC16 F6 77 / PIC 16F 68 5/PI C1 6F 68 7/P IC1 6F 689 /P IC16 F690 only.
5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only .
6: When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers 13-2 and 13-3 for more detail.
7: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
Value on
POR, BOR
(1)
0000 000x 37,200
Page
2005-2015 Microchip Technology Inc. DS40001262F-page 31
PIC16F631/677/685/687/689/690
TABLE 2-2: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
81h OPTION_REG RABPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
83h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 35,200
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
85h TRISA
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 57,200
— — — — 1111 ---- 68,201
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 74,200
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
8Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF
8Ch PIE1
—ADIE
(4)
8Dh PIE2 OSFIE C2IE C1IE EEIE
8Eh PCON
8Fh OSCCON
90h OSCTUNE
— — ULPWUE SBOREN — —PORBOR --01 --qq 42,201
— IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 46,201
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 50,201
RCIE
(2)
TXIE
(2)
SSPIE
(5)
CCP1IE
(3)
TMR2IE
(3)
TMR1IE -000 0000 38,201
— — — — 0000 ---- 39,201
91h — Unimplemented — —
92h PR2
(3)
93h SSPADD
93h SSPMSK
94h SSPSTAT
95h WPUA
(6)
96h IOCA
97h WDTCON
98h TXSTA
(2)
99h SPBRG
9Ah SPBRGH
9Bh BAUDCTL
Timer2 Period Register 1111 1111 89,201
(5, 7)
Synchronous Serial Port (I2C mode) Address Register 0000 0000 184,201
(5, 7)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 187,201
(5)
SMP CKE D/A PSR/WUA BF 0000 0000 176,201
— —WPUA5WPUA4— WPUA2 WPUA1 WPUA0 --11 -111 60,201
— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 60,201
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 208,201
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 157,201
(2)
BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 160,201
(2)
BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 160,201
(2)
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 159,201
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh ADRESL
9Fh ADCON1
(4)
A/D Result Register Low Byte xxxx xxxx 113,201
(4)
— ADCS2 ADCS1 ADCS0 — — — — -000 ---- 112,201
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR
and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F687/PIC16F689/PIC16F690 only.
3: PIC16F685/PIC16F690 only.
4: P IC16 F6 77/PIC16F685/PIC16F687 /P IC1 6F6 89 /P IC16 F6 90 only.
5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
6: RA3 pull-up is enabled when pin is configured as MCLR
in Configuration Word.
7: Accessible only when SSPCON register bits SSPM<3:0> = 1001.
Value on
POR, BOR
(1)
0000 000x 37,200
Page
36,200
DS40001262F-page 32 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
T ABLE 2-3: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
101h TMR0 Timer0 Module Register xxxx xxxx 79,200
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
103h STATUS IRP RP1 RP0 TO
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
105h PORTA
106h PORTB
107h PORTC
108h — Unimplemented — —
109h — Unimplemented — —
10Ah PCLATH
10Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF
10Ch
10Dh
10Eh EEDATH
10Fh EEADRH
110h — Unimplemented — —
111h — Unimplemented — —
112h — Unimplemented — —
113h — Unimplemented — —
114h — Unimplemented — —
115h WPUB WPUB7 WPUB6 WPUB5 WPUB4
116h IOCB IOCB7 IOCB6 IOCB5 IOCB4
117h — Unimplemented — —
118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 103,201
119h CM1CON0 C1ON C1OUT
11Ah CM2CON0 C2ON C2OUT
11Bh CM2CON1 MC1OUT MC2OUT
11Ch — Unimplemented — —
11Dh — Unimplemented — —
11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3
11Fh ANSELH
Legend: – = Unimplemented locations read as ‘0’, u = unchange d, x = unknown , q = value depends on condition, shaded = unimplemented
Note 1: MCLR
(4)
(4)
(4)
EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 118,201
EEADR EEADR7
(2)
(2)
(3)
mismatch exists.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: P IC16 F6 77 / PIC 16F 68 5/PI C1 6F 68 7/P IC1 6F 689 /P IC16 F690 only.
4: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 57,200
RB7 RB6 RB5 RB4 — — — — xxxx ---- 67,200
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 74,200
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
(3)
EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 118,201
— —
— — — —
— — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 113,201
and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 96,201
C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 97,201
— — — — T1GSS C2SYNC 00-- --10 99,201
PD ZDCC0001 1xxx 35,200
EEADRH3 EEADRH2 EEADRH1 EEADRH0
— — — — 1111 ---- 68,201
— — — — 0000 ---- 68,201
(3)
ANS2
(3)
ANS1 ANS0 1111 1111 59,201
Value o n
POR, BOR
(1)
0000 000x 37,200
--00 0000 118,201
---- 0000 118,201
Page
2005-2015 Microchip Technology Inc. DS40001262F-page 33
PIC16F631/677/685/687/689/690
TABLE 2-4: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
(1)
Value on
POR, BOR
0000 000x
Page
36,200
37,200
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
181h OPTION_REG RABPU
182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
183h STATUS IRP RP1 RP0 TO
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
185h TRISA
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4
187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 74,201
188h — Unimplemented — —
189h — Unimplemented — —
18Ah PCLATH
18Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF
18Ch EECON1 EEPGD
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 117,201
18Eh — Unimplemented — —
18Fh — Unimplemented — —
190h — Unimplemented — —
191h — Unimplemented — —
192h — Unimplemented — —
193h — Unimplemented — —
194h — Unimplemented — —
195h — Unimplemented — —
196h — Unimplemented — —
197h — Unimplemented — —
198h — Unimplemented — —
199h — Unimplemented — —
19Ah — Unimplemented — —
19Bh — Unimplemented — —
19Ch — Unimplemented — —
19Dh PSTRCON
19Eh SRCON SR1 SR0 C1SEN C2REN PULSS PULSR
19Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unkno wn, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
2: PIC16F685/PIC16F690 only.
(2)
mismatch exists.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
PD ZDCC0001 1xxx 35,200
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 57,200
— — — — 1111 ---- 68,201
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
(2)
— — — WRERR WREN WR RD x--- x000 119,201
— — — STRSYNC STRD STRC STRB STRA ---0 0001 144,201
— — 0000 00-- 101,201
DS40001262F-page 34 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of t he ALU
• the Reset status
• the bank select bits for data memory (GPR and
SFR)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS r egister as dest ination may be different than
intended.
and PD bits are not
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged) .
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affecting any Status bit s , s ee Se ction 15.0 “Instruction Set
Summary”
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS: STATUS REGIS TER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PD ZDC
(1)
(1)
C
bit 7 IRP: Register Bank Select bit (used for indire ct addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Borrow
bit 0 C: Carry/Borrow
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by th e CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
(1)
(1)
Note 1: For Borrow
second operand. For rotate (RRF, RLF) instru ctions, t his bit i s loaded w ith eithe r the high -order or low -order
bit of the source register.
2005-2015 Microchip Technology Inc. DS40001262F-page 35
, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
PIC16F631/677/685/687/689/690
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
2.2.2.2 OPTION Register
The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:
• Timer0/WDT prescaler
• External RA2/INT interrupt
•Timer0
• Weak pull-ups on PORTA/PORTB
REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RABPU
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
INTEDG T0CS T0SE PSA PS2 PS1 PS0
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit of the OPT IO N r eg i ste r
to ‘1’. See Section 6.3 “Timer1 Pres-
caler”.
bit 7 RABPU
: PORTA/PORTB Pull-up Enable bit
1 = PORTA/PORTB pull-ups are disabled
0 = PORTA/PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/INT pin
0 = Interrupt on falling edge of RA2/INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on R A2/T0CKI pin
0 = Internal in struction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI pin
0 = Increment on low-to-high transition on RA2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
DS40001262F-page 36 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
2.2.2.3 INTCON Register
The INTCON register, shown in Register 2-3, is a
readable and writable register , which con tains the va rious
enable and flag bits for TMR0 register overflow, PORTA
change and external RA2/AN2/T0CKI/INT/C1OUT pin
interrupts.
Note: Interrupt flag bits are set when an in terrupt
condition occurs, re gardless of the st ate of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RABIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overfl ow Interru pt Enab le bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3 RABIE: PORTA/PORTB Change Interrupt Enable bit
1 = Enables the PORTA/PORTB change interrupt
0 = Disables the PORTA/PORTB change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 regi ster has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0 RABIF: PORTA/PORTB Change Interrupt Flag bit
1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be
cleared in software)
0 = None of the PORTA or PORTB general purpose I/O pins have changed state
(2)
(1,3)
(1,3)
T0IF
(2)
INTF RABIF
Note 1: IOCA or IOCB register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
3: Includes ULPWU interrupt.
2005-2015 Microchip Technology Inc. DS40001262F-page 37
PIC16F631/677/685/687/689/690
2.2.2.4 PIE1 Register
The PIE1 register contai ns th e in terru pt enable bits, as
shown in Register 2-4.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—
ADIE
(5)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note 1: PIC16F685/PIC16F690 only.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: PIC16F687/PIC16F689/PIC16F690 only.
4: PIC16F677/PIC16F687/PIC16F689/PIC1 6F6 90 onl y.
5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
RCIE
(3)
TXIE
(3)
(2)
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
SSPIE
(5)
(3)
(5)
(1)
(4)
CCP1IE
(4)
(2)
TMR2IE
(1)
TMR1IE
DS40001262F-page 38 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
2.2.2.5 PIE2 Register
The PIE2 register contai ns th e in terru pt enable bits, as
shown in Register 2-5.
REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
OSFIE C2IE C1IE EEIE — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
bit 4 EEIE: EE Write Operation Interrupt Enable bit
1 = Enables write operation interrupt
0 = Disables write operation interrupt
bit 3-0 Unimplemented: Read as ‘0’
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
2005-2015 Microchip Technology Inc. DS40001262F-page 39
PIC16F631/677/685/687/689/690
2.2.2.6 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
(5)
—
ADIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSA RT transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register over flowed (must be cleared in software)
0 = The TMR1 register did not overflow
Note 1: PIC16F685/PIC16F690 only.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: PIC16F687/PIC16F689/PIC16F690 only.
4: PIC16F677/PIC16F687/PIC16F689/PIC1 6F6 90 onl y.
5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
RCIF
(3)
TXIF
(2)
(3)
(5)
(3)
(1)
Note: Interrupt flag bits ar e set when an interrupt
condition occurs, regard less of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software sh ould ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
(3)
SSPIF
(4)
CCP1IF
(4)
(2)
TMR2IF
(1)
TMR1IF
DS40001262F-page 40 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
2.2.2.7 PIR2 Register
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
OSFIF C2IF C1IF EEIF — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4 EEIF: EE Write Operation Interrupt Flag bit
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
bit 3-0 Unimplemented: Read as ‘0’
Note: Interrupt flag bits are set when an in terrupt
condition occurs, re gardless of the st ate of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software sh ould ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
2005-2015 Microchip Technology Inc. DS40001262F-page 41
PIC16F631/677/685/687/689/690
2.2.2.8 PCON Register
The Power Control (PCON) register (see Register 2-8)
contains flag bits to differentiate between a:
Reset
)
.
(1)
— —PORBOR
• Power-on Reset (POR
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOR
REGISTER 2-8: PCON: POWER CONTROL REGISTER
U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
— — ULPWUE SBOREN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit
1 = Ultra Low-Power Wake-up enabled
0 = Ultra Low-Power Wake-up disabled
bit 4 SBOREN: Software BOR Enable bit
1 = BOR enabled
0 = BOR disabled
bit 3-2 Unimplemented: Read as ‘0’
bit 1 POR
bit 0 BOR
Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
(1)
.
DS40001262F-page 42 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
PC
12 8 7 0
5
PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
OPCODE<10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The lo w byte
comes from the PCL register, which is a readable and
writable register . The hig h byte (PC<12:8>) is not directl y
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-9 shows the two
situatio ns fo r t he l o ad i n g of t h e PC . T he u p per e x am pl e
in Figure 2-9 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> PCH). The lower example in
Figure 2-9 shows how the PC is lo aded during a CALL or
GOTO instruction (PCLATH<4:3> PCH).
FIGURE 2-9: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.2 STACK
The PIC16F631/677 /685/687/689/690 device s have an
8-level x 13-bit wide hardware stack (see Figures 2-2
and 2-3). The stack sp ace is not p art of either pro gram
or data space and the Stack Pointer is not readable or
writable. The PC is PUSHed onto the stack when a
CALL instruction is executed or an interrupt causes a
branch. The st ack i s POPed i n the e vent o f a RETURN,
RETLW or a RETFIE instructio n execu tion. PC LATH is
not affected by a PUSH or POP operation.
The stack operat es as a circular buf fer . This means th at
after the st ack ha s been PUSHed eight time s, th e nin th
push overwrites th e valu e that was s tore d from the firs t
push. The tenth pus h ov erwr i tes the se co nd push (and
so on).
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
2.4 Indirect Addressing, INDF and FSR Registers
2.3.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. Th is allo ws the enti re
contents of the program counter to be changed by
writing the desired upper five bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 13 bits of the program counter will
change to the values co ntaine d in the PCLATH register
and those being written to the PCL register.
A computed GOTO is accomplish ed by adding an offs et
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program b ranch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the low er eight bi ts of the memo ry
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
The INDF register is not a physica l register . Addr essing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actually
accesses data pointe d to by the File Select Register
(FSR). Reading IN DF itself in directly wil l produc e 00h.
Writing to the INDF register indirectly results in a no
operation (although Status bits may be affected). An
effectiv e 9-bit ad dress is ob tain ed by con caten ating th e
8-bit FSR and the IRP bit of the STATUS register, as
shown in Figure 2-10.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESSING
2005-2015 Microchip Technology Inc. DS40001262F-page 43
PIC16F631/677/685/687/689/690
For memory map detail, see F igures 2-6, 2-7 and 2-8.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Locat ion Select
RP1 RP0 6
0
From Opcode
IRP File Select Register
7
0
Bank Select
Location Select
00 01 10 11
180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
FIGURE 2-10: DIRECT/INDIRECT ADDRESS ING PIC16F631/677/685/687/689/690
DS40001262F-page 44 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
(CPU and Peripherals)
OSC1
OSC2
Sleep
External Oscillator
LP, XT, HS, RC, RCIO, EC
System Clock
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000
31 kHz
Power-up Timer (PWRT)
FOSC<2:0>
(Configuration Word Register)
SCS<0>
(OSCCON Register)
Internal Oscillator
(OSCCON Register)
Watchdog Time r (WDT)
Fail-Safe Clock Monitor (FSCM)
HFINTOSC
8 MHz
LFINTOSC
31 kHz
INTOSC
3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
3.1 Overview
The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applicati ons while maximiz ing performance and minimizing power consumption. Figure 3-1
illustrates a block diagram of the Oscillator module.
Clock sources can be configured from external
oscillators, quartz cryst al resonators , ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds select able via
software. Additional clo ck feat ures inc lud e:
• Selectable system clock source between external
or intern al via software.
• T wo -Speed Start-up mode, which min im iz es
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
The Oscillator mod ule can be c onfigured in one of eig ht
clock modes.
1. EC – External clock with I/O on OSC2/CLKOUT.
2. LP – 32 kHz Low-Power Crystal mode.
3. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
4. HS – High Gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC) with
OSC/4 output on OSC2/CLKOUT.
F
6. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
7. INTOSC – Internal oscillator with F
OSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
Clock Source modes are configured by the FO SC<2:0>
bits in the Configuration Word register (CONFIG). The
internal clock can be generated from two internal
oscillators. The HFINTOSC is a calibrated highfrequency oscillator. The LFINTOSC is an uncalibrate d
low-frequency oscillator.
FIGURE 3-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
2005-2015 Microchip Technology Inc. DS40001262F-page 45
PIC16F631/677/685/687/689/690
3.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 3-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• Frequency Status bits (HTS, LTS)
• System clock control bits (OSTS, SCS)
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
(1)
(1)
HTS LTS SCS
— IRCF2 IRCF1 IRCF0 OSTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 =8MHz
110 =4MHz (default)
101 =2MHz
100 =1MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
bit 3 OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG register
0 = Device is running from the internal os cillator (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stabl e
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the CONFIG register
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
DS40001262F-page 46 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
OSC1/CLKIN
OSC2/CLKOUT
(1)
I/O
Clock from
Ext. System
PIC
®
MCU
Note 1: Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
3.3 Clock Source Modes
Clock Source modes can be classified as external or
internal.
• External Clock m odes rely on e xternal c ircui try fo r
the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
• Internal clock sources are contained internally
within the Oscillator module. The Oscillator
module has two internal oscillators: the 8 MHz
High-Frequency Internal Oscillator (HFINTOSC)
and the 31 kHz Low-Frequency Inte rnal Osci llator
(LFINTOSC).
The system clock can be selected between extern al or
internal clock sources via the System Clock Select
(SCS) bit of the OSCCON register. See Section 3.6
“Clock Switching” for additional information.
3.4 External Clock Modes
3.4.1 OSCILLATOR START-UP TIMER (OST)
If the Oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator o r ce ramic res onator, has started and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 3-1.
In order to minimize laten cy between externa l oscillator
start-up and code execution, the Two-Speed Clock
Start -up mode ca n be selected (s ee Section 3.7 “T wo-
Speed Clock Start-up Mode”).
TABLE 3-1: OSCILLATOR DELAY EXAMPLES
Switch From Switch To Frequency Oscillator Delay
Sleep/POR
Sleep/POR EC, RC DC – 20 MHz 2 cycles
LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)
LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 s (approx.)
LFINTOSC
HFINTOSC
31 kHz
125 kHz to 8 MHz
Oscillator Warm-up Delay (T
WARM)
3.4.2 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 3-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
2005-2015 Microchip Technology Inc. DS40001262F-page 47
®
MCU design is fully
FIGURE 3-2: EXTERNAL CLOCK (EC)
MODE OPERATION
PIC16F631/677/685/687/689/690
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of R
F varies with the Oscillator mode
selected (typically between 2 M to 10 M.
C1
C2
Quartz
R
S
(1)
OSC1/CLKIN
RF
(2)
Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of R
F varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (R
P)
may be required for proper ceramic resonator
operation.
C1
C2
Ceramic
R
S
(1)
OSC1/CLKIN
RF
(2)
Sleep
To Internal
Logic
PIC® MCU
RP
(3)
Resonator
OSC2/CLKOUT
3.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 3-3). The mode selects a low ,
medium or high gain setting of the internal inverteramplifier to support v arious resonato r types and spee d.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consum ption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medi um of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode select s the highest gain setting of the
internal inverter-amplifie r. H S mode current consum ption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 3-3 and Figure 3-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
.
Note 1: Quartz crystal characteristics vary accord-
ing to type, p ackage an d manuf acturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
2: Always verify oscillator pe rformance over
DD and temperature range that is
the V
expected for the application.
3: For oscillator desig n assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC
Devices” (DS00826)
• AN849, “Basic PIC
(DS00849)
• AN943, “Practical PIC
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
®
and PIC®
®
Oscillator Design”
®
Oscillator
FIGURE 3-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 3-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
DS40001262F-page 48 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
OSC2/CLKOUT
(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
F
OSC/4 or
Internal
Clock
VDD
VSS
Recommended values: 10 k REXT 100 k, <3V
3 k R
EXT 100 k, 3-5V
C
EXT > 20 pF, 2-5V
Note 1: Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO Clock
mode.
I/O
(2)
3.4.4 EXT ERN AL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 3-5 shows the
external RC mode connections.
FIGURE 3-5: EXTERNAL RC MODES
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capa citance
The user also needs to take into account variation due
to tolerance of external RC components used.
2005-2015 Microchip Technology Inc. DS40001262F-page 49
EXT) and capacitor (CEXT) values
3.5 Internal Clock Modes
The Oscillator module has two independent, internal
oscillators that can be configured or selected as the
system clock sou rce.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
8 MHz. The frequency o f the HFINT O SC can be
user-adjusted via software using the OSCTUNE
register (Register 3-2).
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
The system cloc k speed can be selecte d via softwar e
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
The system clock ca n be se lec ted betw ee n external or
internal cloc k sourc es via th e System Cl ock Select ion
(SCS) bit of the OSCCON register. See Section 3.6
“Clock Switching” for more information.
3.5.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is progra mmed usi ng the osc illator selectio n
or the FOSC<2:0> bits in the Configuration Word
register (CONFIG).
In INTOSC mode, OSC1/CLKIN i s available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator fre quency div ided by 4. The C LKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
3.5.2 HFINTOSC
The High-Frequency Int ernal Oscillato r (HFINT OSC) is
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 3-2).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 3.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz by set ting th e IRCF <2:0 >
bits of the OSCCON register 000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to ‘1’ or enabl e Two-Speed Start-up by setting
the IESO bit in the Configuration Word register
(CONFIG) to ‘1’.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
PIC16F631/677/685/687/689/690
3.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register3-2).
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not af fected by the
change in frequency.
REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the factory-calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
DS40001262F-page 50 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
3.5.3 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure3-1). Select 31 kHz, via
software, using the IRCF<2:0> bits of the OSCCON
register. See Section 3.5.4 “Frequency Select Bits
(IRCF)” for more information. The LFINTO SC is also the
frequency for the Power-up Timer (PWRT), Watchdog
Timer (WDT) and Fail-Safe Clock Mo nitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<2:0> bits of the OSCCON register= 000) as the
system clock source (SCS bit of the OSCCON
register = 1), or when any of the following are enable d:
• T wo-Speed Start-up IESO bit of the Con fig urati on
Word register = 1 and IRCF<2:0> bits of the
OSCCON register = 000
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit of the OSCCON
register indicates whether the LFINTOSC is stable or
not.
3.5.4 FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 3 -1). The Internal Oscillator Frequency
Select b its IRCF<2:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
eight frequencies can be selected via software:
•8 MHz
• 4 MHz (Default after Reset)
•2 MHz
•1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
• 31 kHz (LFINTOSC)
Note: Following any Reset, the IRCF<2:0> bits
of the OSCCON register are set to ‘110’
and the frequency selection is set to
4 MHz. The user can modify the IRCF bit s
to select a different frequency.
3.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
down to save power (s ee Figure 3-6). If this is th e case,
there is a delay after the IRCF<2:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The LTS and HTS bits of the
OSCCON regis ter will re flect th e current active status
of the LFINTOSC and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
1. IRCF<2:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch ci rcuitry waits for a fal ling edge of
the current cl ock.
4. CLKOUT is held low and the clock switch
circuitry waits fo r a ris ing edge in the new clock.
5. CLKOUT is now connected with the new clock.
LTS and HTS bits of the OS CCON regi ster are
updated as required.
6. Clock switch is complete.
See Figure 3-1 for more details.
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and new frequencies are derived from the HFINTOSC
via the postscaler and multi ple xe r.
Start-up delay specifications are located in the
oscillator tables of Section 17.0 “Electrical
Specifications”.
2005-2015 Microchip Technology Inc. DS40001262F-page 51
PIC16F631/677/685/687/689/690
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
0 0
0 0
Start-up Time
2-cycle Sync Running
2-cycle Sync Running
HFINTOSC LFINTOSC (FSCM and WDT disabled)
HFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
LFINTOSC
HFINTOSC
IRCF <2:0>
System Clock
= 0 ¼ 0
Start-up Time 2-cycle Sync
Running
LFINTOSC HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
FIGURE 3-6: INTE RNAL OSCILLATOR SWITCH TIMING
DS40001262F-page 52 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
3.6 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit of the OSCCON
register.
3.6.1 SYSTEM CLOCK SELECT (SCS) BIT
The System C lock Select (SCS) bit of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bit of the OSCCON register = 0,
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Configuration Word register ( CONFIG).
• When the SCS bit of the OSCCON register = 1,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<2:0>
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is always
cleared.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or FailSafe Clock Monitor, does not update the
SCS bit of the OSCCON register . The user
can monitor the OSTS bit of the OSCCON
register to determine the current system
clock source.
3.6.2 O SCIL LA TOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word register (CONFIG), or from the internal clock
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
3.7 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 3.4.1 “Oscillator Start-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count rea ches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
3.7.1 TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Word register) = 1;
Internal/External Switc hov er b it (Two-Speed St artup mode enabled).
• SCS (of the OSCCON register) = 0.
• FOSC<2:0> bits in the Configuration Word
register (CONFIG) configured for LP, XT or HS
mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Twospeed Start-up is disabled. This is because the external
clock oscillator do es not require any stabilizat ion time
after POR or an exit from Sleep.
3.7.2 TWO-SPEED START-UP SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS b it of the OSCCON register to
remain clear.
2005-2015 Microchip Technology Inc. DS40001262F-page 53
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0 1 1022 1023
PC + 1
TOSTT
HFINTOSC
OSC1
OSC2
Program Counter
System Clock
PC - N
PC
3.7.3 CHECKING TWO-SPEED CLOCK STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word register
(CONFIG), or the internal oscillator.
FIGURE 3-7: TWO-SPEED START-UP
DS40001262F-page 54 2005-2015 Microchip Technology Inc.
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External
LFINTOSC
÷ 64
S
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
3.8 Fail-Safe Clock Monitor
The Fail-Safe Clock Monit or (FSCM) al low s the dev ic e
to continue operat ing sh ould the external osci ll ator fai l.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word register (CONFIG). The FSCM is
applicable to all exte rnal Oscillator modes (L P, XT, HS,
EC, RC and RCIO).
FIGURE 3-8: FSCM BLOCK DIAGRAM
3.8.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the ex tern al osci llator to the FS CM samp le
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 3-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock cle ars the latch on each ris ing edge of th e
sample clock. A fail ure is d ete cte d w h en an ent ire halfcycle of the sample clock elapses before the primary
clock goes low.
3.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or togg ling the S CS bit
of the OSCCON register. When th e S C S b i t i s t o g gl ed ,
the OST is restarted. While the OST is running, the
device continue s to op erat e from t he INT OSC sele cted
in OSCCON. When the OST times out, the Fail-Safe
condition is cleared and the device will be operating
from the external clock s ource. Th e Fail-Sa fe condi tion
must be cleared before th e O SFIF f lag ca n be cle are d.
3.8.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the R eset or wake- up has complet ed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
3.8.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal cl ock sourc e and set s the b it
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
2005-2015 Microchip Technology Inc. DS40001262F-page 55
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OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system clock is normally at a much higher frequency than t he sample clock. The r elative frequencies in
this example have been chosen for clarity.
(Q)
Test
Test Test
Clock Monitor Output
FIGURE 3-9: FSCM TIMING DIAGRAM
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG
OSCCON
OSCTUNE
PIE1
PIR1
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR
(2)
2: See Configuration Word register (Register 14-1) for operation of all register bits.
CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
— IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
— ADIF RCIF T XIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
Reset and Watchdog Timer Reset during normal operation.
Val ue on
POR, BOR
Val ue on
all other
Resets
(1)
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BCF STATUS,RP0;Bank 0
BCF STATUS,RP1;
CLRF PORTA ;Init PORTA
BSF STATUS,RP1;Bank 2
CLRF ANSEL ;digital I/O
BSF STATUS,RP0;Bank 1
BCF STATUS,RP1;
MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ;and set RA<5:4,1:0>
;as outputs
BCF STATUS,RP0;Bank 0
4.0 I/O PORTS
There are as many as eighteen general purpose I/O
pins available. Depending on which peripherals are
enabled, some or all of the pins may not be a vailable a s
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
4.1 PORTA and the TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Regis ter 4-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRIS A bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables output
driver and puts the contents of the output latch on the
selected pin). The exception is RA3, which is input only
and its TRIS bit will always read as ‘1’. Example 4-1
shows how to initialize PORTA.
Reading the PORTA register (Register 4-1) reads the
status of the pins, whereas writing to it wil l write to the
PORT latch. All write operations are read-modify-write
REGISTER 4-1: PORTA: PORTA REGISTER
operations. Therefore, a write t o a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1.
The TRISA register controls the PORTA pin output
drivers, even when they are being used as analog inputs.
The user should ensure the bits in the TRISA register are
maintained set when using them as analog inputs. I/O
pins configured as analog input always read ‘0’.
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
EXAMPLE 4-1: INITIALIZING PORTA
U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 7-6 U nimplemented: Read as ‘0’
bit 5-0 RA<5:0>: PORTA I/O Pin bit
1 = Port pin is > V
0 = Port pin is < VIL
REGISTER 4-2: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 7-6 U nimplemented: Read as ‘0’
bit 5-0 TRISA<5: 0>: PORTA Tri-S tate Control bit
Note 1: TRISA<3> always reads ‘1’.
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
2005-2015 Microchip Technology Inc. DS40001262F-page 57
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
IH
PIC16F631/677/685/687/689/690
4.2 Additional Pin Functions
Every PORT A pin o n this device family has an in terrupton-change option and a weak pull-up option. RA0 also
has an Ultra Low-Power Wake-up option. The next
three sections describe these functions.
4.2.1 ANSEL AND ANSELH REGISTERS
The ANSEL and ANSELH registers are used to disable
the input buffers of I/O pins, which allow analog voltages
to be applied to those pins witho ut causing excessive
current. Setting the ANSx bit of a corresponding pin will
cause all digital reads of th at pin to return ‘ 0’ and also
permit analog functions of that pin to operate correctly.
The state of the ANSx bit has no effect on the digital
output function of its corresponding pin. A pin w ith the
TRISx bit clear and ANSx bit set will operate as a digital
output, together with the analog input function of that
pin. Pins with the A NSx bit set always re ad ‘0’, which
can cause unexpected behavior when execu ting read
or write operations on the port due to the r ead-modifywrite sequence of all such operations.
4.2.2 WEAK PULL-UPS
Each of the PORTA pins, except RA3, has an
individually configurable internal weak pull-up. Control
bits WPUAx enable or disable each pull-up. Refer to
Register 4-4. Each weak pull-up i s automatically turne d
off when the p ort pin is co nfigured as an output. T he
pull-ups are disabled on a Power-on Reset by the
RABPU
automatically enabled for RA3 when configured as
MCLR
software control of the MCLR
bit of the OPTION register. A weak pull-up is
and disabled when RA3 is an I/O. There is no
pull-up.
4.2.3 INTERRUPT-ON-CHANGE
Each PORTA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCAx enable or
disable the interrupt function for each pin. Refer to
Register 4-6. The i nte r rup t -o n- c ha n ge is di sa bl e d on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latch ed on the last rea d of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set th e PORTA Change Interrupt Flag
bit (RABIF) in the INTCON register (Register 2-6).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a) Any read or write of PORTA. This will end the
mismatch condition, then,
b) Clear the flag bit RABIF.
A mismatch condition will continue to set flag bit RABIF .
Reading PORTA will end the mismatch condition and
allow flag bit RABIF to be cleared. The latch holding the
last read value is not affected by a MCLR
Reset. After these R esets, the RABIF flag w il l continue
to be set if a mismatch is present.
Note: If a change on the I/O pin should occur
when the read operation is being executed (start of the Q2 cycle), then the
RABIF interrupt flag may not get set.
nor BOR
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REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANS<7:0>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
REGISTER 4-4: ANSELH: ANALOG SELECT HIGH REGISTER
(1)
.
(2)
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — ANS11 ANS10 ANS9 ANS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 ANS<11:8>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
(1)
.
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REGISTER 4-5: WPUA: PORTA REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 WPUA<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 WPUA<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RABPU
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
bit of the OPTION register must be enabled for individual pull-ups to be enabled.
REGISTER 4-6: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
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BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
BSF PORTA,0 ;Set RA0 data latch
BSF STATUS,RP1 ;Bank 2
BCF ANSEL,0 ;RA0 to digital I/O
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
BCF TRISA,0 ;Output high to
CALL CapDelay ;charge capacitor
BSF PCON,ULPWUE ;Enable ULP Wake-up
BSF IOCA,0 ;Select RA0 IOC
BSF TRISA,0 ;RA0 to input
MOVLW B’10001000’ ;Enable interrupt
MOVWF INTCON ;and clear flag
BCF STATUS,RP0 ;Bank 0
SLEEP ;Wait for IOC
NOP ;
4.2.4 ULTRA LOW-POWER WAKE-UP
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows
a slow falling voltage to generate an interrupt-on-change
on RA0 without excess current consumption. The mode
is selected by setting the ULPWUE bit of the PCON
register. This enables a small c urrent sink, which can be
used to discharge a capacitor on RA0.
Follow these steps to use this feature:
a) Charge the capacitor on RA0 by configuring the
RA0 pin to output (= 1).
b) Configure RA0 as an input.
c) Enable interrupt-on-change for RA0.
d) Set the ULPWUE bit of the PCON register to
begin the capacitor discharge.
e) Execute a SLEEP instruction.
When the voltage on RA0 drops below V
will be generated which will cause the device to wakeup and execute the next instruction. If the GIE bit of the
INTCON register is set, the device will then call the
interrupt vector (0004h). See Section 4.4.2 “Interrupt-
on-change” and Section 14.3.3 “PORTA/PORTB
Interrupt” for more information.
This feature provides a low-power technique for
periodically waking up the device from Sleep. The
time-out is dependent on the discharge time of the RC
circuit on RA0. See Example 4-2 for initializing the
Ultra Low-Power Wake-up module.
IL, an interrupt
A series resistor between RA0 and the external
capacitor provides overcurrent protection for the RA0/
AN0/C1IN+/ICSPDAT/ULPWU pin and can allow for
software calibration of the time-out (see Figure 4-1). A
timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to pro vi de th e de si red i nter r upt d ela y.
This technique will compensate for the affects of
temperature, voltage and component accuracy. The
Ultra Low-Power Wake-up peripheral can also be
configured as a simple Programmable Low-Voltage
Detect or temperature sensor.
Note: For more information, refer to Application
Note AN879, “Using the Microchip Ultra
Low-Power Wa ke-up Modul e” (DS00879).
EXAMPLE 4-2: ULTRA LOW-POWER
WAKE-UP INITIALIZATION
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I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
RD PORTA
RD
WR
WR
RD
WR
IOCA
RD
IOCA
Interrupt-on-Change
To Comparator
Analog
(1)
Input Mode
RABPU
Analog
(1)
Input Mode
Q3
WR
RD
01
IULP
WPUA
Data Bus
WPUA
PORTA
TRISA
TRISA
PORTA
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
-
+V
T
ULPWUE
To A/D Converter
(2)
VSS
4.2.5 PIN DESCRIPTIONS AND DIAGRAMS
Each PORT A pin is multiplexed with other functio ns. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D Converter (ADC),
refer to the appropriate section in this data sheet.
FIGURE 4-1: BLOCK DIAGRAM OF RA0
4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU
Figure 4-2 shows the diagram for this pin. The RA0/
AN0/C1IN+/ICSPDAT/ULPWU pin is configurable to
function as one of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• an analog input to Comparator C1
• In-Circuit Serial Programming™ data
• an analog input for the Ultra Low-Power Wake-up
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I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUA
RD
WPUA
RD PORTA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
Interrupt-on-
To Compar ator
Analog
(1)
Input Mode
RABPU
Analog
(1)
Input Mode
Change
Q3
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
To A/D Converter
(2)
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
(1)
Input Mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To A/D Converter
(2)
0
1
C1OUT
C1OUT
Enable
To INT
To Timer0
Analog
(1)
Input Mode
RABPU
RD PORTA
Interrupt-on-
Change
Q3
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
4.2.5.2 RA1/AN1/C12IN0-/VREF/ICSPCLK
Figure 4-2 shows the diagram for this pin. The RA1/
AN1/C12IN0-/V
REF/ICSPCLK pin is configurable to
function as one of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• an analog input to Comparator C1 or C2
• a voltage reference input for the ADC
• In-Circuit Serial Programming clock
FIGURE 4-2: BLOCK DIAGRAM OF RA1
2005-2015 Microchip Technology Inc. DS40001262F-page 63
4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT
Figure 4-3 shows the di agram for th is pin. The RA2 /AN2/
T0CKI/INT/C1OU T pin is con figura ble t o fu nction as on e
of the followi ng:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• the clock input for Timer0
• an external edge triggered interrupt
• a digital output from Comparator C1
FIGURE 4-3: BLOCK DIAGRAM OF RA2
PIC16F631/677/685/687/689/690
Input
V
SS
D
Q
CK
Q
D
EN
Q
Data Bus
RD PORTA
RD
PORTA
WR
IOCA
RD
IOCA
Reset
MCLRE
RD
TRISA
VSS
D
EN
Q
MCLRE
VDD
Weak
MCLRE
Interrupt-on-
Change
Pin
Q3
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
FOSC/4
To A/D Converter
(4)
Oscillator
Circuit
OSC1
CLKOUT
0
1
CLKOUT
Enable
Enable
Analog
(3)
Input Mode
RABPU
RD PORTA
To T1G
INTOSC/
RC/EC
(2)
CLK
(1)
Modes
CLKOUT
Enable
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3: ANSEL determines Analog Input mode.
4: Not implemented on PIC16F631.
Interrupt-on-
Change
Q3
4.2.5.4 RA3/MCLR/VPP
Figure 4-4 shows the dia gram for this pin. The RA3/
/VPP pin is configurab le t o fu nct ion as one of the
MCLR
following:
• a general purpose input
• as Master Clear Reset with weak pull-up
FIGURE 4-4: BLOCK DIAGRAM OF RA3
4.2.5.5 RA4/AN3/T1G
/OSC2/CLKOUT
Figure 4-5 shows the diagram for this pin. The RA4/
AN3/T1G
/OSC2/CLKOUT pin is configurable to
function as one of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a Timer1 gat e input
• a crystal/reso na tor con nection
• a clock output
FIGURE 4-5: BLOCK DIAGRAM OF RA4
DS40001262F-page 64 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To TMR1 or CLKGEN
INTOSC
Mode
RD PORTA
INTOSC
Mode
RABPU
OSC2
(2)
Note 1:Timer1 LP Oscillator enabled.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
TMR1LPEN
(1)
Interrupt-on-
Change
Oscillator
Circuit
Q3
4.2.5.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagr am for this pin. The RA5/
T1CKI/OSC1/CLKIN pin is configurable to function as
one of the following:
• a general purpose I/O
• a Timer1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 4-6: BLOCK DIAGRAM OF RA5
2005-2015 Microchip Technology Inc. DS40001262F-page 65
PIC16F631/677/685/687/689/690
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADCON0
ANSEL
CM1CON0
INTCON GIE
IOCA
OPTION_REG
PORTA
SSPCON
T1CON
TRISA
WPUA
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
ADFM VCFG CHS3 CHS2 CHS1 CHS0
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000
PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
— — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111
GO/DONE
ADON 0000 0000 0000 0000
POR, BOR
Value on
Value on
all other
Resets
DS40001262F-page 66 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTB ;Init PORTB
BSF STATUS,RP0 ;Bank 1
MOVLW FFh ;Set RB<7:4> as inputs
MOVWF TRISB ;
BCF STATUS,RP0 ;Bank 0
4.3 PORTB and TRISB Registers
PORTB is a 4-bit wide, bidirectional port. The
corresponding data direct ion regist er is TRISB (Regis ter
4-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output d river in a Hi gh-Impedance mod e).
Clearing a TRIS B bi t (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 4-3 shows how to initialize PORTB. Reading
the PORTB register (Register 4-5) reads the st atus of the
pins, whereas writ ing to it will wri te to the PORT l atch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is m odified and then writte n to the PO RT
data latch.
The TRISB register controls the PORTB pin output
drivers, even when they are being used as analog inputs.
The user should ensure the bits in the TRISB register are
maintained set when using them as analog inputs. I/O
pins configured as analog input always read ‘0’.
EXAMPLE 4-3: INITIALIZING PORTB
Note: The ANSELH register must be initialized
to configure an analo g channel as a di gital
input. Pins configured as analog inputs
will read ‘0’.
4.4 Additional PORTB Pin Functions
PORTB pins RB<7 :4> on the device fam ily device have
an interrupt-on-change option and a weak pull-up
option. The following three sections describe these
PORTB pin functions.
4.4.1 WEAK PULL-UPS
Each of the PORTB pins has an indiv idually configurable
internal weak pull-up. Control bits WPUB<7:4> enable or
disable each pull-up (see Register 4-9). Each weak
pull up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RABPU
bit of the OPTION
register.
4.4.2 INTERRUPT-ON-CHANGE
Four of the PORTB pins are individually configurable as
an interrupt-on-change pin. Control bits IOCB<7:4>
enable or disable the interrupt function for each pin.
Refer to Register 4-10. The interrupt-on-change feature
is disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present
value is compared w ith the old value latched on the las t
read of PORTB to determine which bits have changed
or mismatch the old value. The ‘mismatch’ outputs are
OR’d together to set the PORTB Change Interrupt flag
bit (RABIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The user ,
in the Interrupt Service Routine, clears the interrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RABIF.
A mismatch conditio n will contin ue to set flag bit RABIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RABIF to be cleared. The latch
holding the last read value is not affected by a MCLR
Brown-out Reset . After these Resets, the RABIF fla g will
continue to be set if a mismatch is present.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pins in Interrupt- on-Change mode.
Changes on one pin may not be seen while
servicing changes on another pin.
nor
REGISTER 4-7: PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 RB<7:4>: PORTB I/O Pin bit
bit 3-0 Unimplemented: Read as ‘0’
2005-2015 Microchip Technology Inc. DS40001262F-page 67
1 = Port pin is > V
0 = Port pin is < VIL
— — — —
IH
PIC16F631/677/685/687/689/690
REGISTER 4-8: TRISB: PORTB TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
TRISB7 TRISB6 TRISB5 TRISB4
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
— — — —
bit 7-4 TRISB<7: 4>: PORTB Tri-State Control bit
bit 3-0 U nimplemented: Read as ‘0’
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
REGISTER 4-9: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 7-4 WPUB<7:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 U nimplemented: Read as ‘0’
Note 1: G lobal RABPU
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISB<7:4> = 0).
bit of the OPTION register must be enabled for individual pull-ups to be enabled.
— — — —
REGISTER 4-10: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4
bit 7 bit 0
— — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 3-0 U nimplemented: Read as ‘0’
DS40001262F-page 68 2005-2015 Microchip Technology Inc.
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I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To SSPSR
Analog
(1)
Input Mode
RABPU
Analog
(1)
Input Mode
Change
Q3
To A/D Converter
(2)
ST
SSPEN
0
1
1
0
Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690
only.
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
0
1
1
0
SSPSR
From
SSP
4.4.3 PIN DESCRIPTIONS AND DIAGRAMS
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about i ndividual functions
such as the SSP, I
appropriate section in this data sheet.
2
C™ or interrupts, refer to the
4.4.3.1 RB4/AN10/SDI/SDA
Figure 4-7 shows the diagram for this pin. The RB4/
AN10/SDI/SDA
of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a SPI data I/O
2
C data I/O
•an I
(1)
pin is configurable to fu nction as on e
Note 1: SDI and SDA are available on
PIC16F677
/PIC16F687/PIC16F689/
PIC16F690 only.
FIGURE 4-7: BLOCK DIAGRAM OF RB4
2005-2015 Microchip Technology Inc. DS40001262F-page 69
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I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
T o EUSART RX/DT
Analog
(1)
Input Mode
RABPU
Analog
(1)
Input Mode
Change
Q3
To A/D Converter
(2)
SYNC
ST
EUSART
DT
SPEN
Available on PIC16F687/PIC16F689/PIC16F690 only.
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
0
1
1
0
0
1
1
0
From
EUSART
4.4.3.2 RB5/AN11/RX/DT
(1, 2)
Figure 4-8 shows the dia gram for this pin. The RB5/
AN11/RX/DT pin is configurable to function as one of
the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• an asynchronous serial input
• a synchronous serial data I/O
Note 1: RX and DT are avai lab le o n PIC 16F68 7/
PIC16F689/PIC16F690 only.
2: AN11 is not imp lemen ted o n PIC 1 6F6 31.
FIGURE 4-8: BLOCK DIAGRAM OF RB5
DS40001262F-page 70 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To SSP
RABPU
Change
Q3
SSPEN
ST
0
1
1
0
Available on PIC16F6 77/PIC16F 687/P IC16F68 9/PIC16F690
only.
0
1
1
0
From
SSP
SSP
Clock
4.4.3.3 RB6/SCK/SCL
Figure 4-9 shows the diagr am for this pin. The RB6/
SCK/SCL
following:
• a general purpose I/O
• a SPI clock
•an I
(1)
pin is configura ble to func tion as one of the
2
C™ clock
Note 1: SCK and SCL are available on
PIC16F677/PIC16F687/PIC16F689/
PIC16F690 only.
FIGURE 4-9: BLOCK DIAGRAM OF RB6
2005-2015 Microchip Technology Inc. DS40001262F-page 71
PIC16F631/677/685/687/689/690
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
RABPU
Change
Q3
SPEN
TXEN
CK
TX
SYNC
EUSART
EUSART
0
1
1
0
0
1
1
0
Available on PIC16F687/PIC16F689/PIC16F690 only.
0
1
1
0
‘1’
4.4.3.4 RB7/TX/CK
Figure 4-10 shows the diagram for this pin. The RB7/
(1)
TX/CK
following:
• a general purpose I/O
• an asynchronous serial output
• a synchronous clock I/O
pin is configurable to function as one of the
Note 1: TX and CK are available on PIC16F687/
PIC16F689/PIC16F690 only.
FIGURE 4-10: BLOCK DIAGRAM OF RB7
DS40001262F-page 72 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
T ABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ----
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----
TRISB TRISB7 TRISB6 TRISB5 TRISB4
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PORTB.
— — — — 1111 ---- 1111 ----
Value on
POR, BOR
Value on
all other
Resets
2005-2015 Microchip Technology Inc. DS40001262F-page 73
PIC16F631/677/685/687/689/690
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTC ;Init PORTC
BSF STATUS,RP1 ;Bank 2
CLRF ANSEL ;digital I/O
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW 0Ch ;Set RC<3:2> as inputs
MOVWF TRISC ;and set RC<5:4,1:0>
;as outputs
BCF STATUS,RP0 ;Bank 0
4.5 PORTC and TRISC Registers
PORTC is a 8-bit wide, bidirectional port. The
corresponding data direction regi s ter is T RISC (Register
4-10). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
correspondin g output dr iver in a H igh-Impeda nce mode ).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e ., en able the ou tput d rive r and
put the contents of t he outp ut l atc h on t h e se le cted pi n) .
The TRISC register controls the PORTC pin output
drivers, even w hen they are be ing used as analo g inputs .
The user should ensure the bits in the TRISC register are
maintained set when using them as analog inputs. I/O
pins config ure d a s an al og i np ut always read ‘0’.
Note: The ANSEL and ANSELH registers must
be initialized to configure an analog
channel as a digital input. Pins configu red
as analog inputs will read ‘0’.
Example 4-4 sh ows how to initialize P ORTC. Reading
the PORTC regi ster (Register 4 -9) reads the st atus of the
EXAMPLE 4-4: INITIALIZING PORTC
pins, whereas wr iting to it will wr ite to the POR T la tch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the PORT
data latch.
REGISTER 4-11: PORTC: PORTC REGISTER
R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bit
1 = Port pin is > V
0 = Port pin is < VIL
IH
REGISTER 4-12: TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISC<7: 0>: PORTC Tri-State Control bit
DS40001262F-page 74 2005-2015 Microchip Technology Inc.
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
PIC16F631/677/685/687/689/690
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter
(2)
RD
PORTC
Analog Input
Mode
(1)
To Compar ators
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To Comparators
RD
PORTC
Analog Input
Mode
(1)
CCP1OUT
CCP1OUT
Enable
Available on PIC16F685/PIC16F690 only.
Note 1: ANSEL determines Analog Input mode.
2: Not implem ented on PIC16F631.
0
1
1
0
I/O Pin
To A/D Converter
(2)
4.5.1 RC0/AN4/C2IN+
The RC0 is configurable to function as one of the
following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• an analog input to Comparator C2
4.5.2 RC1/AN5/C12IN1-
The RC1 is configurable to function as one of the
following:
• a general purpose I/O
• an analog input for the ADC
• an analog input to Comparator C1 or C2
FIGURE 4-11: BLOCK DIAGRAM OF RC0
AND RC1
4.5.3 RC2/AN6/C12IN2-/P1D
The RC2/AN6/P1D
one of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a PWM output
• an analog input to Comparator C1 or C2
Note 1: P1D is available on PIC16F685/
(1)
is configurable to function as
PIC16F690 only.
4.5.4 RC3/AN7/C12IN3-/P1C
The RC3/AN7/P1C
of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a PWM output
• a PWM output
• an analog input to Comparator C1 or C2
Note 1: P1C is available on PIC16F685/
(1)
is configurable to function as one
PIC16F690 only.
FIGURE 4-12: BLOCK DIAGRAM OF RC2
AND RC3
2005-2015 Microchip Technology Inc. DS40001262F-page 75
PIC16F631/677/685/687/689/690
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
RD
PORTC
Available on PIC16F68 5/PIC1 6F 690 onl y.
C2OUT EN
CCP1OUT EN
C2OUT EN
C2OUT
CCP1OUT EN
CCP1OUT
I/O Pin
0
1
1
0
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data bus
WR
PORTC
WR
TRISC
RD
TRISC
To Enhanced CCP
RD
PORTC
Available on PIC16F685/PIC16F690 only.
CCP1OUT
CCP1OUT
Enable
0
1
1
0
I/O Pin
4.5.5 RC4/C2OUT/P1B
The RC4/C2OUT/P1B
as one of the following:
• a general purpose I/O
• a digital output from Comparator C2
• a PWM output
Note 1: Enabling both C2OUT and P1B will cause
a conflict on RC4 and create
unpredictable results. Therefore, if
C2OUT is enabled, the ECCP+ can not be
used in Half-Bridge or Full-Bridge mode
and vise-versa.
2: P1B is available on PIC16F685/
PIC16F690 only.
(1, 2)
is configurable to function
FIGURE 4-13: BLOCK DIAGRAM OF RC4
4.5.6 RC5/CCP1/P1A
The RC5/CCP1/P1A
one of the following:
• a general purpose I/O
• a digital input/output for the Enhanced CCP
• a PWM output
Note 1: CCP1 and P1A are available on
PIC16F685/PIC16F690 only.
(1)
is configurable to function as
FIGURE 4-14: BLOCK DIAGRAM OF RC5
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VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter
(2)
RD
PORTC
Analog Input
Mode
(1)
To SS Input
Available on PIC16F685/ P IC1 6F 69 0 only.
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
I/O Pin
0
1
1
0
SDO
PORT/SDO
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter
(2)
RD
PORTC
Analog Input
Mode
(1)
Available on PIC16F685/PIC16F690 only.
Note 1: ANSEL determines Analog Input mode.
2: Not implem ented on PIC16F631.
I/O Pin
Select
4.5.7 RC6/AN8/SS
The RC6/AN8/SS
of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a slave select input
Note 1: SS is available on PIC16F687/PIC16F689/
2: AN8 is not implemented on PIC16F631.
(1,2)
is configurable to fun ction as one
PIC16F690 only.
FIGURE 4-15: BLOCK DIAGRAM OF RC6
4.5.8 RC7/AN9/SDO
The RC7/AN9/SDO
one of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a serial data output
Note 1: SDO is available on PIC16F687/
2: AN9 is not implemented on PIC16F631.
(1,2)
is configurable to function as
PIC16F689/PIC16F690 only.
FIGURE 4-16: BLOCK DIAGRAM OF RC7
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TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ANSEL ANS7 ANS6 ANS5 ANS4
ANSELH
CCP1CON
CM2CON0 C2ON C2OUT
CM2CON1
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
PSTRCON
SRCON SR1
(1)
SSPCON
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
VRCON C1VREN C2 VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC .
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
2: PIC16F685/PIC16F690 only.
— — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111
(2)
P1M1 P1M0 DC1B1 D C1B0 CCP1M3 CCP1M2 CCP1 M1 CCP1M0 0000 0000 0000 0000
C2OE C2POL — C2R C2CH1 C2CH0 0000 -000
MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10
— — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001
SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00--
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
Value o n
POR, BOR
Value o n
all other
Resets
0000 -000
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T0CKI
T0SE
pin
TMR0
Watchdog
Timer
WDT
Time-out
PS<2:0>
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.
0
1
0
1
0
1
Sync 2
cycles
8
8
8-bit
Prescaler
0
1
FOSC/4
PSA
PSA
PSA
16-bit
Prescaler
16
WDTPS<3:0>
31 kHz
INTOSC
SWDTEN
5.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/c ounter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (shared with Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
Figure 5-1 is a block diagram of the Timer0 module.
5.1 Timer0 Operation
When used as a timer, the Timer0 module can be used
as either an 8-bit timer or an 8-bit counter.
5.1.1 8-BIT TIMER MODE
When used as a timer, the Timer0 module will
increment every instruction cyc le (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjus ted, in order to account for
the two instruction cycle delay when
TMR0 is written.
5.1.2 8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
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BANKSEL TMR0 ;
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W; bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ; to 1:32
CLRWDT ;Clear WDT and
;prescaler
BANKSEL OPTION_REG ;
MOVLW b’11110000’;Mask TMR0 select and
ANDWF OPTION_REG,W; prescaler bits
IORLW b’00000011’;Set prescale to 1:16
MOVWF OPTION_REG ;
5.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlle d by the PSA bit o f the OPTION
register. To assign the prescaler to Tim er 0, th e PSA b it
must be cleared to a ‘0’.
There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are
selectable via th e PS<2:0> bits of the OPTION regi ster .
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When the
prescaler is assigned to the Timer0 module, all
instructions writing to the TMR0 register will clear the
prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1 Switching Prescaler Between
Timer0 and WDT Modules
As a result of hav ing the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changin g th e presca le r ass ig nme nt fro m
Timer0 to the WDT module, the instr uction sequence
shown in Example 5-1, must be executed.
EXAMPLE 5-1: CHANGING PRESCALER
(TIMER0 WDT)
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
EXAMPLE 5-2: CHANGING PRESCALER
(WDT TIMER0)
5.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen dur ing Sleep.
5.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK
When Timer0 is in Coun ter mo de, t he synchronizatio n
of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phas e clocks. Ther efore, t he
high and low periods of the extern al cl oc k so urc e mus t
meet the timing requirements as shown in
Section 17.0 “Electrical Specifications”.
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000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
BIT VALUE T MR 0 RA TE WDT RATE
REGISTER 5-1: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RABPU
: PORTA/PORTB Pull-up Enable bit
1 = Pull-ups on PORTA/PORTB are disabled
0 = Pull-ups on PORTA/PORTB are disabled by individual WPUAx control bits
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal in struction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 14.5 “Watchdog Timer (WDT)” for more
information.
TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE
OPTION_REG
TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
TRISA
Legend: – = Unimplemented locations, read as ‘ 0’, u = unchanged, x = un kn ow n. Shad ed cells are not used by th e
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RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Timer0 module.
Value on
POR, BOR
Value on
all other
Resets
PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000
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6.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter reg ister p air (TMR1 H:TMR1 L)
• Programmable internal or external clock source
• 3-bit prescaler
• Optional LP oscillator
• Synchronous or asynchronous operation
• Timer1 gate (count enable) via comparator or
T1G
pin
• Interrupt on overflow
• Wake-up on overflow (external c lock,
Asynchronous mode only)
• Time base for the Capture/Compare function
(PIC16F685/PIC16F690 only)
• Special Event Trigger (with ECCP)
(PIC16F685/PIC16F690 only)
• Comparator output synchronization to Timer1
clock
Figure 6-1 is a block diagram of the Timer1 module.
6.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an interna l clock so urce, the module i s
a timer. When used with an ext ernal cl ock sou rce, t he
module can be used as either a timer or counter.
6.2 Clock Source Selection
The TMR1CS bit of the T1CON register is used to select
the clock source. When TMR1CS = 0, the clock source
OSC/4. When TMR1CS = 1, the clock source is
is F
supplied externally.
Clock
Source
OSC/4 x xxx 0
F
T1CKI pin 0 xxx 1
T1LPOSC 1 LP or
T1OSCEN
FOSC
Mode
INTOSCIO
TMR1CS
1
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TMR1H TMR1L
Oscillator
T1SYNC
T1CKPS<1:0>
Prescaler
1, 2, 4, 8
Synchronize
(3)
det
1
0
0
1
Synchronized
clock input
2
Set flag bit
TMR1IF on
Overflow
TMR1
(2)
TMR1GE
TMR1ON
T1OSCEN
1
0
SYNCC2OUT
(4)
T1GSS
T1GINV
To C2 Comparator Module
Timer1 Clock
TMR1CS
OSC2/T1G
OSC1/T1CKI
Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: SYNCC2OUT is synchronized when the C2SYNC bit of the
CM2CON1 register is set.
(1)
EN
INTOSC
Without CLKOUT
F
OSC/4
Internal
Clock
FIGURE 6-1: TIMER1 BLOCK DIAGRAM
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6.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
OSC as determined by the Timer1 prescaler.
of F
6.2.2 EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run asynchronously.
If an external clock oscillator is needed (and the
microcontroller is us ing the INTOS C without CLKOUT),
Timer1 can use the LP oscillator as a clock source.
Note 1: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing risin g edge af ter any one or
more of the following conditions:
•Timer1 enabled after POR reset
•Write to TMR1H or TMR1L
•Timer1 is disabled
•Timer1 is dis abled (TMR1O N 0) when
T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI
is low.
2: See Figure 6-2
6.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cl eared upon a write to
TMR1H or TMR1L.
6.4 Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in
between pins OSC1 (input) and OSC2 (amplifier
output). The oscillator is enabled by setting the
T1OSCEN control bit of the T1CON register. The
oscillator will continue to run during Sleep.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer 1 can use th is mode on ly when
the primary system clock is derived from the internal
oscillator or when the oscillator is in the LP mode. The
user must provide a software time delay to ensure
proper oscillator start-up.
TRISA5 and TRISA4 bits are set when the Timer1
oscillator is enabled. RA5 and RA4 bit s rea d a s ‘0’ and
TRISA5 and TRISA4 bits read as ‘1’.
Note: The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
6.5 Timer1 Operation in Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
6.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asyn chronous cl ock will e nsure a valid
read (taken care of in hardware). However, the user
should keep in mind that rea ding t he 1 6-bit ti mer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommend ed that th e user s imply sto p
the timer and write the desired values. A write
contention may occ ur by w ritin g to th e timer regist ers,
while the register is incrementi ng. This may pro duce an
unpredictable value in the TMR1 H:TMR1L register pair .
6.6 Timer1 Gate
The Timer1 gate (when enable d) allows T imer1 to count
when Timer1 gate is active. Timer1 gate source is
software configurable to be the T1G
Comparator C2. This allows the device to directly time
external events using T1G
Comparator C2. See the CM2CON1 register
(Register 8-3) for selecting the Timer1 gate source. This
feature can simplify the software for a Delta-Sigma A/D
converter and many other applications.
pin or the output of
or analog events using
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Note: TMR1GE bit of the T1CON register must
be set to use either T1G
Timer1 gate source. See the CM2CON1
register (Register 8-3) for more information on selecting the Timer1 gate source.
Timer1 gate can be in verted using the T1GINV bit of
the T1CON register , wh ether it originate s from the T1G
pin or Comparator C2 output. This configures Timer1 to
measure either the active-high or active-low time
between ev ents.
or C2OUT as the
6.7 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over , the T i mer1 in terrupt fl ag bit of th e PIR1 regis ter is
set. To enable the interrupt on rollover, you must set
these bits:
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
In Compare mode, an event is trigge red when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For more information, see Section 11.0 “Enhanced
Capture/Compare/PWM Module”.
6.10 ECCP Special Event Trigger
When the ECCP is configured to trigger a special
event, the trigger will clear the TMR1H:TMR1L register
pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to
generate a ECCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized to the F
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the event that a write to TMR1H or TM R1L coinci des
with a Special Event Trigger from the ECCP, the write
will take precedence.
For more information, see Section 11.2.4 “Special
Event Trigger”.
OSC to utilize
Note: The TMR1H:TTMR1L register pair and
the TMR1IF bit should be cleared before
enabling interrupts.
6.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Count er mode. In this mode, a n external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC
• TMR1CS bit of the T1CON register must be set
• T1OSCEN bit of the T1CON register (can be set)
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
bit of the T1CON register must be set
6.9 ECCP Capture/Compare Time Base
The ECCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
6.11 Comparator Synchronization
The same cl ock used to increment Timer1 can also be
used to synchronize the comparator output. This
feature is enabled in the Comparator module.
When using the comparator for Timer1 gate, the
comparator output should be synchronized to Timer1.
This ensures Timer1 does not miss an increment if the
comparator chang es.
For more information, see Section8.8.2
“Synchronizing Comparator C2 output to Timer1”.
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T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arr o ws indicate counter inc remen ts.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
FIGURE 6-2: TIMER1 INCREMENTING EDGE
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6.12 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
T1GINV
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TMR1GE
(2)
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 T1GINV: Timer1 Gate Invert bit
1 = Timer1 gate is active-high (Timer1 counts when Timer1 gate signal is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 6 TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON =
1 = Timer1 counting is controlled by the Timer1 Gate function
0 = Timer1 is always counting
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored
bit 2 T1SYNC
TMR1CS =
1 = Do not synchronize external clock inp ut
0 = Synchronize external clock input
TMR1CS =
This bit is ignored. Timer1 uses the internal clock
bit 1 TMR1CS: Timer1 Clock Source Sele ct bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (F
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
1:
: Timer1 External Clock Input Synchronization Control bit
1:
0:
OSC/4)
(1)
(2)
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use e ither T1 G
register, as a Timer1 gate source.
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pin or C2OUT, as selected by t he T1GSS b it of th e CM 2CON1
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TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CM2CON1 MC1OUT MC2OUT
INTCON GIE PEIE
PIE1
PIR1
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
— — — — T1GSS C2SYNC ---- --10 ---- --10
T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000
TMR1CS TMR1ON 0000 0000 uuuu uuuu
Value o n
POR, BOR
Value o n
all other
Resets
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Comparator
TMR2
Sets Flag
TMR2
Output
Reset
Postscaler
Prescaler
PR2
2
F
OSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
TOUTPS<3:0>
T2CKPS<1:0>
7.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
• 8-bit timer register (TMR2)
• 8-bit period register (PR2)
• Interrupt on TMR2 match with PR2
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
See Figure 7-1 for a block diagram of Timer2.
7.1 Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (F
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescal er is the n use d to
increment the TMR2 register.
The values of T MR2 and PR2 are co nstan tly comp ared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is fed
into the Timer2 postscaler. The postscaler has
postscale op tions of 1 :1 to 1:16 i nclusiv e. The out put of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
OSC/4). The clock is fed into the
The TMR2 and PR2 registers are both fully readable
and writable . On any Re set, th e TMR2 regis ter is set to
00h and the PR2 register is set to FFh.
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned of f by clearing
the TMR2ON bit to a ‘0’.
The Timer2 prescale r is co ntro lle d by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset oc curs (Power-on Rese t, MCLR
Reset, Watchdog Timer Reset or Brown-out
Reset).
Note: TMR2 is not cleared when T2CON is
written.
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
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REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER
(1)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 =1:1 Postscaler
0001 =1:2 Postscaler
0010 =1:3 Postscaler
0011 =1:4 Postscaler
0100 =1:5 Postscaler
0101 =1:6 Postscaler
0110 =1:7 Postscaler
0111 =1:8 Postscaler
1000 =1:9 Postscaler
1001 =1:10 Postscaler
1010 =1:11 Postscaler
1011 =1:12 Postscaler
1100 =1:13 Postscaler
1101 =1:14 Postscaler
1110 =1:15 Postscaler
1111 =1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x =Prescaler is 16
Note 1: PIC16F685/PIC16F690 only.
TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE PEIE
PIE1
PIR1
PR2 Timer2 Module Period Register 1111 1111 1111 1111
TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
T2CON
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
Note 1: PIC16F685/PIC16F690 only.
DS40001262F-page 90 2005-2015 Microchip Technology Inc.
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
— ADIF RCIF TXIF SSPIF CCP1IF T MR2IF TMR1IF -000 0000 -000 0000
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
(1)
REGISTERS
Value on
POR, BOR
Value on
all other
Resets
PIC16F631/677/685/687/689/690
–
+
VIN+
V
IN-
Output
Output
VIN+
VIN-
Note: The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
8.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The Analog
Comparator module includes the following features:
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
•PWM shutdown
• Time r1 gate (co unt ena ble )
• Output synchronization to Timer1 clock input
•SR Latch
• Programmable and Fixed V olt age R eference
Note: Only Comparator C2 can be linked to
Timer1.
8.1 Comparator Overview
FIGURE 8-1: SINGLE COMPARATOR
A single comparator is shown in Figure 8-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at V
less than the analog voltage at V
comparator is a digital low level. When the analog
voltage at V
V
IN-, the output of the comp arator is a dig ital hig h level.
IN+ is greater than the analog voltage at
IN-, the output of the
IN+ is
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C1POL
C1OUT
RD_CM1CON0
Set C1IF
To
DQ
EN
Q1
Data Bus
C1POL
DQ
EN
CL
Q3*RD_CM1CON0
NRESET
MUX
C1
0
1
2
3
C1ON
(1)
C1CH<1:0>
2
C1VINC1V
IN+
C12IN0C12IN1C12IN2C12IN3-
+
-
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (F
OSC).
3: Q1 is held high during Sleep mode.
0
1
C1R
MUX
C1IN+
0
1
MUX
To other peripherals
C1OUT (to SR latch)
CVREF
C1VREN
FixedRef
MUX
C2
C2POL
C2OUT
0
1
2
3
C2ON
(1)
C2CH<1:0>
2
From TMR1
Clock
DQ
EN
DQ
EN
CL
DQ
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C2IF
To
NRESET
C2V
IN-
C2V
IN+
C12IN0C12IN1C12IN2C12IN3-
0
1
C2SYNC
C2POL
Data Bus
MUX
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (F
OSC).
3: Q1 is held high during Sleep mode.
0
1
C2R
CV
REF
MUX
C2IN+
0
1
MUX
SYNCC2OUT
to Timer1 Gate, SR latch
C2V
REN
FixedRef
and other peripherals
FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
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8.2 Comparator Control
Each comparator has a separate control and
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
Comparator C2 has a second control register,
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Registers
8-1 and 8-2, respe ctively) cont ain the contro l and St atus
bits for the follow ing:
• Enable
• Input selection
• Reference selection
•Output selection
• Output polarity
8.2.1 COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
8.2.2 COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
Note: To use CxIN+ and C12INx- pins a s analog
inputs, the appropriate bits must be set in
the ANSEL register and the
correspondi n g TR IS b i ts mus t al so b e se t
to disable the output drivers.
8.2.3 COMPARATOR REFERENCE
SELECTION
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting input of the comparator. See Section 8.9
“Comparator SR Latch” for more information on the
Internal V ol tage Reference module.
8.2.4 COMPARATOR OUTPUT SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit overrides the PORT data
latch. Setting the Cx ON has no im pact on
the port ov erride.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
8.2.5 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit result s in a non-inverted output.
Table 8-1 shows the output state versus input
conditions, including polarity control.
T ABLE 8-1: COMPARATOR OUTPUT
STATE VS. INPUT CONDITIONS
Input Condition CxPOL CxOUT
CxV
IN- > CxVIN+ 00
CxVIN- < CxVIN+ 01
CxVIN- > CxVIN+ 11
IN- < CxVIN+ 10
CxV
8.3 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference volta ge. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 17.0
“Electrical Specifications” for more details.
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Q1
Q3
CxIN+
Cxout
Set CxIF (edge)
CxIF
TRT
reset by software
Q1
Q3
CxIN+
Cxout
Set CxIF (edge)
CxIF
TRT
reset by software
cleared by CMxCON0 read
8.4 Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a chang e in the o utput val ue of the compa rator .
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusiveor gate (see Figure 8 -2 an d Figure8-3). One latch is
updated with the comparator output level when the
CMxCON0 register i s read . Th is la tc h re t ai ns the v alu e
until the next read of the CMxCON0 register or the
occurrence of a Reset. The other latc h of the mism atch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate
correctly regardless of the state of CxOE.
FIGURE 8-4: COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 8-5: COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the interrupt flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch regi sters. Wh en the mism atch regis ters are
cleared, an interrup t will oc cur upon the compara tor’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred.
The CxIF bit of the PIR1 register is the comparator
interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is als o poss ible t o writ e a ‘1’ to
this register, an interrupt can be generated.
The CxIE bit of the PIE1 re gister and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabl ed, althou gh the CxIF bi t of the
PIR1 register will still be set if an interrupt condition
occurs.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF of the PIR1
register interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
interrupt flags before enabling
comparator interrupt s.
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8.5 Operation During Sleep
The comparator , if enabled b efore entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is show n sep arately in the
Section 17.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comparator . Each comparator is turned off
by clearing the CxON bit of the CMxCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CxIE bit of the PIE1 reg ister
and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
8.6 Effects of a Reset
A device Reset forces the CMxCON0 and CM2CON1
registers to their Reset states. This forces both
comparators and the voltage references to their OFF
states.
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REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C1ON: Comparator C1 Enable bit
1 = Comparator C1 is enabled
0 = Comparator C1 is disabled
bit 6 C1OUT: Comparator C1 Output bit
If C1POL =
C1OUT = 0 when C1VIN+ > C1VIN-
C1OUT = 1 when C1V
If C1POL =
C1OUT = 1 when C1VIN+ > C1VIN-
C1OUT = 0 when C1V
bit 5 C1OE: Comparator C1 Output Enable bit
1 = C1OUT is present on the C1OUT pin
0 = C1OUT is internal only
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3 Unimplemented: Read as ‘0’
bit 2 C1R: Comparat or C1 Referenc e Select bit (non-inverting input)
1 = C1VIN+ connects to C1VREF output
0 = C1V
bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit
00 = C1VIN- of C1 connects to C12IN0- pin
01 = C1V
10 = C1V
11 = C1V
1 (inverted polarity):
IN+ < C1VIN-
0 (non-inverted polarity):
IN+ < C1VIN-
IN+ connects to C1IN+ pin
IN- of C1 connects to C12IN1- pin
IN- of C1 connects to C12IN2- pin
IN- of C1 connects to C12IN3- pin
(1)
Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding
PORT TRIS bit = 0.
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REGISTER 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2ON: Comparator C2 Enable bit
1 = Comparator C2 is enabled
0 = Comparator C2 is disabled
bit 6 C2OUT: Comparator C2 Output bit
If C2POL =
C2OUT = 0 when C2VIN+ > C2VIN-
C2OUT = 1 when C2V
If C2POL =
C2OUT = 1 when C2VIN+ > C2VIN-
C2OUT = 0 when C2V
bit 5 C2OE: Comparator C2 Output Enable bit
1 = C2OUT is present on C2OUT pin
0 = C2OUT is internal only
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3 Unimplemented: Read as ‘0’
bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)
1 = C2V
0 = C2VIN+ connects to C2IN+ pin
bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits
00 = C2VIN- of C2 connects to C12IN0- pin
01 = C2V
10 = C2V
11 = C2V
1 (inverted polarity):
IN+ < C2VIN-
0 (non-inverted polarity):
IN+ < C2VIN-
(1)
IN+ connects to C2VREF
IN- of C2 connects to C12IN1- pin
IN- of C2 connects to C12IN2- pin
IN- of C2 connects to C12IN3- pin
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding
PORT TRIS bit = 0.
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VA
Rs < 10K
C
PIN
5 pF
VDD
VT 0.6V
V
T 0.6V
RIC
ILEAKAGE
(1)
Vss
AIN
Legend: CPIN = Input Capacitance
I
LEAKAGE = Leakage Current at the pin due to various junctions
R
IC = Interconnect Resistance
R
S = Source Impedance
V
A = Analog Voltage
V
T = Threshold Voltage
To Comparator
Note 1: See Section 17.0 “Electrical Specifications”
8.7 Analog Input Connection Considerations
A simplified circuit for an analog input is shown in
Figure 8-6. Since the analog inpu t pins sh are their co n-
nection with a digital input, they have reverse biased
ESD protection diodes to V
input, therefore, must be between V
input voltage deviates from this range by more than
0.6V in either direction, one of the diodes is forward
biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage curr ent to
minimize inaccuracies introduced.
FIGURE 8-6: ANALOG INPUT MODEL
DD and VSS. The analog
SS and VDD. If the
Note 1: When reading a PORT register, all pins
configured as ana log input s wi ll read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may c ause the input buf fer to
consume more current than is specified.
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8.8 Additional Comparator Features
There are three additional comparator features:
• Timer1 count enable (gate)
• Synchronizing output with Timer1
• Simultaneous read of comparator outputs
8.8.1 COMPARATOR C2 GATING TIMER1
This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CM2CON1 register will enable Timer1 to increment
based on the output of Comparator C2. This requires
that Timer1 is on and gating is enabled. See
Section 6.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize the comparator with
Timer1 by setting the C2SYNC bit when the comparator
is used as t he T imer1 gate sou rce. T his ensur es T imer1
does not miss an increme nt if the compar a tor ch an ges
during an increment.
8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1
The Comparator C2 output can be synchronized with
Timer1 by setting the C2SYNC bit of the CM2CON1
register. When enabled, the C2 output is latched on the
falling edge of the Timer1 clock source. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latch ed on the falling e dge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 8-3) and the Timer1 Block
Diagram (Figure 6-1) for more information.
8.8.3 SIMULTANEOUS COMPARATOR OUTPUT READ
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate regi sters.
Note 1: Obtaining the status of C1OUT or
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.
REGISTER 8-3: CM2CON1: COMPARATOR C2 CONTROL REGISTER 1
R-0 R-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
MC1OUT MC2OUT — — — — T1GSS C2SYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MC1OUT: Mirror Copy of C1OUT bit
bit 6 MC2OUT: Mirror Copy of C2OUT bit
bit 5-2 Unimplemented: Read as ‘0’
bit 1 T1GSS: Timer1 Gate Source Select bit
1 = Timer1 gate source is T1G
0 = Timer1 gate source is SYNCC2OUT.
bit 0 C2SYNC: Comparator C2 Output Synchronization bit
1 = Output is synchronous to falling edge of Timer1 clock
0 = Output is asynchronous
Note 1: Refer to Section 6.6 “Timer1 Gate”.
2: Refer to Figure 8-3.
(1)
(2)
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C2OE
C1SEN
SR0
PULSS
SRQ
Q
C2REN
PULSR
SR1
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
2: Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width.
3: Output shown for reference only. See I/O port pin block diagram for more detail.
Pulse
Gen
(2)
Pulse
Gen
(2)
SYNCC2OUT (from comparator)
C1OUT (from comparator)
C2OUT pin
(3)
C1OE
C1OUT pin
(3)
0
1
MUX
1
0
MUX
SR
Latch
(1)
8.9 Comparator SR Latch
The SR Latch module provides additional control of the
comparator outputs. The module consists of a single
SR latch and output multiplexers. The SR latch can be
set, reset or toggled by the comparator outputs. The SR
latch may also be set or reset, independent of
comparator output, by control bits in the SRCON control
register. The SR latch output multiplexers select
whether the latch outputs or the comparator outputs are
directed to the I/O port logic for eventual output to a pin.
8.9.2 LATCH OUTPUT
The SR<1:0> bits of the SRCON register control the
latch output multiplexers and determine four possible
output configurations. In these four configurations, the
CxOUT I/O port logic is connected to:
• C1OUT and C2OUT
• C1OUT and SR latch Q
• C2OUT and SR latch Q
• SR latch Q and Q
After any Reset, the default output configuration is the
8.9.1 LATCH OPERATION
The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. Each latch input is connected to a
comparator output and a software controlled pulse
generator. The latch can be set by C1OUT or the PULSS
bit of the SRCON register. The latch can be reset by
C2OUT or the PULSR bit of the SRCON register. The
latch is reset-dominant, therefore, if both Set and Reset
inputs are high, the latch will go to the Reset st ate. Both
unlatched C1OUT and C2OUT mode. This maintains
compatibility with devices that do not have the SR latch
feature.
The applicable TRIS bits of the corresponding ports
must be cleared to enable the port pin output drivers.
Additionally, the CxOE comparator output enable bits of
the CMxCON0 registers must be set in order to make the
comparator or latch outputs available on the output pins.
The latch configuration enable states are completely
independent of the enable states for the comparators.
the PULSS and PULSR bits are self resetting which
means that a single write to either of the bits is all that is
necessary to complete a latch set or reset operation.
FIGURE 8-7: SR LATCH SIMPLIFIED BLOCK DIAGRAM
DS40001262F-page 100 2005-2015 Microchip Technology Inc.
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