Datasheet PIC12F635, PIC16F636, PIC16F639 Datasheet

PIC12F635/PIC16F636/639

Data Sheet

8/14-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

with nanoWatt Technology

*8-bit, 8-pin Devices Protecte d by Microchip’ s Low Pin Coun t Patent: U. S. Patent N o. 5,847,450. Additi onal U.S. and foreign patents and applications may be issued or pending.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfP IC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MX DEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC® DSCs, KEELOQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

code hopping devices, Serial

PIC12F635/PIC16F636/639

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers

With nanoWatt Technology

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instr uction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range of 8 MHz to 125 kHz

- Software tunable

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for power savings

• Clock mode switching for low-power operation

• Power-Saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended Temperature range

• Power-on Reset (POR)

• Wake-up Reset (WUR)

• Independent weak pull-up/pull-down resistors

• Programmable Low-Voltage Detect (PLVD)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Reset (BOR) with software control option

• Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection (program and data independent)

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM Retention: > 40 years

Low-Power Features:

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

-8.5μA @ 32 kHz, 2.0V, typical

-100μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Features:

• 6/12 I/O pins with individual dire ct ion contro l:

- High-current source/sink for direct LED drive

- Interrupt-on-change pin

- Individually programmable weak pull-ups/ pull-downs

- Ultra Low-Power Wake-up

• Analog Comparator module with:

- Up to tw o analog comparators

- Programmable On-chip Voltage Reference

REF) module (% of VDD)

(CV

- Comparator inputs and outputs externally accessible

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Gate (count enable)

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode selected

EELOQ

•K module

• In-Circuit Serial Programming™ (ICSP™) via two pins

compatible hardware Crypt ographic

Low-Frequency Analog Front-End Features (PIC16F639 only):

• Three input pins for 125 kHz LF input signals

• High input detection sensitivity (3mV

• Demodulated data, Carrier clock or RSSI output selection

• Input carrier frequency: 125 kHz, typical

• Input modulation frequency: 4 kHz, maximum

• 8 internal Configuration registers

• Bidirectional transponder communication (LF talk back)

• Programmable antenna tuning capac itance (up to 63 pF, 1 pF/step)

• Low standby current: 5 μA (with 3 channels enabled), typical

• Low operating current: 15 μA (with 3 channels enabled), typical

• Serial Peripheral Interface (SPI) with internal MCU and external devices

• Supports Battery Back-up mode and batteryless operation with external circuits

PP, typical)

PIC12F635/PIC16F636/639

Program Memory Data Memory

Device

PIC12F635 1024 64 128 6 1 N PIC16F636 2048 128 256 12 2 N PIC16F639 2048 128 256 12 2 Y

Note 1: Any references to PORT A, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively.

2: V

3: VSST is the grou n d r ef e re n ce vo l tage of t h e A na l og Fr on t -E nd s ec t ion ( PIC 1 6 F63 9 on l y) . VSST is treated

Flash (words) SRAM (bytes) EEPROM (bytes)

DDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in

this document unless ot herwise stated.

SS in this document unless otherwise stated.

as V

I/O Comparators

Low Frequency

Analog

Front-End

PIC12F635/PIC16F636/639

8-Pin Diagrams (PDIP, SOIC, DFN, DFN-S)

PDIP, SOIC

DFN, DFN-S

GP5/T1CKI/OSC1/CLKIN

GP4/T1G

GP5/T1CKI/OSC1/CLKIN

GP4/T1G

/OSC2/CLKOUT

GP3/MCLR

VDD

/OSC2/CLKOUT

GP3/MCLR

/VDD

/VPP

1 2

3 4

1 2

3 4

8 7

PIC12F635

VSSVDD GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT

8 7 6 5

VSS GP0/CIN+/ICSPDAT/ULPWU GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT

TABLE 1: 8-PIN SUMMARY (PDIP, SOIC, DFN, DFN-S)

I/O Pin Comparators Timer Interrupts Pull-ups Basic

GP0 7 C1IN+ — IOC Y ICSPDAT/ULPWU GP1 6 C1IN- — IOC Y ICSPCLK GP2 5 C1OUT T0CKI INT/IOC Y —

(1)

GP3 GP4 3 — T1G IOC Y OSC2/CLKOUT

GP5 2 — T1CKI IOC Y OSC1/CLKIN

— 1 — — — — VDD —8———— VSS

Note 1: Input only.

4— — IOC Y

2: Only when pin is configured for external MCLR.

(2)

MCLR/VPP

PIC12F635/PIC16F636/639

14-Pin Diagram (PDIP, SOIC, TSSOP)

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/T1G

/OSC2/CLKOUT

RA3/MCLR

RC4/C2OUT

/VPP RC5

RC3

1 2 3 4 5 6 7

14 13 12 11 10

PIC16F636

9 8

VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C2INRC2

REF/ICSPCLK

TABLE 2: 14-PIN SUMMARY (PDIP, SOIC, TSSOP)

I/O Pin Comparators Timer Interrupts Pull-ups Basic

RA0 13 C1IN+ — IOC Y ICSPDAT/ULPWU RA1 12 C1IN- — IOC Y VREF/ICSPCLK RA2 11 C1OUT T0CKI INT/IOC Y —

(1)

RA3 RA4 3 — T1G IOC Y OSC2/CLKOUT

RA5 2 — T1CKI IOC Y OSC1/CLKIN RC0 10 C2IN+ — — — — RC1 9 C2IN- — — — — RC2 8 — — — — — RC37———— — RC4 6 C2OUT — — — — RC55———— —

— 1 — — — — VDD —14———— VSS

Note 1: Input only.

4— — IOC Y

2: Only when pin is configured for external MCLR

(2)

MCLR/VPP

16-Pin Diagram

QFN

PIC12F635/PIC16F636/639

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR

/VPP RC5

VDD

1 2

PIC16F636

3 4

RC4/C2OUT

NCNCV

RC3

RC2

12 11 10

RC1/C2IN-

RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V

RA2/T0CKI/INT/C1OUT

RC0/C2IN+

REF/ICSPCLK

TABLE 3: 16-PIN SUMMARY

I/O Pin Comparators Timer Interrupts Pull-ups Basic

RA0 12 C1IN+ — IOC Y ICSPDAT/ULPWU RA1 11 C1IN- — IOC Y VREF/ICSPCLK RA2 10 C1OUT T0CKI INT/IOC Y —

(1)

RA3 RA4 2 — T1G IOC Y OSC2/CLKOUT

RA5 1 — T1CKI IOC Y OSC1/CLKIN RC0 9 C2IN+ — — — — RC1 8 C2IN- — — — — RC2 7 — — — — — RC36———— — RC4 5 C2OUT — — — — RC54———— —

— 16 — — — — VDD —13———— VSS — 14 — — — — NC —15———— NC

Note 1: Input only.

3— — IOC Y

2: Only when pin is configured for external MCLR.

(2)

MCLR/VPP

PIC12F635/PIC16F636/639

20-Pin Diagram

SSOP

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/CLKOUT

RA3/MCLR

/VPP RC5

RC4/C2OUT

RC3/LFDATA/RSSI/CCLK/SDIO

(3)

DDT

LCZ

LCY

1 2 3 4 5 6 7 8 9 10

20 19 18 17

16 15 14

PIC16F639

13 12 11

VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V

REF/ICSPCLK

RA2/TOCKI/INT/C1OUT RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT

(4)

VSST LCCOM LCX

TABLE 4: 20-PIN SUMMARY

I/O Pin Analog Front-End Comparators Timer Interrupts Pull-ups Basic

RA0 19 — C1IN+ — IOC Y ICSPDAT/ULPWU RA1 18 — C1IN- — IOC Y VREF/ICSPCLK RA2 17 — C1OUT T0CKI INT/IOC Y —

(1)

RA3

4— ——IOCY RA4 3 — — T1G IOC Y OSC2/CLKOUT RA5 2 — — T1CKI IOC Y OSC1/CLKIN RC0 16 — C2IN+ — — — — RC1 15 — C2IN- — — — CS RC2 14 ALERT — — — — SCLK RC3 7 LFDATA/RSSI — — — — CCLK/SDIO RC4 6 — C2OUT — — — — RC5 5 — — — — — —

— 8 — — — — — VDDT —13 — — ——— VSST — 11 LCX — — — — — —10 LCY — ——— — — 9 LCZ — — — — — — 12 LCCOM — — — — — — 1 — — — — — VDD —20 — — ——— VSS

Note 1: Input only.

2: Only when pin is configured for external MCLR. 3: V

DDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in

this document unless ot herwise stated.

4: V

SST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated

as V

SS in this document unless otherwise stated.

(2)

MCLR/VPP

(3) (4)

PIC12F635/PIC16F636/639

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 9

2.0 Memory Organization................................................................................................................................................................. 17

3.0 Clock Sources............................................................................................................................................................................ 35

4.0 I/O Ports...................... .................................................... ........................................ ...................................................................47

5.0 Timer0 Module ........................................................................................................................................................................... 61

6.0 Timer1 Module with Gate Control............................................................................................................................................... 64

7.0 Comparator Module.................................................................. .... .. .... .. ......... .... .. .... ......... .......................................................... 71

8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 87

9.0 Data EEPROM Memory................................................ ........................................ ..................................................................... 91

10.0 K

11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 97

12.0 Special Features of the CPU......................... ........................... ........................................ ........................................................ 129

13.0 Instruction Set Summary.......................................................................................................................................................... 149

14.0 Development Support............................................................................................................................................................... 159

15.0 Electrical Specifications............................................................................................................................................................ 163

16.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................191

17.0 Packaging Information. ........................... ........................................ ..........................................................................................211

On-Line Support 223

Systems Information and Upgrade Hot Line..................................................................................................................................... 223

Reader Response............................................................................................................................................................................. 224

Appendix A: Data Sheet Revision History......................................................................................................................................... 225

Product Identification System........................................................................................................................................................... 231

Worldwide Sales and Service ...................................................... ........................... .......................................................................... 232

EELOQ

Compatible Cryptographic Module............................................................................................................................. 95

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Customer Notification System

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the PIC12F635/PIC16F636/639 devices.

FIGURE 1-1: PIC12F635 BLOCK DIAGRAM

Program

Bus

Configuration

Flash

1K x 14

Program

Memory

Instruction Reg

Program Counter

8-level Stack

(13-bit)

Direct Addr

Block Diagrams and pinout descriptions of the devices are as follows:

• PIC12F635 (Figure 1-1, Table 1-1)

• PIC16F636 (Figure 1-2, Table 1-2)

• PIC16F639 (Figure 1-3, Table 1-3)

RAM Addr

Data Bus

RAM

64 bytes

File

Registers

Addr MUX

FSR Reg

STATUS Reg

Indirect

Addr

GPIO

GP0 GP1 GP2 GP3 GP4 GP5

OSC1/CLKIN

OSC2/CLKOUT

Oscillator

T1G

T1CKI

T0CKI

Cryptographic

Instruction

Decode and

Control

Timing

Generation

8 MHz

Internal

Timer0 Timer1

Module

31 kHz

Internal

Oscillator

Low-Voltage Detect

MCLR

C1IN- C1IN+ C1OUT

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Programmable

Wake-up

Reset

VDD

VSS

1 Analog

Comparator

and Reference

MUX

ALU

W Reg

EEDAT

128 bytes

Data

EEPROM EEADDR

PIC12F635/PIC16F636/639

FIGURE 1-2: PIC16F636 BLOCK DIAGRAM

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

8 MHz

Internal

Oscillator

Configuration

Flash

2K x 14

Program

Memory

Instruction Reg

Instruction

Decode and

Control

Timing

Generation

31 kHz

Internal

Oscillator

Program Counter

8-level Stack

(13-bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Programmable

Low-Voltage Detect

Wake-up

Reset

RAM Addr

Data Bus

RAM

128

bytes

File

Registers

Addr MUX

FSR Reg

STATUS Reg

ALU

W Reg

T1CKI

MUX

Indirect

Addr

T1G

PORTA

RA0 RA1 RA2 RA3 RA4 RA5

PORTC

RC0 RC1 RC2 RC3 RC4 RC5

VDD

MCLR

T0CKI

Timer0 Timer1

Cryptographic

Module

C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

2 Analog Comparators

and Reference

VSS

EEDAT

256 bytes

Data

EEPROM

EEADDR

PIC12F635/PIC16F636/639

FIGURE 1-3: PIC16F639 BLOCK DIAGRAM

OSC1/CLKIN

OSC2/CLKOUT

T0CKI

Configuration

Flash 2K x 14 Program

Memory

Program

Bus

8 MHz

Internal

Oscillator

Instruction Reg

Instruction

Decode and

Control

Timing

Generation

31 kHz Internal

Oscillator

Timer0 Timer1

Program Counter

8-level Stack

(13-bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Programmable

Low-voltage Detect

Wake-up

Reset

VDD

MCLR

RAM Addr

VSS

Data Bus

RAM

128

bytes

File

Registers

(1)

Addr MUX

FSR Reg

STATUS Reg

MUX

ALU

W Reg

T1CKI T1G

Indirect

Addr

PORTA

PORTC

VDDT

SST

LCCOM

RA0 RA1 RA2 RA3 RA4 RA5

RC0 RC1 RC2 RC3 RC4 RC5

125 kHz

Analog Front-End

(AFE)

LCX

LCY LCZ

KEELOQ Module

2 Analog

Comparators

and Reference

C1IN- C1IN+ C1OUT C2IN-

C2IN+ C2OUT

EEDAT

256 bytes

DATA

EEPROM

EEADDR

PIC12F635/PIC16F636/639

TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS

Name Function

GP0/C1IN+/ICSPD AT/ULPWU GP0 TTL — General purpose I/O. Individually controlled

C1IN+ AN — Comparator 1 input – positive.

ICSPDAT TTL CMOS Serial programming data I/O.

ULPWU AN — Ultra Low-Power Wake-up input.

GP1/C1IN-/ICSPCLK GP1 TTL CMOS General purpose I/O. Individually controlled

C1IN- AN — Comparator 1 input – negative.

ICSPCLK ST — Serial programming clock.

GP2/T0CKI/INT/C1OUT GP2 ST CMOS General purpose I/O. Individually controlled

T0CKI ST — External clock for Timer0.

INT ST — External interrupt.

C1OUT — CMOS Comparator 1 output.

GP3/MCLR

GP4/T1G

GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O. Individually controlled

DD VDD D — Power supply for microcontroller.

V V

SS VSS D — Ground reference for microcontroller.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

/VPP GP3 TTL — General purpose input. Individually controlled

MCLR

PP HV — Programming voltage.

/OSC2/CLKOUT GP4 TTL CMOS General purpose I/O. Individually controlled

T1G

OSC2 — XTAL XTAL connection.

CLKOUT — CMOS T

T1CKI ST — Timer1 clock.

OSC1 XTAL — XTAL connection.

CLKIN ST — T

HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XT AL = Crystal

Input

Type

Output

Type

interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.

interrupt-on-change. Individually enabled pull-up/pull-down.

interrupt-on-change.

ST — Master Clear Reset. Pull-up enabled when configured as MCLR.

interrupt-on-change. Individually enabled pull-up/pull-down.

ST — Timer1 gate.

OSC/4 reference clock.

interrupt-on-change. Individually enabled pull-up/pull-down.

OSC reference clock.

Description

PIC12F635/PIC16F636/639

TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS

Name Function

RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL — General purpose I/O. Individually controlled

C1IN+ AN — Comparator 1 input – positive.

ICSPDAT TTL CMOS Serial programming data I/O.

ULPWU AN — Ultra Low-Power Wake-up input.

RA1/C1IN-/V

RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled

RA3/MCLR

RA4/T1G

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

RC0/C2IN+ RC0 TTL CMOS General purpose I/O.

RC1/C2IN- RC1 TTL CMOS General purpose I/O.

RC2 RC2 TTL CMOS General purpose I/O. RC3 RC3 TTL CMOS General purpose I/O. RC4/C2OUT RC4 TTL CMOS General purpose I/O.

RC5 RC5 TTL CMOS General purpose I/O.

DD VDD D — Power supply for microcontroller.

V V

SS VSS D — Ground reference for microcontroller.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled

C1IN- AN — Comparator 1 input – negative.

REF AN — External voltage reference

ICSPCLK ST — Serial progra mm ing clock.

T0CKI ST — External clock for Timer0.

INT ST — External interrupt.

C1OUT — CMOS Comparator 1 output.

/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-change.

MCLR

/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

T1G

OSC2 — XTAL XTAL connection.

CLKOUT — CMOS T

T1CKI ST — Timer1 clock. OSC1 XTAL — XTAL connection.

CLKIN ST — T

C2IN+ AN — Comparator 1 input – positive.

C2IN- AN — Comparator 1 input – negative.

C2OUT — CMOS Comparator 2 output.

HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XT AL = Crystal

Input

Type

PP HV — Programming voltage.

Output

Type

interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.

interrupt-on-change. Individually enabled pull-up/pull-down.

ST — Mast er Clear Reset. Pull-up enabled when configured as MCLR.

Individually enabled pull-up/pull-down.

ST — Timer1 gate.

OSC/4 reference clock.

Individually enabled pull-up/pull-down.

OSC reference clock.

Description

PIC12F635/PIC16F636/639

TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS

Name Function

LCCOM LCCOM AN — Common reference for analog inputs. LCX LCX AN — 125 kHz analog X channel input. LCY LCY AN — 125 kHz analog Y channel input. LCZ LCZ AN — 125 kHz analog Z channel input. RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL — General purpose I/O. Individually controlled interrupt-on-change.

C1IN+ AN — Comparator1 input – positive.

ICSPDAT TTL CMOS Serial Programming Data IO.

ULPWU AN — Ultra Low-Power Wake-up input.

RA1/C1IN-/V

RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.

RA3/MCLR

RA4/T1G

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

RC0/C2IN+ RC0 TTL CMOS General purpose I/O.

RC1/C2IN-/CS

RC2/SCLK/ALERT

Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

C1IN- AN — Comparator1 input – negative.

REF AN — External voltage reference

ICSPCLK ST — Serial Programming Clock.

T0CKI ST — External clock for Timer0.

INT ST — External Interrupt.

C1OUT — CMOS Comparator1 output.

/VPP

/OSC2/CLKOUT

HV = High Voltage ST = Schmitt Trigger input with CMOS levels OD = Open Drain TTL = TTL compatible input XTAL = Crystal

RA3 TTL

MCLR

PP HV — Programming voltage.

RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

T1G

OSC2 — XTAL XTAL connection.

CLKOUT — CMOS T

T1CKI ST — Timer1 clock.

OSC1 XTAL — XTAL connection.

CLKIN ST — T

C2IN+ AN — Comparator1 input – positive.

RC1 TTL CMOS General purpose I/O.

C2IN- AN — Comparator1 input – negative.

RC2 TTL CMOS General purpose I/O.

SCLK TTL — Digital clock input for SPI communication.

ALERT

Input

Type

Output

Type

Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.

Individually enabled pull-up/pull-down.

General purpose input. Individually controlled

—

interrupt-on-change.

ST —

ST — Timer1 gate.

TTL — Chip select input for SPI communication with internal pull-up

— OD Output with internal pull-up resistor for AFE error signal.

Master Clear Reset. Pull-up enabled when configured as MCLR

Individually enabled pull-up/pull-down.

OSC reference clock.

Individually enabled pull-up/pull-down.

OSC/4 reference clock.

resistor.

Description

PIC12F635/PIC16F636/639

TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS (CONTINUED)

Name Function

RC3/LFDATA/RSSI/CCLK/SDO RC3 TTL CMOS General purpose I/O.

LFDATA — CMOS Digital output representation of analog input signal to LC pins.

RSSI — Current Received signal strength indicator. Analog current that is

CCLK — — Carrier clock output.

SDIO TTL CMOS Input/Output for SPI communication.

RC4/C2OUT RC4 TTL CMOS General purpose I/O.

C2OUT — CMOS Comparator2 output.

RC5 RC5 TTL CMOS General purpose I/O.

DDT VDDT D — Power supply for Analog Front-End. In this document, VDDT is

SST VSST D — Ground reference for Analog Front-End. In this document, VSST is

DD VDD D — Power supply for microcontroller. SS VSS D — Ground reference for microcontroller.

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

HV = High Voltage ST = Schmitt Trigger input with CMOS levels OD = Open Drain TTL = TTL compatible input XTAL = Crystal

Input

Type

Output

Type

Description

proportional to input amplitude.

treated the same as V

DD, unless otherwise stated.

SS, unless otherwise stated.

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh, for the PIC12F635) and 2K x 14 (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs, implemented as static RAM for the PIC16F636/639. For the PIC12F635, reg ister locat ions 4 0h throug h 7Fh are GPRs implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. RP0 of the STATUS register is the bank select bit.

RP1

RP0

00→ Bank 0 is selected 01→ Bank 1 is selected 10→ Bank 2 is selected 11→ Bank 3 is selected

FIGURE 2-1: PROGRAM MEMOR Y M AP AND

STAC K OF THE PIC12F635

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

Access 0-3FFh

0000h

0004h 0005h

03FFh 0400h

1FFFh

FIGURE 2-2: PROGRAM MEMORY MAP AND

ST AC K OF T HE PIC16F636/639

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

Access 0-7FFh

0000h

0004h 0005h

07FFh 0800h

1FFFh

PIC12F635/PIC16F636/639

2.2.1 GENERAL PURPOSE REGISTER

The register file is organized as 64 x 8 for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select R egister, FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Figure 2-1). These registers are static RAM.

The special re gisters can be classifi ed into two sets: core and peripheral. The Special Function Registers associated with the “c ore” are des cribed in this sect ion. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

PIC12F635/PIC16F636/639

FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS

File File File File Address Address Address Address

Indirect addr.

(1)

00h Indirect addr.

TMR0 01h OPTION_REG 81h 101h 181h

PCL 02h PCL 82h 102h 182h

STATUS 03h STATUS 83h 103h 183h

FSR 04h FSR 84h 104h 184h

GPIO 05h TRISIO 85h 105h 185h

06h 86h 106h 186h 07h 87h 107h 187h 08h 88h 108h 188h

09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh

PIR1 0Ch PIE1 8Ch

0Dh 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh T1CON 10h OSCTUNE 90h CRCON 110h 190h

11h 91h CRDAT0 12h 92h CRDAT1 13h 93h CRDAT2 14h LVDCON 94h CRDAT3 15h WPUDA 95h 115h 195h 16h IOCA 96h 116h 196h 17h WDA 97h 117h 197h

WDTCON 18h

CMCON0 19h VRCON 99h 119h 199h CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah

1Bh EEADR 9Bh 11Bh 19Bh 1Ch EECON1 9Ch 11Ch 19Ch 1Dh EECON2 1Eh 9Eh 11Eh 19Eh 1Fh 9Fh 11Fh 19Fh 20h

(1)

80h Accesses

00h-0Bh

100h Accesses

80h-8Bh

10Ch 18Ch

10Fh 18Fh

(2)

111h 191h

(2)

112h 192h

(2)

113h 193h

(2)

114h 194h

98h 118h 198h

(1)

9Dh 11Dh 19Dh

A0h 120h 1A0h

180h

3Fh

General

40h Purpose Register

64 Bytes

Accesses

7Fh FFh 17Fh 1FFh

70h-7Fh

EFh 16Fh 1EFh F0h Accesses

70h-7Fh

170h Accesses

Bank 0

1F0h

Bank 0Bank 1Bank 2Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDA T<3:0> registers are K

“K registers. T he “K

EELOQ

Encoder License Agreement” regarding implementation of the module and access to related

EELOQ

Encoder Lice nse Agre emen t” ma y be ac cess ed thr oug h the Micr ochi p web site

located at www .m ic roc hi p.c om /K

hardware peripheral rel ated registers and requ ire the execution of the

EELOQ or by contacting your local Microchip Sales Representative.

PIC12F635/PIC16F636/639

FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS

File File File File Address Address Address Address

Indirect addr.

(1)

00h Indirect addr.

TMR0 01h OPTION_REG 81h 101h 181h

PCL 02h PCL 82h 102h 182h

STATUS 03h ST ATUS 83h 103h 183h

FSR 04h FSR 84h 104h 184h

PORTA 05h TRISA 85h 105h 185h

06h 86h 106h 186h

PORTC 07h TRISC 87h 107h 187h

08h 88h 108h 188h

09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh

PIR1 0Ch PIE1 8Ch

0Dh 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h CRCON 110h

11h 91h CRDAT0

12h 92h CRDAT1

13h 93h CRDAT2

14h LVDCON 94h CRDAT3

15h WPUDA 95h 115h 195h

16h IOCA 96h 116h 196h

17h WDA 97h 117h 197h

WDTCON 18h 98h 118h 198h

CMCON0 19h VRCON 99h CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah

1Bh EEADR 9Bh 11Bh 19Bh

1Ch EECON1 9Ch 11Ch 19Ch

1Dh EECON2

1Eh 9Eh 11Eh 19Eh

1Fh 9Fh 11Fh 19Fh

General Purpose Register

96 Bytes

20h General

Purpose Register

32 Bytes

Accesses

7Fh FFh 17Fh 1FFh

70h-7Fh

Bank 0Bank 1Bank 2Bank 3

(1)

80h Accesses

00h-0Bh

100h Accesses

80h-8Bh

10Ch 18Ch

(2)

111h 191h

(2)

112h 192h

(2)

113h 193h

(2)

114h 194h

119h 199h

(1)

9Dh 11Dh 19Dh

A0h

120h 1A0h

BFh C0h

EFh 16Fh 1EFh F0h Accesses

70h-7Fh

170h Accesses

Bank 0

180h

190h

1F0h

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDAT<3:0> registers are K

“K registers. T he “K

EELOQ

Encoder License Agreement” regarding implementation of the module and access to related

EELOQ

located at www.m ic roc hip.c om /K

EELOQ hardware peripheral rel ated reg is ters and require the execution o f the

Encoder License Agreement” may be accessed through the Microchip web site

EELOQ or by contacting your local Microchip Sales Representative.

PIC12F635/PIC16F636/639

TABLE 2-1: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory

01h TMR0 T imer0 Module Register xxxx xxxx 61,137 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 32,137 03h STATUS IRP RP1 RP0 TO 04h FSR Indirect Data Me mory Address Pointer xxxx xxxx 32,137 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 64,137 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 64,137

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

(not a physical register)

PD ZDC C0001 1xxx 26,137

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xx00 47,137

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 32,137

EEIF LVDIF CRIF —C1IFOSFIF—TMR1IF000- 00-0

TMR1CS TMR1ON 0000 0000 68,137

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 144,137 —COUT— CINV CIS CM2 CM1 CM0 -0-0 0000 79,137 — — — — — — T1GSS CMSYNC ---- --10 82,137

shaded = unimplemente d

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mis-

match exists.

Reset and Watchdog Timer Reset during normal operation.

Value on

POR/BOR/

WUR

xxxx xxxx 32,137

(2)

0000 000x

Page

28,137 30,137

PIC12F635/PIC16F636/639

TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr N a m e Bit 7 B i t 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory

81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000

83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE —C1IEOSFIE—TMR1IE000- 00-0 8Dh — Unimplemented — —

8Eh PCON 8Fh OSCCON — IRCF2 IRCF1 IRCF0 O STS HTS LTS SCS -110 q000 36,137 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 40,137 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT 9Bh EEADR 9Ch EECON1 9Dh EECON 2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---9Eh — Unimplemented — — 9Fh — Unimplemented — —

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

(2)

shaded = unimplemented

2: GP3 pull-up is enabled when pin is configured as MCLR

3: MCLR

again if the mismatch exists.

(not a physical register)

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000

— — ULPWUE SBOREN WUR —PORBOR --01 q-qq 31,137

(2)

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -000 --00 -000 — — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 — — W DA5 WDA4 — WDA2WDA1WDA0--11 -111 --11 -111

—VRR—VR3VR2VR1VR00-0- 0000 0-0- 0000

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

— — — — WRERR WREN W R RD ---- x000 ---- q000

Reset and Watchdog Timer Res et during normal operation.

in the Configuration Word register.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set

POR/BOR/

xxxx xxxx

(3)

0000 000x

Value on

Page

WUR

32,137

63,137 32,137 26,137 32,137

32,137 28,137

29,137

PIC12F635/PIC16F636/639

TABLE 2-3: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory

01h TMR0 Timer0 Module Register xxxx xxxx 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000

03h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xx00 48,137 06h — Unimplemented — — 07h PORTC 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 EEIF LVDIF CRIF C2IF C1IF OSFIF —TMR1IF0000 00-0 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 1Ah CMCON1 — — — — — — T1GSS C2SYNC ---- --10 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

(not a physical register)

— — RC5 RC4 RC3 RC2 RC1 RC0 --xx xx00 57,137

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000

shaded = unimplemented

Reset and Watchdog Timer Reset during normal operation.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

POR/BOR/

xxxx xxxx

(2)

0000 000x

Val ue on

Page

WUR

32,137

61,137 32,137

26,137 32,137

32,137 28,137 30,137

64,137 64,137

68,137

144,137

79,137 82,137

PIC12F635/PIC16F636/639

TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory

81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 82h PCL Pr ogram Count er’s (PC) Least Significant Byte 0000 0000

83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 86h — Unimplemented — — 87h TRISC 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE C2IE C1IE OSFIE —TMR1IE0000 00-0 8Dh — Unimplemented — —

8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDA T4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 9Ch EECON1 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---9Eh — Unimplemented — — 9Fh — Unimplemented — —

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

(2)

shaded = unimplemented

2: RA3 pull-up is enabled when pin is configured as MCLR

3: MCLR

again if the mismatch exists.

(not a physical register)

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000

— — ULPWUE SBOREN WUR —PORBOR --01 q-qq --0u u-uu — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 x000 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

(2)

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

— — — — WRERR WREN WR RD ---- x000 ---- q000

Reset and Watchdog Timer Res et during normal operation.

in the Configuration Word register.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

POR/BOR/

xxxx xxxx

(3)

0000 000x

Value on

Page

WUR

32,137

63,137 32,137 26,137 32,137

32,137 28,137

29,137

PIC12F635/PIC16F636/639

TABLE 2-5: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2 10Ch — Unimplemented — — 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplement ed — —

110h CRCON GO/DONE 111h CRDAT0 112h CRDAT1 113h CRDAT2 114h CRDAT3 115h — Unimplemented — — 116h — Unimplemented — —

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: CRDAT<3:0> registers are K

(2)

Cryptographic Data Register 0 0000 0000 0000 0000

(2)

Cryptographic Data Register 1 0000 0000 0000 0000

(2)

Cryptographic Data Register 2 0000 0000 0000 0000

(2)

Cryptographic Data Register 3 0000 0000 0000 0000

shaded = unimplemented

Encoder License Agreement” regarding implementation of the module and access to related registers. The “K Encoder License Agreement” may be accessed through the Microchip web site located at www.microchip.com/K or by contacting your local Microchip Sales Representative.

ENC/DEC — — — — CRREG1 CRREG0 00-- --00 00-- --00

Reset and Watchdog Timer Reset during normal operation.

hardware peripheral related registers and require the execution of the “KEELOQ

EELOQ

Value on

POR/BOR/

WUR

Page

EELOQ

PIC12F635/PIC16F636/639

2.2.2.1 STATUS Register

The STATUS register, shown i n Re gis t er2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (GPR and SFR)

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destin ation may be di fferent than intended.

and PD bits are not

For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bit s , s ee Section13.0 “Instruction Set

Summary”

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in subtraction.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

bit 0 C: Carry/Borrow

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

(1)

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, t his bit i s loaded with eithe r the high -order or low -order bit of the source register.

PIC12F635/PIC16F636/639

2.2.2.2 OPTION Register

The OPTION register is a readable and writable register which contains various control bits to configure:

• TMR0/WDT prescaler

• External RA2/INT interrupt

•TMR0

• Weak pull-up/pull-downs on PORTA

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION register to ‘1’. See Section 5.1.3 “Software Programmable Prescaler”.

bit 7 RAPU

: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on R A2/T0CKI pi n 0 = Internal instruction cycle clock (F

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

OSC/4)

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

PIC12F635/PIC16F636/639

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register which co nt ains th e vari ous e nable and fl ag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regard less of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RAIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overflow Interrupt Enab le bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt

bit 3 RAIE: PORTA Change Interrupt Enable bit

1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur

bit 0 RAIF: PORTA Change Interrupt Flag bit

1 = When at least one of the PORTA general purpose I/O pins changed state (must be cleared in

software)

0 = None of the PORTA general purpose I/O pins have changed state

(2)

(1,3)

T0IF

(2)

INTF RAIF

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

3: Includes ULPWU interrupt.

PIC12F635/PIC16F636/639

2.2.2.4 PIE1 Regi st er

The PIE1 register contai ns th e in terru pt enable bits, as shown in Register 2-4.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

EEIE LVDIE CRIE C2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt

bit 6 LVDIE: Low-Voltage Detect Interrupt Enable bit

1 = Enables the LVD interrupt 0 = Disables the LVD interrupt

bit 5 CRIE: Cryptographic Interrupt Enable bit

1 = Enables the cryptographic interrupt 0 = Disables the cryptographic interrupt

bit 4 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator 2 interrupt 0 = Disables the Comparator 2 interrupt

bit 3 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt

bit 2 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt

bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

(1)

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

C1IE OSFIE —TMR1IE

Note 1: PIC16F636/639 only.

PIC12F635/PIC16F636/639

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

EEIF LVDIF CRIF C2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIF: EE Write Complete Interrupt Flag bit

1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started

bit 6 LVDIF: Low-Voltage Detect Interrupt Flag bit

1 = The supply voltage has crossed selected LVD voltage (must be cleared in software) 0 = The supply voltage has not crossed selected LVD voltage

bit 5 CRIF: Cryptographic Interrupt Flag bit

1 = The Cryptographic module has completed an operation (must be cleared in software) 0 = The Cryptographic module has not completed an operation or is Idle

bit 4 C2IF: Comparator 2 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed

bit 3 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed INTOSC (must be cleared in software) 0 = System clock operating

bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Timer1 rolled over (must be cleared in software) 0 = Timer1 has not rolled over

(1)

Note: Interrupt f lag bit s are set when an in terrupt

condition occurs, regar dless of the st ate of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

C1IF OSFIF —TMR1IF

Note 1: PIC16F636/639 only.

PIC12F635/PIC16F636/639

2.2.2.6 PCON Regist er

The Power Control (PCON) register (see Table 12-3) contains flag bit s to differentiate between a:

• Power-on Reset (POR

• Wake-up Reset (WUR)

• Brown-out Reset (BOR

• Watchdog Timer Reset (WDT)

• External MCLR Reset The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOR The PCON register bits are shown in Register 2-6.

U-0 U-0 R/W-0 R/W-1 R/W-x U-0 R/W-0 R/W-x

— — ULPWUE SBOREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

)

(1)

WUR

—PORBOR

bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit

1 = Ultra low-power wake-up enabled 0 = Ultra low-power wake-up disabled

bit 4 SBOREN: Software BOR Enable bit

1 = BOR enabled 0 = BOR disabled

bit 3 WUR

bit 2 Unimplemented: Read as ‘0’ bit 1 POR

bit 0 BOR

Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR

: Wake-up Reset Status bit

1 = No Wake-up Reset occurred 0 = A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs)

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

(1)

PIC12F635/PIC16F636/639

2.3 PCL and PCLA TH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-5: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PCLATH<4:0>

PCLATH

PCH PCL

12 11 10 0

PCLATH<4:3>

PCLATH

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC< 12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired up per 5 bit s to the PCLATH register. When the lower 8 bits are written to the PCL regis ter , all 13 bits of the program counter will chan ge to the values contained in the PCLATH register and those being written to the PCL register.

A computed GOTO is accomplish ed by adding an offs et to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program b ranch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table.

For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556).

Instruction with

PCL as

Destination

ALU Result

GOTO, CALL

Opcode<10:0>

2.3.2 STACK

The PIC12F635/PIC16F636/639 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the S ta ck Pointer i s not rea dable or writa ble. The PC is PUSHed onto the stack when a CALL instruction is execute d or an interrupt ca uses a branc h. The stack is POP ed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a P USH or POP operation.

The stack operat es as a circular buf fer . This means th at after the stack has been PUSHed eight times, the ninth push overwrites the va lue tha t was s tored fro m the first push. The tenth pus h ov erwr i tes the se co nd push (and so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the exec ution of the CALL, RETURN, RETLW and RETFIE instru ction s or the vectoring to an interrupt address.

2.4 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physica l register . Addr essing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-6.

A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIR ECT ADDRESSING

MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;INC POINTER BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

PIC12F635/PIC16F636/639

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639

Indirect A ddressingDirect Addressing

RP1 RP0

From Opcode

IRP File Select Register

Bank Select Locatio n Select

00h

Data Memory

7Fh

Note: For memory map det ail, see Figure2-2.

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

Bank Select

180h

1FFh

Location Select

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

3.1 Overview

The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applicati ons while maximiz ing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module.

Clock sources can be configured from external oscillators, quartz cryst al resonators , ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds select able via software. Additional clo ck feat ures inc lud e:

• Selectable system clock source between external

or internal via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.

The Oscillator mod ule can be c onfigured in one of eig ht clock modes.

1. EC – External clock with I/O on OSC2/CLKOU T.

2. LP – 32 kHz Low-Power Crystal mode.

3. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator mode.

5. RC – External Resistor-Capacitor (RC) with

OSC/4 output on OSC2/CLKOUT.

6. RCIO – External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with F

OSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT.

Clock Source modes are configured by the FOSC <2:0> bits in the Configuration Word register (CONFIG). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated high-frequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator.

FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

External Oscillator

OSC2

OSC1

Internal Oscillator

HFINTOSC

8 MHz

LFINTOSC

31 kHz

Sleep

Postscaler

IRCF<2:0>

(OSCCON Register)

8 MHz 4 MHz 2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

31 kHz

111

110

101

100

011

010

001

000

LP, XT, HS, RC, RCIO, EC

MUX

FOSC<2:0>

(Configuration Word Register)

SCS<0>

(OSCCON Register)

MUX

(CPU and Peripherals)

INTOSC

Power-up Timer (PWRT) Watchdog Time r (WDT) Fail-Safe Clock Monitor (FSCM)

System Clock

PIC12F635/PIC16F636/639

3.2 Oscillator Control

The Oscillator Control (OSCCON) register (Figure3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits:

• Frequency selection bits (IRCF)

• Frequency Status bits (HTS, LTS)

• System clock control bits (OSTS, SCS)

U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0

(1)

HTS LTS SCS

— IRCF2 IRCF1 IRCF0 OSTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

111 =8MHz 110 = 4 MHz (default) 101 =2MHz 100 =1MHz 011 =500kHz 010 =250kHz 001 =125kHz 000 = 31 kHz (LFINTOSC)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)

1 = HFINTOSC is stable 0 = HFINTOSC is not stable

bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)

1 = LFINTOSC is stable 0 = LFINTOSC is not stabl e

bit 0 SCS: System Clock Select bit

1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the Configuration Word

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

PIC12F635/PIC16F636/639

3.3 Clock Source Modes

Clock Source modes can be classified as external or internal.

• External Clock mod es rely on e xternal circui try fo r the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for additional information.

3.4 External Clock Modes

3.4.1 OSCILLATOR START-UP TIMER (OST)

If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator o r ce ramic res onator, has st arte d and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1.

In order to minimize laten cy between externa l oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 3.7

“Two-Speed Clock Start-up Mode”).

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles

LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each

Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)

LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 μs (approx.)

LFINTOSC

HFINTOSC

31 kHz

125 kHz to 8 MHz

Oscillator Warm-Up Delay (T

WARM)

3.4.2 EC MODE

The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

MCU design is fully

FIGURE 3-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Clock from Ext. System

I/O

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

OSC1/CLKIN

PIC

MCU

OSC2/CLKOUT

(1)

PIC12F635/PIC16F636/639

3.4.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figu re 3-3). The mode selects a low , medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medi um of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode select s the highest gain setting of the internal inverter-amplifie r. H S mode current consum ption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.

FIGURE 3-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

PIC® MCU

OSC1/CLKIN

Quartz Crystal

(2)

To Internal Logic

Sleep

Note 1: Quartz crystal charac teristics vary a ccording

to type, package and manufacturer. The user should consult the manu facturer data sheets for sp ecifica tions and re comm ende d application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, re ference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

and PIC®

Devices” (DS00826)

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

FIGURE 3-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

PIC® MCU

OSC1/CLKIN

Ceramic Resonator

(3)

(1)

OSC2/CLKOUT

(2)

To Internal Logic

Sleep

Note 1: A series resistor (RS) may be required for

2: The value of R

(1)

quartz crystals with low drive level.

selected (typically between 2 MΩ to 10 MΩ).

OSC2/CLKOUT

F varies with the Oscillator mode

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

selected (typically between 2 MΩ to 1 0 MΩ).

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

F varies with the Oscillator mode

PIC12F635/PIC16F636/639

3.4.4 EXT ERN AL RC MODES

The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1. OSC2/CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be us ed to provide a cl ock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the external RC mode connections.

FIGURE 3-5: EXTERNAL RC MODES

VDD

REXT

OSC1/CLKIN

CEXT

VSS

OSC/4 or

(2)

I/O

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

Note 1: Alternate pin functions are listed in the

2: Output depe nds upon RC or RCIO clo ck mod

OSC2/CLKOUT

Section 1.0 “Device Overview”.

In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacito r (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance The user also needs to take into account variation due

to tolerance of external RC components used.

PIC® MCU

(1)

3 kΩ ≤ R C

EXT ≤ 100 kΩ, 3-5V

EXT > 20 pF, 2-5V

Internal

Clock

3.5 Internal Clock Modes

The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source.

1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequ ency of t he HFINT OSC can be user-adju ste d via software using the OSCTUNE register (Register 3-2).

2. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz.

The system cloc k speed ca n be selec ted via sof tware using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register.

The system clock ca n be se lec ted betw ee n external or internal cloc k sourc es via th e System Cl ock Select ion (SCS) bit of the OSCCON register. See Section 3.6 “Clock Switching” for more information.

3.5.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is progra mmed usi ng the osc illator se lectio n or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 12.0 “Special Features of the CPU” for more information.

In INTOSC mode, OSC1/CLKIN i s available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator fre quency divide d by 4. The CLKO UT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O.

3.5.2 HFINTOSC

The High-Frequency Int ernal Oscillato r (HFINT OSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 3-2).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information.

The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz by setting th e IRCF <2:0 > bits of the OSCCON register ≠ 000. Then, set the System Clock Source (SCS) bit of the OSCCON register to ‘1’ or en able Two-Speed Start-up by se tting the IESO bit in the Configuration Word register (CONFIG) to ‘1’.

The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.

PIC12F635/PIC16F636/639

3.5.2.1 OSCTUNE Register

The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register3-2).

The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number.

When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not af fected by the change in frequency.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximum frequen cy 01110 =

•

00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 =

•

• 10000 = Minimum frequency

PIC12F635/PIC16F636/639

3.5.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTO SC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Mo nitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF<2:0> bits of the OSCCON register= 000) as the system clock source (SCS bit of the OSCCON register = 1), or when any of the following are enabled:

• Two-Spe ed Start-up IESO bi t of the C o nfi gura tio n Word register = 1 and IRCF<2:0> bits of the OSCCON register = 000

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit of the OSCCON register indicates whether the LFINTOSC is stable or not.

3.5.4 FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency Select b its IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software:

•8 MHz

• 4 MHz (Default after Reset)

•2 MHz

•1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

• 31 kHz (LFINTOSC) Note: Follow ing any Reset, the I RCF<2 :0> bits of

the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.

3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING

When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6). If this is the case, there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows:

1. IRCF<2:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. CLKOUT is held low and the clock switch

circuitry waits fo r a ris ing edge in the new clock.

5. CLKOUT is now connected with the new clock.

LTS and HTS bits of the OS CCON regi ster are updated as required.

6. Clock switch is comple te.

See Figure 3-1 for more details. If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multi ple xe r.

Start-up delay specifications are located in the A/C Specifications (Oscillator Module) in Section 15.0 “Electrical Specifications”.

PIC12F635/PIC16F636/639

FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING

(1)

HF HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC

Start-up Time

LFINTOSC

2-cycle Sync Running

IRCF <2:0>

System Clock

Note 1: When going from LF to HF.

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC

LFINTOSC

IRCF <2:0>

System Clock

LFINTOSC HFINTOSC

LFINTOSC

HFINTOSC

≠ 0 = 0

2-cycle Sync Running

≠ 0 = 0

LFINTOSC turns off unless WDT or FSCM is enabled

Start-up Time 2-cycle Sync

Running

IRCF <2:0>

System Clock

= 0 ≠ 0

PIC12F635/PIC16F636/639

3.6 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register.

3.6.1 SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals.

• When the SCS bit of the OSCCON register = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word regist er (CONFIG).

• When the SCS bit of the OSCCON register = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<2:0> bits of the OSCCON register. After a Reset, the SCS bit of the OSCCON register is always cleared.

Note: Any automatic clock switch, which may

occur from T wo-Speed Sta rt-up or Fail-Safe Clock Monitor , does not update the SCS bit of the OSCCON register. The user can monitor the OSTS bit of the OSCCON register to determine the current system clock source.

3.6.2 OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.

3.7 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy us e of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.

This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable.

When the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count rea ches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator.

3.7.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO (of the Configuration Word register) = 1;

Internal/External Switchover bit (Two-Speed Start-up mode enabled).

• SCS (of the OSCCON register) = 0.

• FOSC<2:0> bits in the Configuration Word

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.

3.7.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<2:0> bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next fallin g edg e

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear.

PIC12F635/PIC16F636/639

3.7.3 CHE CKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator.

FIGURE 3-7: TWO-SPEED START-UP

HFINTOSC

TOSTT

OSC1

OSC2

Program Counter

System Clock

0 1 1022 1023

PC - N

PC + 1

PIC12F635/PIC16F636/639

3.8 Fail-Safe Clock Monitor

The Fail-Safe Clock Monit or (FSCM) al low s the dev ic e to continue operat ing sh oul d the external oscill ator fai l. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO).

FIGURE 3-8: FSCM BLOCK DIAGRAM

Clock Monitor

External

Clock

LFINTOSC

Oscillator

31 kHz

(~32 μs)

Sample Clock

÷ 64

488 Hz

(~2 ms)

3.8.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by comparing the ex tern al osci llator to the FS CM sa mple clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 3-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock cle ars the latch on each ris ing edge of th e sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the primary clock goes low.

Latch

Clock

Failure

Detected

3.8.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or togg ling the SC S bit of the OSCCON register. When the SCS bit is toggled, the OST is restarted. While the OST is running, the device continue s to op erat e from t he INT OSC sele cted in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock s ource. Th e Fail-Saf e condi tion must be cleared before th e O SFIF f lag ca n be cle are d.

3.8.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the R eset or wake- up has complet ed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed.

3.8.2 FAIL-SAFE OPERATI ON

When the external clock fails, the FSCM switches the device clock to an internal cl ock sourc e and set s the bit flag OSFIF of the PIR1 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation.

The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.

PIC12F635/PIC16F636/639

FIGURE 3-9: FSCM TIMING DIAGRAM

Sample Clock

System

Clock

Output

Clock Monitor Output

(Q)

OSFIF

Test

Note: The system c lock is normally at a mu ch higher frequency than the sam ple clock. The relative frequencies in

this example have been chosen for clarity.

Oscillator Failure

Failure

Detected

Test Test

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CONFIG INTCON GIE PEIE OSCCON OSCTUNE PIE1 PIR1

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR

(2)

CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

— I RCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu EEIE LVDIE CRIE C2IE EEIF LVDIF CRIF C2IF

2: See

3: PIC16F636/639 only.

Configuration Word register (CONFIG) for operation of all register bits.

T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x

(3)

C1IE OSFIE — TMR1IE 000- 00-0 000- 00-0

(3)

C1IF OSFIF — TMR1IF 000- 00-0 000- 00-0

Reset and Watchdog Timer Reset during normal operation.

Val ue on

POR, BOR

Val ue on

all other

Resets

(1)

PIC12F635/PIC16F636/639

4.0 I/O PORTS

There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be a vailable a s general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin.

4.1 PORTA and the TRISA Registers

PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and it s TRIS bit will always read as ‘1’. Example4-1 shows how to initialize PORT A.

Note: PORTA = GPIO

TRISA = TRISIO

Reading the PORTA register (Register 4-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified a nd then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1.

The TRISA register controls the direction of the PORT A pins, even when they are being used as an alog inputs. The user must ensure the bits in the TRISA register are maint ai ned set when using the m as an alog inputs. I/O pins configured as analog inputs always read ‘0’.

4.2 Additional Pin Functions

Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/pull-down option. RA0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions.

4.2.1 WEAK PULL-UP/PULL-DOWN

Each of th e PORTA pins, excep t RA3, has a n inte rnal weak pull-up and pull-down . The WDA bits select either a pull-up or pull-down for an individual port bit. Individual control bits can turn on the pull-up or pull-down. These pull-u ps/pull-downs are automaticall y turned off when the port pin is configured as an output, as an alternate function or on a Power-on Reset, setting the RAPU pull-up on RA3 is enabled when configured as MCLR in the Configuration Word register and disabled when high voltage is detected, to reduce current consumption through RA3, while in Programming mode.

Note: PORTA = GPIO

bit of the OPTION register. A weak

TRISA = TRISIO

Note: The CMCON0 register must be initialized

to configure an analog chan nel as a digit al input. Pins configu red as analo g input s will read ‘0’.

EXAMPLE 4-1: INITIALIZING PORTA

BANKSEL PORTA ; CLRF PORTA ;Init PORTA MOVLW 07h ;Set RA<2:0> to MOVWF CMCON0 ;digital I/O BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; MOVLW 0Ch ;Set RA<3:2> as inputs MOVWF TRISA ;and set RA<5:4,1:0>

;as outputs

PIC12F635/PIC16F636/639

U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x

— — RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit

1 = Port pin is > V 0 = Port pin is < VIL

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISA<5:0>: PORTA Tri-State Control bits

1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output

Note 1: TRISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

PIC12F635/PIC16F636/639

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WDA5 WDA4 — WDA2 WDA1 WDA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WDA<5:4>: Pull-up/Pull-down Selection bits

1 = Pull-up selected 0 = Pull-down selected

bit 3 Unimplemented: Read as ‘0’ bit 2-0 WDA<2:0>: Pull-up/Pull-down Selection bits

1 = Pull-up selected 0 = Pull-down selected

Note 1: The weak pull-up/pull-down device is enabled only when the global RAPU

= 1), the individual WDA bit is enabled (WDA = 1) and the pin is not configured as an analog input or clock function.

2: RA3 pull-up is enabled when the pin is configured as MCLR

Programming mode.

in the Configuration Word register and the device is not in

bit is enabled, the pin is in Input mode (TRIS

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WPUDA5

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUDA<5:4>: Pull-up/Pull-down Direction Selection bits

1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUDA<2:0>: Pull-up/Pull-down Direction Selection bits

1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled

Note 1: The weak pull-up/pull-down direction device is enabled only when the global RAPU

(TRIS = 1), the individual WPUDA bit is enabled (WPUDA = 1) and the pin is not configured as an analog input or clock function.

2: RA3 pull-up is enabled when the pin is configured as MCLR

Programming mode.

3: WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled; otherwise, the bit can not be written and reads

as ‘1’. WPUDA4 bit can be written if not configured as OSC2; otherwise, the bit can not be written and reads as ‘1’

(3)

WPUDA4

(3)

— WPUDA2 WPUDA1 WPUDA0

(3)

bit is enabled, the pin is in Input mode

in the Configuration Word register and the device is not in

PIC12F635/PIC16F636/639

4.2.2 INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as an interrupt-on-chang e pin. Control bit s, IOCAx, enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the values are compared with the old value la tched on the last rea d of PORTA. The ‘mismatch’ outputs of the last read are OR’d together to set t he PORT A C hange Interrupt Flag bit (RAIF) in the INTCON register.

This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by:

a) Any read or write of PORTA. This will end the

mismatch condition, then

b) Clear the flag bit RAIF.

A mismatch c ond it i on wi ll cont i n ue to s et f lag bi t RA IF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the last read value is not affected by a MCLR Reset. After these Resets, the RAIF flag will continue to be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when the read operation is bei ng executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.

nor BOR

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— —IOCA5

bit 7 bit 0

(2)

IOCA4

(2)

IOCA3

(3)

IOCA2 IOCA1 IOCA0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCA<5:0>: Interrupt-on-Change PORT A Control bits

1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOCA<5:4> always reads ‘0’ in XT, HS and LP Oscillator modes. 3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.

(1)

(2,3)

PIC12F635/PIC16F636/639

4.2.3 ULTRA LOW-POWER WAKE-UP

The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on RA0.

To use this feature, the RA0 pin is configured to output ‘1’ to charge the capacitor, interrupt-on-change for RA0 is enabled and RA0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on RA0 drops below V the device to wake-up. Depending on the state of the GIE bit of the INTCON register, the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See

Section 4.2.2 “Interrupt-on-Change” and Section 12.9.3 “PORTA Interrupt” for more

information. This feature provides a low-power technique for

periodically waking up the device from Sleep. The time-out is dependent on the discharge time of the RC circuit on RA0. See Ex ample 4-2 for initializing the Ultra Low Power Wake-up module.

The series resistor provides overcurrent protection for the RA0 pin and can allow for software calibration of the time-out (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor.

IL, an interrupt will be generated which will cause

EXAMPLE 4-2: ULTRA LOW-POWER

WAKE-UP INITIALIZATION

BANKSEL PORTA ; BSF PORTA,0 ;Set RA0 data latch MOVLW H’7’ ;Turn off MOVWF CMCON0 ; comparators BANKSEL TRISA ; BCF TRISA,0 ;Output high to CALL CapDelay ; charge capacitor BSF PCON,ULPWUE ;Enable ULP Wake-up BSF IOCA,0 ;Select RA0 IOC BSF TRISA,0 ;RA0 to input MOVLW B’10001000’ ;Enable interrupt MOVWF INTCON ; and clear flag SLEEP ;Wait for IOC NOP ;

Note: For more information, refer to the

Application Note AN879, “Using the

Microchip Ultra Low-Power Wake-up Module” (DS00879).

PIC12F635/PIC16F636/639

4.2.4 PIN DESCRIPTIONS AND DIAGRAMS

Each PORT A pin is multiplexed with other functio ns. The pins and their combined functions are briefly described here. For specific information about individual functions, such as the comparator , refe r to the appropriate section in this data sheet.

FIGURE 4-1: BLOCK DIAGRAM OF RA0

Analog

(1)

RAPU

Data Bus

WPUDA

WDA

Input Mode

4.2.4.1 RA0/C1IN+/ICSPDAT/ULPWU

Figure 4-2 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

• In-Circuit Serial Programming™ data

• an analog input for the Ultra Low-Power Wake-up

VDD

Weak

VDD

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

Change

–

Analog

Input Mode

RD PORTA

(1)

ULPWUE

IULP

I/O pin

VSS

Note 1: Comparator mode determines Analog Input mode.

PIC12F635/PIC16F636/639

4.2.4.2 RA1/C1IN-/VREF/ICSPCLK

Figure 4-2 shows th e diagr am for thi s pin. Th e RA1 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

• In-Circuit Serial Pr ogramming™ clock

FIGURE 4-2: BLOCK DIAGRAM OF RA1

Analog

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

To Comparator

Input Mode

(1)

RAPU

Analog

Input Mode

RD PORTA

VDD

Weak

VSS

VDD

I/O pin

VSS

(1)

4.2.4.3 RA2/T0CKI/INT/C1OUT

Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following:

• a general purpose I/O

• the clock input for Timer0

• an external edge-triggered interrupt

• a digital output from the comparator

FIGURE 4-3: BLOCK DIAGRAM OF RA2

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

RAPU

C1OUT

Enable

C1OUT

RD PORTA

VDD

Weak

VSS

VDD

I/O pin

VSS

Note 1: Comparator mode determines Analog Input mode.

To Timer0 To INT

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4.2.4.4 RA3/MCLR/VPP

Figure 4-4 shows th e diagr am for thi s pin. Th e RA3 pin is configurable to function as one of the following:

• a general purpose input

• as Master Clear Reset with weak pull-up

• a high-voltage detect for Program mode entry

FIGURE 4-4: BLOCK DIAGRAM OF RA3

VDD

Data Bus

TRISA

PORTA

IOCA

Program

Mode

VSS

MCLRE

Reset

HV Detect

MCLRE

RD PORTA

Weak

Input pin

Interrupt-on-

change

WURE Sleep

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4.2.4.5 RA4/T1G/OSC2/CLKOUT

Figure 4-5 shows th e diagr am for thi s pin. Th e RA4 pi n is configurable to function as one of the following:

• a general purpose I/O

• a Timer1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 4-5: BLOCK DIAGRAM OF RA4

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

T1G To T imer1

OSC1

RAPU

FOSC/4

CLKOUT

INTOSC/ RC/EC

CLKOUT

(1)

CLK

Modes

Oscillator

Circuit

CLKOUT

Enable

(2)

Enable

XTAL

RD PORTA

VDD

Weak

VSS

VDD

I/O pi

VSS

4.2.4.6 RA5/T1CKI/OSC1/CLKIN

Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following:

• a general purpose I/O

• a Timer1 clock inpu t

• a crystal/resona tor connec tio n

• a clock input

FIGURE 4-6: BLOCK DIAGRAM OF RA5

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

T1G T o Timer1

OSC2

(1)

CLK

RAPU

Oscillator

Circuit

INTOSC

Mode

RD PORTA

Modes

VDD

Weak

VSS

VDD

I/O pin

VSS

(2)

Note 1: Oscillator modes are XT, HS, LP, LPTMR1 and

CLKOUT Enable.

2: With CLKOUT option.

Note 1: Oscillator modes are XT, HS, LP and LPTMR1.

2: When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

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TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PORTA INTCON GIE TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC CMCON1 CMCON0 OPTION_REG TRISA WPUDA IOCA WDA Legend: x = unknown , u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xx00 --uu uu00

PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x

TMR1CS TMR1ON 0000 0000 uuuu uuuu

— — — — — —T1GSSCxSYNC ---- --10 ---- --10

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

RAPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 — — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 — — WDA5 WDA4 — WDA2 WDA1 WDA0 --11 -111 --11 -111

Value on

POR, BOR,

WUR

Value on all

other Resets

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4.3 PORTC

PORTC is a general purpose I/O port consisting of 6 bidirectional pins . The pins can be con figured for e ither digital I/O or analog input to comparator. For specific information about individual functions, refer to the appropriate section in this data sheet.

Note: The CMCON0 register must be initialized

to configure an analog chan nel as a digit al input. Pins configu red as analo g input s will read ‘0’.

EXAMPLE 4-3: INITIALIZING PORTC

BANKSEL PORTC ; CLRF PORTC ;Init PORTC MOVLW 07h ;Set RC<4,1:0> to MOVWF CMCON0 ;digital I/O BANKSEL TRISC ; MOVLW 0Ch ;Set RC<3:2> as inputs MOVWF TRISC ;and set RC<5:4,1:0>

;as outputs

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0

— — RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC<5:0>: PORTC General Purpose I/O Pin bits

1 = Port pin is > V 0 = Port pin is < VIL

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output

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4.3.1 RC0/C2IN+

Figure 4-7 shows th e diag ram for th is pi n. The RC0 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

4.3.2 RC1/C2IN-

Figure 4-7 shows th e diag ram for th is pi n. The RC1 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

4.3.3 RC2

Figure 4-8 shows th e diag ram for th is pi n. The RC2 pi n is configurable to function as a general purpose I/O.

4.3.4 RC3

Figure 4-8 shows th e diag ram for th is pi n. The RC3 pi n is configurable to function as a general purpose I/O.

4.3.5 RC5

Figure 4-8 shows th e diag ram for th is pi n. The RC5 pi n is configurable to function as a general purpose I/O.

FIGURE 4-7: BLOCK DIAGRAM OF RC0

AND RC1

Data Bus

VDD

I/O pin

VSS

PORTC

TRISC

PORTC

To Comparators

Analog Input

Mode

FIGURE 4-8: BLOCK DIAGRAM OF

RC2, RC3 AND RC5

Data Bus

PORTC

TRISC

PORTC

VDD

I/O pin

VSS

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4.3.6 RC4/C2OUT

Figure 4-9 shows th e diag ram fo r this pin. T he RC4 pin is configurable to function as one of the following:

• a general purpose I/O

• a digital output from the comparator

FIGURE 4-9: BLOCK DIAGRAM OF RC4

C2OUT Enable

C2OUT

Data Bus

VDD

I/O pin

VSS

PORTC

TRISC

PORTC

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PORTC CMCON0 TRISC Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

— — RC5 RC4 RC3 RC2 RC1 RC0 --xx xx00 --uu uu00

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

— — TRISC5 TRISC4 TRISC3 T RISC2 T RISC1 T RISC0 --11 1111 --11 1111

Val ue on

POR, BOR,

WUR

Val ue on

all other

Resets

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NOTES:

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5.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/c ounter with the following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow Figure 5-1 is a block diagram of the Timer0 module.

5.1 Timer0 Operation

When used as a timer, the T im er0 mo dule ca n be use d as either an 8-bit timer or an 8-bit counter.

5.1.1 8-BIT TIMER MODE

When used as a timer, the Timer0 module will increment every instruction cyc le (without prescaler ). Timer mode is selected by clearing the T0CS bit of the OPTION register to ‘0’.

When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write.

Note: The val ue written to the TMR0 register ca n

be adjusted, in order to ac count for th e two instruction cycle delay when TMR0 is written.

5.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4

T0CKI

T0SE

WDTE

SWDTEN

31 kHz

INTOSC

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register.

T0CS

Watchdog

Timer

PSA

16-bit

Prescaler

8-bit

Prescaler

WDTPS<3:0>

PS<2:0>

PSA

Sync

2 T

WDT

Time-out

Data Bus

TMR0

Set Flag bit T0IF

on Overflow

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5.1.3 SOFTWARE PROGRAMMABLE PRESCALER

A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit o f the OP TION register. To assign t he p res caler to Timer0, th e PSA b it must be cleared to a ‘0’.

There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable vi a the PS<2:0> bit s of the OPTIO N register . In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module.

The prescaler is not readable or writable. When assigned to the Tim er0 module, all instructions w riting to the TMR0 register will clear the prescaler .

When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.

5.1.3.1 Switching Prescaler Between

Timer0 and WDT Modules

As a result of hav ing the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changin g th e presca le r ass ig nme nt from Timer0 to the WDT module, the instr uction sequence shown in Example 5-1, must be executed.

EXAMPLE 5-1: CHANGING PRESCALER

(TIMER0 → WDT)

BANKSEL TMR0 ; CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and

;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ;

; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32

When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 5-2).

EXAMPLE 5-2: CHANGIN G PRESCALER

(WDT → TIMER0)

CLRWDT ;Clear WDT and

;prescaler BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG ;

5.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register..

Note: The Timer0 interrupt cannot wake the

processor from Sleep since the timer is frozen during Sleep.

5.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK

When Timer0 is in Coun ter mo de, t he synchronizatio n of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phas e clocks. Ther efore, t he high and low periods of the extern al cl oc k so urc e mus t meet the timing requirements as shown in the Section 15.0 “Electrical Specifications”.

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R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 R

APU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

BIT VALUE TMR0 RATE WDT RATE

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available. See Section 12.11 “Watchdog Timer (WDT)” for more

information.

TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on :

POR, BOR

TMR0 Timer0 Mo dule Register xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE OPTION_REG

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented l oc ati ons , re ad as ‘0’, u = unchanged, x = un kn ow n. Shad ed cells are not used by th e

Timer0 module.

Value on

all other

Resets

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6.0 TIMER1 MODULE WITH GATE CONTROL

The Timer1 module is a 16-bit timer/counter with the following features:

• 16-bit timer/counter regist er pair (TMR1H: TMR1L)

• Programmable internal or external clock source

• 3-bit prescaler

• Optional LP oscillator

• Synchronous or asynchronous operation

• Timer1 gate (count enable) via comparator or

T1G

• Interrupt on overflow

• Wake-up on overflow (exter nal clock,

Asynchronous mode only)

• Comparator output synchronization to Timer1

clock

Figure 6-1 is a block diagram of the Timer1 module.

6.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.

When used with an interna l clock so urce, the module i s a timer. When used with an exter nal cl ock sou rce, t he module can be used as either a timer or counter.

6.2 Clock Source Selection

The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally.

Clock

Source

OSC/4 x xxx x

F T1CKI pin x1 T1LPOSC 1 LP or

T1OSCEN

FOSC

Mode

INTOSCIO

T1CS

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FIGURE 6-1: TIMER1 BLOCK DIAGRAM

Set flag bit TMR1IF on Overflow

OSC1/T1CKI

OSC2/T1G

INTOSC

Without CLKOUT

T1OSCEN

(2)

TMR1

TMR1H TMR1L

Oscillator

Internal

OSC/4

Clock

OSC

(1)

T1ACS

TMR1ON

To C2 Comparator Module Timer1 Clock

TMR1CS

T1SYNC

Prescaler

1, 2, 4, 8

T1CKPS<1:0>

CxOUT

TMR1GE

Synchronized

clock input

Synchronize

T1GSS

T1GINV

(3)

det

Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.

2: Ti mer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.

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6.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples

CY as determined by the Timer1 prescaler.

of T

6.2.2 EXT ERN AL CLOCK SOURCE

When the external clock source is selected, the Timer1 module may work as a timer or a counter.

When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions:

• Timer1 is enabled after POR or BOR Reset

• A write to TMR1H or TMR1L

• T1CKI is high when Timer1 is disabled and when

Timer1 is reena bl ed T1 CKI is l ow. See Figure 6-2.

6.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cl eared upon a write to TMR1H or TMR1L.

6.4 Timer1 Oscillator

A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (amplifier output). The oscillator is enabl ed by settin g the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep.

The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer 1 can use th is mode on ly when the primary system clock is derived from the internal oscillator or when in LP osci llator m ode. The us er must provide a software time delay to ensure proper oscillator start-up.

TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bit s rea d a s ‘0’ and TRISA5 and TRISA4 bits read as ‘1’.

Note: The oscillator requires a start-up and

stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.

6.5 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 “Reading and Writing

Timer1 in Asynchronous Counter Mode”).

Note: When switching from synchronous to

asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment.

6.5.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running from an external asyn chronous cl ock will e nsure a valid read (taken care of in hardware). However, the user should keep in mind that rea ding t he 16-bi t ti mer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads.

For writes, it is recommend ed that th e user s imply sto p the timer and write the desired values. A write contention may occ ur by w ritin g to th e timer regist ers, while the register is incrementi ng. This may pro duce an unpredictable value in the TMR1H:TTMR1L register pair.

6.6 Timer1 Gate

Timer1 gate source is software configurable to be the

pin or the output of Comparator 2. This allows the

T1G device to directly time external events using T1G analog events using Comparator 2. See the CMCON1 register (Register 7-3) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com).

Note: TMR1GE bit of the T1CON register must

be set to use either T1G Timer1 gate so urce. See Register 7-3 for more information on selecting the Timer1 gate source.

Timer1 gate can be inverted using the T1GINV bit of the T1CON register , wheth er it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events.

or C2OUT as the

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6.7 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over , the T i mer1 in terrupt fl ag bit of th e PIR1 regis ter is set. To enable the interrupt on rollover, you must set these bits:

• Timer1 interrupt enable bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note: The TMR1 H:TTMR1L reg ister pair and the

TMR1IF bit should be cleared before enabling interrupts.

6.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in Asynchronous Count er mode. In this mode, a n external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute

the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).

6.9 Comparator Synchronization

The same cl ock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module.

When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator chang es.

For more information, see Section 7.0 “Comparator

Module”.

FIGURE 6-2: TIMER1 INCREMENTING EDGE

T1CKI = 1 when TMR1

Enabled

T1CKI = 0 when TMR1 Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the firs t incrementing rising edge of

the clock.

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6.10 Timer1 Control Register

The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

T1GINV

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

TMR1GE

(2)

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 T1GINV: Timer1 Gate Invert bit

1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 6 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0: This bit is ignored If TMR1ON =

1 = Timer1 is on if Timer1 gate is active 0 = Timer1 is on

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off

Else: This bit is ignored. LP oscillator is disabled.

bit 2 T1SYNC

TMR1CS =

1 = Do not synchronize external clock inp ut 0 = Synchronize external clock input

TMR1CS = This bit is ignored. Timer1 uses the internal clock

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (F

bit 0 TMR1ON: Timer1 On b it

1 = Enables Timer1 0 = Stops Timer1

: Timer1 External Clock Input Synchronization Control bit

OSC/4)

(1)

(2)

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G

pin or C2OUT, as selected by the T1GSS bit of the CMCON1

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TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CMCON1 — — — — — — T 1G SS CMSYNC ---- --10 00-- --10 INTCON GIE PEIE PIE1 PIR1 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC16F636/639 only.

EEIE LVDIE CRIE C2IE

EEIF LVDIF CRIF C2IF

T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x

(1)

C1IE OSFIE —TMR1IE000- 00-0 000- 00-0

(1)

C1IF OSFIF —TMR1IF

TMR1CS TMR1ON 0000 0000 uuuu uuuu

Val ue on

POR, BOR

000- 00-0 000- 00-0

Val ue on all other

Resets

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

7.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The Analog Comparator module includes the following features:

• Dual comparators (PIC16F636/639 only)

• Multiple comparator configurations

• Comparator(s) output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

• Timer1 gate (co unt ena ble )

• Output synchronization to Timer1 clock input

• Programmable voltage reference

7.1 Comparator Overview

A comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at V

IN-, the output of the

comparator is a digital low level. When the analog voltage at V V

IN-, the output of the comparat or is a digit al high le vel.

IN+ is greater than the analog voltage at

The PIC12F635 contains a single comparator as shown in Figure 7-2.

The PIC16F636/639 devices contains two comparators as shown in Figure 7-3 and Figure 7-4. The comparators are not independently configurable.

FIGURE 7-1: SINGLE COMPARATOR

VIN+

IN-

VINVIN+

Output

Note: The black areas of the output of the

comparator represents the uncertainty due to input offsets and response time.

–

Output

FIGURE 7-2: COMPARATOR OUTPUT BLOCK DIAGRAM (PIC12F635)

MULTIPLEX

Port Pins

Note 1: Comparator output is latched on falling edge of Timer1 clock source.

2: Q1 and Q3 are phases of the four-phase system clock (F 3: Q1 is held high during Sleep mode.

CINV

Timer1

clock source

Q3*RD CMCON0

(1)

Reset

CMSYNC

RD CMCON0

OSC).

To Timer1 Gate

To COUT pin

To Data Bus

Set CMIF bit

PIC12F635/PIC16F636/639

FIGURE 7-3: COMPARATOR C1 OUTPUT BLOCK DIAGRAM (PIC16F636/639)

MULTIPLEX

Port Pins

C1INV

To C1OUT pin

Q3*RD CMCON0

Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC).

2: Q1 is held high during Sleep mode.

Reset

RD CMCON0

To Data Bus

Set C1IF bit

FIGURE 7-4: COMPARATOR C2 OUTPUT BLOCK DIAGRAM (PIC16F636/639 )

C2SYNC

T o Timer1 Gate

To C2OUT pin

Port Pins

MULTIPLEX

C2INV

Timer1

clock source

(1)

Q3*RD CMCON0

Note 1: Comparator output is latched on falling edge of Timer1 clock source.

2: Q1 and Q3 are phases of the four-phase system clock (F 3: Q1 is held high during Sleep mode.

Reset

RD CMCON0

OSC).

To Data Bus

Set C2IF bit

PIC12F635/PIC16F636/639

7.2 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in Figure 7-5. Since the analog i nput pins share thei r connection with a digital input, they have reverse biased ESD protection diodes to V input, therefore, must be between V input voltage deviates from this range by more than

0.6V in either direction, one of the diodes is forward

biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended

for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage curr ent to minimize inaccuracies introduced.

FIGURE 7-5: ANALOG INPUT MODEL

DD and VSS. The analog

SS and VDD. If the

VDD

Note 1: When reading a PORT register, all pins

configured as anal og inp uts will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to consume more current than is specified.

Rs < 10K

AIN

Legend: CPIN = Input Capacitanc e

LEAKAGE = Leakage Current at the pin due to various junctions

I R

IC = Interconnect Resistance S = Source Impedance

A = Analog Voltage

V V

T = Threshold Voltage

5 pF

VT ≈ 0.6V

RIC

To Comparator

ILEAKAGE ±500 nA

Vss

PIC12F635/PIC16F636/639

7.3 Comparator Configuration

There are eight mod es of operat ion fo r the comp arato r. The CM<2:0> bits of th e CMCON0 reg ister are used to select these modes as shown in Figures 7-6 and 7-7. I/O lines change as a function of the mode and are designed as follows:

• Analog function (A): digital input buffer is disabled

• Digital function (D): comparator digital output, overrides port function

• Normal port function (I/O): independent of

The port pins denoted as “A” will read as a ‘0’ regardless of the state of the I/O pin or the I/O control TRIS bit. Pins used as analog inputs should also have the corresponding TRIS bit set to ‘1’ to disable the digital output driver. Pins denoted as “D” should have the corresponding TRIS bit set to ‘0’ to enable the digital output driver.

Note: Comparator interr upts sh ould be dis abled

during a Comparator mode change to prevent unintended interru pt s .

comparator

FIGURE 7-6: COMPARATOR I/O OPERATING MODES (PIC12F635)

Comparator Reset (POR Default Value – low power) Comparator w/o Output and with Internal Reference CM<2:0> = 000 CM<2:0> = 100

CINCIN+

COUT (pin)

I/O

Off

(1)

Comparator with Output Multiplexed Input with Internal Reference and Output CM<2:0> = 001 CM<2:0> = 101

CINCIN+

COUT (pin)

I/O

COUT

From CVREF Module

CINCIN+

COUT (pin)

A A

COUT

CINCIN+

COUT (pin)

CIS = 0

CIS = 1

From CVREF Module

Comparator without Output Multiplexed Input with Internal Reference CM<2:0> = 010 CM<2:0> = 110

CINCIN+

COUT (pin)

A A

I/O

COUT

COUT (pin)

CINCIN+

A A

I/O

CIS = 0 CIS = 1

From CVREF Module

Comparator with Output and Internal Reference Comparator Off (Lowest power) CM<2:0> = 011 CM<2:0> = 111

CINCIN+

COUT (pin)

I/O

COUT

From CVREF Module

COUT (pin)

CINCIN+

I/O I/O

I/O

Off

(1)

COUT

Legend: A = Analog Input, ports always reads ‘0’ CIS = Comparator Input Switch (CMCON0<3>)

I/O = Normal port I/O D = Comparator Digital Output

Note 1: Reads as ‘0’, unless CINV = 1.

PIC12F635/PIC16F636/639

FIGURE 7-7: COMPARATOR I/O OPERATING MODES (PIC16F636/639)

Comparators Reset (POR Default Value) CM<2:0> = 000

C1INC1IN+

C2INC2IN+

VIN-

(1)

IN+

VIN-

IN+

Off

(1)

Two Independent Comparators CM<2:0> = 100

C1INC1IN+

C2INC2IN+

VIN-

IN+

VIN-

IN+

C1OUT

C2OUT

Three Inputs Multiplexed to Two Comparators CM<2:0> = 001

C1INC1IN+

C2INC2IN+

CIS = 0

CIS = 1

A A

VINVIN+

Four Inputs Multiplexed to Two Comparators CM<2:0> = 010

C1INC1IN+

C2INC2IN+

A A

CIS = 0 CIS = 1

VIN-

VIN+

VIN-

VIN+

From CVREF Module

Two Common Reference Comparators CM<2:0> = 011

I/O

VIN-

IN+

C1OUT

C1INC1IN+

C1OUT

C2OUT

C1OUT

C2OUT

One Independent Comparator CM<2:0> = 101

I/O I/O

A A

VIN-

IN+

VIN-

IN+

(1)

Off

C2OUT

C1INC1IN+

C2INC2IN+

Two Common Reference Comparators with Outputs CM<2:0> = 110

C1IN-

C1OUT(pin)

C2INC2IN+

C2OUT(pin)

VIN-

IN+

VIN-

IN+

C1OUT

C2OUT

Comparators Off (Lowest Power) CM<2:0> = 111

I/O I/O

VIN-

IN+

Off

(1)

C1INC1IN+

C2INC2IN+

VIN-

VIN+

C2OUT

C2INC2IN+

I/O I/O

VIN-

IN+

Off

(1)

Legend: A = Analog Input, ports always reads ‘0’ CIS = Comparator Input Switch (CMCON0<3>)

I/O = Normal port I/O D = Comparator Digital Output

Note 1: Reads as ‘0’, unless CxINV = 1.

PIC12F635/PIC16F636/639

7.4 Comparator Control

The CMCON0 register (Register 7-1) provides access to the following comparator features:

• Mode selection

• Output state

• Output polarity

• Input switch

7.4.1 COMPARATOR OUTPUT STATE

Each comparator state can always be read internally via the CxOUT bit of the CMCON0 register. The comparator state ma y a ls o be directed to the CxO UT p in i n the following modes:

PIC12F635

• CM<2:0> = 001

• CM<2:0> = 011

• CM<2:0> = 101

PIC16F636/639

• CM<2:0> = 110

When one of the above modes is selected, the associated TRIS bit of the C xOUT pin mu st be cleare d.

7.4.2 COMPARATOR OUTPUT POLARITY

Inverting the output of a comparator is functionally equivalent to swapping the comparator inputs. The polarity of a comparator output can be inverted by setting the C

XINV results in a non-inverted output. A complete

C table showing the output state versus input conditions and the polarity bit is shown in Table 7-1.

XINV bit of the CMCON0 register. Clearing

7.4.3 COMPARATOR INPUT SWITCH

The inverting inpu t of the compa rators may be switc hed between two analog pins in the following modes:

PIC12F635

•CM<2:0> = 101

•CM<2:0> = 110 PIC16F636/639

•CM<2:0> = 001 (Comparator C1 only)

•CM<2:0> = 010 (Comparators C1 and C2) In the above modes, both pins remain in Analog mode

regardless of which pin is sele cted as the input. The CIS bit of the CMCON0 register controls the comparator input switch.

TABLE 7-1: OUTPUT STATE VS. INPUT

CONDITIONS

Input Conditions CxINV CxOUT

IN- > VIN+ 00

V VIN- < VIN+ 01

IN- > VIN+ 11

V VIN- < VIN+ 10

Note: CxOUT refers to both the register bit and

output pin.

PIC12F635/PIC16F636/639

7.5 Comparator Response Time

The comparator output is indeterminate for a period of time after the chang e of an input source o r the selectio n of a new reference voltage . This period is refe rred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input ch ange. See the Comparato r and Voltage Specifications in Section 15.0 “Electrical

Specifications” for more details.

7.6 Comparator Interrupt Operation

The compar ator in terrupt flag i s set wh eneve r there i s a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latc hes and an exclusiv e-or gate (see Figures 7-8 and 7-9). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latc h of the mismatch circuit i s updated on every Q1 system clock. A mismatch condition will occur when a comparator outp ut change is clocked thro ugh the second latch on t he Q1 cl ock cycl e. The mi smatch condition will persist, holding the CxIF bit of the PIR1 register true , until e ither the CMCON0 re gister is read or the comparator output returns to the previous state.

Note: A write operati on to the CMCON0 reg ister

will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle.

Software will need to maintain information about the status of the comparat or output to dete rmine the actual change that has occurred.

The CxIF bit of the PIR1 register, is the comparator interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to wr ite a ‘1’ to this register, a simulated interrupt may be initiated.

The CxIE bit of the PIE1 re gister and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabl ed, althou gh the CxI F bit of the PIR1 register will still be set if an interrupt condition occurs.

The user , in the Interru pt Service Routi ne, can cle ar the interrupt in the following manner:

a) Any read or write of CMCON0. This will end the

mismatch condition. See Figures 7-8 and 7-9.

b) Clear the CxIF interrupt flag. A persistent mismatch condition will preclude clearing

the CxIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CxIF bit to be cleared.

Note: If a change in the CMCON0 register

(CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), the n the CxIF int err upt flag m ay not get set.

PIC12F635/PIC16F636/639

FIGURE 7-8: COMPARATOR

INTERRUPT TIMING W/O CMCON0 READ

Q1 Q3

IN+

C CxOUT Set CxIF (level) CxIF

FIGURE 7-9: COMPARATOR

Q1 Q3

IN+

C CxOUT Set CxIF (level) CxIF

cleared by CMCON0 read

TRT

reset by software

INTERRUPT TIMING WITH CMCON0 READ

TRT

reset by software

Note 1: If a change in the CMCON0 register

(CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF of the PIR1 register interrupt flag may not get set.

2: When either comparator is first enabled,

bias circuitry in the Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.

PIC12F635/PIC16F636/639

7.7 Operation During Sleep

The comparator , if enabled b efore entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is show n sep arately in the Section 15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by

7.8 Effects of a Reset

A device Reset forces the CMCON0 and CMCON1 registers to their R eset st ates . This forces th e Co mp arator module to be in the Comparator Reset mode (CM<2:0> = 000). Thus, all comparator inputs are analog inputs with the co mparator disab led to consume

the smallest current possible. turning off the comparator. The comparator is turned off by selectin g mod e C M<2:0 > = 000 or CM<2:0> = 111 of the CMCON0 register.

A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE1 reg ister and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine.

U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—COUT— CINV CIS CM2 CM1 CM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6 COUT: Comparator Output bit

bit 5 Unimplemented: Read as ‘0’ bit 4 CINV: Comparator Output Inversion bit

bit 3 CIS: Comparat or Input Switch bit

bit 2-0 CM<2:0>: Comparator Mode bits (See Figure 7-5)

When CINV = 1 = VIN+ > VIN-

IN+ < VIN-

0 = V When CINV =

1 = VIN+ < VIN0 = V

IN+ > VIN-

1 = Output inverted 0 = Output not inverted

When CM<2:0> =

1 = CIN+ connects to VIN0 = CIN- connects to V

When CM<2:0> = CIS has no effect.

000 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off 001 = CIN pins are configured as analog, COUT pin configured as Comparator output 010 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally 011 = CIN- pin is configured as analog, CIN+ pin is con figured as I/O, COUT pin configured as

100 = CIN- pin is configured as analog , CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comp arator output

101 = CIN pins are configured as analog and multip lexed, COUT pin is configured as

110 = CIN pins are configured as analog and multip lexed, COUT pin is configured as I/O,

111 = CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off.

110 or 101:

IN-

0xx or 100 or 111:

Comparator output, CV

available internally, CV

Comparator output, CV

Comparator output available internally, CV

REF is non-inverting input

PIC12F635/PIC16F636/639

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2OUT: Comparator 2 Output bit

When C2INV =

1 = C2 VIN+ > C2 VIN0 = C2 V

When C2INV =

1 = C2 VIN+ < C2 VIN0 = C2 V

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 = C1 VIN+ > C1 VIN0 = C1 V

When C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 V

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output inverted 0 = C2 output not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 Output inverted 0 = C1 Output not inverted

bit 3 CIS: Comparator Input Switch bit

When CM<2:0> = 010: 1 = C1IN+ connects to C1 VIN-

C2IN+ connects to C2 V 0 = C1IN- connects to C1 V C2IN- connects to C2 V When CM<2:0> =

1 = C1IN+ connects to C1 VIN0 = C1IN- connects to C1 V

bit 2-0 CM<2:0>: Comparator Mo de bits (See Fi gure 7-5)

000 = Comparators off. CxIN pins are configured as analog 001 = Three inputs multiplexed to two comparators 010 = Four inputs multiplexed to two comparators 011 = Two common reference comparators 100 = Two independent comparators 101 = One independent comparator 110 = Two comparators with outputs and common reference 111 = Comparators off. CxIN pins are configured as digital I/O

IN+ < C2 VIN-

IN+ > C2 VIN-

IN+ < C1 VIN-

IN+ > C1 VIN-

IN-

001:

IN-

PIC12F635/PIC16F636/639

7.9 Comparator Gating Timer1

This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator (or Comparator C2 for PIC16F636/639). This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details.

It is recommended to synchronize the comparator with Timer1 by setting the CxSYNC bit when the comparator is used as t he T imer1 gate sou rce. T his ensur es T imer1 does not miss an increme nt if the compar a tor ch an ges during an increment.

Note: References to the comparator in this

section specifically are referring to Comparator C2 on the PIC16F636/639.

7.10 Synchronizing Comparator Output

to Timer1

The comparator (or Comparator C2 for PIC16F636/639) output can be synchronized with Timer1 by setting the CxSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the ri sing edge of its clock source. See the Comparator Block Diagram (Figure 7-2) and the Timer1 Block Diagram (Figure 6-1) for more information.

Note: References to the comparator in this

section specifically are referring to Comparator C2 on the PIC16F636/639.

PIC12F635/PIC16F636/639

U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0

— — — — — — T1GSS CMSYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer1 Gate Source is comparator output

bit 0 CMSYNC: Comparator Output Synchronization bit

1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous

Note 1: Refer to Section 6.6 “Timer1 Gate”.

2: Refer to Figure 7-2.

(1)

(2)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0

— — — — — — T1GSS C2SYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer1 gate source is T1G pin (pin should be configured as digital input) 0 = Timer1 gate source is Comparator C2 output

bit 0 C2SYNC: Comparator C2 Output Synchronization bit

1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous

Note 1: Refer to Section 6.6 “Timer1 Gate”.

2: Refer to Figure 7-4.

(1)

(2)

PIC12F635/PIC16F636/639

)

7.11 Comparator Voltage Reference

The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available:

• Independent from Comparator operation

• Two 16-level voltage ranges

• Output clamped to V

• Ratiometric with VDD

• Fixed Voltage Reference The VRCON register (Register 7-5) controls the

Voltage Reference module shown in Figure 7-10.

7.11.1 INDEPENDENT OPERATION

The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference.

7.11.2 OUTPUT VOLTAGE SELECTION

The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register.

The CVREF output voltage is determined by the following

equations:

7.11.3 OUTPUT CLAMPED TO VSS

The CVREF output voltage can be set to Vss with no

power consumption by configuring VRCON as follo ws:

•VREN=0

•VRR=1

•VR<3:0>=0000

This allows the comparator to detect a zero-crossing

while not consuming additional CV

REF module current.

7.11.4 OUTPUT RATIOMETRIC TO VDD

The comparator voltage reference is VDD d erived and

therefore, the CV

DD. The tested absolute accur acy of the Comparator

Voltage Reference can be found in Section 15.0 “Elec-

trical Specifications”.

REF output changes with fluctuations in

EQUATION 7-1: CVREF OUTPUT VOLTAGE

(INTERNAL CV

VRR 1 (low range):=

REF (VR<3:0>/24) VDD×=

VRR 0 (high range):=

REF (VDD/4) + =

EQUATION 7-2: CV

(VR<3:0> V

REF OUTPUT VOLTAGE

(EXTERNAL CV

VRR 1 (low range):=

REF (VR<3:0>/24) VLADDER×=

RR 0 (high range):=

REF (VLADDER/4) + =

LADDER VDD= or ([VREF+] - [VREF-]) or VREF+

The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 7-10.

(VR<3:0> V

REF)

LADDER/32

DD/32)×

PIC12F635/PIC16F636/639

R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN —VRR— VR3 VR2 VR1 VR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VREN: CV

1 = CV 0 = CV

REF Enable bit

REF circuit powered on REF circuit powered down, no IDD drain and CVREF = VSS.

bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit

1 = Low range 0 = High range

bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0>: CV

When V

REF Value Selection bits (0 ≤ VR<3:0> ≤ 15 )

RR = 1: CVREF = (VR<3:0>/24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0> /32) * VDD

FIGURE 7-10: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8R R R R R

VDD

16-1 Analog

MUX

VREN

CVREF to

Comparator

Input

15 14

2 1 0

VRR

VR<3:0>

(1)

VREN VR<3:0> = 0000 VRR

Note 1: Care should be taken to ensure VREF remains

within the comparator common mode input range. See Section 15.0 “Electrical Specifica-

tions” for more detail.

PIC12F635/PIC16F636/639

T ABLE 7-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE

REFERENCE MODULES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CMCON0 CMCON1 INTCON GIE PEIE PIE1 PIR1 PORTA PORTC TRISA TRISC VRCON VREN Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

—COUT— CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 — — — — — — T1GSS CMSYNC ---- --10 ---- --10

T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x EEIE LVDIE CRIE —C1IEOSFIE — TMR1IE 000- 00-0 000- 00-0 EEIF LVDIF CRIF —C1IFOSFIF — TMR1IF 000- 00-0 000- 00-0

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

Val ue on

POR, BOR

Value on

all other

Resets

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

8.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE

The Programmable Low-Voltage Detect (PLVD) module is a p ower supp ly d ete ctor whic h mon it ors t he internal power supply. This module is typically used in key fobs and other devices, where certain actions need to be taken as a result of a fall ing bat tery vol tag e.

FIGURE 8-1: PLVD BLOCK DIAGRAM

8 Stages

VDD

LVDEN

The PLVD module includes the following capabilities:

• Eight programmable trip points

• Interrupt on falling V

• Stab le refe renc e ind ica tio n

• Operation during Sleep A Block diagram of the PLVD module is shown in

Figure 8-1.

8-to-1

Analog MUX

0 1 2

6 7

det

LVDIF

Reference

Generator

FIGURE 8-2: PLVD OPERATION

VDD

PLVD Trip Point

LVDIF

Set by Hardware

LVDL<2:0>

Voltage

Cleared by Software

PIC12F635/PIC16F636/639

8.1 PLVD Operation

To setup the PLVD for operation, the following steps must be taken:

• Enable the module by setting the LVDEN bit of the LVDCON register.

• Configure the trip point by setting the LVDL<2:0> bits of the LVDCON register.

• Wait for the reference voltage to become stable. Refer to Section 8.4 “Stable Reference Indication”.

• Clear the LVDIF bit of the PIRx

The LVDIF bit will be set when V PL VD trip po int. Th e LVDIF bit re mains s et until cleared by software. Refer to Figure 8-2.

DD falls below the

8.2 Programmable T rip Point

The PLVD trip point is selectable from one of eight voltage levels. The LVDL bits of the LVDCON register select the trip point. Refer to Register 8-1 for the available PLVD trip points.

8.3 Interrupt on Falling VDD

When VDD falls below the PLVD trip point, the falling edge detector will set t he LVDIF bit. See Figure 8-2. An interrupt will be generated if the following bits are also set:

• GIE and PEIE bits of the INTCON register

• LVDIE bit of the PIEx

The L VDIF bit must be c leared by software. An interrupt can be generated from a simulated PLVD event when the LVDIF bit is set by software.

8.4 Stable Ref erence Indication

When the PLVD module is en abl ed, the re feren ce vol tage must be allowed to stabilize before the PLVD will provide a valid result. Refer to Electrical Section, PLVD Characteristics for the stabilization time.

When the HFINTOSC is running, the IRVST bit of the LVDCON register indicates the stability of the voltage reference. The voltage reference is stable when the IRVST bit is set.

8.5 Operation During Sleep

To wake from Sleep, set the LVDIE bit of the PIEx register and the PEIE bit of the INTCO N register . When the LVDIE and PEIE bits are set, the device will wake from Sleep and execute the next instruction. If the GIE bit is also set, th e progr am will c all the I nterrupt Serv ice Routine upon completion of the first instruction after waking from Sleep.

PIC12F635/PIC16F636/639

U-0 U-0 R-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— — IRVST

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Status Flag bit

1 = Indicates that the PLVD is stable and PLVD interrupt is reliable 0 = Indicates that the PLVD is not stable and PLVD interrupt must not be enabled

bit 4 LVDEN: Low-Voltage Detect Module Enable bit

1 = Enables PLVD Module, powers up PLVD circuit and supporting reference circuitry 0 = Disables PLVD Module, powers down PLVD circuit and supporting reference circuitry

bit 3 Unimplemented: Read as ‘0’ bit 2-0 LVDL<2:0>: Low-Voltage Detection Level bits (nominal values)

111 = 4.5V 110 = 4.2V 101 = 4.0V 100 = 2.3V (default) 011 = 2.2V 010 = 2.1V 001 = 2.0V

(2)

000 = Reserved

(1)

LVDEN — LVDL2 LVDL1 LVDL0

(1)

Note 1: The IRVST bit is usable only when the HFINTOSC is running.

2: Not tested and below minimum operating conditions.

TABLE 8-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

INTCON GIE PEIE PIE1 PIR1 LVDCON Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used by the PLVD module.

OSFIE C2IE C1IE LCDIE —LVDIE— CCP2IE 0000 -0-0 0000 -0-0 OSFIF C2IF C1IF LCDIF —LVDIF— CCP2IF 0000 -0-0 0000 -0-0

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -100 --00 -100

T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x

POR, BOR

Value on

all other

Resets

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

9.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable during normal operation (full V is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

• EEDA T

• EEADR EEDAT holds the 8-bit data for read/write and EEADR

holds the address of the EEPROM location being accessed. PIC16F636/639 has 256 bytes of data EEPROM and the PIC12F635 has 128 bytes.

DD range). This memory

The EEPROM data memory allows b yte read and write. A byte write automatically erases the location and writes the new data (erase be fore write). The EEPROM data memory is rated fo r high er ase/writ e cycles. T he write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to A/C specifications in Section 15.0 “Electrical Specifications” for exact limits.

When the data memory is code-protected, the CPU may continue to read and write the data EEPROM memory . The device progra mmer can no longer access the data EEPROM data and will read zeroes.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EEDATn: Byte Value to Write To or Read From Data EEPROM bits

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

EEADR7

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits Note 1: PIC16F636/639 only. Read as ‘0’ on PIC12F635.

EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0

PIC12F635/PIC16F636/639

9.1 EECON1 AND EECON2 Registers

EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non-implemented and read as ‘0’s.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or wr i t e ope r a tio n. T he ina bi l it y t o cl ea r t he WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is c lear . T he WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situ ations, fol lowing Re set, the user can check the WRERR bit, clear it and rewrite the location. The data and address will be cleared. Therefore, the EEDAT and EEADR registers will need to be re-initialized.

Interrupt flag, EEIF bit of the PIR1 reg is ter, is set when write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence.

Note: The EECON1, EEDAT and EEADR

registers should not be modified during a data EEPROM write (WR bit = 1).

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

Legend:

S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any MCLR

normal operation or BOR Reset)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles 0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycl e (The bit is cle ared by hardw are o nce wr ite is co mplet e. The WR b it ca n only

be set, not cleared, in software.)

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared i n hardware. The RD bit can o nly

be set, not cleared, in software.)

0 = Does not initiate an EEPROM read

Reset, any WDT Reset during

PIC12F635/PIC16F636/639

9.2 Reading the EEPROM Data Memory

To read a data memory location, the user must write the address to the EEADR register and then set control bit RD of the EECON1 register, as shown in Example9-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDA T holds this value until another read, or until it is written to by the user (during a write operation).

EXAMPLE 9-1: DATA EEPROM READ

BANKSEL EEADR ; MOVLW CONFIG_ADDR ; MOVWF EEADR ;Address to read BSF EECON1,RD ;EE Read MOVF EEDAT,W ;Move data to W

9.3 Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 9-2.

The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. A ny number th at is not equa l to the required cycles to execute the required sequence will prevent the data from being writte n into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accident al writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the WREN bit will not af fect this wri te cycle. The W R bit will be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit of the PIR1 register must be cleared by software.

9.4 Write Verify

Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 9 -3) to the desired value to be written.

EXAMPLE 9-3: WRITE VERIFY

BANKSEL EEDAT ; MOVF EEDAT,W ;EEDAT not changed

;from previous write

BSF EECON1,RD ;YES, Read the

;value written XORWF EEDAT,W ; BTFSS STATUS,Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue

9.4.1 USING THE DATA EEPROM

The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memo ry.

EXAMPLE 9-2: DATA EEPROM WRITE

BANKSEL EEADR ; BSF EECON1,WREN ;Enable write BCF INTCON,GIE ;Disable INTs MOVLW 55h ;Unlock write MOVWF EECON2 ; MOVLW AAh ; MOVWF EECON2 ;

Required

Sequence

BSF EECON1,WR ;Start the write BSF INTCON,GIE ;Enable INTS

PIC12F635/PIC16F636/639

9.5 Protection Against Spurious Write

There are c onditions when the user may no t want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Als o, the Power-up Timer (nominal 64 ms duration) prevents EEPROM write.

The write initiate se quence and the WREN bit together help preven t an accidental write duri ng:

• Brown-out

•Power Glitch

• Software Malfunction

9.6 Data EEPROM Operation During Code Protection

Data memory can be code-p rotected by progr amming the CPD bit in the Co nfigur ation Word (Regis ter 12-1 ) to ‘0’.

When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to ‘0’ will also help prevent data memory code protection from becoming breached.

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE PIR1 EEIF PIE1 EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEADR EEADR7 EECON1 EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----

Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.

Note 1: PIC16F636/639 only.

EEIE LVDIE CRIE C2IE

— — — — WRERR WREN WR RD ---- x000 ---- q000

Shaded cells are not used by the data EEPROM module.

LVDIF CRI F C2IF

(1)

EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x

(1)

C1IF OSFIF — TMR1IF 0000 00-0 0000 00-0

(1)

C1IE OSFIE —TMR1IE0000 00-0 0000 00-0

Value on

POR, BOR

Value on

all other

Resets

PIC12F635/PIC16F636/639

10.0 KEELOQ® COMPATIBLE CRYPTOGRAPHIC MODULE

To obtain information regarding the implementation of

EELOQ module, Microchip Technology requires

the K the execution of the “K Agreement”.

The “KEELOQ® Encoder Lice nse Agreement” may be accessed through the Microchip web site located at www.microchip.com/K be obtained by contacting you r local Microc hip Sales Representative.

EELOQ. Further information may

EELOQ

Encoder License

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

11.0 ANALOG FRONT-END (AFE) FUNCTIONAL DESCRIPTION (PIC16F639 ONLY)

The PIC16F639 device consists of the PIC16F636 device and low frequency (LF) Analog Front-End (AFE), with the AFE section containing three analog-input channels for signal detection and LF talk-back. This sectio n des cribes t he Analog Fro nt-End (AFE) in detail.

The PIC16F639 device can detect a 125 kHz input signal as low as 1 mVpp and transmit data by using internal LF talk-back modulation or via an external transmitter. The PIC16F639 can also be used for various bidirectional communication applications. Figure 11-3 and Figure 11-4 show application examples of the device.

Each analog input channel has internal tuning capacitance, sensitivity control circuits, an input signal strength limiter and an LF talk-back modulation transistor. An Automatic Gain Control (AGC) loop is used for all three input channel gains. The output of each channel is OR’d and fed into a demodulator. The digital output is passed to the LFDATA pin. Figure 11-1 shows the block diagram of the AFE and Figure 11-2 shows the LC input path.

There are a total of eig ht Confi guratio n regis ter s. Six of them are used for AFE operation options, one for column parity bits and one for status indication of AFE operation. Each register has 9 bits including one row parity bit. These regis te rs are readable and writable by SPI (Serial Protocol Interface) commands except for the STATUS register, which is read-only.

11.1 RF Limiter

The RF Limiter limits LC pin input voltage by de-Q’ing the attached LC resonant circuit. The absolute voltage limit is defined by the silicon process’s maximum allowed input voltage (see Section 15.0 “Electrical Specifications”). The limiter begins de-Q’ing the external LC antenna when the input voltage exceeds

VDE_Q, progressively de-Q’ing harder to reduce the

antenna input voltage. The signal levels from all 3 channels are combined

such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal.

11.2 Modulation Circuit

The modulation circuit consists of a modulation transistor (FET), internal tunin g capacitors and ext ernal LC antenna components. The modulation transistor and the internal tuning capacitors are connected between the LC input pin and LCCOM pin. Each LC input has its own modulation transistor.

When the modulation transistor turns o n, it s low T urn-on Resistance (R voltage. The coil voltage is minimized when the modulation transistor turns-on and maximized when the modulation transistor turns-off. The modulation transistor’s low Turn-on Resistance (R high modulation depth.

The LF talk-back is achieved by turning on and off the modulation transistor.

The modulation data comes from the microcontroller section via the digital SPI interface as “Clamp On”, “Clamp Off” commands. Only those inputs that are enabled will execute the clamp command. A basic block diagram of the modulation circuit is shown in Figure 11-1 and Figure 11-2.

The modulation FET is also shorted momentarily after Soft Reset and Inactivity timer time-out.

M) clamps the induced LC antenna

M) results in a

11.3 Tuning Capacitor

Each channel has internal tuning capacitors for external antenna tuning. The capacitor values are programmed by the Configuration registers

Note: The user can control the tuning c apacitor

by programming the AFE Configuration registers.

up to 63 pF , 1 pF per step.

11.4 Variable Attenuator

The variable attenuator is used to attenuate, via AGC control, the input signal voltage to avoid saturating the amplifiers and demodulators.

Note: The variable attenuator function is

accomplished by the device itself. The user cannot control its function.

11.5 Sensitivity Control

The sensitivity of each channel can be reduced by the channel’s Configuration register sensitivity setting. This is used to desensitize the channel from optimum.

Note: The user can desensitize the channel

sensitivity by programming the AFE Configura tion registers.

PIC12F635/PIC16F636/639

11.6 AGC Control

The AGC controls the variable attenuator to limit the internal signal voltage to avoid saturation of internal amplifiers and demodulators (Refer to Section 11.4 “Varia ble A ttenu ator”).

The signal levels from all 3 channels are combined such that AGC attenuates all 3 channels uniformly in respect to the channel with the strongest signal.

Note: The AGC c ontrol fu nctio n is ac comp lishe d

by the device itself. The user cannot control its function .

11.7 Fixed Gain Amplifiers 1 and 2

FGA1 and FGA2 provides a maximum two-stage gain of 40 dB.

Note: The user cannot control the gain of these

two amplifiers.

11.8 Auto Channel Selection

The Auto Channel Selection feature is enabled if the Auto Channel Select bit AUTOCHSEL<8> in Configuration Register 5 (Register 11-6) is set, and disabled if the bit is cleared. When this feature is active (i.e., AUTOCHSE <8> = 1), the control circuit checks the demodulator output of each input channel immediately after the AGC settling time (T it allows this channel to pass data, otherwise it is blocked.

The status of this operation is monitored by AFE Status Register 7 bits <8:6> (Register 11-8). These bits indicate the current status of the channel selection activity, and automatically updates for every Soft Reset period. The auto channel selection function resets after each Soft Reset (or after Inactivity timer time- out) . Ther efor e, th e blocked channels are reenabled after Soft Reset.

This feature can make the output signal cleaner by blocking any channel that was not high at the end of

AGC. This function works only for demodulated data

T output, and is not applied for carrier clock or RSSI output.

STAB). If the output is hig h,

11.10 Demodulator

The Demodulator consists of a full-wave rectifier, low pass filter, peak detector and Data Slicer that detects the envelope of the input signal.

11. 11 Data Slicer

The Data Slicer consists of a reference generator and comparator. The Data Slicer compares the input with the reference voltage. The reference voltage comes from the minimum modulation depth requirement setting and input peak voltage. The data from all 3 channels are OR’d together and sent to the output enable filter.

11.12 Output Enable Filter

The Output Enable Filter enables the LFDATA output once the incoming signal meets the wake-up sequence requirements (see Section 11.15 “Configurable

Output Enable Filter”).

11. 1 3 RSSI (Received Signal Strength Indicator)

The RSSI provides a current which is propo rtional to the input signal amplitude (see Section 11.31.3 “Received

Signal Strength Indicator (RSSI) Output”).

11.14 Analog Front-End Timers

The AFE has an internal 32 kHz RC oscillator. The oscillator is used in several timers:

• Inactivity timer

• Alarm timer

• Pulse Width timer

• Period timer

• AGC settling timer

11.14.1 RC OSCILLATOR

The RC oscillator is low power, 32 kHz ± 10% over temperature and volta ge variations.

11. 9 Carrier Clock Detector

The Detector senses the input carrier cycles. The output of the Detector switches di gitally at the signal carrier frequency. Carrier clock output is available when the output is selected by the DATOUT bit in the AFE Configuration Register 1 (Register 11-2).

Datasheet PIC12F635, PIC16F636, PIC16F639 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC12F635 BLOCK DIAGRAM

FIGURE 1-2: PIC16F636 BLOCK DIAGRAM

FIGURE 1-3: PIC16F639 BLOCK DIAGRAM

TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS

TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS

2.0 MEMORY ORGANIZATION

FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS

FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS

TABLE 2-1: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

TABLE 2-3: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

TABLE 2-5: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639

3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

FIGURE 3-5: EXTERNAL RC MODES

FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING

FIGURE 3-7: TWO-SPEED START-UP

FIGURE 3-8: FSCM BLOCK DIAGRAM

FIGURE 3-9: FSCM TIMING DIAGRAM

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

4.0 I/O PORTS

FIGURE 4-1: BLOCK DIAGRAM OF RA0

FIGURE 4-2: BLOCK DIAGRAM OF RA1

FIGURE 4-3: BLOCK DIAGRAM OF RA2

FIGURE 4-4: BLOCK DIAGRAM OF RA3

FIGURE 4-5: BLOCK DIAGRAM OF RA4

FIGURE 4-6: BLOCK DIAGRAM OF RA5

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

FIGURE 4-9: BLOCK DIAGRAM OF RC4

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

5.0 TIMER0 MODULE

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

6.0 TIMER1 MODULE WITH GATE CONTROL

FIGURE 6-1: TIMER1 BLOCK DIAGRAM

FIGURE 6-2: TIMER1 INCREMENTING EDGE

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

7.0 COMPARATOR MODULE

FIGURE 7-1: SINGLE COMPARATOR

FIGURE 7-2: COMPARATOR OUTPUT BLOCK DIAGRAM (PIC12F635)

FIGURE 7-3: COMPARATOR C1 OUTPUT BLOCK DIAGRAM (PIC16F636/639)

FIGURE 7-4: COMPARATOR C2 OUTPUT BLOCK DIAGRAM (PIC16F636/639 )

FIGURE 7-5: ANALOG INPUT MODEL

FIGURE 7-6: COMPARATOR I/O OPERATING MODES (PIC12F635)

FIGURE 7-7: COMPARATOR I/O OPERATING MODES (PIC16F636/639)

FIGURE 7-10: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

8.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE

FIGURE 8-1: PLVD BLOCK DIAGRAM

FIGURE 8-2: PLVD OPERATION

TABLE 8-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT

9.0 DATA EEPROM MEMORY

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

10.0 KEELOQ® COMPATIBLE CRYPTOGRAPHIC MODULE

11.0 ANALOG FRONT-END (AFE) FUNCTIONAL DESCRIPTION (PIC16F639 ONLY)