Datasheet PIC16F631, PIC16F677, PIC16F685, PIC16F687, PIC16F689 Datasheet

...
PIC16F631/677/685/687/689/690
Data Sheet
20-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
© 2008 Microchip Technology Inc. DS41262E
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC
32
logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS41262E-page ii © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
nanoWatt Technology

High-Performance RISC CPU:

• Only 35 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:
- Factory calibrated to ± 1%
- Software selectable frequency range of 8 MHz to 32 kHz
- Software tunable
- Two-Speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for power savings
• Power-Saving Sleep mode
• Wide Operating Voltage Range (2.0V-5.5V)
• Industrial and Extended Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRTE) and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Software Control Option
• Enhanced Low-Current Watchdog Timer (WDT) with On-Chip Oscillator (Software selectable nominal 268 Seconds with Full Prescaler) with Software Enable
• Multiplexed Master Clear/Input Pin
• Programmable Code Protection
• High Endurance Flash/EEPROM Cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
• Enhanced USART Module:
- Supports RS-485, RS-232 and LIN 2.0
- Auto-Baud Detect
- Auto-wake-up on Start bit

Low-Power Features:

Standby Current:
- 50 nA @ 2.0V, typical
• Operating Current:
-11μA @ 32 kHz, 2.0V, typical
-220μA @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
-<1μA @ 2.0V, typical

Peripheral Features:

• 17 I/O Pins and 1 Input-Only Pin:
- High current source/sink for direct LED drive
- Interrupt-on-Change pin
- Individually programmable weak pull-ups
- Ultra Low-Power Wake-up (ULPWU)
• Analog Comparator Module with:
- Two analog comparators
- Programmable on-chip voltage reference
REF) module (% of VDD)
(CV
- Comparator inputs and outputs externally accessible
- SR Latch mode
- Timer 1 Gate Sync Latch
- Fixed 0.6V V
• A/D Converter:
- 10-bit resolution and 12 channels
• Timer0: 8-bit Timer/Counter with 8-bit Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode selected
• Timer2: 8-bit Timer/Counter with 8-bit Period Register, Prescaler and Postscaler
• Enhanced Capture, Compare, PWM+ Module:
- 16-bit Capture, max resolution 12.5 ns
- Compare, max resolution 200 ns
- 10-bit PWM with 1, 2 or 4 output channels,
programmable “dead time”, max frequency 20 kHz
- PWM output steering control
• Synchronous Serial Port (SSP):
- SPI mode (Master and Slave)
2
C™ (Master/Slave modes):
•I
2
C™ address mask
-I
• In-Circuit Serial Programming Pins
REF
TM
(ICSPTM) via Two
© 2008 Microchip Technology Inc. DS41262E-page 1
PIC16F631/677/685/687/689/690
Program
Memory
Device
Flash
(words)
Data Memory
SRAM
EEPROM
(bytes)
(bytes)
I/O
10-bit A/D
(ch)
Comparators
Timers
8/16-bit
SSP ECCP+ EUSART
PIC16F631 1024 64 128 18 2 1/1 No No No PIC16F677 2048 128 256 18 12 2 1/1 Yes No No PIC16F685 4096 256 256 18 12 2 2/1 No Yes No PIC16F687 2048 128 256 18 12 2 1/1 Yes No Yes PIC16F689 4096 256 256 18 12 2 1/1 Yes No Yes PIC16F690 4096 256 256 18 12 2 2/1 Yes Yes Yes

PIC16F631 Pin Diagram

20-pin PDIP, SOIC, SSOP
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G
/OSC2/CLKOUT
RA3/MCLR
RC3/C12IN3-
/VPP RC5
RC4/C2OUT
RC6 RC7 RB7
1 2 3 4 5 6 7 8 9 10
PIC16F631
20 19 18 17
16 15 14 13 12 11
VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C12IN0-/ICSPCLK RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C12IN1­RC2/C12IN2­RB4 RB5 RB6

TABLE 1: PIC16F631 PIN SUMMARY

I/O Pin Analog Comparators Timers Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ IOC Y ICSPDAT
RA1 18 AN1 C12IN0- IOC Y ICSPCLK
RA2 17 C1OUT T0CKI IOC/INT Y
RA3 4 IOC Y
RA4 3 T1G IOC Y OSC2/CLKOUT
RA5 2 T1CKI IOC Y OSC1/CLKIN
RB4 13 IOC Y
RB5 12 IOC Y
RB6 11 IOC Y
RB7 10 IOC Y
RC0 16 AN4 C2IN+
RC1 15 AN5 C12IN1-
RC2 14 AN6 C12IN2-
RC3 7 AN7 C12IN3-
RC4 6 C2OUT
RC55— ————
RC6 8
RC79— ————
1 VDD
20— ———— VSS
Note 1: Pull-up enabled only with external MCLR configuration.
(1)
MCLR/VPP
DS41262E-page 2 © 2008 Microchip Technology Inc.

PIC16F677 Pin Diagram

20-pin PDIP, SOIC, SSOP
PIC16F631/677/685/687/689/690
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR
RC3/AN7C12IN3-
RC7/AN9/SDO
VDD
/VPP RC5
RC4/C2OUT
RC6/AN8/SS
RB7
1 2 3 4 5 6 7 8 9 10
PIC16F677
20 19 18 17
16 15 14 13 12 11
VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/V RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1­RC2/AN6/C12IN2­RB4/AN10/SDI/SDA RB5/AN11 RB6/SCK/SCL
REF/ICSPCLK

TABLE 2: PIC16F677 PIN SUMMARY

I/O Pin Analog Comparators Timers SSP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ IOC Y ICSPDAT
RA1 18 AN1/VREF C12IN0- IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI IOC/INT Y
RA3 4 IOC Y
RA4 3 AN3
T1G
IOC Y OSC2/CLKOUT
RA5 2 T1CKI IOC Y OSC1/CLKIN
RB4 13 AN10 SDI/SDA IOC Y
RB5 12 AN11 IOC Y
RB6 11 SCL/SCK IOC Y
RB7 10 IOC Y
RC0 16 AN4 C2IN+
RC1 15 AN5 C12IN1-
RC2 14 AN6 C12IN2-
RC3 7 AN7 C12IN3-
RC4 6 C2OUT
RC5 5
RC6 8 AN8 SS
RC7 9 AN9 SDO
1 VDD
—20 VSS
Note 1: Pull-up activated only with external MCLR configuration.
(1)
MCLR/VPP
© 2008 Microchip Technology Inc. DS41262E-page 3
PIC16F631/677/685/687/689/690

PIC16F685 Pin Diagram

20-pin PDIP, SOIC, SSOP
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C
VDD
/VPP
RC6/AN8 RC7/AN9
RB7
1 2 3 4 5 6 7 8 9 10
PIC16F685
20
19 18 17
16 15 14 13 12 11
VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/V RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1­RC2/AN6/C12IN2-/P1D RB4/AN10 RB5/AN11 RB6
REF/ICSPCLK

TABLE 3: PIC16F685 PIN SUMMARY

I/O Pin Analog Comparators Timers ECCP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ IOC Y ICSPDAT
RA1 18 AN1/VREF C12IN0- IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI IOC/INT Y
RA3 4 IOC Y
RA4 3 AN3
T1G
IOC Y OSC2/CLKOUT
RA5 2 T1CKI IOC Y OSC1/CLKIN
RB4 13 AN10 IOC Y
RB5 12 AN11 IOC Y
RB6 11 IOC Y
RB7 10 IOC Y
RC0 16 AN4 C2IN+
RC1 15 AN5 C12IN1-
RC2 14 AN6 C12IN2- P1D
RC3 7 AN7 C12IN3- P1C
RC4 6 C2OUT P1B
RC5 5 CCP1/P1A
RC6 8 AN8
RC7 9 AN9
1 VDD
—20 — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
(1)
MCLR/VPP
DS41262E-page 4 © 2008 Microchip Technology Inc.

PIC16F687/689 Pin Diagram

20-pin PDIP, SOIC, SSOP
PIC16F631/677/685/687/689/690
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR
RC3/AN7/C12IN3-
RC7/AN9/SDO
VDD
/VPP RC5
RC4/C2OUT
RC6/AN8/SS
RB7/TX/CK
1 2 3 4 5 6 7 8 9 10
PIC16F687/689
20 19 18 17
16 15 14 13 12 11
VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/V RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1­RC2/AN6/C12IN2­RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL
REF/ICSPCLK

TABLE 4: PIC16F687/689 PIN SUMMARY

I/O Pin Analog Comparators Timers EUSART SSP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ IOC Y ICSPDAT
RA1 18 AN1/VREF C12IN0- IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI IOC/INT Y
RA3 4 IOC Y
RA4 3 AN3
T1G
IOC Y OSC2/CLKOUT
RA5 2 T1CKI IOC Y OSC1/CLKIN
RB4 13 AN10 SDI/SDA IOC Y
RB5 12 AN11 RX/DT IOC Y
RB6 11 SCL/SCK IOC Y
RB7 10 TX/CK IOC Y
RC0 16 AN4 C2IN+
RC1 15 AN5 C12IN1-
RC2 14 AN6 C12IN2-
RC3 7 AN7 C12IN3-
RC4 6 C2OUT
RC5 5
RC6 8 AN8
SS
RC7 9 AN9 SDO
1 VDD
—20 VSS
Note 1: Pull-up activated only with external MCLR configuration.
(1)
MCLR/VPP
© 2008 Microchip Technology Inc. DS41262E-page 5
PIC16F631/677/685/687/689/690

PIC16F690 Pin Diagram (PDIP, SOIC, SSOP)

20-pin PDIP, SOIC, SSOP
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G
/OSC2/CLKOUT
RA3/MCLR RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C
RC7/AN9/SDO
VDD
/VPP
RC6/AN8/SS
RB7/TX/CK
1 2 3 4 5 6 7 8 9 10
PIC16F690
20 19 18 17
16 15 14 13 12 11
VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/V RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1­RC2/AN6/C12IN2-/P1D RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL
REF/ICSPCLK

TABLE 5: PIC16F690 PIN SUMMARY

I/O Pin Analog Comparators Timers ECCP EUSART SSP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ IOC Y ICSPDAT
RA1 18 AN1/V
RA2 17 AN2 C1OUT T0CKI IOC/INT Y
RA3 4 IOC Y
RA4 3 AN3
RA5 2 T1CKI IOC Y OSC1/CLKIN
RB4 13 AN10 SDI/SDA IOC Y
RB5 12 AN11 RX/DT IOC Y
RB6 11 SCL/SCK IOC Y
RB7 10 TX/CK IOC Y
RC0 16 AN4 C2IN+
RC1 15 AN5 C12IN1-
RC2 14 AN6 C12IN2- P1D
RC3 7 AN7 C12IN3- P1C
RC4 6 C2OUT P1B
RC5 5 CCP1/P1A
RC6 8 AN8
RC7 9 AN9 SDO
1 VDD
—20 VSS
Note 1: Pull-up activated only with external MCLR configuration.
REF C12IN0- IOC Y ICSPCLK
T1G
(1)
IOC Y OSC2/CLKOUT
SS
MCLR/VPP
DS41262E-page 6 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690

PIC16F631/677/685/687/689/690 Pin Diagram (QFN)

20-pin QFN
DD
RA5/T1CKI/OSC1/CLKIN
V
VSS
19
18
17
7
8
9
RA3/MCLR/VPP
RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C
RC6/AN8/SS
RA4/AN3/T1G/OSC2/CLKOUT
20
1
(1)
(1)
(1)
(2)
2
PIC16F631/677/
3
685/687/689/690
4
5
6
10
RA0/AN0/C1IN+/ICSPDAT/ULPWU
16
15
14
13
12
11
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-/P1D
(1)
(2)
(3)
(2)
(3)
(2)
RB7/TX/CK
RC7/AN9/SDO
Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only.
, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
2: SS
3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F690 only.
RB6/SCK/SCL
RB5/AN11/RX/DT
RB4/AN10/SDI/SDA
© 2008 Microchip Technology Inc. DS41262E-page 7
PIC16F631/677/685/687/689/690
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Memory Organization ................................................................................................................................................................. 25
3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 47
4.0 I/O Ports ..................................................................................................................................................................................... 59
5.0 Timer0 Module ........................................................................................................................................................................... 81
6.0 Timer1 Module with Gate Control............................................................................................................................................... 84
7.0 Timer2 Module ........................................................................................................................................................................... 91
8.0 Comparator Module.................................................................................................................................................................... 93
9.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 107
10.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 119
11.0 Enhanced Capture/Compare/PWM Module ............................................................................................................................. 127
12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 151
13.0 SSP Module Overview ............................................................................................................................................................. 179
14.0 Special Features of the CPU.................................................................................................................................................... 197
15.0 Instruction Set Summary.......................................................................................................................................................... 217
16.0 Development Support............................................................................................................................................................... 227
17.0 Electrical Specifications............................................................................................................................................................ 231
18.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 259
19.0 Packaging Information.............................................................................................................................................................. 287
Appendix A: Data Sheet Revision History .......................................................................................................................................... 293
Appendix B: Migrating from other PIC
®
Devices................................................................................................................................ 293
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DS41262E-page 8 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690

1.0 DEVICE OVERVIEW

The PIC16F631/677/685/687/689/690 devices are covered by this data sheet. They are available in 20-pin PDIP, SOIC, TSSOP and QFN packages.

FIGURE 1-1: PIC16F631 BLOCK DIAGRAM

INT
Program
Bus
Configuration
Flash
1K x 14
Program
Memory
14
Instruction Reg
13
Program Counter
8-Level Stack (13-bit)
Direct Addr
7
Block Diagrams and pinout descriptions of the devices are as follows:
• PIC16F631 (Figure 1-1, Table 1-1)
• PIC16F677 (Figure 1-2, Table 1-2)
• PIC16F685 (Figure 1-3, Table 1-3)
• PIC16F687/PIC16F689 (Figure 1-4, Table 1-4)
• PIC16F690 (Figure 1-5, Table 1-5)
Data Bus
RAM
64 bytes
File
Registers
Addr MUX
8
FSR Reg
RAM Addr
9
Indirect
Addr
8
PORTA
RA0 RA1 RA2 RA3 RA4 RA5
PORTB
RB4 RB5 RB6
RB7
OSC1/CLKI
OSC2/CLKO
Internal
Oscillator
Block
Ultra Low-Power
Instruction
Decode and
Generation
ULPWU
Wake-up
Control
Timing
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
MCLR
Timer0 Timer1
VSS
T1G T1CKIT0CKI
STATUS Reg
PORTC
3
8
ALU
W Reg
MUX
EEDAT
128 Bytes
Data
EEPROM
EEADR
C1IN- C1IN+ C1OUT
Analog Comparators
and Reference
8
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
C2IN- C2IN+ C2OUT
2
© 2008 Microchip Technology Inc. DS41262E-page 9
PIC16F631/677/685/687/689/690

FIGURE 1-2: PIC16F677 BLOCK DIAGRAM

INT
Program
OSC1/CLKI
OSC2/CLKO
Internal
Oscillator
Block
Configuration
Program
14
Bus
Instruction Reg
Instruction
Decode and
Generation
ULPWU
Flash
2K x 14
Memory
Control
Timing
13
Program Counter
8-Level Stack (13-bit)
Direct Addr
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
MCLR
VSS
RAM Addr
9
Indirect
Addr
8
Data Bus
RAM
128 bytes
File
Registers
Addr MUX
7
3
8
T1G T1CKIT0CKI
8
FSR Reg
STATUS Reg
MUX
ALU
W Reg
PORTA
PORTB
PORTC
SDO
RA0 RA1
RA2 RA3 RA4 RA5
SDI/ SCK/
SDA SCL
RB4 RB5 RB6 RB7
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
SS
Ultra Low-Power
Wake-up
AN8 AN9 AN10 AN11
Analog-to-Digital Converter
VREF
AN0 AN1 AN2 AN3 AN4 AN5 AN6
Timer0 Ti mer1
Analog Comparators
AN7
C1IN- C1IN+ C1OUT
2
and Reference
C2IN- C2IN+ C2OUT
8
Synchronous
Serial Port
EEDAT
256 Bytes
Data
EEPROM
EEADR
DS41262E-page 10 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690

FIGURE 1-3: PIC16F685 BLOCK DIAGRAM

INT
Program
Bus
Configuration
Flash
4K x 14
Program
Memory
14
Instruction Reg
13
Program Counter
8-Level Stack (13-bit)
Direct Addr
8
Data Bus
RAM
256 bytes
File
Registers
RAM Addr
9
Addr MUX
7
Indirect
8
FSR Reg
Addr
PORTA
RA0 RA1 RA2 RA3 RA4 RA5
PORTB
RB4 RB5 RB6
RB7
Instruction
Decode and
Control
OSC1/CLKI
OSC2/CLKO
Internal
Oscillator
Block
Ultra Low-Power
AN8 AN9 AN10 AN11
Generation
ULPWU
Wake-up
Timi ng
Analog-to-Digital Converter
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
MCLR
Timer0 Timer1
VSS
T1G
STATUS Reg
3
ALU
8
W Reg
T1CKIT0CKI
2
Analog Comparators
and Reference
MUX
Timer2
PORTC
8
CCP1/
EEDAT
256 Bytes
Data
EEPROM
EEADR
RC0 RC1
RC2 RC3 RC4 RC5 RC6 RC7
P1B P1C P1DP1A
ECCP+
VREF
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN7
C1IN- C1IN+ C1OUT
C2IN- C2IN+ C2OUT
© 2008 Microchip Technology Inc. DS41262E-page 11
PIC16F631/677/685/687/689/690

FIGURE 1-4: PIC16F687/PIC16F689 BLOCK DIAGRAM

INT
Program
Bus
OSC1/CLKI
OSC2/CLKO
Internal
Oscillator
Block
Configuration
Flash
(1)
2K
/4K x 14
Program
Memory
14
Instruction Reg
Instruction
Decode and
Control
Timing
Generation
ULPWU
13
Program Counter
8-Level Stack (13-bit)
Direct Addr
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
MCLR
VSS
RAM Addr
Indirect
Addr
RX/DT
8
Data Bus
RAM
(1)
/256 bytes
128
File
Registers
9
Addr MUX
7
3
8
T1G T1CKIT0CKI
8
FSR Reg
STATUS Reg
MUX
ALU
W Reg
TX/CK
PORTA
PORTB
PORTC
RA0 RA1
RA2 RA3 RA4 RA5
SDO
RB4 RB5 RB6
RB7
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
SDI/ SCK/
SDA SCL
SS
Ultra Low-Power
Wake-up
AN8 AN9 AN10 AN11
Analog-to-Digital Converter
VREF
AN0 AN1 AN2 AN3 AN4 AN5 AN6
Note 1: PIC16F687 only.
Timer0 Ti mer1
Analog Comparators
AN7
C1IN- C1IN+ C1OUT
2
and Reference
C2IN- C2IN+ C2OUT
EUSART
8
EEDAT
256 Bytes
Data
EEPROM
EEADR
Synchronous
Serial Port
DS41262E-page 12 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690

FIGURE 1-5: PIC16F690 BLOCK DIAGRAM

INT
Program
OSC1/CLKI
OSC2/CLKO
Internal
Oscillator
Block
ULPWU
Configuration
14
Bus
Instruction Reg
Instruction
Decode and
Generation
Flash
4k x 14
Program
Memory
Control
Timi ng
T0CKI
13
Program Counter
8-Level Stack (13-bit)
Direct Addr
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
MCLR
T1G T1CKI
7
3
8
VSS
Data Bus
RAM
256 bytes
File
Registers
Addr MUX
8
FSR Reg
STATUS Reg
MUX
ALU
W Reg
TX/CK RX/DT
RAM Addr
9
Indirect
Addr
8
PORTA
RA0 RA1 RA2 RA3 RA4 RA5
PORTB
RB4 RB5 RB6 RB7
PORTC
CCP1/
P1A
P1B P1C P1D
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
SDO
SDI/ SCK/ SDA SCL
SS
Ultra Low-Power
Wake-up
AN8 AN9 AN10 AN11
Timer0
Analog-to-Digital Converter
VREF
AN0 AN1 AN2 AN3 AN4 AN5 AN6
Timer1
AN7
C1IN- C1IN+ C1OUT
Timer2
2
Analog Comparators
and Reference
C2IN- C2IN+ C2OUT
EUSART
8
ECCP+
EEDAT
256 Bytes
Data
EEPROM
EEADR
Synchronous
Serial Port
© 2008 Microchip Technology Inc. DS41262E-page 13
PIC16F631/677/685/687/689/690
TABLE 1-1: PINOUT DESCRIPTION – PIC16F631
Input
Name Function
RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
C1IN+ AN Comparator C1 non-inverting input.
ICSPDAT ST CMOS ICSP™ Data I/O.
ULPWU AN Ultra Low-Power Wake-up input.
RA1/C12IN0-/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
C12IN0- AN Comparator C1 or C2 inverting input.
ICSPCLK ST ICSP™ clock.
RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.
T0CKI ST Timer0 clock input.
INT ST External interrupt pin.
C1OUT CMOS Comparator C1 output.
RA3/MCLR
RA4/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB4 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB5 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB6 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/C2IN+ RC0 ST CMOS General purpose I/O.
RC1/C12IN1- RC1 ST CMOS General purpose I/O.
RC2/C12IN2- RC2 ST CMOS General purpose I/O.
RC3/C12IN3- RC3 ST CMOS General purpose I/O.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
RC5 RC5 ST CMOS General purpose I/O.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
/VPP RA3 TTL General purpose input. Individually controlled interrupt-on-
MCLR
PP HV Programming voltage.
V
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
T1G
OSC2 XTAL Crystal/Resonator.
CLKOUT CMOS F
T1CKI ST Timer1 clock input.
OSC1 XTAL Crystal/Resonator.
CLKIN ST External clock input/RC oscillator connection.
C2IN+ AN Comparator C2 non-inverting input.
C12IN1- AN Comparator C1 or C2 inverting input.
C12IN2- AN Comparator C1 or C2 inverting input.
C12IN3- AN Comparator C1 or C2 inverting input.
C2OUT CMOS Comparator C2 output.
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
Output
Typ e
Typ e
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
change.
ST Master Clear with internal pull-up.
Individually enabled pull-up.
ST Timer1 gate input.
OSC/4 output.
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
Description
DS41262E-page 14 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 (CONTINUED)
Input
Name Function
RC6 RC6 ST CMOS General purpose I/O.
RC7 RC7 ST CMOS General purpose I/O.
SS VSS Power Ground reference.
V
DD VDD Power Positive supply.
V
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
Typ e
Output
Typ e
Description
© 2008 Microchip Technology Inc. DS41262E-page 15
PIC16F631/677/685/687/689/690
TABLE 1-2: PINOUT DESCRIPTION – PIC16F677
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/ ULPWU
RA1/AN1/C12IN0-/V ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB5/AN11 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
/VPP RA3 TTL General purpose input. Individually controlled interrupt-on-
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
REF/
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN0 AN A/D Channel 0 input.
C1IN+ AN Comparator C1 non-inverting input.
ICSPDAT ST CMOS ICSP™ Data I/O.
ULPWU AN Ultra Low-Power Wake-up input.
RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN1 AN A/D Channel 1 input.
C12IN0- AN Comparator C1 or C2 inverting input.
REF AN External Voltage Reference for A/D.
V
ICSPCLK ST ICSP™ clock.
AN2 AN A/D Channel 2 input.
T0CKI ST Timer0 clock input.
INT ST External interrupt pin.
C1OUT CMOS Comparator C1 output.
MCLR
PP HV Programming voltage.
V
AN3 AN A/D Channel 3 input.
T1G
OSC2 XTAL Crystal/Resonator.
CLKOUT CMOS F
T1CKI ST Timer1 clock input.
OSC1 XTAL Crystal/Resonator.
CLKIN ST External clock input/RC oscillator connection.
AN10 AN A/D Channel 10 input.
SDI ST SPI data input.
SDA ST OD I
AN11 AN A/D Channel 11 input.
SCK ST CMOS SPI clock.
SCL ST OD I
Output
Typ e
Typ e
Individually enabled pull-up.
Individually enabled pull-up.
Individually enabled pull-up.
change.
ST Master Clear with internal pull-up.
Individually enabled pull-up.
ST Timer1 gate input.
OSC/4 output.
Individually enabled pull-up.
Individually enabled pull-up.
2
C™ data input/output.
Individually enabled pull-up.
Individually enabled pull-up.
2
C™ clock.
Description
DS41262E-page 16 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 (CONTINUED)
Input
Name Function
RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN A/D Channel 4 input.
C2IN+ AN Comparator C2 non-inverting input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN A/D Channel 5 input.
C12IN1- AN Comparator C1 or C2 inverting input.
RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O.
AN6 AN A/D Channel 6 input.
C12IN2- AN Comparator C1 or C2 inverting input.
RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O.
AN7 AN A/D Channel 7 input.
C12IN3- AN Comparator C1 or C2 inverting input.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
C2OUT CMOS Comparator C2 output.
RC5 RC5 ST CMOS General purpose I/O.
RC6/AN8/SS
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
SS VSS Power Ground reference.
V
DD VDD Power Positive supply.
V
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
RC6 ST CMOS General purpose I/O.
AN8 AN A/D Channel 8 input.
SS
AN9 AN A/D Channel 9 input.
SDO CMOS SPI data output.
Output
Typ e
Typ e
Individually enabled pull-up.
ST Slave Select input.
Description
© 2008 Microchip Technology Inc. DS41262E-page 17
PIC16F631/677/685/687/689/690
TABLE 1-3: PINOUT DESCRIPTION – PIC16F685
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/ ULPWU
RA1/AN1/C12IN0-/V
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB4/AN10 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB5/AN11 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB6 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
/VPP RA3 TTL General purpose input. Individually controlled interrupt-on-
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
AN0 AN A/D Channel 0 input.
C1IN+ AN Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN Ultra Low-Power Wake-up input.
AN1 AN A/D Channel 1 input.
C12IN0- AN Comparator C1 or C2 negative input.
REF AN External Voltage Reference for A/D.
V
ICSPCLK ST ICSP™ clock.
AN2 AN A/D Channel 2 input.
T0CKI ST Timer0 clock input.
INT ST
C1OUT CMOS Comparator C1 output.
MCLR
PP HV Programming voltage.
V
AN3 AN A/D Channel 3 input.
T1G
OSC2 XTAL Crystal/Resonator.
CLKOUT CMOS F
T1CKI ST Timer1 clock input.
OSC1 XTAL Crystal/Resonator.
CLKIN ST External clock input/RC oscillator connection.
AN10 AN A/D Channel 10 input.
AN11 AN A/D Channel 11 input.
AN4 AN A/D Channel 4 input.
C2IN+ AN Comparator C2 positive input.
Type
Output
Type
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
Description
External interrupt pin.
change.
ST Master Clear with internal pull-up.
change. Individually enabled pull-up.
ST Timer1 gate input.
OSC/4 output.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
DS41262E-page 18 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 (CONTINUED)
Input
Name Function
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN A/D Channel 5 input.
C12IN1- AN Comparator C1 or C2 negative input.
RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O.
AN6 AN A/D Channel 6 input.
C12IN2- AN Comparator C1 or C2 negative input.
P1D CMOS PWM output.
RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O.
AN7 AN A/D Channel 7 input.
C12IN3- AN Comparator C1 or C2 negative input.
P1C CMOS PWM output.
RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O.
C2OUT CMOS Comparator C2 output.
P1B CMOS PWM output.
RC5/CCP1/P1A RC5 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare input.
P1A ST CMOS PWM output.
RC6/AN8 RC6 ST CMOS General purpose I/O.
AN8 AN A/D Channel 8 input.
RC7/AN9 RC7 ST CMOS General purpose I/O.
AN9 AN A/D Channel 9 input.
SS VSS Power Ground reference.
V
V
DD VDD Power Positive supply.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
Type
Output
Type
Description
© 2008 Microchip Technology Inc. DS41262E-page 19
PIC16F631/677/685/687/689/690
TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/ ULPWU
RA1/AN1/C12IN0-/V
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
/VPP RA3 TTL General purpose input. Individually controlled
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
AN0 AN A/D Channel 0 input.
C1IN+ AN Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN Ultra Low-Power Wake-up input.
AN1 AN A/D Channel 1 input.
C12IN0- AN Comparator C1 or C2 negative input.
REF AN External Voltage Reference for A/D.
V
ICSPCLK ST ICSP™ clock.
AN2 AN A/D Channel 2 input.
T0CKI ST Timer0 clock input.
INT ST External Interrupt.
C1OUT CMOS Comparator C1 output.
MCLR
PP HV Programming voltage.
V
AN3 AN A/D Channel 3 input.
T1G
OSC2 XTAL Crystal/Resonator.
CLKOUT CMOS F
T1CKI ST Timer1 clock input.
OSC1 XTAL Crystal/Resonator.
CLKIN ST External clock input/RC oscillator connection.
AN10 AN A/D Channel 10 input.
SDI ST SPI data input.
SDA ST OD I
AN11 AN A/D Channel 11 input.
RX ST EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
Output
Type
Type
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
interrupt-on-change.
ST Master Clear with internal pull-up.
change. Individually enabled pull-up.
ST Timer1 gate input.
OSC/4 output.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
2
C™ data input/output.
change. Individually enabled pull-up.
Description
DS41262E-page 20 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 (CONTINUED)
Input
Name Function
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
SCK ST CMOS SPI clock.
SCL ST OD I
RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
TX CMOS EUSART asynchronous output.
CK ST CMOS EUSART synchronous clock.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN A/D Channel 4 input.
C2IN+ AN Comparator C2 positive input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN A/D Channel 5 input.
C12IN1- AN Comparator C1 or C2 negative input.
RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O.
AN6 AN A/D Channel 6 input.
C12IN2- AN Comparator C1 or C2 negative input.
RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O.
AN7 AN A/D Channel 7 input.
C12IN3- AN Comparator C1 or C2 negative input.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
C2OUT CMOS Comparator C2 output.
RC5 RC5 ST CMOS General purpose I/O.
RC6/AN8/SS
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
SS VSS Power Ground reference.
V
DD VDD Power Positive supply.
V
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
RC6 ST CMOS General purpose I/O.
AN8 AN A/D Channel 8 input.
SS
AN9 AN A/D Channel 9 input.
SDO CMOS SPI data output.
Output
Type
Type
change. Individually enabled pull-up.
2
C™ clock.
change. Individually enabled pull-up.
ST Slave Select input.
Description
© 2008 Microchip Technology Inc. DS41262E-page 21
PIC16F631/677/685/687/689/690
TABLE 1-5: PINOUT DESCRIPTION – PIC16F690
Input
Name Function
RA0/AN0/C1IN+/ICSPDAT/ ULPWU
RA1/AN1/C12IN0-/V
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
RA3/MCLR
RA4/AN3/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
/VPP RA3 TTL General purpose input. Individually controlled interrupt-on-
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
AN0 AN A/D Channel 0 input.
C1IN+ AN Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN Ultra Low-Power Wake-up input.
AN1 AN A/D Channel 1 input.
C12IN0- AN Comparator C1 or C2 negative input.
REF AN External Voltage Reference for A/D.
V
ICSPCLK ST ICSP™ clock.
AN2 AN A/D Channel 2 input.
T0CKI ST Timer0 clock input.
INT ST External interrupt.
C1OUT CMOS Comparator C1 output.
MCLR
PP HV Programming voltage.
V
AN3 AN A/D Channel 3 input.
T1G
OSC2 XTAL Crystal/Resonator.
CLKOUT CMOS F
T1CKI ST Timer1 clock input.
OSC1 XTAL Crystal/Resonator.
CLKIN ST External clock input/RC oscillator connection.
AN10 AN A/D Channel 10 input.
SDI ST SPI data input.
SDA ST OD I
AN11 AN A/D Channel 11 input.
RX ST EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
Output
Type
Type
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
change.
ST Master Clear with internal pull-up.
change. Individually enabled pull-up.
ST Timer1 gate input.
OSC/4 output.
change. Individually enabled pull-up.
change. Individually enabled pull-up.
2
C™ data input/output.
change. Individually enabled pull-up.
Description
DS41262E-page 22 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 (CONTINUED)
Input
Name Function
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
SCK ST CMOS SPI clock.
SCL ST OD I
RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
TX CMOS EUSART asynchronous output.
CK ST CMOS EUSART synchronous clock.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN A/D Channel 4 input.
C2IN+ AN Comparator C2 positive input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN A/D Channel 5 input.
C12IN1- AN Comparator C1 or C2 negative input.
RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O.
AN6 AN A/D Channel 6 input.
C12IN2- AN Comparator C1 or C2 negative input.
P1D CMOS PWM output.
RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O.
AN7 AN A/D Channel 7 input.
C12IN3- AN Comparator C1 or C2 negative input.
P1C CMOS PWM output.
RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O.
C2OUT CMOS Comparator C2 output.
P1B CMOS PWM output.
RC5/CCP1/P1A RC5 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare input.
P1A ST CMOS PWM output.
RC6/AN8/SS
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
SS VSS Power Ground reference.
V
DD VDD Power Positive supply.
V
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
RC6 ST CMOS General purpose I/O.
AN8 AN A/D Channel 8 input.
SS
AN9 AN A/D Channel 9 input.
SDO CMOS SPI data output.
Output
Type
Type
change. Individually enabled pull-up.
2
C™ clock.
change. Individually enabled pull-up.
ST Slave Select input.
Description
© 2008 Microchip Technology Inc. DS41262E-page 23
PIC16F631/677/685/687/689/690
NOTES:
DS41262E-page 24 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F631/677/685/687/689/690 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) is physically implemented for the PIC16F631, the first 2K x 14 (0000h-07FFh) for the PIC16F677/PIC16F687, and the first 4K x 14 (0000h-0FFFh) for the PIC16F685/PIC16F689/ PIC16F690. Accessing a location above these boundaries will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1 through 2-3).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE PIC16F631
PC<12:0>
CALL, RETURN RETFIE, RETLW
Stack Level 1
Stack Level 2
13
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE PIC16F685/689/690
PC<12:0>
CALL, RETURN RETFIE, RETLW
On-Chip
Program
Memory
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
Interrupt Vector
Access 0-FFFh
Page 0
Page 1
13
0000h
0004h
0005h
07FFh 0800h
0FFFh 1000h
1FFFh
On-Chip
Memory
Stack Level 8
Reset Vector
Interrupt Vector
Page 0
Access 0-3FFh
0000h
0004h
0005h
03FFh 0400h
1FFFh
FIGURE 2-3: PROGRAM MEMORY MAP
AND STACK FOR THE PIC16F677/PIC16F687
PC<12:0>
CALL, RETURN RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
Interrupt Vector
On-Chip
Memory
Access 0-7FFh
Page 0
13
0000h
0004h
0005h
07FFh 0800h
1FFFh
© 2008 Microchip Technology Inc. DS41262E-page 25
PIC16F631/677/685/687/689/690

2.2 Data Memory Organization

The data memory (see Figures 2-6 through 2-8) is partitioned into four banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. The General Purpose Registers, implemented as static RAM, are located in the last 96 locations of each Bank. Register locations F0h-FFh in Bank 1, 170h-17Fh in Bank 2 and 1F0h-1FFh in Bank 3 point to addresses 70h-7Fh in Bank 0. The actual number of General Purpose Resisters (GPR) in each Bank depends on the device. Details are shown in Figures 2-4 through 2-8. All other RAM is unimplemented and returns ‘0’ when read. RP<1:0> of the STATUS register are the bank select bits:
RP1
RP0
00 Bank 0 is selected 01 Bank 1 is selected 10 Bank 2 is selected 11 Bank 3 is selected

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file is organized as 128 x 8 in the PIC16F687 and 256 x 8 in the PIC16F685/PIC16F689/PIC16F690. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tables 2-1 through 2-4). These registers are static RAM.
The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Registers related to the operation of peripheral features are described in the section of that peripheral feature.
DS41262E-page 26 © 2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
FIGURE 2-4: PIC16F631 SPECIAL FUNCTION REGISTERS
File File File File Address Address Address Address
Indirect addr.
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2
TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h
(1)
00h Indirect addr.
08h 88h 108h 188h 09h 89h 109h 189h
11h 91h 111h 191h 12h 92h 112h 192h 13h 93h 113h 193h 14h 94h 114h 194h 15h WPUA 95h WPUB 115h 195h 16h IOCA 96h IOCB 116h 196h 17h WDTCON 97h 117h 197h 18h 98h VRCON 118h 198h 19h 99h CM1CON0 119h 199h 1Ah 9Ah CM2CON0 11Ah 19Ah 1Bh 9Bh CM2CON1 11Bh 19Bh 1Ch 9Ch 11Ch 19Ch 1Dh 9Dh 11Dh 19Dh 1Eh 9Eh ANSEL 11Eh SRCON 19Eh 1Fh 9Fh 11 Fh 19Fh 20h
(1)
80h Indirect addr.
A0h 120h 1A0h
(1)
100h Indirect addr.
110h 190h
(1)
(1)
180h
18Dh
3Fh
General
Purpose
Registers
64 Bytes
Bank 0Bank 1Bank 2Bank 3
Note 1: Not a physical register.
© 2008 Microchip Technology Inc. DS41262E-page 27
40h
6Fh EFh 16Fh 1EFh 70h accesses 7Fh FFh 17Fh 1FFh
Unimplemented data memory locations, read as ‘0’.
70h-7Fh
F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
PIC16F631/677/685/687/689/690
FIGURE 2-5: PIC16F677 SPECIAL FUNCTION REGISTERS
File File File File Address Address Address Address
Indirect addr.
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h
SSPBUF 13h SSPADD
SSPCON 14h SSPSTAT 94h 114h 194h
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh
General Purpose Register
(1)
00h Indirect addr.
08h 88h 108h 188h 09h 89h 109h 189h
11h 91h 111h 191h 12h 92h 112h 192h
15h WPUA 95h WPUB 115h 195h 16h IOCA 96h IOCB 116h 196h 17h WDTCON 97h 117h 197h 18h 98h VRCON 118h 198h 19h 99h CM1CON0 119h 199h 1Ah 9Ah CM2CON0 11Ah 19Ah 1Bh 9Bh CM2CON1 11Bh 19Bh 1Ch 9Ch 11Ch 19Ch 1Dh 9Dh 11Dh 19Dh
20h General
Purpose Register
32 Bytes
(1)
80h Indirect addr.
(2)
93h 113h 193h
A0h
BFh C0h
(1)
100h Indirect addr.
110h 190h
120h 1A0h
(1)
(1)
180h
18Dh
19Fh
96 Bytes
accesses
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.
See Registers 13-2 and 13-3 for more details.
DS41262E-page 28 © 2008 Microchip Technology Inc.
70h-7Fh
EFh 16Fh 1EFh F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
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