PIC16F630/676
Memory Programming Specification
This document includes the
programming specifications for the
following devices:
• PIC16F630
• PIC16F676
1.0 PROGRAMMING THE PIC16F630/676
The PIC16F630/676 is programmed using a serial
method. The Serial mode will allow the PIC16F630/676
to be programmed while in the user’s system. This
allows for increased design flexibility. This
programming specification applies to PIC16F630/676
devices in all packages.
FIGURE 1-1: 14-PIN DIAGRAM FOR PIC16F630
PDIP, SOIC, TSSOP
RA5/T1CKI/OSC1/CLKIN
RA4/T1G
/OSC1/CLKOUT
RA3/MCLR
V
/VPP
RC5
RC4
RC3
DD
1
PIC16F630
2
3
4
5
6
7
14
13
12
11
10
9
8
1.1 Hardware Requirements
The PIC16F630/676 requires one power supply for
DD (5.0V) and one for VPP (12V).
V
1.2 Programming Mode
The Programming mode for the PIC16F630/676 allows
programming of user program memory, data memory,
special locations used for ID, and the configuration
word.
V
SS
RA0/CIN+/ICSPDAT
RA1/CIN-/ICSPCLK
RA2/COUT/T0CKI/INT
RC0
RC1
RC2
FIGURE 1-2: 14-PIN DIAGRAM FOR PIC16F676
PDIP, SOIC, TSSOP
RA5/T1CKI/OSC1/CLKIN
RA4/T1G
/OSC2/AN3/CLKOUT
RA3/MCLR
2003 Microchip Technology Inc. Preliminary DS41191B-page 1
VDD
/VPP
RC5
RC4
RC3/AN7
1
PIC16F676
2
3
4
5
6
7
14
13
12
11
10
9
8
V
SS
RA0/AN0/CIN+/ICSPDAT
RA1/AN1/CIN-/VREF/ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RC0/AN4
RC1/AN5
RC2/AN6
PIC16F630/676
TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F630/676
Pin Name
RA1 CLOCK I Clock input – Schmitt Trigger input
RA0 DATA I/O Data input/output – TTL input
MCLR
DD VDD P Power Supply
V
SS VSS P Ground
V
Legend: I = Input, O = Output, P = Power
Note 1: In the PIC16F630/676, the programming high voltage is internally generated. To activate the Programming
mode, high voltage needs to be applied to MCLR
means that MCLR
Function Pin Type Pin Description
Programming mode P
does not draw any significant current.
During Programming
(1)
Program Mode Select
input. Since the MCLR is used for a level source, this
DS41191B-page 2 Preliminary 2003 Microchip Technology Inc.
PIC16F630/676
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF. In Programming mode, the program memory
space extends from 0x0000 to 0x3FFF, with the first
half (0x0000-0x1FFF) being user program memory and
the second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to 0x1FFF
and wrap to 0x000, 0x2000 to 0x3FFF and wrap
around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a ‘1’, thus
always pointing to the configuration memory. The only
way to point to user program memory is to RESET the
part and re-enter Program/Verify mode as described in
Section 2.3.
In the configuration memory space, 0x2000-0x201F
are physically implemented. However, only locations
0x2000 through 0x2003, and 0x2007 are available.
Other locations are reserved.
FIGURE 2-1: PROGRAM MEMORY MAPPING
03FF
OSCCAL
2.2 ID Locations
A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000:
0x2003]. It is recommended that the user use only the
seven Least Significant bits (LSb) of each ID location.
The ID locations read out normally, even after code
protection is enabled. It is recommended that ID
location is written as “xx xxxx xbbb bbbb” where
‘bbb bbbb’ is ID information.
The 14 bits may be programmed, but only the LSb’s are
displayed by MPLAB
as they won’t be read by MPLAB
1 KW
03FE
03FF
400
Implemented
Implemented
®
IDE. xxxx’s are “don’t care” bits
®
IDE.
2000
ID Location
2001
ID Location
2002
ID Location
2003
ID Location
2004
Reserved
2005
Reserved
2006
Reserved
2007
Configuration Word
1FFF
2000
2008
201F
3FFF
Maps to
0 - 3FF
Implemented
Reserved
Maps to
2000 - 201F
2003 Microchip Technology Inc. Preliminary DS41191B-page 3
PIC16F630/676
2.3 Program/Verify Mode
The Program/Verify mode is entered by holding pins
clock and data low while raising MCLR
IHH (high voltage). Apply VDD and data. Once in this
V
mode, the user program memory, data memory and the
configuration memory can be accessed and
programmed in serial fashion. Clock is Schmitt Trigger
and data is TTL input in this mode. RA4 is tristate,
regardless of fuse setting.
The sequence that enters the device into the Programming/Verify mode places all other logic into the RESET
state (the MCLR
that all I/O are in the RESET state (hi-impedance
inputs).
pin was initially at VIL). This means
FIGURE 2-2: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
TPPDP
VPP
VDD
DATA
CLOCK
SDATA = Input
The normal sequence for programming is to use the
Load Data command to set a value to be written at the
selected address. Issue the Begin Programming
command followed by Read Data command to verify
and then increment the address.
THLD0
pin from VIL to
A device RESET will clear the PC and set the address
to ‘0’. The Increment Address command will increment
the PC. The Load Configuration command will set the
PC to 0x2000. The available commands are shown in
Ta bl e 2 -1 .
2.3.1 SERIAL PROGRAM/VERIFY
OPERATION
The clock pin is used as a clock input pin and the data
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (CLOCK) is cycled six times. Each command
bit is latched on the falling edge of the clock with the
LSb of the command being input first. The data on pin
DATA is required to have a minimum setup and hold
time (see AC/DC specifications), with respect to the
falling edge of the clock. Commands that have data
associated with them (read and load) are specified to
have a minimum delay of 1 µs between the command
and the data. After this delay, the clock pin is cycled 16
times with the first cycle being a START bit and the last
cycle being a STOP bit. Data is also input and output
LSb first.
Therefore, during a read operation, the LSb will be
transmitted onto pin DATA on the rising edge of the
second cycle and, during a load operation, the LSb will
be latched on the falling edge of the second cycle. A
minimum 1 µs delay is also specified between
consecutive commands.
All commands are transmitted LSb first. Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1 µs is required between a command and a data word
(or another command).
The commands that are available are described below
in Table 2-1.
TABLE 2-1: COMMAND MAPPING FOR PIC16F630/676
Command Mapping (MSb … LSb) Data
Load Configuration xx00000, data (14), 0
Load Data For Program Memory xx00100, data (14), 0
Load Data For Data Memory xx00110, data (8), zero (6),
0
Read Data From Program Memory xx01000, data (14), 0
Read Data From Data Memory xx01010, data (8), zero (6),
0
Increment Address xx0110
BEGIN PROGRAMMING 001000Internally Timed
BEGIN PROGRAMMING 011000Externally Timed
END PROGRAMMING 001010
BULK ERASE PROGRAM MEMORY XX1001Internally Timed
BULK ERASE DATA MEMORY XX1011Internally Timed
DS41191B-page 4 Preliminary 2003 Microchip Technology Inc.
2.3.1.1 LOAD CONFIGURATION
After receiving this command, the program counter
(PC) will be set to 0x2000. Then, by applying 16 cycles
to the clock pin, the chip will load 14 bits in a “data
word,” as described above, which will be programmed
into the configuration memory. A description of the
memory mapping schemes of the program memory for
normal operation and Configuration mode operation is
shown in Figure 2-3. After the configuration memory is
entered, the only way to get back to the user program
memory is to exit the Program/Verify mode by taking
low (VIL).
MCLR
FIGURE 2-3: LOAD CONFIGURATION COMMAND
PIC16F630/676
12 3 4 5 15
Tdly2
strt_bit
LSb
Ts et 1
RA1
CLOCK
RA0
DATA
12 3 4 56
0
000
0
X
X
Tdly1
2.3.1.2 LOAD DATA FOR PROGRAM
MEMORY
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the Load
Data command is shown in Figure 2-4.
FIGURE 2-4: LOAD DATA FOR PROGRAM MEMORY COMMAND
12 3 4 5 15
Tdly2
strt_bit
LSb MSb
Ts et 1
RA1
CLOCK
RA0
DATA
12 3 4 56
0
1
Ts et 1
Thld1
0
0
X
X
Tdly1
Thld1
Thld1
MSb
16
stp_bit
16
stp_bit
2003 Microchip Technology Inc. Preliminary DS41191B-page 5
PIC16F630/676
2.3.1.3 LOAD DATA FOR DATA MEMORY
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied.
However, the data memory is only 8-bits wide and thus,
only the first 8 bits of data after the START bit will be
programmed into the data memory. It is still necessary
to cycle the clock the full 16 cycles in order to allow the
internal circuitry to RESET properly. The data memory
contains 128 bytes. Only the lower 8 bits of the PC are
decoded by the data memory, and therefore, if the PC
is greater than 0x7F, it will wrap around and address a
location within the physically implemented memory.
FIGURE 2-5: LOAD DATA FOR DATA MEMORY COMMAND
Tdly2
RA1
CLOCK
RA0
DATA
12 3 4 56
1
1
0
0
input
X
X
12 3 4 5 15
Tdly3
strt_bit
Tdly1
LSb
2.3.1.4 READ DATA FROM PROGRAM
MEMORY
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (hi-impedance) after the
16th rising edge.
If the program memory is code protected (CP
= 0), the
data is read as zeros.
FIGURE 2-6: READ DATA FROM PROGRAM MEMORY COMMAND
output
MSb
16
stp_bit
input
Tdly2
RA1
CLOCK
RA0
DATA
DS41191B-page 6 Preliminary 2003 Microchip Technology Inc.
12 3 4 56
0
1
0
Ts et 1
0
1
Thld1
input
X
X
12 3 4 5 15
Tdly3
strt_bit
Tdly1
LSb
output
MSb
16
stp_bit
input
2.3.1.5 READ DATA FROM DATA
MEMORY
After receiving this command, the chip will transmit
data bits out of the data memory starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising edge, and it
will revert to Input mode (hi-impedance) after the 16th
rising edge. As previously stated, the data memory is
8-bits wide, and therefore, only the first 8 bits that are
output are actual data. If the data memory is code
protected, the data is read as all zeros. A timing
diagram of this command is shown in Figure 2-7.
FIGURE 2-7: READ DATA FROM DATA MEMORY COMMAND
Tdly2
PIC16F630/676
RA1
CLOCK
RA0
DATA
12 3 4 56
1
Ts et 1
0
Thld1
0
1
input
X
X
12 3 4 5 15
Tdly3
strt_bit
Tdly1
LSb
output
2.3.1.6 INCREMENT ADDRESS
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 2-8.
It is not possible to decrement the address counter. To
RESET this counter, the user should exit and re-enter
Programming mode.
FIGURE 2-8: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
Tdly2
12 3 4 56
RA1
CLOCK
12
Next Command
MSb
16
stp_bit
input
RA0
DATA
2003 Microchip Technology Inc. Preliminary DS41191B-page 7
011 XX
0
Tdly1Ts et 1
Thld1
X0
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