Datasheet PIC16F630, PIC16F676 Datasheet

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PIC16F630/676

Data Sheet

14-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

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The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, an d SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

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Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology I ncorporat ed in the U.S.A. and other countries.

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All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC® DSCs, KEELOQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

code hopping devices, Serial

PIC16F630/676

14-Pin, Flash-Based 8-Bit CMOS Microcontroller

High Performance RISC CPU:

• Only 35 instructions to learn

- All single-cycle instructions except branches

• Operating speed:

- DC - 20 MHz oscillator/clock input

- DC - 200 ns instruction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect, and Relative Addressing modes

Low Power Features:

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

-8.5μA @ 32 kHz, 2.0V, typical

-100μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current

- 300 nA @ 2.0V, typical

• Timer1 oscillator current:

-4μA @ 32 kHz, 2.0V, typical

Special Microcontroller Features:

• Internal and external oscilla tor opti ons

- Precision Internal 4MHz oscillator factory calibrated to ±1%

- External Oscillator support for crystals and resonators

-5μs wake-up from SLEEP, 3.0V, typical

• Power saving SLEEP mode

• Wide operating voltage range - 2.0V to 5.5V

• Industrial and Extended tempera ture range

• Low power Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Detect (BOD)

• Watchdog Timer (WDT) with independent oscillator for reliable operation

• Multiplexed MCLR

• Interrupt-on-pin change

• Individual programmable weak pull-ups

• Programmable code protection

• High Endurance FLASH/EEPROM Cell

- 100,000 write FLASH endurance

- 1,000,000 write EEPROM endurance

- FLASH/Data EEPROM Retention: > 40 years

Device

PIC16F630 1024 64 128 12 – 1 1/1 PIC16F676 1024 64 128 12 8 1 1/1

/Input-pin

Program

Memory

FLASH

(words)

Data Memory

SRAM (bytes)

EEPROM

(bytes)

Peripheral Features:

• 12 I/O pins with indiv idual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- One analog comparator

- Programmable on-chip comparator voltage reference (CVREF) module

- Programmable input multiplexing from device inputs

- Comparator output is externally accessible

• Analog-to-Digital Converter module (PIC16F676):

- 10-bit resolution

- Programmable 8-channel input

- Voltage reference input

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

• Enhanced Ti mer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator, if INTOSC mode selected

• In-Circuit Serial Programming two pins

I/O

10-bit A/D

(ch)

(ICSPTM) via

Comparators

Timers

8/16-bit

PIC16F630/676

Pin Diagrams

14-pin PDIP, SOIC, TSSOP

RA5/T1CKI/OSC1/CLKIN

RA4/T1G

/OSC2/CLKOUT

RA3/MCLR

RA5/T1CKI/OSC1/CLKIN

RA4/T1G

/OSC2/AN3/CLKOUT

RA3/MCLR

VDD

/VPP RC5 RC4 RC3

VDD

/VPP RC5 RC4

RC3/AN7

PIC16F630

PIC16F676

VSS RA0/CIN+/ICSPDAT RA1/CIN-/ICSPCLK RA2/COUT/T0CKI/INT RC0 RC1 RC2

VSS RA0/AN0/CIN+/ICSPDAT RA1/AN1/CIN-/V RA2/AN2/COUT/T0CKI/INT RC0/AN4 RC1/AN5 RC2/AN6

REF/ICSPCLK

PIC16F630/676

Table of Contents

1.0 Device Overview ......................................................................... ................................................................................................ 5

2.0 Memory Organization ............................................................................................. ..................................................................... 7

3.0 Ports A and C ................................................... .. .... .. .. .... ....... .. .. .. .... .. .. ....... .... .. .. .. .... .................................................................19

4.0 Timer0 Module ................................................. .. .. .. .... .. .. ....... .. .. .... .. .. .. ....... .. .. .... .. .. ....... ............................................................29

5.0 Timer1 Module with Gate Control .................................................................................... .... .. .. ................................................. 32

6.0 Comparator Module .................................................................................................................................................................. 37

7.0 Analog-to-Digital Converter (A/D) Module (PIC16F676 only) ................................................................................................... 43

8.0 Data EEPROM Memory............................................................................................................................................................ 49

9.0 Special Features of the CPU .................................................................................................................................................... 53

10.0 Instruction Set Summary ........................................................................................................................................................... 71

11.0 Development Support ....................................................................................................... ........................................................ 79

12.0 Electrical Specifications ............................ ..................................................... ........................................................................... 83

13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 105

14.0 Packaging Information ............................................................................................................................................................ 115

Appendix A: Data Sheet Revision History ......................................................................................................................................... 119

Appendix B: Device Differences .......................................................................................................................................................119

Appendix C: Device Migrations ......................................................................................................................................................... 120

Appendix D: Migrating from other PIC

Index ................................................................................................................................................................................................. 121

On-Line Support ................................................................................................................................................................................125

Systems Information and Upgrade Hot Line .....................................................................................................................................125

Reader Response .............................................................................................................................................................................126

Product Identific ation System ........................................................................................................................................................... 127

Devices .............................................................................................................................. 120

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Errata

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using.

Customer Notification System

PIC16F630/676

NOTES:

PIC16F630/676

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the PIC16F630/676. Additional information may be found in the PIC® Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a com pleme nt ary do cume nt to this Da t a

FIGURE 1-1: PIC16F630/676 BLOCK DIAGRAM

INT

Program Counter

8-Level Stack

Direct Addr

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog Brown-out

(13-bit)

Timer

Reset

Timer

Detect

RAM Addr

OSC1/CLKIN

OSC2/CLKOUT

Program

Bus

Internal

Oscillator

Configuration

FLASH

1K x 14

Program Memory

Instruction reg

Instruction

Decode &

Control

Timing

Generation

Sheet and is highly recommended reading for a better understanding o f the d ev ic e arc hi tec ture a nd operation of the peripheral modules.

The PIC16F630 and PIC16F676 devices are covered by this Data Sheet. They are identical, except the PIC16F676 has a 10-bit A/D converter. They come in 14-pin PDIP, SOIC and TSSOP packages. Figure 1-1 shows a block diagram of th e PIC16F 630/67 6 devices . Table 1-1 shows the pinout description.

Data Bus

Registers

Addr MUX

RAM

bytes

File

FSR reg

STATUS reg

ALU

W reg

MUX

Indirect

Addr

PORTA

RA0 RA1 RA2 RA3 RA4 RA5

PORTC

RC0 RC1 RC2 RC3 RC4 RC5

T1G

T1CKI

T0CKI

VREF

AN0 AN1AN2 AN3

MCLR

Timer0 Timer1

Analog to Digital Converter

(PIC16F676 only)

AN4 AN5 AN6AN7

VSS

Comparator

and reference

CIN- CIN+ COUT

Analog

EEDATA

128 bytes

EEPROM EEADDR

DATA

PIC16F630/676

TABLE 1-1: PIC16F630/676 PINOUT DESCRIPTION

Name Function

RA0/AN0/CIN+/ICSPDAT RA0 TTL CMOS Bi-directional I/O w/ programmable pull-up and

AN0 AN — A/D Channel 0 input

CIN+ AN Comparator input

ICSPDAT TTL CMOS Serial Programming Data I/O

RA1/AN1/CIN-/VREF/ ICSPCLK

RA2/AN2/COUT/T0CKI/INT RA2 ST CMOS Bi-directional I/O w/ programmable pull-up and

RA3/MCLR

RA4/T1G CLKOUT

RA5/T1CKI/OSC1/CLKIN

RC0/AN4 RC0 TTL CMOS Bi -dire ctional I/O

RC1/AN5 RC1 TTL CMOS Bi -dire ctional I/O

RC2/AN6 RC2 TTL CMOS Bi -dire ctional I/O

RC3/AN7 RC3 TTL CMOS Bi -dire ctional I/O

RC4 RC4 TTL CMOS Bi -dire ctional I/O RC5 RC5 TTL CMOS Bi -dire ctional I/O

SS VSS Power — Ground reference

V VDD VDD Power — Positive supply Legend: Shade = PIC16F676 only

/VPP RA3 TTL — Input port with Interrupt-on-change

/AN3/OSC2/

TTL = TTL input buffer

ST = Schmitt Trigger input buffer

RA1 TTL CMOS Bi-directional I/O w/ programmable pull-up and

AN1 AN — A/D Channel 1 input CIN- AN — Comparator input

VREF AN — External Voltage reference

ICSPCLK ST — Serial Programming Clock

AN2 AN — A/D Channel 2 input COUT — CMOS Comparator output T0CKI ST — Timer0 clock input

INT ST — External Interrupt

MCLR

PP HV — Programming voltage

RA4 TTL CMOS Bi-directional I/O w/ programmable pull-up and

T1G

AN3 AN3 — A/D Channel 3 input OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS F

RA5 TTL CMOS Bi-directional I/O w/ programmable pull-up and

T1CKI ST — Timer1 clock OSC1 XTAL — Crystal/Resonator

CLKIN ST — External cl ock input/RC oscillator connection

AN4 AN4 — A/D Channel 4 input

AN5 AN5 — A/D Channel 5 input

AN6 AN6 — A/D Channel 6 input

AN7 AN7 — A/D Channel 7 input

Input Type

ST — Master Clea r

ST — Timer1 gate

Output

Type

Description

Interrupt-on-change

OSC/4 output

Interrupt-on-change

PIC16F630/676

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F630/676 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h - 03FFh) for the PIC16F630/676 devices is physically implemented. Accessing a location above these boundaries will cause a wrap around withi n the firs t 1K x 14 sp ac e. The RESET vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC16F630/676

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1 Stack Level 2

Stack Level 8

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose registers and the Special Function registers. The Special Function registers are located in the first 32 lo cations of each bank. Register locations 20h-5Fh are General Purpose registers, imple mented as st atic RAM and a re mapped across both banks. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS<5>) is the bank select bit.

• RP0 = 0 Bank 0 is selected

• RP0 = 1 Bank 1 is selected Note: The IRP an d RP1 bits STAT US<7:6> are

reserved and shoul d always be mai ntaine d as ‘0’s.

2.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the PIC16F630/676 devices. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4).

RESET Vector

Interrupt Vector

On-chip Program

Memory

000h

0004 0005

03FFh 0400h

1FFFh

PIC16F630/676

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM.

The special re gisters can be classifi ed into two sets: core and peripheral. The Special Function registers associated with the “c ore” are des cribed in this sect ion. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

FIGURE 2-2: DATA MEMORY MAP OF

THE PIC16F630/676

File

Address

(1)

Indirect addr.

TMR0

PCL

STATUS

FSR

PORTA

PORTC

PCLATH INTCON

PIR1

TMR1L

TMR1H

T1CON

CMCON VRCON

ADRESH ADCON0

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh

(2)

1Eh

(2)

1Fh 20h

Indirect addr.

OPTION_REG

EECON2 ADRESL ADCON1

PCL

STATUS

FSR

TRISA

TRISC

PCLATH INTCON

PIE1

PCON

OSCCAL

ANSEL

WPUA

IOCA

EEDAT

EEADR

EECON1

(2)

(1) (2) (2)

Address

(1)

File

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h

General

Purpose

Registers

64 Bytes

5Fh 60h

7Fh

Bank 0

Unimplemented data memory locations, read as '0'.

1: Not a physical register. 2: PIC16F676 only.

accesses

20h-5Fh

DFh E0h

FFh

Bank 1

PIC16F630/676

TABLE 2-1: PIC16F630/676 SPECIAL REGISTERS SUMMARY BANK 0

Value on

AddrNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 18,61 01h TMR0 Timer0 Module’s Register xxxx xxxx 29 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17 03h STATUS

04h FSR Indirect data memory address pointer xxxx xxxx 18 05h PORTA

06h — Unimplemented — — 07h PORTC

08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 13 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 32 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 32

10h T1CON 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h CMCON 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH

1Fh ADCON0

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: IRP & RP1 bits are reserved, always maintain these bits clear. 3: PIC16 F6 76 onl y.

(3) (3)

(2)

IRP

— —

— — — Write buffer for upper 5 bits of program counter ---0 0000 17

EEIF ADIF — —CMIF— —TMR1IF00-- 0--0 15

— T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

—COUT— CINV CIS CM2 CM1 CM0 -0-0 0000 37

Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 44

ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON

RP1

(2)

RP0 TO PD ZDCC

I/O Control Registers --xx xxxx 19

I/O Control Registers --xx xxxx 26

Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.

POR,

Page

BOD

0001 1xxx 11

-000 0000 34

00-0 0000 45,61

PIC16F630/676

TABLE 2-2: PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on

AddrName Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 18,61 81h OPTION_REG

82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17 83h STATUS

84h FSR Indirect data memory address pointer xxxx xxxx 18 85h TRISA 86h — Unimplemented — — 87h TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write buffer for upper 5 bits of progra m coun ter ---0 0000 17 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 13 8Ch PIE1 EEIE ADIE 8Dh — Unimplemented — — 8Eh PCON

8Fh — — 90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

91h ANSEL 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h WPUA

96h IOCA 97h — Unimplemented — — 98h — Unimplemented — — 99h VRCON VREN 9Ah EEDAT EEPROM data register 0000 0000 49 9Bh EEADR 9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 50 9Dh EECON2 EEPROM control register 2 (not a physical register) ---- ---- 49 9Eh ADRESL 9Fh ADCON1

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: IRP & RP1 bits are reserved, always maintain these bits clear. 3: PIC16F676 only.

(3)

RAPU

IRP

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 19

— — — — — —PORBOD

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 46

— — — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 21

— EEPROM address register 0000 0000 49

Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 44

(3)

— ADCS2 ADCS1 ADCS0 — — — — -000 ---- 45,61

INTEDG T0CS T0SE PSA PS2 PS1 PS0

(2)

RP1

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 42

RP0 TO PD ZDCC

— —CMIE— —TMR1IE00-- 0--0 14

WPUA5 WPUA4

Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.

—

WPUA2 WPUA1 WPUA0

— —

POR,

Page

BOD

1111 1111 12,30

0001 1xxx 11

---- --qq 16

1000 00-- 16

--11 -111 20

PIC16F630/676

2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the RESET status

• the bank select bits for data memory (SRAM) The STATUS register can be the destination for any

instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS regis ter as destin ation may be diffe rent than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

and PD bits are not

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the “Instruction Set Summary”.

Note 1: Bits IRP a nd RP1 (ST ATUS<7:6>) are not

used by the PIC16F630/676 and should be maintained as clear. Use of these bits is not recommended, s ince this may af fect upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h - FFh) 0 = Bank 0 (00h - 7Fh)

bit 4 TO

bit 3 PD: Power-down bit

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruct ion 0 = A WDT time-out occurred

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

For borrow ,

1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow

the polarity is reversed.

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.2 OPTION Register

The OPTION register is a readable and writable register, which contains various control bits to configure:

• TMR0/WDT prescaler

• External RA2/INT interrupt

•TMR0

• Weak pull-ups on PORTA

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescale r to th e WDT b y setting PSA bit to ‘1’ (OPTION<3>). See Section 4.4.

bit 7 RAPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS2:PS0: Prescaler Rate Select bits

: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin

1 = Transition on RA 2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register , which c ontains the various en able and fl ag bit s for TMR0 register overflow, PORTA change and external RA2/INT pin in terrupts.

Note: Interrupt flag bit s are se t whe n an in terrupt

condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are cle ar prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE RAIE T0IF INTF RAIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt

bit 3 RAIE: Port Change Interrupt Enable bit

1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 regis ter has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur

bit 0 RAIF: Port Change Interrupt Flag bit

1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state

(1)

(2)

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when T im er0 roll s ove r. Timer0 is unchanged o n RESET and should

be initialized before clearing T0IF bit.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.4 PIE 1 Regi st er

The PIE1 register contai ns th e in terru pt enable bits, as shown in Register 2-4.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIE ADIE — — CMIE — — TMR1IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Inte rrupt Enable bit

1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC16F676 only)

1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt

bit 5-4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt 0 = Disables the comparator interrupt

bit 2-1 Unimplemented: Read as ‘0’ bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIF ADIF — —CMIF— —TMR1IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC16F676 only)

1 = The A/D conversion is complete (must be cleared in software) 0 = The A/D conversion is not complete

bit 5-4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed

bit 2-1 Unimplemented: Read as ‘0’ bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow

Note: Interrupt flag bits are se t w he n an in terru pt

condition occurs, re gardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bit s are clear prio r to enab ling an interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.6 PCON Regi st er

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR)

• Brown-out Detect (BOD)

• Watchdog Timer Reset (WDT)

• External MCLR The PCON Register bits are shown in Register 2-6.

Reset

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x

— — — — — —PORBOD

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0' bit 1 POR

bit 0 BOD

: Power-on Reset STATUS bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Detect STATUS bit

1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

2.2.2.7 OSCCAL Register

The Oscillator Calibrati on register (OSCCAL) is used to calibrate the internal 4 MHz oscill ator. It contains 6 bits to adjust the frequency up or down to achieve 4 MHz.

The OSCCAL register bits are shown in Register 2-7.

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

bit 7 bit 0

bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits

111111 = Maximum freque ncy 100000 = Center frequency 000000 = Minimum frequency

bit 1-0 Unimplemented: Read as '0'

— —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte comes from the PCL regist er, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes fr om PCLATH. On any RESET, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PCLATH<4:0>

PCLATH

PCH PCL

12 11 10 0

PCLATH<4:3>

Instruction with PCL as Destination

ALU result

GOTO, CALL

Opcode <10:0>

2.3.2 STACK

The PIC16F630/676 family ha s an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operat es as a circular buf fer . This means th at after the stack has been PUSHed eight times, the ninth push overwrites th e valu e that was s tored fro m the firs t push. The tenth pus h ov erwr i tes the se co nd push (and so on).

Note 1: There are no STATUS bits to indicate

stack overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

PCLATH

2.3.1 COMPUTED GOTO

A computed GOTO is accomplish ed by adding an offs et to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercise d i f the t able loca tio n cros ses a PCL memory boundary (each 256-byte block). Refer to the Application Note “Implementing a Table Read" (AN556).

PIC16F630/676

2.4 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physi cal register. Addressing

A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register actually accesses data pointed to by the File Select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a n o operation (although STA TUS bits m ay be affected). An effective 9-bit address is obtained by

NEXT clrf INDF ;clear INDF register

CONTINUE ;yes continue

movlw 0x20 ;initialize pointer movwf FSR ;to RAM

incf FSR ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next

concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4.

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F630/676

(1)

RP0 6

RP1

Ban k Select Location Select

From Opcode

00 01 10 11

00h

(1)

IRP

Bank Select

180h

Indirect AddressingDirect Addressing

FSR Register

Location Select

Data Memory

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

For memory map detail see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

Not Used

1FFh

PIC16F630/676

3.0 PORTS A AND C

There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be a vailable a s general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin.

Note: Additional information on I/O ports may be

found in the PIC Manual, (DS33023)

3.1 PORTA and the TRISA Registers

PORTA is an 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) wi ll make the correspondin g PORTA pin an input (i.e., put the corresponding output driver in a Hi-impedance mode). Clearing a TRISA bit (= 0) will make the correspondin g POR TA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’. Example 3-1 shows how to initialize PORTA.

Reading the PORTA register reads the status of the pins, whereas writing to i t will wri te to th e po rt latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. RA3 reads ‘0’ when MCLREN = 1.

The TRISA register controls the direction of the PORT A pins, even when they are being used as analo g inputs. The user must ensure the bits in the TRISA

Mid-Range Reference

register are maintained set when using the m as analog inputs. I/O pins co nfigure d a s analo g i nput a lways read ‘0’.

Note: The ANSEL (91h) and CMCON (19h)

registers must be initializ ed to c onfigure a n analog channel as a digital input. Pins configured as analog inputs will read ‘0’. The ANSEL register is defined for the PIC16F676.

EXAMPLE 3-1: INITIALIZING PORTA

bcf STATUS,RP0 ;Bank 0 clrf PORTA ;Init PORTA movlw 05h ;Set RA<2:0> to movwf CMCON ;digital I/O bsf STATUS,RP0 ;Bank 1 clrf ANSEL ;digital I/O movlw 0Ch ;Set RA<3:2> as inputs movwf TRISA ;and set RA<5:4,1:0>

bcf STATUS,RP0 ;Bank 0

;as outputs

3.2 Additional Pin Functions

Every PORTA pin on the PIC16F630/676 has an interrupt-on-change option and every PORTA pin, except RA3, has a weak pull-up option. The next two sections describe thes e functions.

3.2.1 WEAK PULL-UP

Each of the PORTA pins, except RA3, has an individually configurable weak internal pull-up. Control bits WPUAx enable or disable each pull-up. Refer to Register 3-3. Each wea k pull-up is autom atically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the

bit (OPTION<7>).

RAPU

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— —

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’ bit 5-0: PORTA<5:0>: PORTA I/O pin

1 = Port pin is >V 0 = Port pin is <VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

RA5 RA4 RA3 RA2 RA1 RA0

PIC16F630/676

U-0 U-0 R/W-x R/W-x R-1 R/W-x R/W-x R/W-x

— —

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’ bit 5-0: TRISA<5:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output

Note: TRISA<3> always reads 1.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0

bit 7 bit 0

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Register bit

1 = Pull-up enabled 0 = Pull-up disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUA<2:0>: Weak Pull-up Register bit

1 = Pull-up enabled 0 = Pull-up disabled

Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode

(TRISA = 0).

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

3.2.2 INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 3-4. The interrupt-on-change is disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the values are compared with the old value la tched on the last rea d of PORTA. The ‘mismatch’ outputs of the last read are OR'd together to s et, the PO RTA Change Interrupt flag bit (RAIF) in the INTCON register.

This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner:

a) Any read or write of PORTA. This will end the

mismatch condition.

b) Clear the flag bit RAIF. A mismatch c ond it i on wi ll cont i n ue to s et f lag bi t RA IF.

Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared.

Note: If a change on the I/O pin should occur

when the read operatio n is b eing ex ecute d (start of the Q2 cycle), then the RAIF interrupt flag may not get set.

PIC16F630/676

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCA<5:0>: Interrupt-on-Change PORTA Control bit

1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled

Note: Global interrupt enable (GIE) must be enabled for individual interrupts to be

recognized.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

3.2.3 PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet.

3.2.3.1 RA0/AN0/CIN+

Figure 3-1 shows th e diagr am for thi s pin. Th e RA0 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D (PIC16F676 only)

• an analog input to the comparator

3.2.3.2 RA1/AN1/CIN-/VREF

Figure 3-1 shows th e diagr am for thi s pin. Th e RA1 pin is configurable to function as one of the following:

• as a general purpose I/O

• an analog input for the A/D (PIC16F676 only)

• an analog input to the comparator

• a voltage reference input for the A/D (PIC16F676

only)

FIGURE 3-1: BLOCK DIAGRAM OF RA0

AND RA1 PINS

Analog

Data Bus

WPUA

PORTA

TRISA

PORTA

IOCA

Input Mode

RAPU

Analog

Input Mode

VDD

Weak

VDD

I/O pin

VSS

Interrupt-on-Change

To Comparator To A/D Converter

RD PORTA

PIC16F630/676

3.2.3.3 RA2/AN2/T0CKI/INT/COUT

Figure 3-2 shows th e diagr am for thi s pin. Th e RA2 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D (PIC16F676 only)

• a digital output from the comparator

• the clock input for TMR0

• an external edge triggered interrupt

FIGURE 3-2: BLOCK DIAGRAM OF RA2

Analog

Data Bus

WPUA

PORTA

TRISA

Input Mode

RAPU

COUT

Enable

COUT

1 0

Analog

Input Mode

Analog

Input

Mode

VDD

Weak

VDD

I/O pin

VSS

3.2.3.4 RA3/MCLR

/VPP

Figure 3-3 shows the di agram fo r this pi n. The RA 3 pin is configurable to function as one of the following:

• a general purpose input

• as Master Clear Reset

FIGURE 3-3: BLOCK DIAGRAM OF RA3

Data Bus

TRISA

PORTA

IOCA

Interrupt-on-Change

RESET

VSS

MCLRE

RD PORTA

I/O pin

PORTA

IOCA

Interrupt-on-Change

To TMR0 To INT To A/D Converter

RD PORTA

PIC16F630/676

3.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT

Figure 3-4 shows th e diagr am for thi s pin. Th e RA4 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D (PIC16F676 only)

• a TMR1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 3-4: BLOCK DIAGRAM OF RA4

Analog

Data Bus

WPUA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-Change

Input Mode

OSC1

OSC/4

CLKOUT

Enable

INTOSC/ RC/EC

CLKOUT

Enable

Input Mode

CLK

Modes

RAPU

Oscillator

Circuit

CLKOUT

Enable

1 0

(2)

Analog

(1)

VDD

Weak

VDD

I/O pin

VSS

3.2.3.6 RA5/T1CKI/OSC1/CLKIN

Figure 3-5 shows the di agram fo r this pi n. The RA 5 pin is configurable to function as one of the following:

• a general purpose I/O

•a TMR1 clock input

• a crystal/resona tor connec tio n

• a clock input

FIGURE 3-5: BLOCK DIAGRAM OF RA5

INTOSC

Data Bus

WPUA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-Change

Mode

TMR1LPEN

RAPU

Oscillator

Circuit

OSC2

INTOSC

Mode

RD PORTA

(1)

VDD

Weak

VDD

I/O pin

VSS

(1)

To TMR1 T1G To A/D Converter

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option.

RD PORTA

To TMR1 or CLKGEN

Note 1: Timer1 LP Oscillator enabled.

2: When using Timer1 with LP oscillator, the Schmitt

Trigger is by-passed.

PIC16F630/676

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR,

BOD

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu 0Bh/8Bh INTCON GIE 19h CMCON 81h OPTION_REG RAPU 85h TRISA 91h ANSEL 95h WPUA 96h IOCA

Note 1: PIC16F676 only.

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

(1)

— COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

ANS7 ANS6 ANS5 ANS4

— — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000

PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 000u

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

ANS3 ANS2 ANS1 ANS0

1111 1111 1111 1111

Value on

all

other

RESETS

PIC16F630/676

3.3 PORTC

PORTC is a general purp ose I/O port co nsisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog i nput to A/D co nver ter. For specific information about individual functions such as the comparator or th e A/D , ref e r to th e appr o p ria t e se ct i on in this Data Sheet.

Note: The ANSEL register (91h) must be clear to

configure an analog channel as a digital input. Pins configu red as an alog in put s wil l read ‘0’. The ANSEL register is define d for the PIC16F676.

EXAMPLE 3-2: INITIALIZING PORTC

bcf STATUS,RP0 ;Bank 0 clrf PORTC ;Init PORTC bsf STATUS,RP0 ;Bank 1 clrf ANSEL ;digital I/O movlw 0Ch ;Set RC<3:2> as inputs movwf TRISC ;and set RC<5:4,1:0>

;as outputs

bcf STATUS,RP0 ;Bank 0

3.3.1 RC0/AN4, RC1/AN5, RC2/AN6, RC3/

AN7

3.3.2 RC4 AND RC5

The RC4 and RC5 pins are configurable to function as a general purpose I/Os.

FIGURE 3-7: BLOCK DIAGRAM OF RC4

AND RC5 PINS

Data bus

VDD

I/O Pin

VSS

PORTC

TRISC

PORTC

The RC0/RC1/RC2/RC3 pins are configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D Converter

(PIC16F676 only)

FIGURE 3-6: BLOCK DIAGRAM OF

RC0/RC1/RC2/RC3 PINs

Data bus

VDD

I/O Pin

VSS

PORTC

TRISC

PORTC

Analog Input

Mode

To A/D Converter

PIC16F630/676

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— —

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’ bit 5-0: PORTC<5:0>: General Purpose I/O pin

1 = Port pin is >V

0 = Port pin is <VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— —

bit 7 bit 0

RC5 RC4 RC3 RC2 RC1 RC0

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7-6: Unimplemented: Read as ’0’ bit 5-0: TRISC<5:0>: PORTC Tri-State Control bit

1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Address Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0

07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu 87h TRISC 91h ANSEL

Note 1: PIC16F676 only.

Legend:

(1)

x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTC.

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

Val ue on:

POR, BOD

1111 1111 1111 1111

Value on all

other

RESETS

PIC16F630/676

NOTES:

+ 100 hidden pages

Datasheet PIC16F630, PIC16F676 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

14-Pin, Flash-Based 8-Bit CMOS Microcontroller

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC16F630/676 BLOCK DIAGRAM

TABLE 1-1: PIC16F630/676 PINOUT DESCRIPTION

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

2.2 Data Memory Organization

TABLE 2-1: PIC16F630/676 SPECIAL REGISTERS SUMMARY BANK 0

TABLE 2-2: PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

2.3 PCL and PCLATH

2.4 Indirect Addressing, INDF and FSR Registers

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F630/676

3.0 PORTS A AND C

3.1 PORTA and the TRISA Registers

3.2 Additional Pin Functions

FIGURE 3-2: BLOCK DIAGRAM OF RA2

FIGURE 3-3: BLOCK DIAGRAM OF RA3

FIGURE 3-4: BLOCK DIAGRAM OF RA4

FIGURE 3-5: BLOCK DIAGRAM OF RA5

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

3.3 PORTC

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC