PIC16F627A/628A/648A
Data Sheet
FLASH-Based
8-Bit CMOS Microcontrollers
2002 Microchip Technology Inc. Preliminary DS40044A
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
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Trademarks
The Microchip name and logo, the Microchip logo, K
EELOQ,
MPLAB, PIC, PICmicro, PICSTART and PRO MATE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS40044A - page ii Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
18-pin FLASH-Based 8-Bit CMOS Microcontrollers
High Performance RISC CPU:
• Operating speeds from DC - 20 MHz
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• 35 single word instructions
- All instructions single cycle except branches
Special Microcontroller Features:
• Internal and external oscillator options
- Precision Internal 4 MHz oscillator factory
calibrated to ±1%
- Low Power Internal 37 kHz oscillator
- External Oscillator support for crystals and
resonators.
• Power saving SLEEP mode
• Programmable weak pull-ups on PORTB
• Multiplexed Master Clear/Input-pin
• Watchdog Timer with independent oscillator for
reliable operation
• Low voltage programming
• In-Circuit Serial Programming™ (via two pins)
• Programmable code protection
• Brown-out Reset
• Power-on Reset
• Power-up Timer and Oscillator Start-up Timer
• Wide operating voltage range. (2.0 - 5.5V)
• Industrial and extended temperature range
• High Endurance FLASH/EEPROM Cell
- 100,000 write FLASH endurance
- 1,000,000 write EEPROM endurance
- 100 year data retention
Program
Device
PIC16F627A 1024 224 128 16 1 Y 2 2/1
PIC16F628A 2048 224 128 16 1 Y 2 2/1
PIC16F648A 4096 256 256 16 1 Y 2 2/1
Memory
FLASH
(words)
Data Memory
SRAM
(bytes)
EEPROM
(bytes)
Low Power Features:
• Standby Current:
- 100 nA @ 2.0V, typical
• Operating Current:
-12µA @ 32 kHz, 2.0V, typical
-120µA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current
-1µA @ 2.0V, typical
• Timer1 oscillator current:
-1.2µA @ 32 kHz, 2.0V, typical
• Dual Speed Internal Oscillator:
- Run-time selectable between 4 MHz and
37 kHz
-4µs wake-up from SLEEP, 3.0V, typical
Peripheral Features:
• 16 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(V
REF) module
- Selectable internal or external reference
- Comparator outputs are externally accessible
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• Timer1: 16-bit timer/counter with external crystal/
clock capability
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• Capture, Compare, PWM module
- 16-bit Capture/Compare
- 10-bit PWM
• Addressable Universal Synchronous/Asynchronous Receiver/Transmitter USART/SCI
CCP
I/O
(PWM)
USART Comparators
Timers
8/16-bit
2002 Microchip Technology Inc. Preliminary DS40044A-page 1
PIC16F627A/628A/648A
Pin Diagrams
PDIP, SOIC
SSOP
RA2/AN2/V
RA3/AN3/CMP1
RA4/TOCKI/CMP2
RA5/MCLR
RA1/AN1
20
PIC16F627A/628A/648A
1
REF
RA2/AN2/V
RA3/AN3/CMP1
REF
/VPP
VSS
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VDD
17
SS
VSS
V
/VPP
RA5/MCLR
RA4/TOCKI/CMP2
VDD
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
RB0/INT
RB1/RX/DT
RA0/AN0
19181615141312
2 3 4 5 6 7 8 910
118
2
3
4
5
6
7
8
9
RB4/PGM
RB5
11
RB3/CCP1
RB2/TX/CK
RA1/AN1
PIC16F627A/628A/648A
17
PIC16F627A/628A/648A
16
15
14
13
12
11
10
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
DD
V
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5
RB4/PGM
28-Pin
QFN
RA5/MCLR/VDD
RB0/INT
VSS
VSS
1
NC
2
3
PIC16F627A/628A
NC
4
5
NC
6
7
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
NC
2827262524
PIC16F648A
8
9
10
11
12
NC
RB4/PGM
RB3/CCP1
RB2/TX/CK
RB1/RX/DT
RA0/AN0
NC
22
23
21
20
19
18
17
16
15
14
13
NC
RB5
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
V
DD
NC
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
DS40044A-page 2 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16F627A/628A/648A Device Varieties ................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization ................................................................................................................................................................. 15
5.0 I/O Ports ..................................................................................................................................................................................... 31
6.0 Timer0 Module ........................................................................................................................................................................... 45
7.0 Timer1 Module ........................................................................................................................................................................... 48
8.0 Timer2 Module ........................................................................................................................................................................... 52
9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 55
10.0 Comparator Module.................................................................................................................................................................... 61
11.0 Voltage Reference Module......................................................................................................................................................... 67
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module........................................................................ 69
13.0 Data EEPROM Memory ............................................................................................................................................................. 89
14.0 Special Features of the CPU...................................................................................................................................................... 93
15.0 Instruction Set Summary .......................................................................................................................................................... 111
16.0 Development Support............................................................................................................................................................... 125
17.0 Electrical Specifications............................................................................................................................................................ 131
18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 147
19.0 Packaging Information.............................................................................................................................................................. 149
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2002 Microchip Technology Inc. Preliminary DS40044A-page 3
PIC16F627A/628A/648A
NOTES:
DS40044A-page 4 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
1.0 GENERAL DESCRIPTION
The PIC16F627A/628A/648A are 18-Pin FLASHbased members of the versatile PIC16CXX family of
low cost, high performance, CMOS, fully-static, 8-bit
microcontrollers.
®
All PICmicro
RISC architecture. The PIC16F627A/628A/648A have
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a singlecycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available, complemented by a large register
set.
PIC16F627A/628A/648A microcontrollers typically
achieve a 2:1 code compression and a 4:1 speed
improvement over other 8-bit microcontrollers in their
class.
PIC16F627A/628A/648A devices have integrated features to reduce external components, thus reducing
system cost, enhancing system reliability and reducing
power consumption.
The PIC16F627A/628A/648A has 8 oscillator configurations. The single-pin RC oscillator provides a low cost
solution. The LP oscillator minimizes power consumption, XT is a standard crystal, and INTOSC is a selfcontained precision two-speed internal oscillator. The
microcontrollers employ an advanced
HS is for High-Speed crystals. The EC mode is for an
external clock source.
The SLEEP (Power-down) mode offers power savings.
Users can wake-up the chip from SLEEP through several external interrupts, internal interrupts and
RESETS.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
Table 1-1 shows the features of the PIC16F627A/
628A/648A mid-range microcon troller fa milies.
A simplified block diagram of the PIC16F627A/628A/
648A is shown in Figure 3-1.
The PIC16F627A/628A/648A series fits in applications
ranging from battery chargers to low power remote
sensors. The FLASH technology makes customizing
application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The
small footprint packages makes this microcontroller
series ideal for all applications with space limitations.
Low cost, low power, high performance, ease of use
and I/O flexibility make the PIC16F627A/628A/648A
very versatile.
1.1 Development Support
The PIC16F627A/628A/648A family is supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a low cost in-circuit debugger, a low
cost development programmer and a full-featured programmer. A Third Party “C” compiler support tool is
also available.
TABLE 1-1: PIC16F627A/628A/648A FAMILY OF DEVICES
PIC16F627A PIC16F628A PIC16F648A PIC16LF627A PIC16LF628A PIC16LF648A
Clock Maximum Frequency
Memory RAM Data Memory
Peripherals Capture/Compare/
Features Voltage Range (Volts) 3.0-5.5 3.0-5.5 3.0-5.5 2.0-5.5 2.0-5.5 2.0-5.5
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability.
All PIC16F627A/628A/648A Family devices use serial programming with clock pin RB6 and data pin RB7.
of Operation (MHz)
FLASH Program Memory (words)
(bytes)
EEPROM Data Memory (bytes)
Timer module(s) TMR0, TMR1,
Comparator(s) 222222
PWM modules
Serial Communications USART USART USART USART USART USART
Internal Voltage
Reference
Interrupt Sources 10 10 10 10 10 10
I/O Pins 16 16 16 16 16 16
Brown-out Reset Yes Yes Yes Yes Yes Yes
Packages 18-pin DIP,
20 20 20 4 4 4
1024 2048 4096 1024 2048 4096
224 224 256 224 224 256
128 128 256 128 128 256
TMR2
111111
Yes Yes Yes Yes Yes Yes
SOIC, 20-pin
SSOP,
28-pin QFN
TMR0, TMR1,
TMR2
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
TMR0, TMR1,
TMR2
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
TMR0, TMR1,
TMR2
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
TMR0, TMR1,
TMR2
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
TMR0, TMR1,
TMR2
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
2002 Microchip Technology Inc. Preliminary DS40044A-page 5
PIC16F627A/628A/648A
NOTES:
DS40044A-page 6 Preliminary 2002 Microchip Technology Inc.
2.0 PIC16F627A/628A/648A DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16F627A/628A/648A
Product Identification System, at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1 FLASH Devices
FLASH devices can be erased and re-programmed
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
A further advantage of the electrically erasable FLASH
is that it can be erased and reprogrammed in-circuit, or
by device programmers, such as Microchip's
PICSTART
2.2 Quick-Turnaround-Production
®
Plus, or PRO MATE® II programmers.
(QTP) Devices
PIC16F627A/628A/648A
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are standard FLASH devices
but with all program locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more
details.
2.3 Serialized Quick-Turnaround-
SM
Production (SQTP
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
) Devices
2002 Microchip Technology Inc. Preliminary DS40044A-page 7
PIC16F627A/628A/648A
NOTES:
DS40044A-page 8 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16F627A/628A/648A
family can be attributed to a number of architectural
features commonly found in RISC microprocessors. To
begin with, the PIC16F627A/628A/648A uses a Harvard architecture, in which program and data are
accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched
from the same memory. Separating program and data
memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a
single-cycle (200 ns @ 20 MHz) except for program
branches.
Table 3-1 lists device memory sizes (FLASH, Data and
EEPROM).
TABLE 3-1: DEVICE MEMORY LIST
Memory
Device
PIC16F627A 1024 x 14 224 x 8 128 x 8
PIC16F628A 2048 x 14 224 x 8 128 x 8
PIC16F648A 4096 x 14 256 x 8 256 x 8
PIC16LF627A 1024 x 14 224 x 8 128 x 8
PIC16LF628A 2048 x 14 224 x 8 128 x 8
PIC16LF648A 4096 x 14 256 x 8 256 x 8
FLASH
Program
RAM
Data
EEPROM
Data
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, and
a description of the device pins in Table 3-2.
Two types of data memory are provided on the
PIC16F627A/628A/648A devices. Non-volatile
EEPROM data memory is provided for long term storage of data such as calibration values, look up table
data, and any other data which may require periodic
updating in the field. These data are not lost when
power is removed. The other data memory provided is
regular RAM data memory. Regular RAM data memory
is provided for temporary storage of data during normal
operation. Data are lost when power is removed.
and Digit Borrow out bit,
The PIC16F627A/628A/648A can directly or indirectly
address its register files or data memory. All Special
Function Registers, including the program counter, are
mapped in the data memory. The PIC16F627A/628A/
648A have an orthogonal (symmetrical) instruction set
that makes it possible to carry out any operation, on
any register, using any Addressing mode. This symmetrical nature and lack of ‘special optimal situations’
make programming with the PIC16F627A/628A/648A
simple yet efficient. In addition, the learning curve is
reduced significantly.
The PIC16F627A/628A/648A devices contain an 8-bit
ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
2002 Microchip Technology Inc. Preliminary DS40044A-page 9
PIC16F627A/628A/648A
FIGURE 3-1: BLOCK DIAGRAM
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
FLASH
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8-Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
Low-Voltage
Programming
(13-bit)
Timer
Reset
Timer
Detect
RAM Addr (1)
7
8
Data Bus
Addr MUX
3
RAM
File
Registers
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
/VPP
VDD, VSS
MCLR
Comparator
VREF
Time r0 Timer1 Timer2
CCP1
USART
Note: Higher order bits are from the STATUS register.
Data EEPROM
DS40044A-page 10 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O port
AN0 AN — Analog comparator input
RA1/AN1 RA1 ST CMOS Bi-directional I/O port
AN1 AN — Analog comparator input
RA2/AN2/V
RA3/AN3/CMP1 RA3 ST CMOS Bi-directional I/O port
RA4/T0CKI/CMP2 RA4 ST OD Bi-directional I/O port
RA5/MCLR
RA6/OSC2/CLKOUT RA6 ST CMOS Bi-directional I/O port
RA7/OSC1/CLKIN RA7 ST CMOS Bi-directional I/O port
RB0/INT RB0 TTL CMOS Bi-directional I/O port. Can be software pro-
RB1/RX/DT RB1 TTL CMOS Bi-directional I/O port. Can be software pro-
RB2/TX/CK RB2 TTL CMOS Bi-directional I/O port. Can be software pro-
RB3/CCP1 RB3 TTL CMOS Bi-directional I/O port. Can be software pro-
Legend: O = Output CMOS = CMOS Output P = Power
REF RA2 ST CMOS Bi-directional I/O port
AN2 AN — Analog comparator input
REF —ANVREF output
V
AN3 AN — Analog comparator input
CMP1 — CMOS Comparator 1 output
T0CKI ST — Timer0 clock input
CMP2 — OD Comparator 2 output
/VPP RA5
MCLR
PP — — Programming voltage input.
V
OSC2 — XTAL Oscillator crystal output. Connects to crystal
CLKOUT — CMOS In RC/INTOSC mode, OSC2 pin can output
OSC1 XTAL — Oscillator crystal input
CLKIN ST — External clock source input. RC biasing pin.
INT ST — External interrupt.
RX ST — USART receive pin
DT ST CMOS Synchronous data I/O.
TX — CMOS USART transmit pin
CK ST CMOS Synchronous clock I/O.
CCP1 ST CMOS Capture/Compare/PWM I/O
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
ST — Input port
ST —
Master clear. When configured as MCLR
pin is an active low RESET to the device.
Voltage on MCLR
during normal device operation.
or resonator in Crystal Oscillator mode.
CLKOUT, which has 1/4 the frequency of
OSC1
grammed for internal weak pull-up.
grammed for internal weak pull-up.
grammed for internal weak pull-up.
grammed for internal weak pull-up.
/VPP must not exceed VDD
, this
2002 Microchip Technology Inc. Preliminary DS40044A-page 11
PIC16F627A/628A/648A
TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RB4/PGM RB4 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
PGM ST — Low voltage programming input pin. When
low voltage programming is enabled, the
interrupt-on-pin change and weak pull-up
resistor are disabled.
RB5 RB5 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS
T1OSO — XTAL Timer1 oscillator output.
T1CKI ST — Timer1 clock input.
PGC ST — ICSP Programming Clock.
RB7/T1OSI/PGD RB7 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
T1OSI XTAL — Timer1 oscillator input.
PGD ST CMOS ICSP Data I/O
SS VSS Power — Ground reference for logic and I/O pins
V
DD VDD Power — Positive supply for logic and I/O pins
V
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
change. Can be software programmed for
internal weak pull-up.
DS40044A-page 12 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
3.1 Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every
Q1, the instruction is fetched from the program memory
and latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
CLKOUT
Q1
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Q1
3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
Execute INST (PC) Fetch INST (PC+2)
Q2 Q3 Q4
Q1
Execute INST (PC+1)
Internal
phase
clock
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, 3 Fetch 4
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
2002 Microchip Technology Inc. Preliminary DS40044A-page 13
Flush
Fetch SUB_1 Execute SUB_1
PIC16F627A/628A/648A
NOTES:
DS40044A-page 14 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16F627A/628A/648A has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h - 03FFh)
for the PIC16F627A, 2K x 14 (0000h - 07FFh) for the
PIC16F628A and 4K x 14 (0000h - 0FFFh) for the
PIC16F648A are physically implemented. Accessing a
location above these boundaries will cause a wraparound within the first 1K x 14 space (PIC16F627A), 2K
x 14 space (PIC16F628A) or 4K x 14 space
(PIC16F648A). The RESET vector is at 0000h and the
interrupt vector is at 0004h (Figure 4-1).
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
13
000h
4.2 Data Memory Organization
The data memory (Figure 4-2 and Figure 4-3) is
partitioned into four banks, which contain the general
purpose registers and the Special Function Registers
(SFR). The SFR’s are located in the first 32 locations of
each Bank. There are general purpose registers implemented as static RAM in each Bank. Table 4-1 lists the
general purpose register available in each of the four
banks.
TABLE 4-1: GENERAL PURPOSE STATIC
RAM REGISTERS
PIC16F627A/628A PIC16F648A
Bank0 20-7Fh 20-7Fh
Bank1 A0h-FF A0h-FF
Bank2 120h-14Fh, 170h-17Fh 120h-17Fh
Bank3 1F0h-1FFh 1F0h-1FFh
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
Table 4-2 lists how to access the four banks of registers
via the STATUS Register bits RP1 and RP0.
TABLE 4-2: ACCESS TO BANKS OF
REGISTERS
Interrupt Vector
On-chip Program
Memory
PIC16F627A,
PIC16F628A and
PIC16F648A
On-chip Program
Memory
PIC16F628A and
PIC16F648A
On-chip Program
Memory
PIC16F648A only
0004
0005
03FFh
07FFh
0FFFh
1FFFh
RP1 RP0
Bank0 00
Bank1 01
Bank2 10
Bank3 11
4.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 224 x 8 in the
PIC16F627A/628A and 256 x 8 in the PIC16F648A.
Each is accessed either directly or indirectly through
the File Select Register (FSR), See Section 4.4.
2002 Microchip Technology Inc. Preliminary DS40044A-page 15
PIC16F627A/628A/648A
FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A
File
Address
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CMCON
General
Purpose
Register
80 Bytes
16 Bytes
Bank 0
PCL
FSR
TRISB
(1)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
1EFh
1F0h
1FFh
TMR0
PCL
FSR
(1)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
11Fh
120h
14Fh
150h
16Fh
170h
17Fh
Indirect addr.
OPTION
STATUS
PCLATH
INTCON
accesses
70h - 7Fh
Bank 3
PCL
FSR
TRISA
TRISB
PIE1
PCON
PR2
(1)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
(1)
9Dh
9Eh
9Fh
A0h
EFh
F0h
FFh
Indirect addr.
STATUS
PORTB
PCLATH
INTCON
General
Purpose
Register
48 Bytes
accesses
70h-7Fh
Bank 2
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
6Fh
70h
7Fh
Indirect addr.
OPTION
STATUS
PCLATH
INTCON
TXSTA
SPBRG
EEDATA
EEADR
EECON1
EECON2
VRCON
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS40044A-page 16 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A
File
Address
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CMCON
General
Purpose
Register
80 Bytes
16 Bytes
Bank 0
PCL
FSR
TRISB
(1)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
1EFh
1F0h
1FFh
TMR0
PCL
FSR
(1)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
11Fh
120h
16Fh
170h
17Fh
Indirect addr.
OPTION
STATUS
PCLATH
INTCON
accesses
70h - 7Fh
Bank 3
PCL
FSR
TRISA
TRISB
PIE1
PCON
PR2
(1)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
(1)
9Dh
9Eh
9Fh
A0h
EFh
F0h
FFh
Indirect addr.
STATUS
PORTB
PCLATH
INTCON
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 2
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
6Fh
70h
7Fh
Indirect addr.
OPTION
STATUS
PCLATH
INTCON
TXSTA
SPBRG
EEDATA
EEADR
EECON1
EECON2
VRCON
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2002 Microchip Technology Inc. Preliminary DS40044A-page 17
PIC16F627A/628A/648A
4.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0
Val ue o n
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR
Reset
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28
01h TMR0 Timer0 module’s Register xxxx xxxx 45
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28
03h STATUS
04h FSR Indirect data memory address pointer xxxx xxxx 28
05h PORTA
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 36
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 28
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24
0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 48
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 48
10h T1CON
11h TMR2 TMR2 module’s register 0000 0000 52
12h T2CON
13h — Unimplemented — —
14h — Unimplemented — —
15h CCPR1L Capture/Compare/PWM register (LSB) xxxx xxxx 55
16h CCPR1H Capture/Compare/PWM register (MSB) xxxx xxxx 55
17h CCP1CON
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 69
19h TXREG USART Transmit data register 0000 0000 76
1Ah RCREG USART Receive data register 0000 0000 79
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh — Unimplemented — —
1Fh CMCON C2OUT C1OUT
IRP RP1 RP0 TO
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 31
EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 26
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 48
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 55
C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61
PD ZDC C
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
0001 1xxx 22
(1)
Details
Page
on
DS40044A-page 18 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK1
(1)
Details
Page
Val ue on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR
Reset
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical
81h OPTION RBPU
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28
83h STATUS IRP RP1 RP0 TO
84h FSR Indirect data memory address pointer xxxx xxxx 28
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 31
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 36
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 25
8Dh — Unimplemented — —
8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 52
93h — Unimplemented — —
94h — Unimplemented — —
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
99h SPBRG Baud Rate Generator Register 0000 0000 71
9Ah EEDATA EEPROM data register xxxx xxxx 89
9Bh EEADR EEPROM address register xxxx xxxx 90
9Ch EECON1
9Dh EECON2 EEPROM control register 2 (not a physical register) ---- ---- 90
9Eh — Unimplemented — —
9Fh VRCON VREN VROE VRR
register)
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23
PD ZDCC0001 1xxx 22
— — — Write buffer for upper 5 bits of program counter ---0 0000 28
— — — — OSCF — POR BOR ---- 1-0x 27
— BRGH TRMT TX9D 0000 -010 71
— — — — WRERR WREN WR RD ---- x000 90
— VR3 VR2 VR1 VR0 000- 0000 67
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
xxxx xxxx 28
on
2002 Microchip Technology Inc. Preliminary DS40044A-page 19
PIC16F627A/628A/648A
TABLE 4-5: SPECIAL FUNCTION REGISTERS SUMMARY BANK2
(1)
Details
Page
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR
Reset
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28
101h TMR0
102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28
103h STATUS IRP RP1 RP0 TO
104h FSR Indirect data memory address pointer xxxx xxxx 28
105h — Unimplemented — —
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 36
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah PCLATH
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24
10Ch — Unimplemented — —
10Dh — Unimplemented — —
10Eh — Unimplemented — —
10Fh — Unimplemented — —
110h — Unimplemented — —
111h — Unimplemented — —
112h — Unimplemented — —
113h — Unimplemented — —
114h — Unimplemented — —
115h — Unimplemented — —
116h — Unimplemented — —
117h — Unimplemented — —
118h — Unimplemented — —
119h — Unimplemented — —
11A h — Unimplemented — —
11B h — Unimplemented — —
11C h — Unimplemented — —
11D h — Unimplemented — —
11E h — Unimplemented — —
11Fh — Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented.
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
Timer0 module’s Register xxxx xxxx
PD ZDCC0001 1xxx
— — — Write buffer for upper 5 bits of program counter ---0 0000 28
on
45
22
DS40044A-page 20 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 4-6: SPECIAL FUNCTION REGISTERS SUMMARY BANK3
(1)
Details
Page
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR
Reset
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28
181h OPTION RBPU
182h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28
183h STATUS IRP RP1 RP0 TO
184h FSR Indirect data memory address pointer xxxx xxxx 28
185h — Unimplemented — —
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 36
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah PCLATH
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24
18Ch — Unimplemented — —
18Dh — Unimplemented — —
18Eh — Unimplemented — —
18Fh — Unimplemented — —
190h — Unimplemented — —
191h — Unimplemented — —
192h — Unimplemented — —
193h — Unimplemented — —
194h — Unimplemented — —
195h — Unimplemented — —
196h — Unimplemented — —
197h — Unimplemented — —
198h — Unimplemented — —
199h — Unimplemented — —
19Ah — Unimplemented — —
19Bh — Unimplemented — —
19Ch — Unimplemented — —
19Dh — Unimplemented — —
19Eh — Unimplemented — —
19Fh — Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23
PD ZDCC0001 1xxx 22
— — — Write buffer for upper 5 bits of program counter ---0 0000 28
on
2002 Microchip Technology Inc. Preliminary DS40044A-page 21
PIC16F627A/628A/648A
4.2.2.1 STATUS Register
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU; the RESET status and
the bank select bits for data memory (SRAM).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
and PD bits are non-
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the status register
as “000uu1uu” (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any STATUS bit. For other instructions, not
affecting any STATUS bits, see the “Instruction Set
Summary”.
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow
bit 0 C: Carry/borrow
: Time out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
, the polarity is reversed. A subtraction is executed by adding the two’s
PD ZDCC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 22 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.2 OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION REGISTER (ADDRESS: 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1). See Section 6.3.1.
bit 7 RBPU
: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS40044A-page 23
PIC16F627A/628A/648A
4.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
REGISTER 4-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 24 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.4 PIE1 Register
This register contains interrupt enable bits.
REGISTER 4-4: PIE1 REGISTER (ADDRESS: 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
EEIE CMIE RCIE TXIE
bit 7 bit 0
bit 7 EEIE: EE Write Complete Interrupt Enable Bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
— CCP1IE TMR2IE TMR1IE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS40044A-page 25
PIC16F627A/628A/648A
4.2.2.5 PIR1 Register
This register contains interrupt flag bits.
REGISTER 4-5: PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
EEIF CMIF RCIF TXIF
bit 7 bit 0
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed
0 = Comparator output has not changed
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
— CCP1IF TMR2IF TMR1IF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 26 Preliminary 2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.6 PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR
WDT Reset or a Brown-out Reset.
Reset,
REGISTER 4-6: PCON REGISTER (ADDRESS: 8Eh)
U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-0 R/W-x
— — — — OSCF —PORBOR
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 OSCF: INTOSC oscillator frequency
1 = 4 MHz typical
0 = 37 kHz typical
bit 2 Unimplemented: Read as '0'
bit 1 POR
bit 0 BOR
: Power-on Reset STATUS bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset STATUS bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR
cleared, indicating a brown-out has
occurred. The BOR
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
clearing the BOREN bit in the
Configuration word).
STATUS bit is a “don't
is
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS40044A-page 27
PIC16F627A/628A/648A
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 4-4 shows
the two situations for loading the PC. The upper example in Figure 4-4 shows how the PC is loaded on a write
to PCL (PCLATH<4:0> → PCH). The lower example in
Figure 4-4 shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-4: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
PCLATH
11
8
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
4.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a nooperation (although STATUS bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-5.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
application note “Implementing a Table Read” (AN556).
4.3.2 STACK
The PIC16F627A/628A/648A family has an 8-level
deep x 13-bit wide hardware stack (Figure 4-1). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not affected by a
PUSH or POP operation.
EXAMPLE 4-1: Indirect Addressing
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
;yes continue
DS40044A-page 28 Preliminary 2002 Microchip Technology Inc.
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