PIC16(L)F18856/76
Full-Featured 28/40/44-Pin Microcontrollers
Description
PIC16(L)F18856/76 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The family will feature the CRC/SCAN, Hardware Limit Timer (HLT) and Windowed Watchdog Timer (WWDT) to support
customers looking to add safety to their application. Additionally, this family includes up to 28 KB of Flash memory, along
with a 10-bit ADC with Computation (ADC
application.
2
) extensions for automated signal analysis to reduce the complexity of the
Core Features
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Three 8-Bit Timers (TMR2/4/6) with Hardware
Limit Timer (HLT) Extensions
• Four 16-Bit Timers (TMR0/1/3/5)
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR) with Fast Recovery
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
• Programmable Code Protection
Memory
• Up to 28 KB Flash Program Memory
• Up to 2 KB Data SRAM
• 256B of EEPROM
• Direct, Indirect and Relative Addressing modes
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF18856/76)
- 2.3V to 5.5V (PIC16F18856/76)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Functionality
• DOZE mode: Ability to run the CPU core slower
than the system clock
• IDLE mode: Ability to halt CPU core while internal
peripherals continue operating
• Sleep mode: Lowest Power Consumption
• Peripheral Module Disable (PMD):
- Ability to disable hardware module to
minimize power consumption of unused
peripherals
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
-8 A @ 32 kHz, 1.8V, typical
-32 A/MHz @ 1.8V, typical
Digital Peripherals
• Four Configurable Logic Cells (CLC):
- Integrated combinational and sequential logic
• Three Complementary Waveform Generators
(CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Five Capture/Compare/PWM (CCP) module:
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• 10-bit PWM:
- Two 10-bit PWMs
• Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control and
increased frequency resolution
- Input Clock: 0 Hz < F
- Resolution: F
• Two Signal Measurement Timers (SMT):
- 24-bit Signal Measurement Timer
- Up to 12 different Acquisition modes
NCO
/2
20
NCO
< 32 MHz
2016-2019 Microchip Technology Inc. DS40001824E-page 1
PIC16(L)F18856/76
Digital Peripherals (Cont.)
• Cyclical Redundancy Check (CRC/SCAN):
- 16-bit CRC
- Scans memory for NVM integrity
• Communication:
- EUSART, RS-232, RS-485, LIN compatible
-Two SPI
2
-Two I
• Up to 36 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
- Current mode enable
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• Data Signal Modulator (DSM)
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
C, SMBus, PMBus™ compatible
Analog Peripherals
• Analog-to-Digital Converter with Computation
(ADC2):
- 10-bit with up to 35 external channels
- Automated post-processing
- Automates math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Operates in Sleep
• Two Comparators (COMP):
- Fixed Voltage Reference at (non) inverting
input(s)
- Comparator outputs externally accessible
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
Flexible Oscillator Structure
• High-Precision Internal Oscillator:
- Software selectable frequency range up to 32
MHz, ±1% typical
• x2/x4 PLL with Internal and External Sources
• Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
• External Oscillator Block with:
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
• Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator
resources
2016-2019 Microchip Technology Inc. DS40001824E-page 2
PIC16(L)F18856/76
PIC16(L)F188XX Family Types
(ch)
2
(1)
Device
Program Flash
Program Flash
Memory (Words)
Data Sheet Index
PIC16(L)F18854 (1) 4096 7 256 512 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18855 (2) 8192 14 256 1024 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18856 (3) 16384 28 256 2048 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18857 (4) 32768 56 256 4096 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18875 (2) 8192 14 256 1024 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18876 (3) 16384 28 256 2048 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18877 (4) 32768 56 256 4096 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
Note 1: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document)
1: DS40001826 PIC16(L)F18854 Data Sheet, 28-Pin, Full-Featured 8-bit Microcontrollers
2: DS40001802 PIC16(L)F18855/75 Data Sheet, 28/40-Pin, Full-Featured 8-bit Microcontrollers
3: DS40001824 PIC16(L)F18856/76 Data Sheet, 28/40-Pin, Full-Featured 8-bit Microcontrollers
4: DS40001825 PIC16(L)F18857/77 Data Sheet, 28/40-Pin, Full-Featured 8-bit Microcontrollers
EEPROM
Memory (KB)
(bytes)
(bytes)
Data SRAM
I/O Pins
10-Bit ADC
5-Bit DAC
Comparator
SMT
Windowed
16-Bit Timers
8-Bit (with HLT)/
Watchdog Timer
CCP/10-Bit PWM
CRC and Memory Scan
Zero-Cross Detect
NCO
CWG
C/SPI
2
CLC
DSM
EUSART/I
Peripheral Pin Select
Disable
Peripheral Module
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
2016-2019 Microchip Technology Inc. DS40001824E-page 3
PIC16(L)F18856/76
Note 1: See Table 2 for location of all peripheral functions.
2: All V
DD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins
to float may result in degraded electrical performance or non-functionality.
PIC16(L)F18856
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RB6
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
VSS
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
V
SS
RA7
RA6
RC0
RC1
RC2
RC3
RC5
RC4
RC7
RC6
RB7
28-pin SPDIP, SOIC, SSOP
TABLE 1: PACKAGES
Packages (S)PDIP SOIC SSOP
PIC16(L)F18856
QFN
(6x6)
PIC16(L)F18876
Note: Pin details are subject to change.
PIN DIAGRAMS
UQFN
(4x4)
VQFN
(4x4)
TQFP
QFN
(8x8)
UQFN
(5x5)
2016-2019 Microchip Technology Inc. DS40001824E-page 4
PIC16(L)F18856/76
Note 1: See Table 2 for location of all peripheral functions.
2: All V
DD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN/VQFN package should be connected to V
SS at the circuit board level.
2
3
6
1
18
19
20
21
15
7
16
17
RC0
5
4
RB7
RB6
RB5
RB4
RB0
V
DD
VSS
RC7
RC6
RC5
RC4
RE3/MCLR
/VPP
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
RC1
RC2
RC3
9
10
13814
12
11
27
26
232822
24
25
RB3
RB2
RB1
PIC16(L)F18856
28-pin QFN (6x6), UQFN (4x4), VQFN (4x4)
Note 1: See Table 3 for location of all peripheral function.
2: All V
DD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
PIC16(L)F18876
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
RB6/ICSPCLK
RB5
RB4
RB0
V
DD
VSS
RD2
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD0
RD1
RC5
RC4
RD3
RD4
RC7
RC6
RD7
RD6
RD5
RB7/ICSPDAT
1
RB3
RB2
RB1
40-pin PDIP
2016-2019 Microchip Technology Inc. DS40001824E-page 5
PIC16(L)F18856/76
Note 1: See Table 3 for location of all peripheral functions.
2: All V
DD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN package should be connected to V
SS at the circuit board level.
10
11
2
3
4
5
6
1
181920
21
22
121314
15
38
8
7
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
37
RA1
RA0
V
PP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA6
RA7
V
SS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
V
SS
VDD
RB0
RB1
RB2
PIC16(L)F18876
RA3
RA2
40-pin UQFN (5x5)
Note 1: See Table 3 for location of all peripheral functions.
2: All V
DD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
10
11
2
3
6
1
1819202122
121314
15
38
8
7
44
43
42
414039
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
37
5
4
PIC16(L)F18876
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA1
AN0/RA0
V
PP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
NC
RA3
RA2
RC7
RD4
RD5
RD6
RD7
V
SS
VDD
RB0
RB1
RB2
RA6
RA7
V
SS
NC
V
DD
RE2
RE1
RE0
RA5
RA4
NC
NC
44-pin TQFP (10x10)
2016-2019 Microchip Technology Inc. DS40001824E-page 6
PIC16(L)F18856/76
Note 1: See Table 3 for location of all peripheral functions.
2: All V
DD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN package should be connected to V
SS at the circuit board level.
10
11
2
3
4
5
6
1
181920
21
22
121314
15
38
8
7
4443424140
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
37
RA0
V
PP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA6
RA7
NC
V
SS
NC
V
DD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
V
SS
VDD
NC
RB0
RB1
RB2
PIC16(L)F18876
RA3
RA2
RA1
44-pin QFN (8x8)
2016-2019 Microchip Technology Inc. DS40001824E-page 7
2016-2019 Microchip Technology Inc. DS40001824E-page 8
PIN ALLOCATION TABLES
PIC16(L)F18856/76
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18856)
C)
2
I/O
ADC
DAC
Comparators
Voltage Reference
28-Pin QFN/UQFN/VQFN
28-Pin SPDIP/SOIC/SSOP
RA0 2 27 ANA0 — — C1IN0-
RA1 3 28 ANA1
— —C1IN1-
C2IN0-
EUSART
Zero-Cross Detect
MSSP (SPI/I
DSM
Timers/SMT
CCP and PWM
CWG
— — — — — — — CLCIN0
— — — — — — —CLCIN1
CLC
NCO
Clock Reference (CLKR)
(1)
— — IOCA0 —
(1)
— —IOCA1 —
Basic
Interrupt-on-Change
C2IN1-
RA2 4 1 ANA2 VREF- DAC1OUT1 C1IN0+
RA3 5 2 ANA3 V
REF+ —C1IN1+— — — MDCARL
C2IN0+
RA4 6 3 ANA4 — — — — — — MDCARH
RA5 7 4 ANA5
— — — — SS1
RA6 10 7 ANA6 — — — — — — — — — — — — — IOCA6 OSC2
RA7 9 6 ANA7
— — — — — — — — — — — — —IOCA7OSC1
— — — — — — — — — — IOCA2 —
(1)
—MDSRC
(1)
(1)
(1)
— — — — — —IOCA3 —
T0CKI
(1)
CCP5
(1)
— — — — IOCA4 —
— — — — — —IOCA5 —
CLKOUT
CLKIN
SCK2
SDI2
(1)
— — — CCP4
(3,4)
—— — —CWG2IN
(1)
(3,4)
— — — — CWG3IN
(1)
(1)
SMTWIN2
(1)
RB0 21 18 ANB0 — — C2IN1+ ZCD SS2
RB1 22 19 ANB1 — — C1IN3-
—SCL2
C2IN3-
RB2 23 20 ANB2 — — — — SDA2
RB3 24 21 ANB3 — — C1IN2-
RB4 25 22 ANB4
ADCACT
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which PORT pins may
be used for this signal.
— — — — — — — T5G
(1)
C2IN2-
—— — — — — — ———IOCB3—
(1)
CWG1IN
(1)
— — — INT
(1)
———IOCB1—
(1)
— — — IOCB2 —
(1)
IOCB0
— — — — — IOCB4 —
—
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I
2
C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
2
C specific or SMbus input buffer thresholds.
2016-2019 Microchip Technology Inc. DS40001824E-page 9
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18856) (CONTINUED)
C)
2
PIC16(L)F18856/76
I/O
28-Pin QFN/UQFN/VQFN
28-Pin SPDIP/SOIC/SSOP
RB5 26 23 ANB5 — — — — — — — T1G
ADC
DAC
Voltage Reference
Zero-Cross Detect
Comparators
MSSP (SPI/I
EUSART
DSM
Timers/SMT
(1)
SMTSIG2
CWG
CCP and PWM
(1)
CCP3
(1)
————IOCB5—
RB6 27 24 ANB6 — — — — — — — — — — CLCIN2
RB7 28 25 ANB7 — DAC1OUT2 — — — — — T6IN
RC0 11 8 ANC0 — — — — — — — T1CKI
T3CKI
(1)
T3G
SMTWIN1
RC1 12 9 ANC1 — — — — — — — SMTSIG1
RC2 13 10 ANC2 — — — — — — — T5CKI
(3,4)
RC3 14 11 ANC3 — — — — SCL1
SCK1
RC4 15 12 ANC4 — — — — SDA1
SDI1
—— T2IN
(1)
(3,4)
— — — — — — — — IOCC4 —
(1)
RC5 16 13 ANC5 — — — — — — — T4IN
(1)
(1)
(1)
(1)
(1)
(1)
(1)
— — CLCIN3
— — — — — IOCC0 SOSCO
(1)
(1)
CCP2
CCP1
(1)
— — — — IOCC1 SOSCI
— — — — IOCC2 —
—————IOCC3—
—————IOCC5—
CLC
NCO
Clock Reference (CLKR)
(1)
— — IOCB6 ICSPCLK
(1)
— — IOCB7 ICSPDAT
Basic
Interrupt-on-Change
RC6 17 14 ANC6 — — — — — CK(3) — — — — — — — IOCC6 —
RC7 18 15 ANC7 — — — — — RX
DT
(1)
(3)
———————IOCC7 —
RE3 1 26 — — — — — — — — — — — — — — IOCE3 MCLR
VPP
VDD 20 17 — — — — — — — — — — — — — — — —
VSS 8, 195,
— — — — — — — — — — — — — — — —
16
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which PORT pins may
be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I
2
C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
2
C specific or SMbus input buffer thresholds.
2016-2019 Microchip Technology Inc. DS40001824E-page 10
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18856) (CONTINUED)
C)
2
PIC16(L)F18856/76
I/O
28-Pin QFN/UQFN/VQFN
28-Pin SPDIP/SOIC/SSOP
(2)
OUT
—— ADGRDA
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which PORT pins may
be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I
ADC
ADGRDB
DAC
Voltage Reference
——C1OUT
2
C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
Comparators
C2OUT
Zero-Cross Detect
—SDO1
SCK1
SDO2
SCK2
MSSP (SPI/I
EUSART
TX/
(3)
CK
(3)
DT
DSM
Timers/SMT
DSM TMR0 CCP1
2
C specific or SMbus input buffer thresholds.
CCP and PWM
CCP2
CCP3
CCP4
CCP5
PWM6OUT
PWM7OUT
CWG
CWG1A
CWG1B
CWG1C
CWG1D
CWG2A
CWG2B
CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
CLC
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
NCO
Interrupt-on-Change
Clock Reference (CLKR)
NCO CLKR — —
Basic
2016-2019 Microchip Technology Inc. DS40001824E-page 11
TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18876)
C)
2
PIC16(L)F18856/76
!/O
40-Pin UQFN
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
ADC
DAC
Comparators
Voltage Reference
RA0 2 17 19 19 ANA0 — — C1IN0-
C2IN0-
RA1 3 18 20 20 ANA1 — — C1IN1-
EUSART
MSSP (SPI/I
Zero-Cross Detect
DSM
Timers/SMT
CCP and PWM
CWG
— — — — — — — CLCIN0
—— — — — — —CLCIN1
CLC
NCO
Clock Reference (CLKR)
(1)
— — IOCA0 —
(1)
——IOCA1 —
Basic
Interrupt-on-Change
C2IN1-
RA2 4 19 21 21 ANA2 VREF- DAC1OUT1 C1IN0+
RA3 5 20 22 22 ANA3 V
REF+ — C1IN1+ — — — MDCARL
C2IN0+
RA4 6 21 23 23 ANA4 — — — — — — MDCARH
RA5 7 22 24 24 ANA5 — — — — SS1
RA6 14 29 33 31 ANA6 — — — — — — — — — — — — — IOCA6 OSC2
— — — — — — — — — — IOCA2 —
(1)
——————IOCA3—
(1)
— MDSRC
(1)
(1)
T0CKI
(1)
CCP5
(1)
— — — — IOCA4 —
——————IOCA5—
CLKOUT
RA7 13 28 32 30 ANA7 — — — — — — — — — — — — — IOCA7 OSC1
CLKIN
SCK2
SDI2
(1)
— — — CCP4
(3,4)
— — — — CWG2IN
(1)
(3,4)
— — — — CWG3IN
(1)
(1)
SMTWIN2
SMTSIG2
(1)
(1)
(1)
RB0 33 8 9 8 ANB0 — — C2IN1+ ZCD SS2
RB1 34 9 10 9 ANB1 — — C1IN3-
C2IN3-
—SCL2
RB2 35 10 11 10 ANB2 — — — — SDA2
RB3 36 11 12 11 ANB3 — — C1IN2-
RB4 37 12 14 14 ANB4
ADCACT
— — — — — — — T5G
(1)
C2IN2-
—— — — — — — — ——IOCB3—
RB5 38 13 15 15 ANB5 — — — — — — — T1G
RB6 39 14 16 16 ANB6 — — — — — — — — — — CLCIN2
RB7 40 15 17 17 ANB7 — DAC1OUT2 — — — — — T6IN
(1)
(1)
CWG1IN
(1)
— — — INT
(1)
———IOCB1—
(1)
— — — IOCB2 —
IOCB0
(1)
— — — — — IOCB4 —
CCP3(1) — — — — IOCB5 —
(1)
— — IOCB6 ICSPCLK
— — CLCIN3
(1)
——IOCB7ICSPDAT
—
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 13-1 for details on which PORT pins may
be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I
2
C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
2
C specific or SMbus input buffer thresholds.
2016-2019 Microchip Technology Inc. DS40001824E-page 12
TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18876) (CONTINUED)
C)
2
PIC16(L)F18856/76
!/O
40-Pin PDIP
44-Pin QFN
40-Pin UQFN
RC0 15 30 34 32 ANC0 — — — — — — — T1CKI
44-Pin TQFP
ADC
DAC
Voltage Reference
Comparators
Zero-Cross Detect
MSSP (SPI/I
EUSART
DSM
T3CKI
T3G
Timers/SMT
SMTWIN1
RC1 16 31 35 35 ANC1 — — — — — — — SMTSIG1
RC2 17 32 36 36 ANC2 — — — — — — — T5CKI
RC3 18 33 37 37 ANC3 — — — — SCL1
RC4 23 38 42 42 ANC4 — — — — SDA1
SCK1
SDI1
(3,4)
—— T2IN
(1)
(3,4)
— — — — — — — — IOCC4 —
(1)
RC5 24 39 43 43 ANC5 — — — — — — — T4IN
DT
(3)
— — — — — — — IOCC6 —
(1)
— — — — — — — IOCC7 —
(3)
RC6 25 40 44 44 ANC6 — — — — — CK
RC7 26 1 1 1 ANC7 — — — — — RX
CWG
CCP and PWM
(1)
(1)
(1)
(1)
(1)
(1)
— — — — — IOCC0 SOSCO
(1)
(1)
CCP2
CCP1
(1)
(1)
— — — — IOCC1 SOSCI
— — — — IOCC2 —
— — — — — IOCC3 —
— — — — — IOCC5 —
CLC
NCO
Interrupt-on-Change
Clock Reference (CLKR)
Basic
RD0 19 34 38 38 AND0 — — — — — — — — — — — — — — —
RD1 20 35 39 39 AND1 — — — — — — — — — — — — — — —
RD2 21 36 40 40 AND2 — — — — — — — — — — — — — — —
RD3 22 37 41 41 AND3 — — — — — — — — — — — — — — —
RD4 27 2 2 2 AND4 — — — — — — — — — — — — — — —
RD5 28 3 3 3 AND5 — — — — — — — — — — — — — — —
RD6 29 4 4 4 AND6 — — — — — — — — — — — — — — —
RD7 30 5 5 5 AND7 — — — — — — — — — — — — — — —
RE0 8 23 25 25 ANE0 — — — — — — — — — — — — — — —
RE1 9 24 26 26 ANE1 — — — — — — — — — — — — — — —
RE2 10 25 27 27 ANE2 — — — — — — — — — — — — — — —
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 13-1 for details on which PORT pins may
be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I
2
C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
2
C specific or SMbus input buffer thresholds.
2016-2019 Microchip Technology Inc. DS40001824E-page 13
TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18876) (CONTINUED)
C)
2
PIC16(L)F18856/76
!/O
40-Pin PDIP
RE3 1 16 18 18 — — — — — — — — — — — — — — IOCE3 MCLR
VDD 11 , 327, 267, 287,
SS 12,
V
31
(2)
OUT
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 13-1 for details on which PORT pins may
— — — — ADGRDA
be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I
44-Pin QFN
40-Pin UQFN
28
6, 276, 306,
29
ADC
44-Pin TQFP
— — — — — — — — — — — — — — — —
—— — ————— — — — —————
ADGRDB
Voltage Reference
— — C1OUT
2
C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
DAC
Comparators
C2OUT
Zero-Cross Detect
— SDO1
SCK1
SDO2
SCK2
EUSART
MSSP (SPI/I
TX/
(3)
CK
(3)
DT
2
C specific or SMbus input buffer thresholds.
DSM
DSM TMR0 CCP1
Timers/SMT
CCP and PWM
CCP2
CCP3
CCP4
CCP5
PWM6OUT
PWM7OUT
CWG
CWG1A
CWG1B
CWG1C
CWG1D
CWG2A
CWG2B
CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
CLC
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
NCO
Interrupt-on-Change
Clock Reference (CLKR)
VPP
NCO CLKR — —
Basic
PIC16(L)F18856/76
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 16
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 33
3.0 Memory Organization ................................................................................................................................................................. 35
4.0 Device Configuration .................................................................................................................................................................. 91
5.0 Resets ...................................................................................................................................................................................... 100
6.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 109
7.0 Interrupts .................................................................................................................................................................................. 128
8.0 Power-Saving Operation Modes .............................................................................................................................................. 154
9.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 161
10.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 169
11.0 Cyclic Redundancy Check (CRC) Module ............................................................................................................................... 187
12.0 I/O Ports ................................................................................................................................................................................... 199
13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 234
14.0 Peripheral Module Disable ....................................................................................................................................................... 244
15.0 Interrupt-On-Change ................................................................................................................................................................ 251
16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 259
17.0 Temperature Indicator Module ................................................................................................................................................. 262
18.0 Comparator Module.................................................................................................................................................................. 264
19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 274
20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 281
21.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 305
22.0 Configurable Logic Cell (CLC).................................................................................................................................................. 311
23.0 Analog-to-Digital Converter With Computation (ADC2) Module............................................................................................... 328
24.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 366
25.0 5-Bit Digital-to-Analog Converter (DAC1) Module .................................................................................................................... 376
26.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 381
27.0 Timer0 Module ......................................................................................................................................................................... 394
28.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 400
29.0 Timer2/4/6 Module ................................................................................................................................................................... 414
30.0 Capture/Compare/PWM Modules ............................................................................................................................................ 435
31.0 Master Synchronous Serial Port (MSSP) Modules .................................................................................................................. 448
32.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 499
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 544
34.0 Reference Clock Output Module .............................................................................................................................................. 572
35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 576
36.0 Instruction Set Summary .......................................................................................................................................................... 578
37.0 Electrical Specifications............................................................................................................................................................ 592
38.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 622
39.0 Development Support............................................................................................................................................................... 638
40.0 Packaging Information.............................................................................................................................................................. 642
Appendix A: Data Sheet Revision History......................................................................................................................................... 671
2016-2019 Microchip Technology Inc. DS40001824E-page 14
PIC16(L)F18856/76
TO OUR VALUED CUSTOMERS
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2016-2019 Microchip Technology Inc. DS40001824E-page 15
PIC16(L)F18856/76
1.0 DEVICE OVERVIEW
The PIC16(L)F18856/76 are described within this data
sheet. The PIC16(L)F18856 devices are available in
28-pin SPDIP, SSOP, SOIC, QFN, UQFN and VQFN
packages. The PIC16(L)F18876 devices are available in
40-pin PDIP and UQFN and 44-pin TQFP and QFN
packages.
Figure 1-1 shows a block diagram of the
PIC16(L)F18856/76 devices. Ta bl e 1 - 2 and Table 1-3
show the pinout descriptions.
Reference Ta b le 1 - 1 for peripherals available per device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F18856
Analog-to-Digital Converter with Computation (ADC2) ●●
Cyclic Redundancy Check (CRC) ●●
Digital-to-Analog Converter (DAC) ●●
Fixed Voltage Reference (FVR) ●●
Enhanced Universal Synchronous/Asynchronous Receiver/
Transmitter (EUSART1)
Digital Signal Modulator (DSM) ●●
Numerically Controlled Oscillator (NCO1) ●●
Temperature Indicator ●●
Zero-Cross Detect (ZCD) ●●
Capture/Compare/PWM (CCP/ECCP) Modules
Comparators
Configurable Logic Cell (CLC)
Complementary Waveform Generator (CWG)
Master Synchronous Serial Ports
MSSP1 ●●
MSSP2 ●●
Pulse-Width Modulator (PWM)
Signal Measure Timer (SMT)
Timers
●●
CCP1 ●●
CCP2 ●●
CCP3 ●●
CCP4 ●●
CCP5 ●●
C1 ●●
C2 ●●
CLC1 ●●
CLC2 ●●
CLC3 ●●
CLC4 ●●
CWG1 ●●
CWG2 ●●
CWG3 ●●
PWM6 ●●
PWM7 ●●
SMT1 ●●
SMT2 ●●
Timer0 ●●
Timer1 ●●
Timer2 ●●
Timer3 ●●
Timer4 ●●
Timer5 ●●
Timer6 ●●
PIC16(L)F18856
2016-2019 Microchip Technology Inc. DS40001824E-page 16
PIC16(L)F18856/76
1.1 Register and Bit naming conventions
1.1.1 REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance, and control identifier.
The control registers section will show just one
instance of all the register names with an ‘x’ in the place
of the peripheral instance number. This naming
convention may also be applied to peripherals when
there is only one instance of that peripheral in the
device to maintain compatibility with other devices in
the family that contain more than one.
1.1.2 BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.1.2.1 Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.1.2.2 Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
1.1.2.3 Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW ~(1<<G1MD1)
ANDWF COG1CON0,F
MOVLW 1<<G1MD2 | 1<<G1MD0
IORWF COG1CON0,F
Example 2:
BSF COG1CON0,G1MD2
BCF COG1CON0,G1MD1
BSF COG1CON0,G1MD0
1.1.3 REGISTER AND BIT NAMING EXCEPTIONS
1.1.3.1 Status, Interrupt, and Mirror Bits
Status, interrupt enables, interrupt flags, and mirror bits
are contained in registers that span more than one
peripheral. In these cases, the bit name shown is
unique so there is no prefix or short name variant.
1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
to these naming conventions. Peripherals that have
existed for many years and are present in almost every
device are the exceptions. These exceptions were
necessary to limit the adverse impact of the new
conventions on legacy code. Peripherals that do
adhere to the new convention will include a table in the
registers section indicating the long name prefix for
each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
peripherals include, but are not limited to, the following:
• EUSART
• MSSP
2016-2019 Microchip Technology Inc. DS40001824E-page 17
2016-2019 Microchip Technology Inc. DS40001824E-page 18
Rev. 10-000039J
11/20/2015
CLKIN/
OSC1
RAM
CPU
(Note 3)
Timing
Generation
INTRC
Oscillator
MCLR
Program
Flash Memory
FVR
ADC
10-bit
Temp
Indicator
TMR0TMR1TMR2
CCPs(5)PWM6/7
ZCD1CWG1
PORTA
DACC1CRCTMR4TMR6 C2
SMT2 SMT1
PORTC
PORTB
CLC1CLC2CLC3CLC4
TMR5 TMR3 Scanner
MSSP1MSSP2EUSART
DSM
NCO1
CLKOUT
/OSC2
PORTD
(4)
PORTE
CWG2 CWG3
Note 1: See applicable chapters for more information on peripherals.
2: See Tab l e 1 -1 for peripherals available on specific devices.
3: See Figure 2-1.
4: PIC16(L)F18876 only.
FIGURE 1-1: PIC16(L)F18856/76 BLOCK DIAGRAM
PIC16(L)F18856/76
PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION
Name Function
RA0/ANA0/C1IN0-/C2IN0-/CLCIN0
IOCA0
(1)
/
RA0 TTL/ST CMOS/OD General purpose I/O.
ANA0 AN — ADC Channel A0 input.
C1IN0- AN — Comparator negative input.
C2IN0- AN — Comparator negative input.
(1)
CLCIN0
IOCA0 TTL/ST — Interrupt-on-change input.
RA1/ANA1/C1IN1-/C2IN1-/CLCIN1
IOCA1
(1)
/
RA1 TTL/ST CMOS/OD General purpose I/O.
ANA1 AN — ADC Channel A1 input.
C1IN1- AN — Comparator negative input.
C2IN1- AN — Comparator negative input.
(1)
CLCIN1
IOCA1 TTL/ST — Interrupt-on-change input.
RA2/ANA2/C1IN0+/C2IN0+/V
DAC1OUT1/IOCA2
REF-/
RA2 TTL/ST CMOS/OD General purpose I/O.
ANA2 AN — ADC Channel A2 input.
C1IN0+ AN — Comparator positive input.
C2IN0+ AN — Comparator positive input.
REF- AN — External ADC and/or DAC negative reference input.
V
DAC1OUT1 — AN Digital-to-Analog Converter output.
IOCA2 TTL/ST — Interrupt-on-change input.
RA3/ANA3/C1IN1+/VREF+/MDCARL
IOCA3
(1)
/
RA3 TTL/ST CMOS/OD General purpose I/O.
ANA3 AN — ADC Channel A3 input.
C1IN1+ AN — Comparator positive input.
V
REF+ AN — External ADC and/or DAC positive reference input.
MDCARL
IOCA3 TTL/ST — Interrupt-on-change input.
(1)
RA4/ANA4/MDCARH
(1)
CCP5
/IOCA4
/T0CKI
(1)
/
RA4 TTL/ST CMOS/OD General purpose I/O.
ANA4 AN — ADC Channel A4 input.
MDCARH
(1)
T0CKI
(1)
CCP5
IOCA4 TTL/ST — Interrupt-on-change input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
HV = High Voltage XTAL = Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
Input
Typ e
Output Type Description
TTL/ST — Configurable Logic Cell source input.
TTL/ST — Configurable Logic Cell source input.
(1)
TTL/ST — Modular Carrier input 1.
(1)
TTL/ST — Modular Carrier input 2.
TTL/ST — Timer0 clock input.
TTL/ST CMOS/OD Capture/compare/PWM5 (default input location for capture
function).
2
C = Schmitt Trigger input with I2C
2016-2019 Microchip Technology Inc. DS40001824E-page 19
PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Input
Typ e
RA5/ANA5/SS1
Name Function
(1)
/MDSRC
(1)
/IOCA5 RA5 TTL/ST CMOS/OD General purpose I/O.
ANA5 AN — ADC Channel A5 input.
(1)
SS1
MDSRC
TTL/ST — MSSP1 SPI slave select input.
(1)
TTL/ST — Modulator Source input.
IOCA5 TTL/ST — Interrupt-on-change input.
RA6/ANA6/OSC2/CLKOUT/IOCA6 RA6 TTL/ST CMOS/OD General purpose I/O.
ANA6 AN — ADC Channel A6 input.
OSC2 — XTAL External Crystal/Resonator (LP, XT, HS modes) driver output.
CLKOUT — CMOS/OD F
IOCA6 TTL/ST — Interrupt-on-change input.
RA7/ANA7/OSC1/CLKIN/IOCA7 RA7 TTL/ST CMOS/OD General purpose I/O.
ANA7 AN — ADC Channel A7 input.
OSC1 XTAL — External Crystal/Resonator (LP, XT, HS modes) driver input.
CLKIN TTL/ST — External digital clock input.
IOCA7 TTL/ST — Interrupt-on-change input.
RB0/ANB0/C2IN1+/ZCD/SS2
CCP4
(1)
/CWG1IN
(1)
(1)
/INT
/IOCB0
(1)
RB0 TTL/ST CMOS/OD General purpose I/O.
/
ANB0 AN — ADC Channel B0 input.
C2IN1+ AN — Comparator positive input.
ZCD AN AN Zero-cross detect input pin.
(1)
SS2
(1)
CCP4
CWG1IN
(1)
INT
TTL/ST — MSSP2 SPI slave select input.
TTL/ST CMOS/OD Capture/compare/PWM4 (default input location for capture
(1)
TTL/ST — Complementary Waveform Generator 1 input.
TTL/ST — External interrupt request input.
IOCB0 TTL/ST — Interrupt-on-change input.
(3,4)
RB1/ANB1/C1IN3-/C2IN3-/SCL2
SCK2
(1)
/CWG2IN
(1)
/IOCB1
RB1 TTL/ST CMOS/OD General purpose I/O.
/
ANB1 AN — ADC Channel B1 input.
C1IN3- AN — Comparator negative input.
C2IN3- AN — Comparator negative input.
(3,4)
SCL2
I2C/
SMBus
(1)
SCK2
CWG2IN
TTL/ST CMOS/OD MSSP2 SPI serial clock (default input location, SCK2 is a PPS
(1)
TTL/ST — Complementary Waveform Generator 2 input.
IOCB1 TTL/ST — Interrupt-on-change input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
HV = High Voltage XTAL = Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
Output Type Description
OSC/4 digital output (in non-crystal/resonator modes).
function).
OD MSSP2 I2C clock input/output.
remappable input and output).
2
C = Schmitt Trigger input with I2C
2016-2019 Microchip Technology Inc. DS40001824E-page 20
PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Input
Typ e
I2C/
SMBus
TTL/ST — MSSP2 SPI serial data input.
TTL/ST — Complementary Waveform Generator 3 input.
RB2/ANB2/SDA2
(1)
CWG3IN
/IOCB2
Name Function
(3,4)
(1)
/SDI2
/
RB2 TTL/ST CMOS/OD General purpose I/O.
ANB2 AN — ADC Channel B2 input.
(3,4)
SDA2
(1)
SDI2
(1)
CWG3IN
IOCB2 TTL/ST — Interrupt-on-change input.
RB3/ANB3/C1IN2-/C2IN2-/IOCB3 RB3 TTL/ST CMOS/OD General purpose I/O.
ANB3 AN — ADC Channel B3 input.
C1IN2- AN — Comparator negative input.
C2IN2- AN — Comparator negative input.
IOCB3 TTL/ST — Interrupt-on-change input.
RB4/ANB4/ADCACT
SMTWIN2
(1)
/IOCB4
/T5G
(1)
/
RB4 TTL/ST CMOS/OD General purpose I/O.
ANB4 AN — ADC Channel B4 input.
(1)
ADCACT
(1)
T5G
SMTWIN2
TTL/ST — ADC Auto-Conversion Trigger input.
TTL/ST — Timer5 gate input.
(1)
TTL/ST — Signal Measurement Timer 2 (SMT2) window input.
(1)
IOCB4 TTL/ST — Interrupt-on-change input.
RB5/ANB5/T1G
(1)
/IOCB5
CCP3
(1)
/SMTSIG2
(1)
/
RB5 TTL/ST CMOS/OD General purpose I/O.
ANB5 AN — ADC Channel B5 input.
(1)
T1G
SMTSIG2
(1)
CCP3
TTL/ST — Timer1 gate input.
(1)
TTL/ST — Signal Measurement Timer 2 (SMT2) signal input.
TTL/ST CMOS/OD Capture/compare/PWM3 (default input location for capture
IOCB5 TTL/ST — Interrupt-on-change input.
RB6/ANB6/CLCIN2
(1)
/IOCB6/ICSPCLK RB6 TTL/ST CMOS/OD General purpose I/O.
ANB6 AN — ADC Channel B6 input.
(1)
CLCIN2
TTL/ST — Configurable Logic Cell source input.
IOCB6 TTL/ST — Interrupt-on-change input.
ICSPCLK ST — In-Circuit Serial Programming™ and debugging clock input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
Output Type Description
OD MSSP2 I2C serial data input/output.
function).
2
C = Schmitt Trigger input with I2C
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PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Name Function
RB7/ANB7/DAC1OUT2/T6IN
(1)
CLCIN3
/IOCB7/ICSPDAT
(1)
/
RB7 TTL/ST CMOS/OD General purpose I/O.
ANB7 AN — ADC Channel B7 input.
Input
Typ e
DAC1OUT2 — AN Digital-to-Analog Converter output.
(1)
T6IN
CLCIN3
TTL/ST — Timer6 external digital clock input.
(1)
TTL/ST — Configurable Logic Cell source input.
IOCB7 TTL/ST — Interrupt-on-change input.
ICSPDAT ST CMOS In-Circuit Serial Programming™ and debugging data input/out-
(1)
(1)
RC0/ANC0/T1CKI(1)/T3CKI
SMTWIN1
(1)
/IOCC0/SOSCO
/T3G
RC0 TTL/ST CMOS/OD General purpose I/O.
/
ANC0 AN — ADC Channel C0 input.
(1)
T1CKI
(1)
T3CKI
(1)
T3G
SMTWIN1
TTL/ST — Timer1 external digital clock input.
TTL/ST — Timer3 external digital clock input.
TTL/ST — Timer3 gate input.
(1)
TTL/ST — Signal Measurement Timer1 (SMT1) input.
IOCC0 TTL/ST — Interrupt-on-change input.
SOSCO — AN 32.768 kHz secondary oscillator crystal driver output.
(1)
RC1/ANC1/SMTSIG1
IOCC1/SOSCI
/CCP2
(1)
/
RC1 TTL/ST CMOS/OD General purpose I/O.
ANC1 AN — ADC Channel C1 input.
SMTSIG1
CCP2
(1)
TTL/ST — Signal Measurement Timer1 (SMT1) signal input.
(1)
TTL/ST CMOS/OD Capture/compare/PWM2 (default input location for capture
IOCC1 TTL/ST — Interrupt-on-change input.
SOSCI AN — 32.768 kHz secondary oscillator crystal driver input.
(1)
RC2/ANC2/T5CKI
(1)
/CCP1
/IOCC2 RC2 TTL/ST CMOS/OD General purpose I/O.
ANC2 AN — ADC Channel C2 input.
(1)
T5CKI
CCP1
(1)
TTL/ST — Timer5 external digital clock input.
TTL/ST CMOS/OD Capture/compare/PWM1 (default input location for capture
IOCC2 TTL/ST — Interrupt-on-change input.
RC3/ANC3/SCL1
IOCC3
(3,4)
/SCK1
(1)
/T2IN
(1)
/
RC3 TTL/ST CMOS/OD General purpose I/O.
ANC3 AN — ADC Channel C3 input.
(3,4)
SCL1
SCK1
T2IN
(1)
(1)
I2C/
SMBus
TTL/ST CMOS/OD MSSP1 SPI clock input/output (default input location, SCK1 is a
TTL/ST — Timer2 external input.
IOCC3 TTL/ST — Interrupt-on-change input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
Output Type Description
put.
function).
function).
OD MSSP1 I2C clock input/output.
PPS remappable input and output).
2
C = Schmitt Trigger input with I2C
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PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Input
Typ e
RC4/ANC4/SDA1
Name Function
(3,4)
(1)
/SDI1
/IOCC4 RC4 TTL/ST CMOS/OD General purpose I/O.
ANC4 AN — ADC Channel C4 input.
SDA1
SDI1
(3,4)
(1)
I2C/
SMBus
TTL/ST — MSSP1 SPI serial data input.
IOCC4 TTL/ST — Interrupt-on-change input.
RC5/ANC5/T4IN
(1)
/IOCC5 RC5 TTL/ST CMOS/OD General purpose I/O.
ANC5 AN — ADC Channel C5 input.
T4IN
(1)
TTL/ST — Timer4 external input.
IOCC5 TTL/ST — Interrupt-on-change input.
(3)
RC6/ANC6/CK
/IOCC6 RC6 TTL/ST CMOS/OD General purpose I/O.
ANC6 AN — ADC Channel C6 input.
(3)
CK
TTL/ST CMOS/OD EUSART synchronous mode clock input/output.
IOCC6 TTL/ST — Interrupt-on-change input.
(1)
(3)
/DT
RC7/ANC7/RX
/IOCC7 RC7 TTL/ST CMOS/OD General purpose I/O.
ANC7 AN — ADC Channel C7 input.
RX
DT
(1)
(3)
TTL/ST — EUSART Asynchronous mode receiver data input.
TTL/ST CMOS/OD EUSART Synchronous mode data input/output.
IOCC7 TTL/ST — Interrupt-on-change input.
RE3/IOCE3/MCLR
/VPP RE3 TTL/ST — General purpose input only (when MCLR is disabled by the
IOCE3 TTL/ST — Interrupt-on-change input.
MCLR
V
PP HV — ICSP™ High-Voltage Programming mode entry input.
V
DD VDD Power — Positive supply voltage input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
ST — Master clear input with internal weak pull up resistor.
Output Type Description
OD MSSP1 I2C serial data input/output.
Configuration bit).
2
C = Schmitt Trigger input with I2C
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PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Name Function
VSS VSS Power — Ground reference.
(2)
OUT
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
ADGRDA — CMOS/OD ADC Guard Ring A output.
ADGRDB — CMOS/OD ADC Guard Ring B output.
C1OUT — CMOS/OD Comparator 1 output.
C2OUT — CMOS/OD Comparator 2 output.
SDO1 — CMOS/OD MSSP1 SPI serial data output.
SCK1 — CMOS/OD MSSP1 SPI serial clock output.
SDO2 — CMOS/OD MSSP2 SPI serial data output.
SCK2 — CMOS/OD MSSP2 SPI serial clock output.
TX — CMOS/OD EUSART Asynchronous mode transmitter data output.
(3)
CK
(3)
DT
DSM — CMOS/OD Data Signal Modulator output.
TMR0 — CMOS/OD Timer0 output.
CCP1 — CMOS/OD Capture/Compare/PWM1 output (compare/PWM functions).
CCP2 — CMOS/OD Capture/Compare/PWM2 output (compare/PWM functions).
CCP3 — CMOS/OD Capture/Compare/PWM3 output (compare/PWM functions).
CCP4 — CMOS/OD Capture/Compare/PWM4 output (compare/PWM functions).
CCP5 — CMOS/OD Capture/Compare/PWM5 output (compare/PWM functions).
PWM6OUT — CMOS/OD PWM6 output.
PWM7OUT — CMOS/OD PWM7 output.
CWG1A — CMOS/OD Complementary Waveform Generator 1 output A.
CWG1B — CMOS/OD Complementary Waveform Generator 1 output B.
CWG1C — CMOS/OD Complementary Waveform Generator 1 output C.
CWG1D — CMOS/OD Complementary Waveform Generator 1 output D.
CWG2A — CMOS/OD Complementary Waveform Generator 2 output A.
CWG2B — CMOS/OD Complementary Waveform Generator 2 output B.
CWG2C — CMOS/OD Complementary Waveform Generator 2 output C.
CWG2D — CMOS/OD Complementary Waveform Generator 2 output D.
CWG3A — CMOS/OD Complementary Waveform Generator 3 output A.
CWG3B — CMOS/OD Complementary Waveform Generator 3 output B.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
Input
Typ e
Output Type Description
— CMOS/OD EUSART Synchronous mode clock output.
— CMOS/OD EUSART Synchronous mode data output.
2
C = Schmitt Trigger input with I2C
2016-2019 Microchip Technology Inc. DS40001824E-page 24
PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Name Function
(2)
OUT
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
CWG3C — CMOS/OD Complementary Waveform Generator 3 output C.
CWG3D — CMOS/OD Complementary Waveform Generator 3 output D.
CLC1OUT — CMOS/OD Configurable Logic Cell 1 output.
CLC2OUT — CMOS/OD Configurable Logic Cell 2 output.
CLC3OUT — CMOS/OD Configurable Logic Cell 3 output.
CLC4OUT — CMOS/OD Configurable Logic Cell 4 output.
NCO1 — CMOS/OD Numerically Controller Oscillator output.
CLKR — CMOS/OD Clock Reference module output.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
Input
Typ e
Output Type Description
2
C = Schmitt Trigger input with I2C
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PIC16(L)F18856/76
TABLE 1-3: PIC16F18876 PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RA0/ANA0/C1IN0-/C2IN0-/
(1)
CLCIN0
RA1/ANA1/C1IN1-/C2IN1-/
CLCIN1
RA2/ANA2/C1IN0+/C2IN0+/V
(1)
/IOCA0
/IOCA1
REF-/
DAC1OUT1/IOCA2
RA3/ANA3/C1IN1+/V
(1)
MDCARL
RA4/ANA4/MDCARH
(1)
/IOCA4
CCP5
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
High Voltage XTAL= Crystal levels
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
REF+/
/IOCA3
(1)
/T0CKI
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
as described in Table 13-3.
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
RA0 TTL/ST CMOS/OD General purpose I/O.
ANA0 AN — ADC Channel A0 input.
C1IN0- AN — Comparator negative input.
C2IN0- AN — Comparator negative input.
(1)
CLCIN0
TTL/ST — Configurable Logic Cell source input.
IOCA0 TTL/ST — Interrupt-on-change input.
RA1 TTL/ST CMOS/OD General purpose I/O.
ANA1 AN — ADC Channel A1 input.
C1IN1- AN — Comparator negative input.
C2IN1- AN — Comparator negative input.
(1)
CLCIN1
TTL/ST — Configurable Logic Cell source input.
IOCA1 TTL/ST — Interrupt-on-change input.
RA2 TTL/ST CMOS/OD General purpose I/O.
ANA2 AN — ADC Channel A2 input.
C1IN0+ AN — Comparator positive input.
C2IN0+ AN — Comparator positive input.
V
REF- AN — External ADC and/or DAC negative reference input.
DAC1OUT1 — AN Digital-to-Analog Converter output.
IOCA2 TTL/ST — Interrupt-on-change input.
RA3 TTL/ST CMOS/OD General purpose I/O.
ANA3 AN — ADC Channel A3 input.
C1IN1+ AN — Comparator positive input.
V
REF+ AN — External ADC and/or DAC positive reference input.
(1)
MDCARL
TTL/ST — Modular Carrier input 1.
IOCA3 TTL/ST — Interrupt-on-change input.
(1)
/
RA4 TTL/ST CMOS/OD General purpose I/O.
ANA4 AN — ADC Channel A4 input.
T0CKI
CCP5
(1)
TTL/ST — Modular Carrier input 2.
(1)
(1)
TTL/ST — Timer0 clock input.
TTL/ST CMOS/OD Capture/compare/PWM5 (default input location for capture
function).
MDCARH
IOCA4 TTL/ST — Interrupt-on-change input.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
2
C = Schmitt Trigger input with I2CHV=
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PIC16(L)F18856/76
TABLE 1-3: PIC16F18876 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
RA5/ANA5/SS1
(1)
RA6/ANA6/OSC2/CLKOUT/IOCA6 RA6 TTL/ST CMOS/OD General purpose I/O.
RA7/ANA7/OSC1/CLKIN/IOCA7 RA7 TTL/ST CMOS/OD General purpose I/O.
RB0/ANB0/C2IN1+/ZCD/SS2
(1)
/CWG1IN
CCP4
RB1/ANB1/C1IN3-/C2IN3-/SCL2
(1)
/CWG2IN
SCK2
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
High Voltage XTAL= Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
/MDSRC
(1)
/INT
(1)
/IOCB1
(1)
/IOCA5 RA5 TTL/ST CMOS/OD General purpose I/O.
ANA5 AN — ADC Channel A5 input.
(1)
SS1
MDSRC
(1)
TTL/ST — MSSP1 SPI slave select input.
TTL/ST — Modulator Source input.
IOCA5 TTL/ST — Interrupt-on-change input.
ANA6 AN — ADC Channel A6 input.
OSC2 — XTAL External Crystal/Resonator (LP, XT, HS modes) driver out-
CLKOUT — CMOS/OD F
put.
OSC/4 digital output (in non-crystal/resonator modes).
IOCA6 TTL/ST — Interrupt-on-change input.
ANA7 AN — ADC Channel A7 input.
OSC1 XTAL — External Crystal/Resonator (LP, XT, HS modes) driver input.
CLKIN TTL/ST — External digital clock input.
IOCA7 TTL/ST — Interrupt-on-change input.
(1)
/IOCB0
(1)
RB0 TTL/ST CMOS/OD General purpose I/O.
/
ANB0 AN — ADC Channel B0 input.
C2IN1+ AN — Comparator positive input.
ZCD AN AN Zero-cross detect input pin.
(1)
SS2
(1)
CCP4
CWG1IN
(1)
INT
(1)
TTL/ST — MSSP2 SPI slave select input.
TTL/ST CMOS/OD Capture/compare/PWM4 (default input location for capture
function).
TTL/ST — Complementary Waveform Generator 1 input.
TTL/ST — External interrupt request input.
IOCB0 TTL/ST — Interrupt-on-change input.
(3,4)
RB1 TTL/ST CMOS/OD General purpose I/O.
/
ANB1 AN — ADC Channel B1 input.
C1IN3- AN — Comparator negative input.
C2IN3- AN — Comparator negative input.
(3,4)
SCL2
(1)
SCK2
CWG2IN
(1)
I2C/SMBus OD MSSP2 I2C clock input/output.
TTL/ST CMOS/OD MSSP2 SPI serial clock (default input location, SCK2 is a
PPS remappable input and output).
TTL/ST — Complementary Waveform Generator 2 input.
IOCB1 TTL/ST — Interrupt-on-change input.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
2
C specific or SMBus input buffer thresholds.
2
C = Schmitt Trigger input with I2CHV=
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PIC16(L)F18856/76
TABLE 1-3: PIC16F18876 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
(3,4)
RB2/ANB2/SDA2
(1)
CWG3IN
/IOCB2
/SDI2
(1)
/
RB3/ANB3/C1IN2-/C2IN2-/IOCB3 RB3 TTL/ST CMOS/OD General purpose I/O.
(1)
RB4/ANB4/ADCACT
SMTWIN2
RB5/ANB5/T1G
CCP3
RB6/ANB6/CLCIN2
ICSPCLK
RB7/ANB7/DAC1OUT2/T6IN
CLCIN3
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
(1)
/IOCB4
(1)
(1)
/IOCB5
(1)
/SMTSIG2
/IOCB7/ICSPDAT
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
High Voltage XTAL= Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
/T5G
(1)
/IOCB6/
(1)
/
(1)
(1)
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
RB2 TTL/ST CMOS/OD General purpose I/O.
ANB2 AN — ADC Channel B2 input.
(3,4)
SDA2
(1)
SDI2
CWG3IN
(1)
I2C/SMBus OD MSSP2 I2C serial data input/output.
TTL/ST — MSSP2 SPI serial data input.
TTL/ST — Complementary Waveform Generator 3 input.
IOCB2 TTL/ST — Interrupt-on-change input.
ANB3 AN — ADC Channel B3 input.
C1IN2- AN — Comparator negative input.
C2IN2- AN — Comparator negative input.
IOCB3 TTL/ST — Interrupt-on-change input.
RB4 TTL/ST CMOS/OD General purpose I/O.
ANB4 AN — ADC Channel B4 input.
(1)
ADCACT
(1)
T5G
SMTWIN2
(1)
TTL/ST — ADC Auto-Conversion Trigger input.
TTL/ST — Timer5 gate input.
TTL/ST — Signal Measurement Timer2 (SMT2) window input.
IOCB4 TTL/ST — Interrupt-on-change input.
RB5 TTL/ST CMOS/OD General purpose I/O.
/
ANB5 AN — ADC Channel B5 input.
(1)
T1G
SMTSIG2
(1)
CCP3
(1)
TTL/ST — Timer1 gate input.
TTL/ST — Signal Measurement Timer2 (SMT2) signal input.
TTL/ST CMOS/OD Capture/compare/PWM3 (default input location for capture
function).
IOCB5 TTL/ST — Interrupt-on-change input.
RB6 TTL/ST CMOS/OD General purpose I/O.
ANB6 AN — ADC Channel B6 input.
(1)
CLCIN2
TTL/ST — Configurable Logic Cell source input.
IOCB6 TTL/ST — Interrupt-on-change input.
ICSPCLK ST — In-Circuit Serial Programming™ and debugging clock input.
RB7 TTL/ST CMOS/OD General purpose I/O.
/
ANB7 AN — ADC Channel B7 input.
DAC1OUT2 — AN Digital-to-Analog Converter output.
(1)
T6IN
CLCIN3
(1)
TTL/ST — Timer6 external digital clock input.
TTL/ST — Configurable Logic Cell source input.
IOCB7 TTL/ST — Interrupt-on-change input.
ICSPDAT ST CMOS In-Circuit Serial Programming™ and debugging data input/
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
output.
2
C = Schmitt Trigger input with I2CHV=
2016-2019 Microchip Technology Inc. DS40001824E-page 28
PIC16(L)F18856/76
TABLE 1-3: PIC16F18876 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
(1)
(1)
(1)
RC0/ANC0/T1CKI
SMTWIN1
RC1/ANC1/SMTSIG1
IOCC1/SOSCI
(1)
RC2/ANC2/T5CKI
RC3/ANC3/SCL1
(1)
/IOCC3
T2IN
RC4/ANC4/SDA1
RC5/ANC5/T4IN
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
/T3CKI
/T3G
/IOCC0/SOSCO
(1)
/CCP2
(1)
(1)
/CCP1
/IOCC2 RC2 TTL/ST CMOS/OD General purpose I/O.
(3,4)
(3,4)
(1)
(1)
/SCK1
/
(1)
/SDI1
/IOCC4 RC4 TTL/ST CMOS/OD General purpose I/O.
/IOCC5 RC5 TTL/ST CMOS/OD General purpose I/O.
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
High Voltage XTAL= Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
as described in Table 13-3.
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
RC0 TTL/ST CMOS/OD General purpose I/O.
/
ANC0 AN — ADC Channel C0 input.
(1)
T1CKI
(1)
T3CKI
(1)
T3G
SMTWIN1
(1)
TTL/ST — Timer1 external digital clock input.
TTL/ST — Timer3 external digital clock input.
TTL/ST — Timer3 gate input.
TTL/ST — Signal Measurement Timer1 (SMT1) input.
IOCC0 TTL/ST — Interrupt-on-change input.
SOSCO — AN 32.768 kHz secondary oscillator crystal driver output.
(1)
/
RC1 TTL/ST CMOS/OD General purpose I/O.
ANC1 AN — ADC Channel C1 input.
SMTSIG1
CCP2
(1)
(1)
TTL/ST — Signal Measurement Timer1 (SMT1) signal input.
TTL/ST CMOS/OD Capture/compare/PWM2 (default input location for capture
function).
IOCC1 TTL/ST — Interrupt-on-change input.
SOSCI AN — 32.768 kHz secondary oscillator crystal driver input.
ANC2 AN — ADC Channel C2 input.
(1)
T5CKI
CCP1
(1)
TTL/ST — Timer5 external digital clock input.
TTL/ST CMOS/OD Capture/compare/PWM1 (default input location for capture
function).
IOCC2 TTL/ST — Interrupt-on-change input.
RC3 TTL/ST CMOS/OD General purpose I/O.
ANC3 AN — ADC Channel C3 input.
(3,4)
SCL1
SCK1
T2IN
(1)
(1)
I2C/SMBus OD MSSP1 I2C clock input/output.
TTL/ST CMOS/OD MSSP1 SPI clock input/output (default input location, SCK1
is a PPS remappable input and output).
TTL/ST — Timer2 external input.
IOCC3 TTL/ST — Interrupt-on-change input.
ANC4 AN — ADC Channel C4 input.
(3,4)
SDA1
SDI1
(1)
I2C/SMBus OD MSSP1 I2C serial data input/output.
TTL/ST — MSSP1 SPI serial data input.
IOCC4 TTL/ST — Interrupt-on-change input.
ANC5 AN — ADC Channel C5 input.
(1)
T4IN
TTL/ST — Timer4 external input.
IOCC5 TTL/ST — Interrupt-on-change input.
2
C = Schmitt Trigger input with I2CHV=
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
2016-2019 Microchip Technology Inc. DS40001824E-page 29
PIC16(L)F18856/76
TABLE 1-3: PIC16F18876 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
RC6/ANC6/CK
RC7/ANC7/RX
RD0 RD0 TTL/ST CMOS/OD General purpose I/O.
RD1 RD1 TTL/ST CMOS/OD General purpose I/O.
RD2 RD2 TTL/ST CMOS/OD General purpose I/O.
RD3 RD3 TTL/ST CMOS/OD General purpose I/O.
RD4 RD4 TTL/ST CMOS/OD General purpose I/O.
RD5 RD5 TTL/ST CMOS/OD General purpose I/O.
RD6 RD6 TTL/ST CMOS/OD General purpose I/O.
RD7 RD7 TTL/ST CMOS/OD General purpose I/O.
RE0 RE0 TTL/ST CMOS/OD General purpose I/O.
RE1 RE1 TTL/ST CMOS/OD General purpose I/O.
RE2 RE2 TTL/ST CMOS/OD General purpose I/O.
RE3/IOCE3/MCLR
V
DD VDD Power — Positive supply voltage input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
(3)
/IOCC6 RC6 TTL/ST CMOS/OD General purpose I/O.
ANC6 AN — ADC Channel C6 input.
(3)
CK
IOCC6 TTL/ST — Interrupt-on-change input.
(1)
(3)
/DT
/IOCC7 RC7 TTL/ST CMOS/OD General purpose I/O.
ANC7 AN — ADC Channel C7 input.
(1)
RX
(3)
DT
IOCC7 TTL/ST — Interrupt-on-change input.
AND0 AN — ADC Channel D0 input.
AND1 AN — ADC Channel D1 input.
AND2 AN — ADC Channel D2 input.
AND3 AN — ADC Channel D3 input.
AND4 AN — ADC Channel D4 input.
AND5 AN — ADC Channel D5 input.
AND6 AN — ADC Channel D6 input.
AND7 AN — ADC Channel D7 input.
ANE0 AN — ADC Channel E0 input.
ANE1 AN — ADC Channel E1 input.
ANE2 AN — ADC Channel E2 input.
/VPP RE3 TTL/ST — General purpose input-only (when MCLR is disabled by
IOCE3 TTL/ST — Interrupt-on-change input.
MCLR
PP HV — ICSP™ high voltage programming mode entry input.
V
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
High Voltage XTAL= Crystal levels
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I
2
C specific or SMBus input buffer thresholds.
2
C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
TTL/ST CMOS/OD EUSART synchronous mode clock input/output.
TTL/ST — EUSART Asynchronous mode receiver data input.
TTL/ST CMOS/OD EUSART Synchronous mode data input/output.
config bit).
ST — Master clear input with internal weak pull-up resistor.
2
C = Schmitt Trigger input with I2CHV=
2016-2019 Microchip Technology Inc. DS40001824E-page 30
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