Datasheet PIC16F1826, PIC16F1827, PIC16LF1826 Datasheet

PIC16(L)F1826/27

Data Sheet

18/20/28-Pin Flash Microcontrollers

with nanoWatt XLP Technology

 2011 Microchip Technology Inc. DS41391D

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-124-7

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41391D-page 2  2011 Microchip Technology Inc.

PIC16(L)F1826/27

18/20/28-Pin Flash Microcontrollers wit h na noWatt XLP Techno logy

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• 256 bytes Data EEPROM

• Up to 8 Kbytes Linear Program Memory
Addressing

• Up to 384 bytes Linear Data Memory Addressing

• Interrupt Capability with Automatic Context Saving

• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Struc ture:

• Precision 32 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%, typical

- Software selectable frequencies range of

31 kHz to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• Four Crystal modes up to 32 MHz

• Three External Clock modes up to 32 MHz

• 4X Phase-Lock Loop (PLL)

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

• Two-Speed Oscillator Start-up

• Reference Clock Module:

- Programmable clock output frequency and

duty-cycle

Special Microcontroller Features:

• 1.8V-5.5V Operation – PIC16F1826/27

• 1.8V-3.6V Operation – PIC16LF1826/27

• Self-Programmable under Software Control

• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)

• Programmable Brown-out Reset (BOR)

• Extended Watchdog Timer (WDT):

- Programmable period from 1ms to 268s

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via
two pins

• In-Circuit Debug (ICD) via two pins

• Enhance Low-Voltage Programming

• Power-Saving Sleep mode

Extreme Low-Power Management PIC16LF1826/27 with nanoWatt XLP:

• Operating Current: 75 A @ 1 MHz, 1.8V, typical

• Sleep mode: 30 nA

• Watchdog Timer: 500 nA

• Timer1 Oscillator: 600 nA @ 32 kHz

Analog Features:

• Analog-to-Digital Converter (ADC) Module:

- 10-bit resolution, 12 channels

- Auto acquisition capability

- Conversion available during Sleep

• Analog Comparator Module:

- Two rail-to-rail analog comparators

- Power mode control

- Software controllable hysteresis

• Voltage Reference Module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection

Peripheral Highlight s:

• 15 I/O Pins and 1 Input Only Pin:

- High current sink/source 25 mA/25 mA

- Programmable weak pull-ups

- Programmable interrupt-on- change pins

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated, low-power 32 kHz oscillator driver

• Up to three Timer2-types: 8-Bit Timer/Counter with
8-Bit Period Register, Prescaler and Postscaler

• Up to two Capture, Compare, PWM (CCP) Modules

• Up to two Enhanced CCP (ECCP) Modules:

- Software selectable time bases

- Auto-shutdown and auto-restart

- PWM steering

• Up to two Master Synchronous Serial Port
(MSSP) with SPI and I

- 7-bit address masking

- SMBus/PMBus

• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) Module

• mTouch™ Sensing Oscillator Module:

- Up to 12 input channels

• Data Signal Modulator Module:

- Selectable modulator and carrier sources

•SR Latch:

- Multiple Set/Reset input options

- Emulates 555 Timer applications

2

CTM with:

TM

compatibility

 2011 Microchip Technology Inc. DS41391D-page 3

PIC16(L)F1826/27

PDIP, SOIC

PIC16(L)F1826/27

1

2

3

4

18

17

16

15

5

6

7

14

13

12

RA2

RA3

RA4

RA5/MCLR

/VPP

VSS

RB0

RB1

RA1

RA0

RA7

RA6

V

DD

RB7

RB6

8

9

11

10

RB2

RB3

RB5

RB4

SSOP

PIC16(L)F1826/27

1

2

3

4

20

19

18

17

5

7

8

16

14

13

RA2

RA3

RA4

RA5/MCLR

/VPP

VSS

RB0

RB1

RA1

RA0

RA7

RA6

V

DD

RB7

RB6

9

10

12

11

RB2

RB3

RB5

RB4

6

15

VSS

VDD

PIC16(L)F1826/27 Family Types

Program

Memory

Device

Words

Data

Memory

SRAM

(bytes)

(1)

I/O’s

(bytes)

10-bit ADC (ch)

CapSense (ch)

Comparators

Timers (8/16-bit)

Data EEPROM

MSSP

EUSART

ECCP (Full-Bridge)

CCP

SR Latch

ECCP (Half-Bridge)

PIC16LF1826 2K 256 256 16 12 12 2 2/1 1 1 1 — — Yes
PIC16F1826 2K 256 256 16 12 12 2 2/1 1 1 1 — — Yes
PIC16LF1827 4K 38425616121224/112112Yes
PIC16F1827 4K 384 256 16 12 12 2 4/1 1 2 1 1 2 Yes

Note 1: One pin is input only.

Pin Diagram – 18-Pin PDIP, SOIC

(PIC16(L)F1826/27)

Pin Diagram – 20-Pin SSOP (PIC16(L)F1826/27)

DS41391D-page 4  2011 Microchip Technology Inc.

Pin Diagram – 28-Pin QFN/UQFN (PIC16(L)F1826/27)

PIC16(L)F1826/27

RA2

RA3

RA4

RA5/MCLR/VPP

VSS

RB0

RB1

RA1

RA0

RA7
RA6
V

DD

RB7
RB6

RB2

RB3

RB5

RB4

VSS

VDD

NC

NC

282726

25

24

23

1

2
3

4
5

6
7

8

9

10

11

22

21
20
19
18
17
16
15

14

13

12

NC

NC

NC

NC

NC

NC

QFN/UQFN

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 5

DS41391D-page 6  2011 Microchip Technology Inc.

TABLE 1: 18/20/28-PIN SUMMARY (PIC16(L)F1826/27)

18-Pin PDIP/SOIC

I/O

28-Pin QFN/UQFN

20-Pin SSOP

ANSEL

A/D

Reference

Cap Sense

Comparator

SR Latch

Timers

CCP

EUSART

MSSP

Interrupt

Modulator

Pull-up

Basic

PIC16(L)F1826/27

RA0 17 19 23 Y AN0 — CPS0 C12IN0- — — — — SDO2

RA1 18 20 24 Y AN1 — CPS1 C12IN1- — — — — SS2

RA2 1 1 26 Y AN2 VREF-

DACOUT

RA3 2 2 27 Y AN3 VREF+ CPS3 C12IN3-

CPS2 C12IN2-

C12IN+

— — — — — — — N —

SRQ — CCP3

(2)

— — — — N —

(2)

(2)

— — N —

— — N —

C1IN+

C1OUT

P2B

CCP2

P2A

P1A

(1)

(1,2)

(1)
(1,2)

(1,2)

(1)

(2)

— — — — N —

— SDO1

(1)

(1)

— — Y

— — N OSC2

(3)

MCLR, VPP

CLKOUT

— — — — N OSC1

(1)

— — INT

IOC

— Y —

RA4 3 3 28 Y AN4 — CPS4 C2OUT SRNQ T0CKI CCP4

RA5 4 4 1 N — — — — — — — — SS1

RA6 15 17 20 N — — — — — — P1D

RA7 16 18 21 N — — — — — — P1C

RB0 6 7 7 N — — — — SRI T1G CCP1

FLT0

RB1 7 8 8 Y AN11 — CPS11 — — — — RX

RB2 8 9 9 Y AN10 — CPS10 — — — — RX

RB3 9 10 10 Y AN9 — CPS9 — — — CCP1

P1A

(1,4)

(1,4)

RB4 10 11 12 Y AN8 — CPS8 — — — — — SCL1

DT

TX
CK

(1,4)
(1,4)

(1)

,DT

(1,4)
(1,4)

SDA1

SDI1

(1)

SDA2

SDI2

(1,4)

SDO1

IOC — Y —

(2)

IOC MDMIN Y —

(2)

— — IOC MDOUT Y —

IOC MDCIN2 Y —

SCK1

RB5 11 12 13 Y AN7 — CPS7 — — — P1B TX

RB6 12 13 15 Y AN5 — CPS5 — — T1CKI

T1OSI

RB7 13 14 16 Y AN6 — CPS6 — — T1OSO P1D

P1C

CCP2

P2A

P2B

(1,4)
(1,2,4)

(1,2,4)

(1,4)

(1,2,4)

CK

(1)
(1)

— — IOC — Y ICSPCLK/

— — IOC MDCIN1 Y ICSPDAT/

SCL2
SCK2
SS1

(1,4)

(2)

IOC — Y —

(2)

ICDCLK

ICDDAT

VDD 14 15,16 17,19 — — — — — — — — — — — — — VDD

Vss55,63,5———— — —— — — — ——— VSS

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16(L)F1827.
3: Weak pull-up always enabled when MCLR
4: Default function location.

is enabled, otherwise the pull-up is under user control.

CLKR

CLKIN

PIC16(L)F1826/27

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Enhanced Mid-Range CPU........................................................................................................................................................ 15

3.0 Memory Organization................................................................................................................................................................. 17

4.0 Device Configuration.................................................................................................................................................................. 43

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51

6.0 Reference Clock Module............................................................................................................................................................ 69

7.0 Resets ........................................................................................................................................................................................ 73

8.0 Interrupts .................................................................................................................................................................................... 81

9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 95

10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 97

11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 101

12.0 I/O Ports ................................................................................................................................................................................... 117

13.0 Interrupt-on-Change ................................................................................................................................................................. 131

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 135

15.0 Temperature Indicator.............................................................................................................................................................. 137

16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 139

17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 153

18.0 SR Latch................................................................................................................................................................................... 157

19.0 Comparator Module.................................................................................................................................................................. 163

20.0 Timer0 Module ......................................................................................................................................................................... 173

21.0 Timer1 Module ......................................................................................................................................................................... 177

22.0 Timer2/4/6 Modules.................................................................................................................................................................. 191

23.0 Data Signal Modulator (DSM) .................................................................................................................................................. 193

24.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4) Modules ..................................................................................... 203

25.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 231

26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 285

27.0 Capacitive Sensing Module ...................................................................................................................................................... 315

28.0 In-Circuit Serial Programming

29.0 Instruction Set Summary.......................................................................................................................................................... 325

30.0 Electrical Specifications............................................................................................................................................................ 339

31.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 371

32.0 Development Support............................................................................................................................................................... 379

33.0 Packaging Information.............................................................................................................................................................. 383

Appendix A: Revision History............................................................................................................................................................. 393

Appendix B: Device Differences ........................................................................................................................................................ 393

Index .................................................................................................................................................................................................. 395

The Microchip Web Site..................................................................................................................................................................... 403

Customer Change Notification Service .............................................................................................................................................. 403

Customer Support .............................................................................................................................................................................. 403

Reader Response .............................................................................................................................................................................. 404

Product Identification System ............................................................................................................................................................ 405

™ (ICSP™) ................................................................................................................................ 321

 2011 Microchip Technology Inc. DS41391D-page 7

PIC16(L)F1826/27

TO OUR VALUED CUSTOMERS

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DS41391D-page 8  2011 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16(L)F1826/27 are described within this data
sheet. They are available in 18/20/28-pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1826/27 devices. Table 1-2 shows the pinout
descriptions.

Reference Ta bl e 1 -1 for peripherals available per
device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1826/27

PIC16F/LF1826

ADC ●●
Capacitive Sensing Module ●●
Digital-to-Analog Converter (DAC) ●●
Digital Signal Modulator (DSM) ●●
EUSART ●●
Fixed Voltage Reference (FVR) ●●
Reference Clock Module ●●
SR Latch ●●
Capture/Compare/PWM Modules

ECCP1 ●●
ECCP2 ●

CCP3 ●
CCP4 ●

Comparators

C1 ●●
C2 ●●

Master Synchronous Serial Ports

MSSP1 ●●
MSSP2 ●

Timers

Timer0 ●●
Timer1 ●●
Timer2 ●●
Timer4 ●
Timer6 ●

PIC16(L)F1827

 2011 Microchip Technology Inc. DS41391D-page 9

PIC16(L)F1826/27

PORTA

EUSART

Comparators

MSSPx

Timer2-

Timer1Timer0

ECCPx

ADC

10-Bit

CCPx

PORTB

SR

Latch

Note 1: See applicable chapters for more information on peripherals.

2: See Ta bl e 1 -1 for peripherals available on specific devices.

CPU

Program

Flash Memory

EEPROM

RAM

OSC1/CLKIN

OSC2/CLKOUT

Timing

Generation

INTRC

Oscillator

MCLR

(Figure 2-1)

Modulator

CapSense

Clock

CLKR

Reference

Type s

DAC

FVR

FIGURE 1-1: PIC16(L)F1826/27 BLOCK DIAGRAM

DS41391D-page 10  2011 Microchip Technology Inc.

T ABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION

Input

Name Function

Type

Output

Type

PIC16(L)F1826/27

Description

RA0/AN0/CPS0/C12IN0-/

(2)

SDO2

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

CPS0 AN — Capacitive sensing input 0.

C12IN0- AN — Comparator C1 or C2 negative input.

SDO2 — CMOS SPI data output.

(2)

RA1/AN1/CPS1/C12IN1-/SS2

RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

CPS1 AN — Capacitive sensing input 1.

C12IN1- AN — Comparator C1 or C2 negative input.

ST — Slave Select input 2.

RA2/AN2/CPS2/C12IN2-/
C12IN+/V

REF-/DACOUT

SS2

RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

CPS2 AN — Capacitive sensing input 2.

C12IN2- AN — Comparator C1 or C2 negative input.

C12IN+ AN — Comparator C1 or C2 positive input.

REF- AN — A/D Negative Voltage Reference input.

V

DACOUT — AN Voltage Reference output.

RA3/AN3/CPS3/C12IN3-/C1IN+/

REF+/C1OUT/CCP3

V

(2)

/SRQ

RA3 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

CPS3 AN — Capacitive sensing input 3.

C12IN3- AN — Comparator C1 or C2 negative input.

C1IN+ AN — Comparator C1 positive input.

REF+ AN — A/D Voltage Reference input.

V

C1OUT — CMOS Comparator C1 output.

CCP3 ST CMOS Capture/Compare/PWM3.

SRQ — CMOS SR latch non-inverting output.

RA4/AN4/CPS4/C2OUT/T0CKI/

(2)

/SRNQ

CCP4

RA4 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

CPS4 AN — Capacitive sensing input 4.

C2OUT — CMOS Comparator C2 output.

T0CKI ST — Timer0 clock input.

CCP4 ST CMOS Capture/Compare/PWM4.

SRNQ — CMOS SR latch inverting output.

RA5/MCLR

/VPP/SS1

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I

(1,2)

RA5 TTL CMOS General purpose I/O.

MCLR

V

PP HV — Programming voltage.

SS1

ST — Master Clear with internal pull-up.

ST — Slave Select input 1.

2

C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16(L)F1827.
3: Default function location.

 2011 Microchip Technology Inc. DS41391D-page 11

PIC16(L)F1826/27

TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RA6/OSC2/CLKOUT/CLKR/

(1)

P1D

/P2B

(1,2)

/SDO1

(1)

RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

CLKR — CMOS Clock Reference Output.

P1D — CMOS PWM output.

P2B — CMOS PWM output.

SDO1 — CMOS SPI data output 1.

RA7/OSC1/CLKIN/P1C
CCP2

(1,2)

/P2A

(1,2)

/

RA7 TTL CMOS General purpose I/O.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

(1)

CLKIN CMOS — External clock input (EC mode).

P1C — CMOS PWM output.

CCP2 ST CMOS Capture/Compare/PWM2.

P2A — CMOS PWM output.

RB0/T1G/CCP1

/INT/

RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

(1)

(1)

/P1A

SRI/FLT0

T1G ST — Timer1 Gate input.

CCP1 ST CMOS Capture/Compare/PWM1.

P1A — CMOS PWM output.

INT ST — External interrupt.

SRI ST — SR latch input.

FLT0 ST — ECCP Auto-Shutdown Fault input.

RB1/AN11/CPS11/RX

(1,3)

DT

/SDA1/SDI1

/

RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

(1,3)

AN11 AN — A/D Channel 11 input.

CPS11 AN — Capacitive sensing input 11.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

SDA1 I

SDI1 CMOS — SPI data input 1.

RB2/AN10/CPS10/MDMIN/

(1,3)

(1,3)

(1)

TX
SDA2

/CK

(2)

/SDI2

/RX

(2)

/DT

/SDO1

(1)

(1,3)

/

RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN10 AN — A/D Channel 10 input.

CPS10 AN — Capacitive sensing input 10.

MDMIN — CMOS Modulator source input.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

SDA2 I

SDI2 ST — SPI data input 2.

SDO1 — CMOS SPI data output 1.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16(L)F1827.
3: Default function location.

Output

Type

Type

OSC/4 output.

Individually enabled pull-up.

Individually enabled pull-up.

2

C™ OD I2C™ data input/output 1.

Individually enabled pull-up.

2

C™ OD I2C™ data input/output 2.

Description

2

C™ = Schmitt Trigger input with I2C

DS41391D-page 12  2011 Microchip Technology Inc.

PIC16(L)F1826/27

TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB3/AN9/CPS9/MDOUT/
CCP1

(1,3)

/P1A

(1,3)

RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN9 AN — A/D Channel 9 input.

CPS9 AN — Capacitive sensing input 9.

MDOUT — CMOS Modulator output.

CCP1 ST CMOS Capture/Compare/PWM1.

P1A — CMOS PWM output.

RB4/AN8/CPS8/SCL1/SCK1/

RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

MDCIN2

AN8 AN — A/D Channel 8 input.

CPS8 AN — Capacitive sensing input 8.

SCL1 I

SCK1 ST CMOS SPI clock 1.

MDCIN2 ST — Modulator Carrier Input 2.

(1)

(1)

/CK

/

RB5/AN7/CPS7/P1B/TX
SCL2

(2)

/SCK2

(2)

/SS1

(1,3)

RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN7 AN — A/D Channel 7 input.

CPS7 AN — Capacitive sensing input 7.

P1B — CMOS PWM output.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

SCL2 I

SCK2 ST CMOS SPI clock 2.

SS1

RB6/AN5/CPS5/T1CKI/T1OSI/
P1C

(1,3)

/CCP2

(1,2,3)

/P2A

(1,2,3)

ICSPCLK

RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

/

AN5 AN — A/D Channel 5 input.

CPS5 AN — Capacitive sensing input 5.

T1CKI ST — Timer1 clock input.

T1OSO XTAL XTAL Timer1 oscillator connection.

P1C — CMOS PWM output.

CCP2 ST CMOS Capture/Compare/PWM2.

P2A — CMOS PWM output.

ICSPCLK ST — Serial Programming Clock.

RB7/AN6/CPS6/T1OSO/
P1D

(1,3)

/P2B

(1,2,3)

/MDCIN1/

ICSPDAT

RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

AN6 AN — A/D Channel 6 input.

CPS6 AN — Capacitive sensing input 6.

T1OSO XTAL XTAL Timer1 oscillator connection.

P1D — CMOS PWM output.

P2B — CMOS PWM output.

MDCIN1 ST — Modulator Carrier Input 1.

ICSPDAT ST CMOS ICSP™ Data I/O.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16(L)F1827.
3: Default function location.

Output

Type

Type

Individually enabled pull-up.

Individually enabled pull-up.

2

C™ OD I2C™ clock 1.

Individually enabled pull-up.

2

C™ OD I2C™ clock 2.

ST — Slave Select input 1.

Individually enabled pull-up.

Individually enabled pull-up.

Description

2

C™ = Schmitt Trigger input with I2C

 2011 Microchip Technology Inc. DS41391D-page 13

PIC16(L)F1826/27

TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

V

DD VDD Power — Positive supply.

V

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

2: Functions are only available on the PIC16(L)F1827.
3: Default function location.

Type

Output

Type

Description

2

C™ = Schmitt Trigger input with I2C

DS41391D-page 14  2011 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 8.5 “Automatic Context Saving”,
for more information.

PIC16(L)F1826/27

2.2 16-level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under­flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft­ware Reset. See section Section 3.4 “Stack” for more
details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See

Section 3.4 “Stack”for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary” for more

details.

 2011 Microchip Technology Inc. DS41391D-page 15

PIC16(L)F1826/27

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

V

DD

8

8

Brown-out

Reset

12

3

VSS

Internal

Oscillator

Block

Configuration

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

15

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory

RAM

FSR regFSR reg

FSR1 Reg

15

15

MUX

15

Program Memory

Read (PMR)

12

FSR regFSR reg

BSR Reg

5

FIGURE 2-1: CORE BLOCK DIAGRAM

DS41391D-page 16  2011 Microchip Technology Inc.

PIC16(L)F1826/27

3.0 MEMORY ORGANIZATION

There are three types of memory in PIC16(L)F1826/27:
Data Memory, Program Memory and Data EEPROM
Memory

• Program Memory

• Data Memory

• Data EEPROM memory

(1)

.

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

- Device Memory Maps

- Special Function Registers Summary

Note 1: The Data EEPROM Memory and the

method to access Flash memory through
the EECON registers is described in

Section 11.0 “Data EEPROM and Flash
Program Memory Control”.

(1)

The following features are associated with access and
control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1826/27 family.
Accessing a location above these boundaries will cause
a wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1 and 3-2).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1826 2,048 07FFh
PIC16(L)F1827 4,096 0FFFh

 2011 Microchip Technology Inc. DS41391D-page 17

PIC16(L)F1826/27

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Wraps to Page 0

Wraps to Page 0

Wraps to Page 0

0800h

CALL, CALLW
RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

Rollover to Page 0

7FFFh

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh
1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR
PIC16(L)F1826

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR
PIC16(L)F1827

DS41391D-page 18  2011 Microchip Technology Inc.

3.1.1 READING PROGRAM MEMORY AS

constants

BRW ;Add Index in W to

;program counter to

;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W

DATA

There are two methods of accessing constants in pro­gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

PIC16(L)F1826/27

The BRW instruction makes this type of table very sim­ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

 2011 Microchip Technology Inc. DS41391D-page 19

PIC16(L)F1826/27

constants

RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

Addresses BANKx

x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR

x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by set­ting bit 7 of the FSRxH register and reading the match­ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro­gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access­ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a
location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2.1 CORE REGISTERS

The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta bl e 3 -2. For for detailed
information, see Tab le 3 -5 .

TABLE 3-2: CORE REGISTERS

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

Data Memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.

DS41391D-page 20  2011 Microchip Technology Inc.

PIC16(L)F1826/27

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in
subtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

TO

PD ZDC

(1)

(1)

C

bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(1)

(1)

 2011 Microchip Technology Inc. DS41391D-page 21

PIC16(L)F1826/27

0Bh
0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3 .5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all
banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

DS41391D-page 22  2011 Microchip Technology Inc.

3.2.5 DEVICE MEMORY MAPS

The memory maps for the device family are as shown
in Table 3-3 and Tab le 3 -4 .

 2011 Microchip Technology Inc. DS41391D-page 23

TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 - 2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh
00Fh
010h

—08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh—
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—090h—110h—190h—210h—290h— 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H
013h PIR3
014h PIR4

015h TMR0 095h OPTION 115h CMOUT 195h EECON1 215h SSP1CON 295h CCP1AS 315h
016h
017h

018h
019h
01Ah
01Bh
01Ch
01Dh

TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h
TMR1H 097h WDTCON 117h FVRCON 197h
T1CON 098h OSCTUNE 118h DACCON0 198h

T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h

TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah

PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh
01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh SSP2CON2
01Fh CPSCON1 09Fh

020h

General

Purpose

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h 0F0h

Register
96 Bytes

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’

Note 1: Available only on PIC16(L)F1827.

(1)

(1)

080h

Core Registers

(Ta bl e 3 - 2)

093h PIE3
094h PIE4

0A0h

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

100h

Core Registers

(Table 3-2)

(1)

113h CM2CON0 193h EEDATL 213h SSP1MASK 293h CCP1CON 313h CCP3CON

(1)

114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h — 394h IOCBP

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

— 217h SSP1CON3 297h — 317h — 397h —
—218h— 298h CCPR2L

SSP2BUF
SSP2ADD

SSP2MASK

— 19Ch SPBRGH 21Ch SSP2STAT

SSP2CON

—11Fh— 19Fh BAUDCON 21Fh SSP2CON3

120h

General
Purpose
Register

80 Bytes

1A0h

General
Purpose
Register

80 Bytes

220h General

(1)

Purpose
Register

48 Bytes

Unimplemented

Read as ‘0’

170h

Accesses

70h – 7Fh

1F0h

Accesses

70h – 7Fh

270h

Accesses

70h – 7Fh

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

— 30Ch — 38Ch —
— 30Dh — 38Dh —

(1)

(1)

(1)

— 395h IOCBN
— 396h IOCBF

(1)

318h CCPR4L

Read as ‘0’

(1)

319h CCPR4H

(1)

31Ah CCP4CON

(1)

31Bh —39Bh—

(1)

31Ch — 39Ch MDCON

(1)

31Dh

(1)

31Eh

320h

Unimplemented

(1)

299h CCPR2H

(1)

29Ah CCP2CON

(1)

29Bh PWM2CON

(1)

29Ch CCP2AS

(1)

29Dh PSTR2CON

(1)

29Eh CCPTMRS

(1)

29Fh —31Fh—39Fh
2A0h

(1)

Unimplemented

(1)

(1)

(1)

—
—

Read as ‘0’

36Fh 3EFh

2F0h

Accesses

70h – 7Fh

370h

Accesses

70h – 7Fh

380h

Core Registers

(Table 3-2)

391h —
392h —
393h —

398h —
399h —
39Ah CLKRCON

39Dh
39Eh

3A0h

MDSRC
MDCARL
MDCARH

Unimplemented

Read as ‘0’

3F0h

Accesses

70h – 7Fh

PIC16(L)F1826/27

DS41391D-page 24  2011 Microchip Technology Inc.

Legend: = Unimplemented data memory locations, read as ‘0’

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

40Bh

Core Registers

(Ta bl e 3 -2 )

480h

48Bh

Core Registers

(Ta bl e 3 -2 )

500h

50Bh

Core Registers

(Ta bl e 3 -2 )

580h

58Bh

Core Registers

(Ta bl e 3 -2 )

600h

60Bh

Core Registers

(Ta bl e 3 -2 )

680h

68Bh

Core Registers

(Ta bl e 3 -2 )

700h

70Bh

Core Registers

(Ta bl e 3 -2 )

780h

78Bh

Core Registers

(Ta bl e 3 -2 )

40Ch

—

48Ch

—

50Ch

—

58Ch

—

60Ch

—

68Ch

—

70Ch

—

78Ch

—

40Dh

—

48Dh

—

50Dh

—

58Dh

—

60Dh

—

68Dh

—

70Dh

—

78Dh

—

40Eh

—

48Eh

—

50Eh

—

58Eh

—

60Eh

—

68Eh

—

70Eh

—

78Eh

—

40Fh

—

48Fh

—

50Fh

—

58Fh

—

60Fh

—

68Fh

—

70Fh

—

78Fh

—

410h

—

490h

—

510h

—

590h

—

610h

—

690h

—

710h

—

790h

—

411h

—

491h

—

511h

—

591h

—

611h

—

691h

—

711h

—

791h

—

412h

—

492h

—

512h

—

592h

—

612h

—

692h

—

712h

—

792h

—

413h

—

493h

—

513h

—

593h

—

613h

—

693h

—

713h

—

793h

—

414h

—

494h

—

514h

—

594h

—

614h

—

694h

—

714h

—

794h

—

415h

TMR4

(1)

495h

—

515h

—

595h

—

615h

—

695h

—

715h

—

795h

—

416h

PR4

(1)

496h

—

516h

—

596h

—

616h

—

696h

—

716h

—

796h

—

417h

T4CON

(1)

497h

—

517h

—

597h

—

617h

—

697h

—

717h

—

797h

—

418h

—

498h

—

518h

—

598h

—

618h

—

698h

—

718h

—

798h

—

419h

—

499h

—

519h

—

599h

—

619h

—

699h

—

719h

—

799h

—

41Ah

—

49Ah

—

51Ah

—

59Ah

—

61Ah

—

69Ah

—

71Ah

—

79Ah

—

41Bh

—

49Bh

—

51Bh

—

59Bh

—

61Bh

—

69Bh

—

71Bh

—

79Bh

—

41Ch

TMR6

(1)

49Ch

—

51Ch

—

59Ch

—

61Ch

—

69Ch

—

71Ch

—

79Ch

—

41Dh

PR6

(1)

49Dh

—

51Dh

—

59Dh

—

61Dh

—

69Dh

—

71Dh

—

79Dh

—

41Eh

T6CON

(1)

49Eh

—

51Eh

—

59Eh

—

61Eh

—

69Eh

—

71Eh

—

79Eh

—

41Fh

—

49Fh

—

51Fh

—

59Fh

—

61Fh

—

69Fh

—

71Fh

—

79Fh

—

420h

Unimplemented

Read as ‘0’

4A0h

Unimplemented

Read as ‘0’

520h

Unimplemented

Read as ‘0’

5A0h

Unimplemented

Read as ‘0’

620h

Unimplemented

Read as ‘0’

6A0h

Unimplemented

Read as ‘0’

720h

Unimplemented

Read as ‘0’

7A0h

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h

Accesses

70h – 7Fh

4F0h

Accesses
70h – 7Fh

570h

Accesses
70h – 7Fh

5F0h

Accesses

70h – 7Fh

670h

Accesses

70h – 7Fh

6F0h

Accesses

70h – 7Fh

770h

Accesses

70h – 7Fh

7F0h

Accesses

70h – 7Fh

47Fh

4FFh 57Fh

5FFh 67Fh 6FFh 77Fh 7FFh

TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED)

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 25

BANK16 BANK17 BANK18 BANK19 BANK20 BANK21 BANK22 BANK23

800h

80Bh

Core Registers

(Ta bl e 3 -2 )

880h

88Bh

Core Registers

(Ta bl e 3 -2 )

900h

90Bh

Core Registers

(Ta bl e 3 -2 )

980h

98Bh

Core Registers

(Ta bl e 3 -2 )

A00h

A0Bh

Core Registers

(Ta bl e 3 -2 )

A80h

A8Bh

Core Registers

(Ta bl e 3 -2 )

B00h

B0Bh

Core Registers

(Ta bl e 3 -2 )

B80h

B8Bh

Core Registers

(Ta bl e 3 -2 )

80Ch

Unimplemented

Read as ‘0’

88Ch

Unimplemented

Read as ‘0’

90Ch

Unimplemented

Read as ‘0’

98Ch

Unimplemented

Read as ‘0’

A0Ch

Unimplemented

Read as ‘0’

A8Ch

Unimplemented

Read as ‘0’

B0Ch

Unimplemented

Read as ‘0’

B8Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh

9EFh

A6Fh

AEFh

B6Fh

BEFh

870h

Common RAM

(Accesses

70h – 7Fh)

8F0h

Common RAM

(Accesses

70h – 7Fh)

970h

Common RAM

(Accesses
70h – 7Fh)

9F0h

Common RAM

(Accesses
70h – 7Fh)

A70h

Common RAM

(Accesses

70h – 7Fh)

AF0h

Common RAM

(Accesses

70h – 7Fh)

B70h

Common RAM

(Accesses
70h – 7Fh)

BF0h

Common RAM

(Accesses
70h – 7Fh)

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3 -2 )

C80h

C8Bh

Core Registers

(Ta bl e 3 -2 )

D00h

D0Bh

Core Registers

(Ta bl e 3 -2 )

D80h

D8Bh

Core Registers

(Ta bl e 3 -2 )

E00h

E0Bh

Core Registers

(Ta bl e 3 -2 )

E80h

E8Bh

Core Registers

(Ta bl e 3 -2 )

F00h

F0Bh

Core Registers

(Ta bl e 3 -2 )

F80h

F8Bh

Core Registers

(Ta bl e 3 -2 )

C0Ch

C6Fh

Unimplemented

Read as ‘0’

C8Ch

CEFh

Unimplemented

Read as ‘0’

D0Ch

D6Fh

Unimplemented

Read as ‘0’

D8Ch

DEFh

Unimplemented

Read as ‘0’

E0Ch

E6Fh

Unimplemented

Read as ‘0’

E8Ch

EEFh

Unimplemented

Read as ‘0’

F0Ch

F6Fh

Unimplemented

Read as ‘0’

F8Ch

F9Fh

Unimplemented

Read as ‘0’

FA0h

See Tab l e 3 - 4 for
more information

FEFh

C70h

Accesses

70h – 7Fh

CF0h

Accesses
70h – 7Fh

D70h

Accesses
70h – 7Fh

DF0h

Accesses
70h – 7Fh

E70h

Accesses
70h – 7Fh

EF0h

Accesses
70h – 7Fh

F70h

Common RAM

(Accesses
70h – 7Fh)

FF0h

Common RAM

(Accesses
70h – 7Fh)

C7Fh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED)

PIC16(L)F1826/27

PIC16(L)F1826/27

= Unimplemented data memory locations, read as ‘0’,

Bank 31

F80h

F8Bh

Core Registers

(Ta bl e 3 -2 )

F8Ch

FE3h

Unimplemented

Read as ‘0’

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

FF0h

Common RAM

(Accesses

70h – 7Fh)

FFFh

TABLE 3-4: PIC16(L)F1826/27 MEMORY MAP (CONTINUED)

DS41391D-page 26  2011 Microchip Technology Inc.

PIC16(L)F1826/27

3.2.6 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3 - 5 can be
addressed from any Bank.

TABLE 3-5: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Value on

POR, BOR

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Value on all

other Resets

 2011 Microchip Technology Inc. DS41391D-page 27

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 0

00Ch PORTA

00Dh PORTB

00Eh

00Fh

010h
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF

013h PIR3

014h PIR4
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111

01Ch T2CON

01Dh

01Eh CPSCON0 CPSON

01Fh CPSCON1

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

(1)
(1)

— Unimplemented — —

RA7

RB7 RB6 RB5 RB4 RB3 RB2

— — CCP4IF CCP3IF TMR6IF —
— — — — — — BCL2IF SSP2IF ---- --00 ---- --00

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

— — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000

RA6 RA5 RA4 RA3 RA2

— —CCP2IF

DONE

— — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000

T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

RA1

RB1 RB0

TMR4IF

—TMR1ON0000 00-0 uuuu uu-u

RA0

xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx

(1)

0000 0--0 0000 0--0

— --00 0-0- --00 0-0-

Bank 1

08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

08Eh

08Fh

090h
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE

093h PIE3

094h PIE4

095h

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0

09Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

(1)
(1)

OPTION_REG

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

— — CCP4IE CCP3IE TMR6IE —
— — — — — — BCL2IE SSP2IE ---- --00 ---- --00

WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— —RMCLRRI POR BOR 00-- 11qq qq-- qquu
— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000

— CHS4 CHS3 CHS2 CHS1 CHS0

— ADNREF

— — CCP2IE

TMR4IE

— SCS1 SCS0 0011 1-00 0011 1-00

GO/DONE

ADPREF1

(1)

0000 0--0 0000 0--0

— --00 0-0- --00 0-0-

ADON -000 0000 -000 0000

ADPREF0 0000 -000 0000 -000

Value on all

other

Resets

DS41391D-page 28  2011 Microchip Technology Inc.

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 2

10Ch LATA LATA7 LATA6 — L ATA4 LATA3 LATA2 LATA1 L ATA0 xx-x xxxx uu-u uuuu
10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu

10Eh

10Fh

110h

111h CM1CON0 C1ON C1OUT C1OE C1POL

112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0

113h CM2CON0 C2ON C2OUT C2OE C2POL

114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0

115h CMOUT

116h BORCON SBOREN

117h FVRCON FVREN FVRRDY

118h DACCON0 DACEN DACLPS DACOE

119h DACCON1
11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000

11Ch

11Dh APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL

11Eh APFCON1

11Fh

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— C1SP C1HYS C1SYNC 0000 -100 0000 -100
— — C1NCH<1:0> 0000 --00 0000 --00
— C2SP C2HYS C2SYNC 0000 -100 0000 -100
— — C2NCH1 C2NCH0 0000 --00 0000 --00

— — — — — — MC2OUT MC1OUT ---- --00 ---- --00

— — — — — — BORRDY 1--- ---q u--- ---u

Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0qrr 0000 0qrr 0000

— DACPSS1 DACPSS0 — DACNSS 000- 00-0 000- 00-0

— — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000

— Unimplemented — —

— — — — — — — TXCKSEL ---- ---0 ---- ---0

— Unimplemented — —

(1)

CCP2SEL

(1)

P1DSEL P1CSEL CCP1SEL 0000 0000 0000 0000

Bank 3

18Ch ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 ---1 1111 ---1 1111

18Dh ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1

18Eh

18Fh

190h
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000

192h EEADRH
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h EEDATH
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000

197h

198h
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000

— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— Unimplemented — —

— Unimplemented — —

— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

Shaded locations are unimplemented, read as ‘0’.

— 1111 111- 1111 111-

Value on all

other

Resets

 2011 Microchip Technology Inc. DS41391D-page 29

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 4

20Ch WPUA — —WPUA5— — — — — --1- ---- --1- ----
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

20Eh

20Fh

210h

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000
213h SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111

214h SSP1STAT SMP CKE D/A

PSR/WUA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

219h SSP2BUF

21Ah SSP2ADD

21Bh SSP2MSK

21Ch SSP2STAT

21Dh SSP2CON1

21Eh SSP2CON2

21Fh SSP2CON3

— Unimplemented — —

(1)

Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

(1)

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000

(1)

MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111

(1)

SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000

(1)

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

(1)

GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

(1)

ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

Bank 5

28Ch — Unimplemented — —

28Dh

28Eh

28Fh

290h

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
294h PWM1CON P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 0000 0000
295h CCP1AS CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000

296h PSTR1CON

297h

298h CCPR2L

299h CCPR2H

29Ah CCP2CON

— Unimplemented — —

(1)

(1)

(1)

29Bh PWM2CON

29Ch CCP2AS

(1)

29Dh PSTR2CON

29Eh CCPTMRS

29Fh

— Unimplemented — —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

(1)

Shaded locations are unimplemented, read as ‘0’.

— — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001

Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000

(1)

P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000

CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000

(1)

— — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001

C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000

Note 1: PIC16(L)F1827 only.

Value on all

other

Resets

DS41391D-page 30  2011 Microchip Technology Inc.

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 6

30Ch — Unimplemented — —

30Dh

30Eh

30Fh

310h

311h CCPR3L

312h CCPR3H

313h CCP3CON

314h

315h

316h

317h

318h CCPR4L

319h CCPR4H

31Ah CCP4CON

31Bh

31Ch

31Dh

31Eh

31Fh

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

(1)

Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu

(1)

Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu

(1)

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

(1)

(1)

(1)

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000

Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu

— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000

Bank 7

38Ch — Unimplemented — —

38Dh

38Eh

38Fh

390h

391h

392h

393h

394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3

395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3

396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3

397h

398h

399h

39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0

39Bh

39Ch MDCON MDEN MDOE MDSLR MDOPOL

39Dh MDSRC MDMSODIS

39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC

39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

IOCBP2 IOCBP1 IOCBP0

IOCBN2 IOCBN1 IOCBN0

IOCBF2 IOCBF1 IOCBF0

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

CLKRDIV2 CLKRDIV1 CLKRDIV0

— Unimplemented — —

— — —

Shaded locations are unimplemented, read as ‘0’.

— — —

MDMS3 MDMS2 MDMS1 MDMS0

—

—

MDCL3 MDCL2 MDCL1 MDCL0

MDCH3 MDCH2 MDCH1 MDCH0

MDBIT

0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000

0011 0000 0011 0000

0010 ---0 0010 ---0
x--- xxxx u--- uuuu
xxx- xxxx uuu- uuuu
xxx- xxxx uuu- uuuu

Value on all

Resets

other

 2011 Microchip Technology Inc. DS41391D-page 31

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 8

40Ch — Unimplemented — —

40Dh

40Eh

40Fh

410h

411h

412h

413h

414h

415h TMR4

416h PR4

417h T4CON

418h

419h

41Ah

41Bh

41Ch TMR6

41Dh PR6

41Eh T6CON

41Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

(1)

(1)

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

(1)

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

Timer4 Module Register 0000 0000 0000 0000
Timer4 Period Register 1111 1111 1111 1111

(1)

(1)

(1)

— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000

Timer6 Module Register 0000 0000 0000 0000
Timer6 Period Register 1111 1111 1111 1111

— T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000

Value on all

other

Resets

DS41391D-page 32  2011 Microchip Technology Inc.

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 9

48Ch
—
49Fh

Bank 10

50Ch
—
51Fh

Bank 11

58Ch
—
59Fh

Bank 12

60Ch
—
61Fh

Bank 13

68Ch
—
69Fh

Bank 14

70Ch
—
71Fh

Bank 15

78Ch
—
79Fh

Bank 16

80Ch
—
86Fh

Bank 17

88Ch
—
8EFh

Bank 18

90Ch
—
96Fh

Bank 19

98Ch
—
9EFh

Bank 20

A0Ch
—
A6Fh

Bank 21

A8Ch
—
AEFh

Bank 22

B0Ch
—
B6Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

Value on

POR, BOR

Value on all

other

Resets

 2011 Microchip Technology Inc. DS41391D-page 33

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 23

B8Ch
—
BEFh

Bank 24

C0Ch
—
C6Fh

Bank 25

C8Ch
—
CEFh

Bank 26

D0Ch
—
D6Fh

Bank 27

D8Ch
—
DEFh

Bank 28

E0Ch
—
E6Fh

Bank 29

E8Ch
—
EEFh

Bank 30

F0Ch
—
F6Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

Value on

POR, BOR

Value on all

other

Resets

DS41391D-page 34  2011 Microchip Technology Inc.

PIC16(L)F1826/27

TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 31

F8Ch
—
FE3h

FE4h STATUS_

FE5h WREG_

FE6h BSR_

FE7h PCLATH_

FE8h FSR0L_

FE9h FSR0H_

FEAh FSR1L_

FEBh FSR1H_

FECh

FEDh

FEEh

FEFh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.

— Unimplemented — —

— — — — — Z_SHAD DC_

SHAD

Working Register Shadow 0000 0000 uuuu uuuu

SHAD

— — — Bank Select Register Shadow ---x xxxx ---u uuuu

SHAD

— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

— Unimplemented — —

STKPTR

TOSL

TOSH

Shaded locations are unimplemented, read as ‘0’.

— — — Current Stack pointer ---1 1111 ---1 1111

Top-of-Stack Low byte xxxx xxxx uuuu uuuu

— Top-of-Stack High byte -xxx xxxx -uuu uuuu

SHAD

C_SHAD ---- -xxx ---- -uuu

Value on

POR, BOR

Value on all

other

Resets

 2011 Microchip Technology Inc. DS41391D-page 35

PIC16(L)F1826/27

PCLPCH

0

14

PC

06

7

ALU Result

8

PCLATH

PCLPCH

0

14

PC

06

4

OPCODE <10:0>

11

PCLATH

PCLPCH

0

14

PC

06

7

W

8

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH

0

14

PC

PC + W

15

BRW

PCLPCH

0

14

PC

PC + OPCODE <8:0>

15

BRA

3.3 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN

DIFFERENT SITUATIONS

3.3.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by com­bining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.

3.3.4 BRANCHING

The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.

If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.

3.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program Coun­ter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values con­tained in the PCLATH register and those being written
to the PCL register.

3.3.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PC L). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a T able Read” (DS00556).

DS41391D-page 36  2011 Microchip Technology Inc.

PIC16(L)F1826/27

TOSH:TOSL

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x03

0x02

0x01

0x00

0x04

0x05

0x06

0x07

0x1F

Stack Reset Disabled
(STVREN = 0)

Stack Reset Enabled
(STVREN = 1)

0x0000

Initial Stack Configuration:

After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.

STKPTR = 0x1F

STKPTR = 0x1F

3.4 Stack

All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-5 through 3-8). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Word 2). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over­flow/Underflow, regardless of whether the Reset is
enabled.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the

CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to

an interrupt address.

3.4.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement STKPTR.

Reference Figure 3-5 through Figure 3-8 for examples
of accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

 2011 Microchip Technology Inc. DS41391D-page 37

PIC16(L)F1826/27

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x03

0x02

0x01

0x00

0x04

0x05

0x06

0x07

Return Address

This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).

STKPTR = 0x00

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x03

0x02

0x01

0x00

0x04

0x05

0x06

0x07

Return Address

After seven CALLs, or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.

STKPTR = 0x06

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

DS41391D-page 38  2011 Microchip Technology Inc.

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x03

0x02

0x01

0x00

0x04

0x05

0x06

0x07

Return Address

When the stack is full, the next CALL or

interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00

so the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

STKPTR = 0x10

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

PIC16(L)F1826/27

3.4.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.

3.5 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

 2011 Microchip Technology Inc. DS41391D-page 39

PIC16(L)F1826/27

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000

Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

FIGURE 3-9: INDIRECT ADDRESSING

DS41391D-page 40  2011 Microchip Technology Inc.

3.5.1 TRADITIONAL DATA MEMORY

Indirect AddressingDirect Addressing

Bank Select

Location Select

4BSR 6

0

From Opcode

FSRxL70

Bank Select

Location Select

0000 0001 0010 1111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

0

FSRxH70

0000

The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 41

PIC16(L)F1826/27

7

0

1

7

0

0

Location Select

0x2000

FSRnH

FSRnL

0x020

Bank 0

0x06F
0x0A0

Bank 1
0x0EF
0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

0

7

1

7

0

0

Location Select

0x8000

FSRnH

FSRnL

0x0000

0x7FFF

0xFFFF

Program
Flash
Memory
(low 8
bits)

3.5.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.

The 16 bytes of common memory are not included in
the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

3.5.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH

MEMORY MAP

DS41391D-page 42  2011 Microchip Technology Inc.

4.0 DEVICE CONFIGURATION

Device Configuration consists of Configuration Word 1
and Configuration Word 2, Code Protection and Device
ID.

4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Word is

managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a '1'.

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 43

PIC16(L)F1826/27

REGISTER 4-1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1/1

FCMEN IESO CLKOUTEN

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CP

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

bit 12 IESO: Internal External Switchover bit

bit 11 CLKOUTEN

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

bit 8 CPD: Data Code Protection bit

bit 7 CP

bit 6 MCLRE: MCLR/VPP Pin Function Select bit

bit 5 PWRTE

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled

1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled

: Clock Out Enable bit

If

FOSC configuration bits are set to LP, XT, HS modes:

This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.

All other

11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled

1 = Data memory code protection is disabled
0 = Data memory code protection is enabled

1 = Program memory code protection is disabled
0 = Program memory code protection is enabled

If LVP bit =

If LVP bit =

1 = PWRT disabled
0 = PWRT enabled

11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled

FOSC modes:

1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin

(2)

: Code Protection bit

1:

This bit is ignored.

0:

1 =MCLR
0 =MCLR

/VPP pin function is MCLR; Weak pull-up enabled.
/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

: Power-up Timer Enable bit

BOREN<1:0> CPD

DS41391D-page 44  2011 Microchip Technology Inc.

REGISTER 4-1: CONFIGURATION WORD 1 (CONTINUED)

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 45

PIC16(L)F1826/27

REGISTER 4-2: CONFIGURATION WORD 2

R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1/1

(1)

LVP

bit 13 bit 8

U-1 U-1 U-1 R/P-1/1 U-1 U-1 R/P-1 R/P-1

— — — Reserved — —WRT<1:0>

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit

1 = Low-voltage programming enabled
0 = High-voltage on MCLR

bit 12 DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11 Unimplemented: Read as ‘1’
bit 10 BORV: Brown-out Reset Voltage Selection bit

1 = Brown-out Reset voltage set to 1.9V (typical)
0 = Brown-out Reset voltage set to 2.5V (typical)

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset

bit 8 PLLEN: PLL Enable bit

1 = 4xPLL enabled
0 = 4xPLL disabled

bit 7-5 Unimplemented: Read as ‘1’
bit 4 Reserved: This location should be programmed to a ‘1’.
bit 3-2 Unimplemented: Read as ‘1’
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

2 kW Flash memory (PIC16(L)F1826 only)

11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control
01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control
00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control

4 kW Flash memory (PIC16(L)F1827 only)

11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control
01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control
00 = 000h to FFFh write-protected, no addresses may be modified by EECON control

DEBUG

must be used for programming

(2)

—BORVSTVRENPLLEN

:

:

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: The DEBUG

including debuggers and programmers. For normal device operation, this bit should be
maintained as a '1'.

DS41391D-page 46  2011 Microchip Technology Inc.

bit in Configuration Word is managed automatically by device development tools

4.2 Code Protection

Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data EEPROM protection are controlled independently.
Internal access to the program memory and data
EEPROM are unaffected by any code protection
setting.

4.2.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP
Word 1. When CP
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.3 “Write

Protection” for more information.

= 0, external reads and writes of

4.2.2 DATA EEPROM PROTECTION

The entire data EEPROM is protected from external
reads and writes by the CPD
nal reads and writes of data EEPROM are inhibited.
The CPU can continue to read and write data EEPROM
regardless of the protection bit settings.

bit in Configuration

bit. When CPD = 0, exter-

PIC16(L)F1826/27

4.3 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot­loader software, can be protected while allowing other
regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Word 2 define the
size of the program memory block that is protected.

4.4 User ID

Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See

Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing

these memory locations.

checksum calculation, see the “PIC16F/LF1826/27

Memory Programming Specification” (DS41390).

For more information on

 2011 Microchip Technology Inc. DS41391D-page 47

PIC16(L)F1826/27

4.5 Device ID and Revision ID

The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See

Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.

DS41391D-page 48  2011 Microchip Technology Inc.

PIC16(L)F1826/27

Device

DEVICEID<13:0> Values

DEV<8:0> REV<4:0>

PIC16F1826 10 0111 100 x xxxx
PIC16F1827 10 0111 101 x xxxx
PIC16LF1826 10 1000 100 x xxxx
PIC16LF1827 10 1000 101 x xxxx

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

RRRRRR

bit 13 bit 8

RRRRRRRR

DEV<2:0> REV<4:0>

bit 7 bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

bit 13-5 DEV<8:0>: Device ID bits

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

(1)

DEV<8:3>

U = Unimplemented bit, read as ‘1’

-n/n = Value at POR and BOR/Value at all other Resets

P = Programmable bit

bit 4-0 REV< 4:0>: Revision ID bits

These bits are used to identify the revision.

Note 1: This location cannot be written.

 2011 Microchip Technology Inc. DS41391D-page 49

PIC16(L)F1826/27

NOTES:

DS41391D-page 50  2011 Microchip Technology Inc.

PIC16(L)F1826/27

5.0OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

5.1 Overview

The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor­mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds
selectable via software. Additional clock features
include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and
code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

The oscillator module can be configured in one of eight
clock modes.

1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode
(0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode
(4 MHz to 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 32 MHz).

Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Word 1. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.

The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT, and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.

The INTOSC internal oscillator block produces low,
medium, and high frequency clock sources, designated
LFINTOSC, MFINTOSC, and HFINTOSC. (see
Internal Oscillator Block, Figure 5-1). A wide selection
of device clock frequencies may be derived from these
three clock sources.

 2011 Microchip Technology Inc. DS41391D-page 51

PIC16(L)F1826/27

FOSC<2:0>

Oscillator

T1OSCEN
Enable
Oscillator

T1OSO

T1OSI

Clock Source Option
for other modules

OSC1

OSC2

Sleep

LP, XT, HS, RC, EC

T1OSC

CPU and

Postscaler

MUX

MUX

16 MHz

8 MHz
4 MHz
2 MHz
1 MHz

250 kHz

500 kHz

IRCF<3:0>

31 kHz

500 kHz

Source

Internal

Oscillator

Block

WDT, PWRT, Fail-Safe Clock Monitor

16 MHz

Internal Oscillator

(HFINTOSC)

Clock

Control

SCS<1:0>

HFPLL

31 kHz (LFINTOSC)

Two-Speed Start-up and other modules

Oscillator

31 kHz

Source

500 kHz

(MFINTOSC)

125 kHz

31.25 kHz

62.5 kHz

FOSC<2:0> = 100

Peripherals

Sleep

External

Timer1

4 x PLL

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS41391D-page 52  2011 Microchip Technology Inc.

PIC16(L)F1826/27

OSC1/CLKIN

OSC2/CLKOUT

Clock from
Ext. System

PIC

®

MCU

FOSC/4 or

I/O

(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Word 1.

5.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator mod­ules (EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resis­tor-Capacitor (RC) mode circuits.

Internal clock sources are contained internally within
the oscillator module. The internal oscillator block has
two internal oscillators and a dedicated Phase-Lock
Loop (HFPLL) that are used to generate three internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC)
and the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).

The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3

“Clock Switching” for additional information.

5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device
system clock by performing one of the following
actions:

• Program the FOSC<2:0> bits in the Configuration
Word 1 to select an external clock source that will
be used as the default system clock upon a
device Reset.

• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:

- Timer1 Oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “Clock Switching”for more informa­tion.

5.2.1.1 EC Mode

The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.

EC mode has 3 power modes to select from through
Configuration Word 1:

• High-power, 4-32 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low-power, 0-0.5 MHz (FOSC = 101)

The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC

®

MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

5.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.

LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).

XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.

HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

 2011 Microchip Technology Inc. DS41391D-page 53

PIC16(L)F1826/27

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

C1

C2

Quartz

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (R

P)

may be required for proper ceramic resonator
operation.

C1

C2

Ceramic

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

RP

(3)

Resonator

OSC2/CLKOUT

FIGURE 5-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR
HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC
Devices” (DS00826)

• AN849, “Basic PIC

(DS00849)

• AN943, “Practical PIC
Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

®

and PIC

®

Oscillator Design”

®

Oscillator

FIGURE 5-4: CERAMIC RESONATOR

OPERATION
(XT OR HS MODE)

5.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not

®

increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.

In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4

“Two-Speed Clock Start-up Mode”).

DS41391D-page 54  2011 Microchip Technology Inc.

5.2.1.4 4X PLL

The oscillator module contains a 4X PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4X PLL must fall within specifications. See the PLL
Clock Timing Specifications in Section 30.0

“Electrical Specifications”.

The 4X PLL may be enabled for use by one of two
methods:

1. Program the PLLEN bit in Configuration Word 2

to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to

a ‘1’. If the PLLEN bit in Configuration Word 2 is
programmed to a ‘1’, then the value of SPLLEN
is ignored.

PIC16(L)F1826/27

C1

C2

32.768 kHz

T1OSI

To Internal
Logic

PIC® MCU

Crystal

T1OSO

Quartz

OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

F

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  R

EXT  100 k, 3-5V

C

EXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Word 1.

I/O

(1)

5.2.1.5 TIMER1 Oscillator

The Timer1 Oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is opti­mized for timekeeping operations with a 32.768 kHz
crystal connected between the T1OSO and T1OSI
device pins.

The Timer1 Oscillator can be used as an alternate sys­tem clock source and can be selected during run-time
using clock switching. Refer to Section 5.3 “Clock

Switching” for more information.

FIGURE 5-5: QUARTZ CRYSTAL

OPERATION (TIMER1
OSCILLATOR)

5.2.1.6 External RC Mode

The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.

The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
state of the CLKOUTEN

bit in Configuration Word 1.

Figure 5-6 shows the external RC mode connections.

FIGURE 5-6: EXTERNAL RC MODES

Note 1: Quartz crystal characteristics vary

according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC
Devices” (DS00826)

• AN849, “Basic PIC

(DS00849)

• AN943, “Practical PIC

 2011 Microchip Technology Inc. DS41391D-page 55

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for
Low-Power External Oscillators”

(DS01288)

®

and PIC

®

Oscillator Design”

®

Oscillator

The RC oscillator frequency is a function of the supply
voltage, the resistor (R

EXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting
the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

®

The user also needs to take into account variation due
to tolerance of external RC components used.

PIC16(L)F1826/27

5.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscil­lator block as the system clock by performing one of the
following actions:

• Program the FOSC<2:0> bits in Configuration
Word 1 to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.

• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3

“Clock Switching”for more information.

In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined
by the state of the CLKOUTEN
Word 1.

The internal oscillator block has two independent
oscillators and a dedicated Phase-Lock Loop, HFPLL
that can produce one of three internal system clock
sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
dedicated Phase-Lock Loop, HFPLL. The
frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 5-3).

2. The MFINTOSC (Medium-Frequency Internal

Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 5-3).

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at
31 kHz.

bit in Configuration

5.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).

The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.

The High Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running and can be utilized.

The High Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.

The High Frequency Internal Oscillator Status Stable
bit (HFIOFS) of the OSCSTAT register indicates when
the HFINTOSC is running within 0.5% of its final value.

5.2.2.2 MFINTOSC

The Medium-Frequency Internal Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 5-3).

The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The MFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’

The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running and can be utilized.

DS41391D-page 56  2011 Microchip Technology Inc.

PIC16(L)F1826/27

5.2.2.3 Internal Oscillator Frequency
Adjustment

The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator a change in
the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.

When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

5.2.2.4 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). Select 31 kHz, via
software, using the IRCF<3:0> bits of the OSCCON
register. See Section 5.2.2.7 “Internal Oscillator

Clock Switch Timing” for more information. The

LFINTOSC is also the frequency for the Power-up Timer
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock
Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired LF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running and can be utilized.

5.2.2.5 Internal Oscillator Frequency
Selection

The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 5-1). The Internal Oscillator Frequency
Select bits IRCF<3:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
the following frequencies can be selected via software:

• 32 MHz (requires 4X PLL)

•16 MHz

•8 MHz

•4 MHz

•2 MHz

•1 MHz

• 500 kHz (Default after Reset)

•250 kHz

•125 kHz

•62.5 kHz

•31.25 kHz

• 31 kHz (LFINTOSC)

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli­cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi­tion times can be obtained between frequency changes
that use the same oscillator source.

 2011 Microchip Technology Inc. DS41391D-page 57

PIC16(L)F1826/27

5.2.2.6 32 MHz Internal Oscillator
Frequency Selection

The Internal Oscillator Block can be used with the 4X
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz inter­nal clock source:

• The FOSC bits in Configuration Word 1 must be

set to use the INTOSC source as the device sys­tem clock (FOSC<2:0> = 100).

• The SCS bits in the OSCCON register must be

cleared to use the clock determined by
FOSC<2:0> in Configuration Word 1
(SCS<1:0> = 00).

• The IRCF bits in the OSCCON register must be

set to the 8 MHz HFINTOSC set to use
(IRCF<3:0> = 1110).

• The SPLLEN bit in the OSCCON register must be

set to enable the 4xPLL, or the PLLEN bit of the
Configuration Word 2 must be programmed to a
‘1’.

Note: When using the PLLEN bit of the

Configuration Word 2, the 4xPLL cannot

be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.

The 4xPLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4xPLL with the internal oscillator.

5.2.2.7 Internal Oscillator Clock Switch
Timing

When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new
clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.

Start-up delay specifications are located in the
oscillator tables of Section 30.0 “Electrical

Specifications”.

DS41391D-page 58  2011 Microchip Technology Inc.

FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

0 0

0 0

Start-up Time

2-cycle Sync Running

2-cycle Sync Running

HFINTOSC/ LFINTOSC (FSCM and WDT disabled)

HFINTOSC/

LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC/

IRCF <3:0>

System Clock

= 0  0

Start-up Time 2-cycle Sync

Running

LFINTOSC HFINTOSC/MFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

MFINTOSC

MFINTOSC

MFINTOSC

MFINTOSC

MFINTOSC

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 59

PIC16(L)F1826/27

5.3 Clock Switching

The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:

• Default system oscillator determined by FOSC
bits in Configuration Word 1

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

5.3.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Word 1.

• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.

• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.

5.3.3 TIMER1 OSCILLATOR

The Timer1 Oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSO and T1OSI device
pins.

The Timer1 oscillator is enabled using the T1OSCEN
control bit in the T1CON register. See Section 21.0

“Timer1 Module with Gate Control” for more

information about the Timer1 peripheral.

5.3.4 TIMER1 OSCILLATOR READY

(T1OSCR) BIT

The user must ensure that the Timer1 Oscillator is
ready to be used before it is selected as a system clock
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.

When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil­lator delays are shown in Table 5-1.

5.3.2 OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word 1, or from the internal clock source. In particular,
OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out for LP, XT or HS modes. The OST
does not reflect the status of the Timer1 Oscillator.

DS41391D-page 60  2011 Microchip Technology Inc.

PIC16(L)F1826/27

5.4 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscil­lator module is configured for LP, XT, or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.

If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT reg­ister is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.

5.4.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the
following settings:

• IESO (of the Configuration Word 1) = 1; Inter-

nal/External Switchover bit (Two-Speed Start-up
mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Word 1

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay

(1)
(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

31 kHz

31.25 kHz-500 kHz

Oscillator Warm-up Delay (T

31.25kHz-16MHz
DC – 32 MHz 2 cycles
DC – 32 MHz 1 cycle of each

32 kHz-20 MHz 1024 Clock Cycles (OST)

31.25 kHz-500 kHz

31.25kHz-16MHz

2 s (approx.)

31 kHz 1 cycle of each

WARM)

LFINTOSC

Sleep/POR

MFINTOSC

HFINTOSC
Sleep/POR EC, RC
LFINTOSC EC, RC

Sleep/POR

Any clock source

Timer1 Oscillator

LP, XT, HS

MFINTOSC

HFINTOSC
Any clock source LFINTOSC
Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST)
PLL inactive PLL active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.

 2011 Microchip Technology Inc. DS41391D-page 61

PIC16(L)F1826/27

0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N

PC

5.4.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 5-8: TWO-SPEED START-UP

5.4.3 CHECKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word 1, or the
internal oscillator.

DS41391D-page 62  2011 Microchip Technology Inc.

PIC16(L)F1826/27

External

LFINTOSC

÷ 64

S

R

Q

31 kHz

(~32 s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Q

Sample Clock

5.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word 1. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, Timer1
Oscillator and RC).

FIGURE 5-9: FSCM BLOCK DIAGRAM

5.5.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.

5.5.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared and the device
will be operating from the external clock source. The
Fail-Safe condition must be cleared before the OSFIF
flag can be cleared.

5.5.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.

5.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.

The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

 2011 Microchip Technology Inc. DS41391D-page 63

PIC16(L)F1826/27

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator
Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te st

Test Test

Clock Monitor Output

FIGURE 5-10: FSCM TIMING DIAGRAM

DS41391D-page 64  2011 Microchip Technology Inc.

PIC16(L)F1826/27

5.6 Oscillator Control Registers

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0

SPLLEN IRCF<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Word 1 =
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Word 1 = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

000x =31 kHz LF
0010 =31.25 kHz MF
0011 =31.25 kHz HF
0100 =62.5 kHz MF
0101 =125 kHz MF
0110 =250 kHz MF
0111 =500 kHz MF (default upon Reset)
1000 =125 kHz HF
1001 =250 kHz HF
1010 =500 kHz HF
1011 =1 MHz HF
1100 =2 MHz HF
1101 =4 MHz HF
1110 =8 MHz or 32 MHz HF(see Section 5.2.2.1 “HFINTOSC”)
1111 =16 MHz HF

bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block
01 = Timer1 oscillator
00 = Clock determined by FOSC<2:0> in Configuration Word 1.

(1)

(1)
(1)
(1)

1:

—

SCS<1:0>

Note 1: Duplicate frequency derived from HFINTOSC.

 2011 Microchip Technology Inc. DS41391D-page 65

PIC16(L)F1826/27

REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q

T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional

bit 7 T1OSCR: Timer1 Oscillator Ready bit

If T1OSCEN =

1 = Timer1 oscillator is ready
0 = Timer1 oscillator is not ready

If T1OSCEN =
1 = Timer1 clock source is always ready

bit 6 PLLR 4x PLL Ready bit

1 = 4x PLL is ready
0 = 4x PLL is not ready

bit 5 OSTS: Oscillator Start-up Time-out Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1
0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready
0 = HFINTOSC is not ready

bit 3 HFIOFL: High Frequency Internal Oscillator Locked bit

1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate

bit 2 MFIOFR: Medium Frequency Internal Oscillator Ready bit

1 = MFINTOSC is ready
0 = MFINTOSC is not ready

bit 1 LFIOFR: Low Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready
0 = LFINTOSC is not ready

bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit

1 = HFINTOSC is at least 0.5% accurate
0 = HFINTOSC is not 0.5% accurate

1:

0:

DS41391D-page 66  2011 Microchip Technology Inc.

PIC16(L)F1826/27

REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — TUN<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits

011111 = Maximum frequency
011110 =

•

•

•

000001 =
000000 = Oscillator module is running at the factory-calibrated frequency.
111111 =

•

•

•
100000 = Minimum frequency

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

(1)
(1)

Register
on Page

94
97

187

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0

OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR

OSCTUNE

PIE2 OSFIE

PIR2

T1CON

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.
Note 1: PIC16(L)F1827 only.

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 67

C2IE C1IE EEIE BCL1IE

OSFIF

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON

C2IF C1IF EEIF BCL1IF — — CCP2IF

— SCS1 SCS0 65

—

— CCP2IE

HFIOFS 66

TABLE 5-3: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD

CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0

Register
on Page

50

 2011 Microchip Technology Inc. DS41391D-page 67

PIC16(L)F1826/27

NOTES:

DS41391D-page 68  2011 Microchip Technology Inc.

PIC16(L)F1826/27

6.0 REFERENCE CLOCK MODULE

The reference clock module provides the ability to send
a divided clock to the clock output pin of the device
(CLKR) and provide a secondary internal clock source
to the modulator module. This module is available in all
oscillator configurations and allows the user to select a
greater range of clock submultiples to drive external
devices in the application. The reference clock module
includes the following features:

• System clock is the source

• Available in all oscillator configurations

• Programmable clock divider

• Output enable to a port pin

• Selectable duty cycle

• Slew rate control

The reference clock module is controlled by the
CLKRCON register (Register 6-1) and is enabled when
setting the CLKREN bit. To output the divided clock sig­nal to the CLKR port pin, the CLKROE bit must be set.
The CLKRDIV<2:0> bits enable the selection of 8 dif­ferent clock divider options. The CLKRDC<1:0> bits
can be used to modify the duty cycle of the output

(1)

. The CLKRSLR bit controls slew rate limiting.

clock

Note 1: If the base clock rate is selected without

a divider, the output clock will always
have a duty cycle equal to that of the
source clock, unless a 0% duty cycle is
selected. If the clock divider is set to base
clock/2, then 25% and 75% duty cycle
accuracy will be dependent upon the
source clock.

For information on using the reference clock output
with the modulator module, see Section 23.0 “Data

Signal Modulator”.

6.3 Conflicts with the CLKR Pin

There are two cases when the reference clock output
signal cannot be output to the CLKR pin, if:

• LP, XT or HS Oscillator mode is selected.

• CLKOUT function is enabled.

Even if either of these cases are true, the module can
still be enabled and the reference clock signal may be
used in conjunction with the modulator module.

6.3.1 OSCILLATOR MODES

If LP, XT or HS oscillator modes are selected, the
OSC2/CLKR pin must be used as an oscillator input pin
and the CLKR output cannot be enabled. See

Section 5.2 “Clock Source Types” for more informa-

tion on different oscillator modes.

6.3.2 CLKOUT FUNCTION

The CLKOUT function has a higher priority than the
reference clock module. Therefore, if the CLKOUT
function is enabled by the CLKOUTEN
tion Word 1, F
pin. Reference Section 4.0 “Device Configuration”
for more information.

OSC/4 will always be output on the port

bit in Configura-

6.4 Operation During Sleep

As the reference clock module relies on the system
clock as its source, and the system clock is disabled in
Sleep, the module does not function in Sleep, even if
an external clock source or the Timer1 clock source is
configured as the system clock. The module outputs
will remain in their current state until the device exits
Sleep.

6.1 Slew Rate

The slew rate limitation on the output port pin can be
disabled. The slew rate limitation can be removed by
clearing the CLKRSLR bit in the CLKRCON register.

6.2 Effects of a Reset

Upon any device Reset, the reference clock module is
disabled. The user's firmware is responsible for
initializing the module before enabling the output. The
registers are reset to their default values.

 2011 Microchip Technology Inc. DS41391D-page 69

PIC16(L)F1826/27

6.5 Reference Clock Control Register

REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference Clock module is enabled
0 = Reference Clock module is disabled

bit 6 CLKROE: Reference Clock Output Enable bit

1 = Reference Clock output is enabled on CLKR pin
0 = Reference Clock output disabled on CLKR pin

bit 5 CLKRSLR: Reference Clock Slew Rate Control limiting enable bit

1 = Slew Rate limiting is enabled
0 = Slew Rate limiting is disabled

bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits

11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%

bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits

111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value

(2)

(1)

(3)

Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.

2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%

is selected.

3: To route CLKR to pin, CLKOUTEN

Word 1 = 0 will result in F

DS41391D-page 70  2011 Microchip Technology Inc.

OSC/4. See Section 6.3 “Conflicts with the CLKR Pin” for details.

of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration

PIC16(L)F1826/27

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CLKRCON CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

CLKRDIV2 CLKRDIV1 CLKRDIV0

TABLE 6-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD

CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0

Register
on Page

70

Register
on Page

44

 2011 Microchip Technology Inc. DS41391D-page 71

PIC16(L)F1826/27

NOTES:

DS41391D-page 72  2011 Microchip Technology Inc.

PIC16(L)F1826/27

External Reset

MCLR

VDD

WDT

Time-out

Power-on

Reset

LFINTOSC

PWRT

64 ms

PWRTEN

Brown-out

Reset

BOR

RESET Instruction

Stack

Pointer

Stack Overflow/Underflow Reset

Sleep

MCLRE

Enable

Device
Reset

Zero

Programming Mode Exit

7.0 RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To a llo w V
can be enabled to extend the Reset time after a BOR
or POR event.

A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 7-1.

FIGURE 7-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Reset

DD to stabilize, an optional power-up timer

 2011 Microchip Technology Inc. DS41391D-page 73

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7.1 Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising V
performance may require greater than minimum V
The PWRT, BOR or MCLR
extend the start-up period until all device operation
conditions have been met.

7.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time­out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the V
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Word 1.

The Power-up Timer starts after the release of the POR
and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 7-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

DD, fast operating speeds or analog

DD.

features can be used to

DD to

11 X X Active Waits for BOR ready

Awake Active

10 X

Sleep Disabled

7.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when Vdd
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.

The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu­ration Word 1. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 7 -1 for more information.

The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Word 2.

DD noise rejection filter prevents the BOR from trig-

A V
gering on small events. If V
duration greater than parameter T
will reset. See Figure 7-2 for more information.

Device Operation

upon release of POR

DD falls below VBOR for a

BORDC, the device

Device Operation

upon wake- up from

Sleep

(1)

Waits for BOR ready

01

00 X X Disabled Begins immediately

Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in

start-up.

1

X

0 Disabled Begins immediately

7.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Word 1 are set
to ‘11’, the BOR is always on. The device start-up will
be delayed until the BOR is ready and V
than the BOR threshold.

BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.

DD is higher

7.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Word 1 are set
to ‘10’, the BOR is on, except in Sleep. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.

BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.

Active Begins immediately

7.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Word 1 are set
to ‘01’, the BOR is controlled by the SBOREN bit of the
BORCON register. The device start-up is not delayed
by the BOR ready condition or the V

BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

DD level.

DS41391D-page 74  2011 Microchip Technology Inc.

FIGURE 7-2: BROWN-OUT SITUATIONS

TPWRT

(1)

VBOR

V

DD

Internal

Reset

VBOR

V

DD

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

V

DD

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

PIC16(L)F1826/27

REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

bit 6-1 Unimplemented: Read as ‘0’
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

— — — — — —BORRDY

If BOREN <1:0> in Configuration Word 1

 01:

SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Word 1 =

01:

1 = BOR Enabled
0 = BOR Disabled

1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive

 2011 Microchip Technology Inc. DS41391D-page 75

PIC16(L)F1826/27

7.3 MCLR

The MCLR is an optional external input that can reset
the device. The MCLR
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2 (Ta b le 7 - 2).

function is controlled by the

TABLE 7-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled
10Enabled
x1Enabled

7.3.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR

DD through an internal weak pull-up.

V

The device has a noise filter in the MCLR
The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR pin low.

pin is connected to

Reset path.

7.3.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.2 “PORTA Regis-

ters” for more information.

7.4 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer” for more information.

7.7 Programming Mode Exit

Upon exit of Programming mode, the device will
behave as if a POR had just occurred.

7.8 Power-Up Timer

The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.

The Power-up Timer is controlled by the PWRTE
Configuration Word 1.

bit of

7.9 Start-up Sequence

Upon the release of a POR or BOR, the following must
occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if

required for oscillator source).

3. MCLR

The total time-out will vary based on oscillator configu­ration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for more information.

The Power-up Timer and oscillator start-up timer run
independently of MCLR
long enough, the Power-up Timer and oscillator start­up timer will expire. Upon bringing MCLR
device will begin execution immediately (see Figure 7-

3). This is useful for testing purposes or to synchronize

more than one device operating in parallel.

must be released (if enabled).

Reset. If MCLR is kept low

high, the

7.5 RESET Instruction

A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Ta b le 7 -4
for default conditions after a RESET instruction has
occurred.

7.6 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration Word

2. See Section 3 .4.2 “Overflow/Underflow Reset”for
more information.

DS41391D-page 76  2011 Microchip Technology Inc.

FIGURE 7-3: RESET START-UP SEQUENCE

TOST

TMCLR

TPWRT

VDD

Internal POR

Power-Up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-Up Timer

Oscillator

F

OSC

Internal Oscillator

Oscillator

F

OSC

External Clock (EC)

CLKIN

F

OSC

External Crystal

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 77

PIC16(L)F1826/27

7.10 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Ta b le 7 - 3 and Ta b le 7 - 4 show the Reset condi­tions of these registers.

TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RMCLR RI POR BOR TO PD Condition

00110x11Power-on Reset
00110x0xIllegal, TO
00110xx0Illegal, PD is set on POR
0011u011Brown-out Reset
uuuuuu0uWDT Reset
uuuuuu00WDT Wake-up from Sleep
uuuuuu10Interrupt Wake-up from Sleep
uu0uuuuuMCLR
uu0uuu10MCLR
u u u 0 u u u u RESET Instruction Executed
1uuuuuuuStack Overflow Reset (STVREN = 1)
u1uuuuuuStack Underflow Reset (STVREN = 1)

is set on POR

Reset during normal operation

Reset during Sleep

(1)

(2)

STATUS

Register

---1 0uuu uu-- uuuu

PCON

Register

TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-- 110x

MCLR

Reset during normal operation 0000h ---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-- uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu
Brown-out Reset 0000h ---1 1uuu 00-- 11u0

Interrupt Wake-up from Sleep PC + 1
RESET Instruction Executed 0000h ---u uuuu uu-- u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program

Counter

DS41391D-page 78  2011 Microchip Technology Inc.

PIC16(L)F1826/27

7.11 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits
to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI

•MCLR Reset (RMCLR)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in Register 7-2.

REGISTER 7-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF

bit 7 bit 0

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

)

)

— —

RMCLR

RI POR BOR

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or set to ‘0’ by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or set to ‘0’ by firmware

bit 5-4 Unimplemented: Read as ‘0’
bit 3 RMCLR

1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR

bit 2 RI

1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction)

bit 1 POR

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

: MCLR Reset Flag bit

Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

: RESET Instruction Flag bit

: Power-on Reset Status bit

: Brown-out Reset Status bit

occurs)

 2011 Microchip Technology Inc. DS41391D-page 79

PIC16(L)F1826/27

TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register
on Page

BORCON SBOREN

PCON STKOVF STKUNF

STATUS

WDTCON

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR

— — —TOPD Z DC C

— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 99

— — — — — — BORRDY 75

— —RMCLRRI POR BOR 79

Reset and Watchdog Timer Reset during normal operation.

21

DS41391D-page 80  2011 Microchip Technology Inc.

8.0 INTERRUPTS

D

CK

R

Q

D

CK

R

Q

RBx

IOCBNx

IOCBPx

Q2

D

CK

S

Q

Q4Q1

Data bus =

0 or 1

Write IOCBFx

IOCIE

To data bus

IOCBFx

Edge

Detect

IOC interrupt

to CPU core

From all other

IOCBFx individual

pin detectors

Q1

Q2
Q3
Q4

Q4Q1

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q4

Q4Q1

Q4Q1

Q4Q1

The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.

This chapter contains the following information for
Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce Interrupts. Refer to the
corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 8-1.

FIGURE 8-1: INTERRUPT LOGIC

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 81

PIC16(L)F1826/27

8.1 Operation

Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt
events)

• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIEx registers)

The INTCON, PIRx registers record individual inter­rupts via interrupt flag bits. Interrupt flag bits will be set,
regardless of the status of the GIE, PEIE and individual
interrupt enable bits.

The following events happen when an interrupt event
occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the
stack

• Critical registers are automatically saved to the
shadow registers (See “Section 8.5 “Automatic

Context Saving”.”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.

For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.

8.2 Interrupt Latency

Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 8-2
and Figure 8.3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other
enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

DS41391D-page 82  2011 Microchip Technology Inc.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

PC 0004h 0005h

PC

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

PC

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC)

Interrupt Sampled
during Q1

Inst(PC)

PC-1 PC+1

NOP

PC

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

PC

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(0005h)

Execute

Execute

Execute

PIC16(L)F1826/27

FIGURE 8-2: INTERRUPT LATENCY

 2011 Microchip Technology Inc. DS41391D-page 83

PIC16(L)F1826/27

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

PC

Instruction
Fetched

Instruction
Executed

Interrupt Latency

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 T

CY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 30.0 “Electrical Specifications””.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

FIGURE 8-3: INT PIN INTERRUPT TIMING

DS41391D-page 84  2011 Microchip Technology Inc.

8.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 9.0 “Power-

Down Mode (Sleep)” for more details.

8.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.

PIC16(L)F1826/27

8.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis­ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica­tions to any of these registers are desired, the corre­sponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s appli­cation, other registers may also need to be saved.

and PD)

 2011 Microchip Technology Inc. DS41391D-page 85

PIC16(L)F1826/27

8.6 Interrupt Control Registers

8.6.1 INTCON REGISTER

The INTCON register is a readable and writable
register, that contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri­ate interrupt flag bits are clear prior to
enabling an interrupt.

REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt
0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed
0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state

(1)

(1)

Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register

have been cleared by software.

DS41391D-page 86  2011 Microchip Technology Inc.

PIC16(L)F1826/27

8.6.2 PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as
shown in Register 8-2.

REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 Gate Acquisition interrupt
0 = Disables the Timer1 Gate Acquisition interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt
0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3 SSP1IE: Synchronous Serial Port 1 (MSSP1) Interrupt Enable bit

1 = Enables the MSSP1 interrupt
0 = Disables the MSSP1 interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2011 Microchip Technology Inc. DS41391D-page 87

PIC16(L)F1826/27

8.6.3 PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as
shown in Register 8-3.

REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0

OSFIE C2IE C1IE EEIE BCL1IE — —CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt

bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit

1 = Enables the EEPROM Write Completion interrupt
0 = Disables the EEPROM Write Completion interrupt

bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit

1 = Enables the MSSP1 Bus Collision Interrupt
0 = Disables the MSSP1 Bus Collision Interrupt

bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

(1)

Note 1: PIC16(L)F1827 only.

DS41391D-page 88  2011 Microchip Technology Inc.

PIC16(L)F1826/27

8.6.4 PIE3 REGISTER

The PIE3 register contains the interrupt enable bits, as
shown in Register 8-4.

REGISTER 8-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0

— — CCP4IE CCP3IE TMR6IE —TMR4IE—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’
bit 5 CCP4IE: CCP4 Interrupt Enable bit

1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt

bit 4 CCP3IE: CCP3 Interrupt Enable bit

1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt

bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt

bit 0 Unimplemented: Read as ‘0’

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

(1)

Note 1: This register is only available on PIC16(L)F1827.

 2011 Microchip Technology Inc. DS41391D-page 89

PIC16(L)F1826/27

8.6.5 PIE4 REGISTER

The PIE4 register contains the interrupt enable bits, as
shown in Register 8-5.

REGISTER 8-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0

— — — — — — BCL2IE SSP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’
bit 1 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit

1 = Enables the MSSP2 Bus Collision Interrupt
0 = Disables the MSSP2 Bus Collision Interrupt

bit 0 SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit

1 = Enables the MSSP2 interrupt
0 = Disables the MSSP2 interrupt

(1)

Note 1: The PIE4 register is available only on the

PIC16(L)F1827 device.

2: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

(1)

Note 1: This register is only available on PIC16(L)F1827.

DS41391D-page 90  2011 Microchip Technology Inc.

PIC16(L)F1826/27

8.6.6 PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as
shown in Register 8-6.

REGISTER 8-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 3 SSP1IF: Synchronous Serial Port 1 (MSSP1) Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 CCP1IF: CCP1 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

 2011 Microchip Technology Inc. DS41391D-page 91

PIC16(L)F1826/27

8.6.7 PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as
shown in Register 8-7.

REGISTER 8-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0

OSFIF C2IF C1IF EEIF BCL1IF — —CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

(1)

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 6 C2IF: Comparator C2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

Note 1: PIC16(L)F1827 only.

(1)

DS41391D-page 92  2011 Microchip Technology Inc.

PIC16(L)F1826/27

8.6.8 PIR3 REGISTER

The PIR3 register contains the interrupt flag bits, as
shown in Register 8-8.

REGISTER 8-8: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0

— — CCP4IF CCP3IF TMR6IF —TMR4IF—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

(1)

bit 7-6 Unimplemented: Read as ‘0’
bit 5 CCP4IF: CCP4 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 CCP3IF: CCP3 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 0 Unimplemented: Read as ‘0’
Note 1: This register is only available on PIC16(L)F1827.

 2011 Microchip Technology Inc. DS41391D-page 93

PIC16(L)F1826/27

8.6.9 PIR4 REGISTER

The PIR4 register contains the interrupt flag bits, as
shown in Register 8-9.

(1)

Note 1: The PIR4 register is available only on the

PIC16(L)F1827 device.

2: Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the
state of its corresponding enable bit or
the Global Enable bit, GIE, of the
INTCON register. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.

REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4

(1)

U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0

— — — — — — BCL2IF SSP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware

bit 7-2 Unimplemented: Read as ‘0’
bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit

1 = A Bus Collision was detected (must be cleared in software)
0 = No Bus collision was detected

bit 0 SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit

1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting to Transmit/Receive/Bus Condition in progress

Note 1: This register is only available on PIC16(L)F1827.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86

OPTION_REG

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87

PIE2 OSFIE C2IE C1IE EEIE BCL1IE

(1)

PIE3

(1)

PIE4

PIR1

PIR2

(1)

PIR3

(1)

PIR4

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
Note 1: PIC16(L)F1827 only.

WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 177

—

— — CCP4IE CCP3IE TMR6IE —TMR4IE—89

— — — — — —

TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF

OSFIF C2IF C1IF EEIF BCL1IF

— — CCP4IF CCP3IF TMR6IF —TMR4IF—93

— — — — — —

— —CCP2IF

— CCP2IE

BCL2IE SSP2IE

BCL2IF SSP2IF

Register
on Page

(1)

(1)

88

90

91

92

94

DS41391D-page 94  2011 Microchip Technology Inc.

PIC16(L)F1826/27

9.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a
SLEEP instruction.

Upon entering Sleep mode, the following conditions
exist:

1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.

bit of the STATUS register is cleared.

2. PD

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.

6. Timer1 oscillator is unaffected and peripherals
that operate from it may continue operation in
Sleep.

7. ADC is unaffected, if the dedicated FRC clock is
selected.

8. Capacitive Sensing oscillator is unaffected.

9. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or high­impedance).

10. Resets other than WDT are not affected by
Sleep mode.

Refer to individual chapters for more details on
peripheral operation during Sleep.

To minimize current consumption, the following condi­tions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be
pulled to V
rents caused by floating inputs.

Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 17.0 “Digital-to-Analog Con-

verter (DAC) Module” and Section 14.0 “Fixed Volt­age Reference (FVR)” for more information on these

modules.

DD or VSS externally to avoid switching cur-

9.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the
following events:

1. External Reset input on MCLR

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running dur­ing Sleep (see individual peripheral for more
information)

The first three events will cause a device Reset. The
last three events are considered a continuation of pro­gram execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 7.10

“Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.

pin, if enabled

 2011 Microchip Technology Inc. DS41391D-page 95

PIC16(L)F1826/27

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(1)

CLKOUT

(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

PC

Instruction
Fetched

Instruction
Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2 0004h 0005h

Dummy Cycle

T

OST

(3)

PC + 2

Note 1: XT, HS or LP Oscillator mode assumed.

2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
3: T

OST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.

4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

9.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared
bit of the STATUS register will not be set

-TO

-PD

bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction

- SLEEP instruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared.

Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD
was executed as a NOP.

FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 91
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 134
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 134
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 134

PIE1 TMR1GIE ADIE RCIE

PIE4

(1)

PIE2

PIR1

PIR2

PIR4

(1)

STATUS

WDTCON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
Note 1: PIC16(L)F1827 only.

DS41391D-page 96  2011 Microchip Technology Inc.

OSFIE C2IE C1IE EEIE BCL1IE

— — — — — —

TMR1GIF ADIF RCIF

OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF

— — — — — —

— — —TOPD Z DC C
— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 105

TXIE SSP1IE CCP1IE TMR2IE TMR1IE 92

—

TXIF SSP1IF CCP1IF TMR2IF TMR1IF

— CCP2IE

BCL2IE SSP2IE

BCL2IF SSP2IF

(1)

(1)

Register on

Page

93
95
96
97
99
23

10.0 WATCHDOG TIMER

LFINTOSC

23-bit Programmable

Prescaler WDT

WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256
seconds (typical)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM

PIC16(L)F1826/27

 2011 Microchip Technology Inc. DS41391D-page 97

PIC16(L)F1826/27

10.1 Independent Clock Source

The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See

Section 30.0 “Electrical Specifications” for the

LFINTOSC tolerances.

10.2 WDT Operating Modes

The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See Table 10-1.

10.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Word 1 are set to
‘11’, the WDT is always on.

WDT protection is active during Sleep.

10.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Word 1 are set to
‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Word 1 are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.

WDT protection is unchanged by Sleep. See

Table 10-1 for more details.

TABLE 10-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN

Device

Mode

WDT

Mode

10.3 Time-Out Period

The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.

10.4 Clearing the WDT

The WDT is cleared when any of the following condi­tions occur:

•Any Reset

• CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail event

• WDT is disabled

• Oscillator Start-up TImer (OST) is running

See Table 10-2 for more information.

10.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.

When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator

Module (With Fail-Safe Clock Monitor)” for more

information on the OST.

When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO
in the STATUS register are changed to indicate the
event. See Register 3-1 for more information.

and PD bits

11 X XActive

10 X

1

01

0 Disabled

00 X X Disabled

Awake Active

Sleep Disabled

Active

X

TABLE 10-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected

DS41391D-page 98  2011 Microchip Technology Inc.

Cleared

PIC16(L)F1826/27

10.6 Watchdog Control Register

REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

— — WDTPS<4:0> SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’
bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

00000 = 1:32 (Interval 1 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01010 = 1:32768 (Interval 1s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01100 = 1:131072 (2
01101 = 1:262144 (2
01110 = 1:524288 (2
01111 = 1:1048576 (2
10000 = 1:2097152 (2
10001 = 1:4194304 (2
10010 = 1:8388608 (2

17

) (Interval 4s nominal)

18

) (Interval 8s nominal)

19

) (Interval 16s nominal)

20

) (Interval 32s nominal)

21

) (Interval 64s nominal)

22

) (Interval 128s nominal)

23

) (Interval 256s nominal)

(1)

10011 = Reserved. Results in minimum interval (1:32)

•

•

•

11111 = Reserved. Results in minimum interval (1:32)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> =
This bit is ignored.
If WDTE<1:0> =

1 = WDT is turned on
0 = WDT is turned off

If WDTE<1:0> =
This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

 2011 Microchip Technology Inc. DS41391D-page 99

00:

01:

1x:

PIC16(L)F1826/27

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

STATUS

WDTCON
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

— IRCF<3:0> —SCS<1:0>

— — —TOPD Z DC C

— — WDTPS<4:0> SWDTEN

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN<1:0> CPD

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

Register
on Page

69

21

99

Register
on Page

44

DS41391D-page 100  2011 Microchip Technology Inc.