PIC16(L)F1826/27
Data Sheet
18/20/28-Pin Flash Microcontrollers
with nanoWatt XLP Technology
2011 Microchip Technology Inc. DS41391D
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC
logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-124-7
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS41391D-page 2 2011 Microchip Technology Inc.
PIC16(L)F1826/27
18/20/28-Pin Flash Microcontrollers wit h na noWatt XLP Techno logy
High-Performance RISC CPU:
• C Compiler Optimized Architecture
• 256 bytes Data EEPROM
• Up to 8 Kbytes Linear Program Memory
Addressing
• Up to 384 bytes Linear Data Memory Addressing
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
Flexible Oscillator Struc ture:
• Precision 32 MHz Internal Oscillator Block:
- Factory calibrated to ± 1%, typical
- Software selectable frequencies range of
31 kHz to 32 MHz
• 31 kHz Low-Power Internal Oscillator
• Four Crystal modes up to 32 MHz
• Three External Clock modes up to 32 MHz
• 4X Phase-Lock Loop (PLL)
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
• Two-Speed Oscillator Start-up
• Reference Clock Module:
- Programmable clock output frequency and
duty-cycle
Special Microcontroller Features:
• 1.8V-5.5V Operation – PIC16F1826/27
• 1.8V-3.6V Operation – PIC16LF1826/27
• Self-Programmable under Software Control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Programmable Brown-out Reset (BOR)
• Extended Watchdog Timer (WDT):
- Programmable period from 1ms to 268s
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via
two pins
• In-Circuit Debug (ICD) via two pins
• Enhance Low-Voltage Programming
• Power-Saving Sleep mode
Extreme Low-Power Management PIC16LF1826/27 with nanoWatt XLP:
• Operating Current: 75 A @ 1 MHz, 1.8V, typical
• Sleep mode: 30 nA
• Watchdog Timer: 500 nA
• Timer1 Oscillator: 600 nA @ 32 kHz
Analog Features:
• Analog-to-Digital Converter (ADC) Module:
- 10-bit resolution, 12 channels
- Auto acquisition capability
- Conversion available during Sleep
• Analog Comparator Module:
- Two rail-to-rail analog comparators
- Power mode control
- Software controllable hysteresis
• Voltage Reference Module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
Peripheral Highlight s:
• 15 I/O Pins and 1 Input Only Pin:
- High current sink/source 25 mA/25 mA
- Programmable weak pull-ups
- Programmable interrupt-on- change pins
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Dedicated, low-power 32 kHz oscillator driver
• Up to three Timer2-types: 8-Bit Timer/Counter with
8-Bit Period Register, Prescaler and Postscaler
• Up to two Capture, Compare, PWM (CCP) Modules
• Up to two Enhanced CCP (ECCP) Modules:
- Software selectable time bases
- Auto-shutdown and auto-restart
- PWM steering
• Up to two Master Synchronous Serial Port
(MSSP) with SPI and I
- 7-bit address masking
- SMBus/PMBus
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) Module
• mTouch™ Sensing Oscillator Module:
- Up to 12 input channels
• Data Signal Modulator Module:
- Selectable modulator and carrier sources
•SR Latch:
- Multiple Set/Reset input options
- Emulates 555 Timer applications
2
CTM with:
TM
compatibility
2011 Microchip Technology Inc. DS41391D-page 3
PIC16(L)F1826/27
PDIP, SOIC
PIC16(L)F1826/27
1
2
3
4
18
17
16
15
5
6
7
14
13
12
RA2
RA3
RA4
RA5/MCLR
/VPP
VSS
RB0
RB1
RA1
RA0
RA7
RA6
V
DD
RB7
RB6
8
9
11
10
RB2
RB3
RB5
RB4
SSOP
PIC16(L)F1826/27
1
2
3
4
20
19
18
17
5
7
8
16
14
13
RA2
RA3
RA4
RA5/MCLR
/VPP
VSS
RB0
RB1
RA1
RA0
RA7
RA6
V
DD
RB7
RB6
9
10
12
11
RB2
RB3
RB5
RB4
6
15
VSS
VDD
PIC16(L)F1826/27 Family Types
Program
Memory
Device
Words
Data
Memory
SRAM
(bytes)
(1)
I/O’s
(bytes)
10-bit ADC (ch)
CapSense (ch)
Comparators
Timers (8/16-bit)
Data EEPROM
MSSP
EUSART
ECCP (Full-Bridge)
CCP
SR Latch
ECCP (Half-Bridge)
PIC16LF1826 2K 256 256 16 12 12 2 2/1 1 1 1 — — Yes
PIC16F1826 2K 256 256 16 12 12 2 2/1 1 1 1 — — Yes
PIC16LF1827 4K 38425616121224/112112Yes
PIC16F1827 4K 384 256 16 12 12 2 4/1 1 2 1 1 2 Yes
Note 1: One pin is input only.
Pin Diagram – 18-Pin PDIP, SOIC
(PIC16(L)F1826/27)
Pin Diagram – 20-Pin SSOP (PIC16(L)F1826/27)
DS41391D-page 4 2011 Microchip Technology Inc.
Pin Diagram – 28-Pin QFN/UQFN (PIC16(L)F1826/27)
PIC16(L)F1826/27
RA2
RA3
RA4
RA5/MCLR/VPP
VSS
RB0
RB1
RA1
RA0
RA7
RA6
V
DD
RB7
RB6
RB2
RB3
RB5
RB4
VSS
VDD
NC
NC
282726
25
24
23
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
NC
NC
NC
NC
NC
NC
QFN/UQFN
PIC16(L)F1826/27
2011 Microchip Technology Inc. DS41391D-page 5
DS41391D-page 6 2011 Microchip Technology Inc.
TABLE 1: 18/20/28-PIN SUMMARY (PIC16(L)F1826/27)
18-Pin PDIP/SOIC
I/O
28-Pin QFN/UQFN
20-Pin SSOP
ANSEL
A/D
Reference
Cap Sense
Comparator
SR Latch
Timers
CCP
EUSART
MSSP
Interrupt
Modulator
Pull-up
Basic
PIC16(L)F1826/27
RA0 17 19 23 Y AN0 — CPS0 C12IN0- — — — — SDO2
RA1 18 20 24 Y AN1 — CPS1 C12IN1- — — — — SS2
RA2 1 1 26 Y AN2 VREF-
DACOUT
RA3 2 2 27 Y AN3 VREF+ CPS3 C12IN3-
CPS2 C12IN2-
C12IN+
— — — — — — — N —
SRQ — CCP3
(2)
— — — — N —
(2)
(2)
— — N —
— — N —
C1IN+
C1OUT
P2B
CCP2
P2A
P1A
(1)
(1,2)
(1)
(1,2)
(1,2)
(1)
(2)
— — — — N —
— SDO1
(1)
(1)
— — Y
— — N OSC2
(3)
MCLR, VPP
CLKOUT
— — — — N OSC1
(1)
— — INT
IOC
— Y —
RA4 3 3 28 Y AN4 — CPS4 C2OUT SRNQ T0CKI CCP4
RA5 4 4 1 N — — — — — — — — SS1
RA6 15 17 20 N — — — — — — P1D
RA7 16 18 21 N — — — — — — P1C
RB0 6 7 7 N — — — — SRI T1G CCP1
FLT0
RB1 7 8 8 Y AN11 — CPS11 — — — — RX
RB2 8 9 9 Y AN10 — CPS10 — — — — RX
RB3 9 10 10 Y AN9 — CPS9 — — — CCP1
P1A
(1,4)
(1,4)
RB4 10 11 12 Y AN8 — CPS8 — — — — — SCL1
DT
TX
CK
(1,4)
(1,4)
(1)
,DT
(1,4)
(1,4)
SDA1
SDI1
(1)
SDA2
SDI2
(1,4)
SDO1
IOC — Y —
(2)
IOC MDMIN Y —
(2)
— — IOC MDOUT Y —
IOC MDCIN2 Y —
SCK1
RB5 11 12 13 Y AN7 — CPS7 — — — P1B TX
RB6 12 13 15 Y AN5 — CPS5 — — T1CKI
T1OSI
RB7 13 14 16 Y AN6 — CPS6 — — T1OSO P1D
P1C
CCP2
P2A
P2B
(1,4)
(1,2,4)
(1,2,4)
(1,4)
(1,2,4)
CK
(1)
(1)
— — IOC — Y ICSPCLK/
— — IOC MDCIN1 Y ICSPDAT/
SCL2
SCK2
SS1
(1,4)
(2)
IOC — Y —
(2)
ICDCLK
ICDDAT
VDD 14 15,16 17,19 — — — — — — — — — — — — — VDD
Vss55,63,5———— — —— — — — ——— VSS
Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.
2: Functions are only available on the PIC16(L)F1827.
3: Weak pull-up always enabled when MCLR
4: Default function location.
is enabled, otherwise the pull-up is under user control.
CLKR
CLKIN
PIC16(L)F1826/27
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-Range CPU........................................................................................................................................................ 15
3.0 Memory Organization................................................................................................................................................................. 17
4.0 Device Configuration.................................................................................................................................................................. 43
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51
6.0 Reference Clock Module............................................................................................................................................................ 69
7.0 Resets ........................................................................................................................................................................................ 73
8.0 Interrupts .................................................................................................................................................................................... 81
9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 95
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 97
11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 101
12.0 I/O Ports ................................................................................................................................................................................... 117
13.0 Interrupt-on-Change ................................................................................................................................................................. 131
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 135
15.0 Temperature Indicator.............................................................................................................................................................. 137
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 139
17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 153
18.0 SR Latch................................................................................................................................................................................... 157
19.0 Comparator Module.................................................................................................................................................................. 163
20.0 Timer0 Module ......................................................................................................................................................................... 173
21.0 Timer1 Module ......................................................................................................................................................................... 177
22.0 Timer2/4/6 Modules.................................................................................................................................................................. 191
23.0 Data Signal Modulator (DSM) .................................................................................................................................................. 193
24.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4) Modules ..................................................................................... 203
25.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 231
26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 285
27.0 Capacitive Sensing Module ...................................................................................................................................................... 315
28.0 In-Circuit Serial Programming
29.0 Instruction Set Summary.......................................................................................................................................................... 325
30.0 Electrical Specifications............................................................................................................................................................ 339
31.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 371
32.0 Development Support............................................................................................................................................................... 379
33.0 Packaging Information.............................................................................................................................................................. 383
Appendix A: Revision History............................................................................................................................................................. 393
Appendix B: Device Differences ........................................................................................................................................................ 393
Index .................................................................................................................................................................................................. 395
The Microchip Web Site..................................................................................................................................................................... 403
Customer Change Notification Service .............................................................................................................................................. 403
Customer Support .............................................................................................................................................................................. 403
Reader Response .............................................................................................................................................................................. 404
Product Identification System ............................................................................................................................................................ 405
™ (ICSP™) ................................................................................................................................ 321
2011 Microchip Technology Inc. DS41391D-page 7
PIC16(L)F1826/27
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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DS41391D-page 8 2011 Microchip Technology Inc.
1.0 DEVICE OVERVIEW
The PIC16(L)F1826/27 are described within this data
sheet. They are available in 18/20/28-pin packages.
Figure 1-1 shows a block diagram of the
PIC16(L)F1826/27 devices. Table 1-2 shows the pinout
descriptions.
Reference Ta bl e 1 -1 for peripherals available per
device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F1826/27
PIC16F/LF1826
ADC ●●
Capacitive Sensing Module ●●
Digital-to-Analog Converter (DAC) ●●
Digital Signal Modulator (DSM) ●●
EUSART ●●
Fixed Voltage Reference (FVR) ●●
Reference Clock Module ●●
SR Latch ●●
Capture/Compare/PWM Modules
ECCP1 ●●
ECCP2 ●
CCP3 ●
CCP4 ●
Comparators
C1 ●●
C2 ●●
Master Synchronous Serial Ports
MSSP1 ●●
MSSP2 ●
Timers
Timer0 ●●
Timer1 ●●
Timer2 ●●
Timer4 ●
Timer6 ●
PIC16(L)F1827
2011 Microchip Technology Inc. DS41391D-page 9
PIC16(L)F1826/27
PORTA
EUSART
Comparators
MSSPx
Timer2-
Timer1Timer0
ECCPx
ADC
10-Bit
CCPx
PORTB
SR
Latch
Note 1: See applicable chapters for more information on peripherals.
2: See Ta bl e 1 -1 for peripherals available on specific devices.
CPU
Program
Flash Memory
EEPROM
RAM
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
INTRC
Oscillator
MCLR
(Figure 2-1)
Modulator
CapSense
Clock
CLKR
Reference
Type s
DAC
FVR
FIGURE 1-1: PIC16(L)F1826/27 BLOCK DIAGRAM
DS41391D-page 10 2011 Microchip Technology Inc.
T ABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION
Input
Name Function
Type
Output
Type
PIC16(L)F1826/27
Description
RA0/AN0/CPS0/C12IN0-/
(2)
SDO2
RA0 TTL CMOS General purpose I/O.
AN0 AN — A/D Channel 0 input.
CPS0 AN — Capacitive sensing input 0.
C12IN0- AN — Comparator C1 or C2 negative input.
SDO2 — CMOS SPI data output.
(2)
RA1/AN1/CPS1/C12IN1-/SS2
RA1 TTL CMOS General purpose I/O.
AN1 AN — A/D Channel 1 input.
CPS1 AN — Capacitive sensing input 1.
C12IN1- AN — Comparator C1 or C2 negative input.
ST — Slave Select input 2.
RA2/AN2/CPS2/C12IN2-/
C12IN+/V
REF-/DACOUT
SS2
RA2 TTL CMOS General purpose I/O.
AN2 AN — A/D Channel 2 input.
CPS2 AN — Capacitive sensing input 2.
C12IN2- AN — Comparator C1 or C2 negative input.
C12IN+ AN — Comparator C1 or C2 positive input.
REF- AN — A/D Negative Voltage Reference input.
V
DACOUT — AN Voltage Reference output.
RA3/AN3/CPS3/C12IN3-/C1IN+/
REF+/C1OUT/CCP3
V
(2)
/SRQ
RA3 TTL CMOS General purpose I/O.
AN3 AN — A/D Channel 3 input.
CPS3 AN — Capacitive sensing input 3.
C12IN3- AN — Comparator C1 or C2 negative input.
C1IN+ AN — Comparator C1 positive input.
REF+ AN — A/D Voltage Reference input.
V
C1OUT — CMOS Comparator C1 output.
CCP3 ST CMOS Capture/Compare/PWM3.
SRQ — CMOS SR latch non-inverting output.
RA4/AN4/CPS4/C2OUT/T0CKI/
(2)
/SRNQ
CCP4
RA4 TTL CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
CPS4 AN — Capacitive sensing input 4.
C2OUT — CMOS Comparator C2 output.
T0CKI ST — Timer0 clock input.
CCP4 ST CMOS Capture/Compare/PWM4.
SRNQ — CMOS SR latch inverting output.
RA5/MCLR
/VPP/SS1
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
(1,2)
RA5 TTL CMOS General purpose I/O.
MCLR
V
PP HV — Programming voltage.
SS1
ST — Master Clear with internal pull-up.
ST — Slave Select input 1.
2
C™ = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.
2: Functions are only available on the PIC16(L)F1827.
3: Default function location.
2011 Microchip Technology Inc. DS41391D-page 11
PIC16(L)F1826/27
TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RA6/OSC2/CLKOUT/CLKR/
(1)
P1D
/P2B
(1,2)
/SDO1
(1)
RA6 TTL CMOS General purpose I/O.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS F
CLKR — CMOS Clock Reference Output.
P1D — CMOS PWM output.
P2B — CMOS PWM output.
SDO1 — CMOS SPI data output 1.
RA7/OSC1/CLKIN/P1C
CCP2
(1,2)
/P2A
(1,2)
/
RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
(1)
CLKIN CMOS — External clock input (EC mode).
P1C — CMOS PWM output.
CCP2 ST CMOS Capture/Compare/PWM2.
P2A — CMOS PWM output.
RB0/T1G/CCP1
/INT/
RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
(1)
(1)
/P1A
SRI/FLT0
T1G ST — Timer1 Gate input.
CCP1 ST CMOS Capture/Compare/PWM1.
P1A — CMOS PWM output.
INT ST — External interrupt.
SRI ST — SR latch input.
FLT0 ST — ECCP Auto-Shutdown Fault input.
RB1/AN11/CPS11/RX
(1,3)
DT
/SDA1/SDI1
/
RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
(1,3)
AN11 AN — A/D Channel 11 input.
CPS11 AN — Capacitive sensing input 11.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
SDA1 I
SDI1 CMOS — SPI data input 1.
RB2/AN10/CPS10/MDMIN/
(1,3)
(1,3)
(1)
TX
SDA2
/CK
(2)
/SDI2
/RX
(2)
/DT
/SDO1
(1)
(1,3)
/
RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN10 AN — A/D Channel 10 input.
CPS10 AN — Capacitive sensing input 10.
MDMIN — CMOS Modulator source input.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
SDA2 I
SDI2 ST — SPI data input 2.
SDO1 — CMOS SPI data output 1.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.
2: Functions are only available on the PIC16(L)F1827.
3: Default function location.
Output
Type
Type
OSC/4 output.
Individually enabled pull-up.
Individually enabled pull-up.
2
C™ OD I2C™ data input/output 1.
Individually enabled pull-up.
2
C™ OD I2C™ data input/output 2.
Description
2
C™ = Schmitt Trigger input with I2C
DS41391D-page 12 2011 Microchip Technology Inc.
PIC16(L)F1826/27
TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RB3/AN9/CPS9/MDOUT/
CCP1
(1,3)
/P1A
(1,3)
RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN9 AN — A/D Channel 9 input.
CPS9 AN — Capacitive sensing input 9.
MDOUT — CMOS Modulator output.
CCP1 ST CMOS Capture/Compare/PWM1.
P1A — CMOS PWM output.
RB4/AN8/CPS8/SCL1/SCK1/
RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
MDCIN2
AN8 AN — A/D Channel 8 input.
CPS8 AN — Capacitive sensing input 8.
SCL1 I
SCK1 ST CMOS SPI clock 1.
MDCIN2 ST — Modulator Carrier Input 2.
(1)
(1)
/CK
/
RB5/AN7/CPS7/P1B/TX
SCL2
(2)
/SCK2
(2)
/SS1
(1,3)
RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN7 AN — A/D Channel 7 input.
CPS7 AN — Capacitive sensing input 7.
P1B — CMOS PWM output.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
SCL2 I
SCK2 ST CMOS SPI clock 2.
SS1
RB6/AN5/CPS5/T1CKI/T1OSI/
P1C
(1,3)
/CCP2
(1,2,3)
/P2A
(1,2,3)
ICSPCLK
RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
/
AN5 AN — A/D Channel 5 input.
CPS5 AN — Capacitive sensing input 5.
T1CKI ST — Timer1 clock input.
T1OSO XTAL XTAL Timer1 oscillator connection.
P1C — CMOS PWM output.
CCP2 ST CMOS Capture/Compare/PWM2.
P2A — CMOS PWM output.
ICSPCLK ST — Serial Programming Clock.
RB7/AN6/CPS6/T1OSO/
P1D
(1,3)
/P2B
(1,2,3)
/MDCIN1/
ICSPDAT
RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
AN6 AN — A/D Channel 6 input.
CPS6 AN — Capacitive sensing input 6.
T1OSO XTAL XTAL Timer1 oscillator connection.
P1D — CMOS PWM output.
P2B — CMOS PWM output.
MDCIN1 ST — Modulator Carrier Input 1.
ICSPDAT ST CMOS ICSP™ Data I/O.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.
2: Functions are only available on the PIC16(L)F1827.
3: Default function location.
Output
Type
Type
Individually enabled pull-up.
Individually enabled pull-up.
2
C™ OD I2C™ clock 1.
Individually enabled pull-up.
2
C™ OD I2C™ clock 2.
ST — Slave Select input 1.
Individually enabled pull-up.
Individually enabled pull-up.
Description
2
C™ = Schmitt Trigger input with I2C
2011 Microchip Technology Inc. DS41391D-page 13
PIC16(L)F1826/27
TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
V
DD VDD Power — Positive supply.
V
SS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: Functions are only available on the PIC16(L)F1827.
3: Default function location.
Type
Output
Type
Description
2
C™ = Schmitt Trigger input with I2C
DS41391D-page 14 2011 Microchip Technology Inc.
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1 Automatic Interrupt Context Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 8.5 “Automatic Context Saving”,
for more information.
PIC16(L)F1826/27
2.2 16-level Stack with Overflow and Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 “Stack” for more
details.
2.3 File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.4 “Stack”for more details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 29.0 “Instruction Set Summary” for more
details.
2011 Microchip Technology Inc. DS41391D-page 15
PIC16(L)F1826/27
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
V
DD
8
8
Brown-out
Reset
12
3
VSS
Internal
Oscillator
Block
Configuration
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W reg
Instruction
Decode &
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
15
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr
7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
FIGURE 2-1: CORE BLOCK DIAGRAM
DS41391D-page 16 2011 Microchip Technology Inc.
PIC16(L)F1826/27
3.0 MEMORY ORGANIZATION
There are three types of memory in PIC16(L)F1826/27:
Data Memory, Program Memory and Data EEPROM
Memory
• Program Memory
• Data Memory
• Data EEPROM memory
(1)
.
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
- Device Memory Maps
- Special Function Registers Summary
Note 1: The Data EEPROM Memory and the
method to access Flash memory through
the EECON registers is described in
Section 11.0 “Data EEPROM and Flash
Program Memory Control”.
(1)
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1826/27 family.
Accessing a location above these boundaries will cause
a wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1 and 3-2).
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words) Last Program Memory Address
PIC16(L)F1826 2,048 07FFh
PIC16(L)F1827 4,096 0FFFh
2011 Microchip Technology Inc. DS41391D-page 17
PIC16(L)F1826/27
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Wraps to Page 0
Wraps to Page 0
Wraps to Page 0
0800h
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
Rollover to Page 0
Rollover to Page 0
7FFFh
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
CALL, CALLW
RETURN, RETLW
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh
1000h
7FFFh
Page 1
Rollover to Page 1
Interrupt, RETFIE
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1826
FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1827
DS41391D-page 18 2011 Microchip Technology Inc.
3.1.1 READING PROGRAM MEMORY AS
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
DATA
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
PIC16(L)F1826/27
The BRW instruction makes this type of table very simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
2011 Microchip Technology Inc. DS41391D-page 19
PIC16(L)F1826/27
constants
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON
3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the program memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
3.2.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta bl e 3 -2. For for detailed
information, see Tab le 3 -5 .
TABLE 3-2: CORE REGISTERS
3.2 Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Data Memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
DS41391D-page 20 2011 Microchip Technology Inc.
PIC16(L)F1826/27
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 29.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TO
PD ZDC
(1)
(1)
C
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Digit Borrow
bit 0 C: Carry/Borrow
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
(1)
(1)
2011 Microchip Technology Inc. DS41391D-page 21
PIC16(L)F1826/27
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset
3.2.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
3.2.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3 .5.2
“Linear Data Memory” for more information.
3.2.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-3: BANKED MEMORY
PARTITIONING
DS41391D-page 22 2011 Microchip Technology Inc.
3.2.5 DEVICE MEMORY MAPS
The memory maps for the device family are as shown
in Table 3-3 and Tab le 3 -4 .
2011 Microchip Technology Inc. DS41391D-page 23
TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta bl e 3 - 2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh
00Fh
010h
—08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh—
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
—090h—110h—190h—210h—290h— 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H
013h PIR3
014h PIR4
015h TMR0 095h OPTION 115h CMOUT 195h EECON1 215h SSP1CON 295h CCP1AS 315h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h
TMR1H 097h WDTCON 117h FVRCON 197h
T1CON 098h OSCTUNE 118h DACCON0 198h
T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h
TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah
PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh
T2CON 09Ch ADRESH 11Ch
— 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh
01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh SSP2CON2
01Fh CPSCON1 09Fh
020h
General
Purpose
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h 0F0h
Register
96 Bytes
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’
Note 1: Available only on PIC16(L)F1827.
(1)
(1)
080h
Core Registers
(Ta bl e 3 - 2)
093h PIE3
094h PIE4
0A0h
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
100h
Core Registers
(Table 3-2)
(1)
113h CM2CON0 193h EEDATL 213h SSP1MASK 293h CCP1CON 313h CCP3CON
(1)
114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h — 394h IOCBP
180h
Core Registers
(Table 3-2)
200h
Core Registers
(Table 3-2)
— 217h SSP1CON3 297h — 317h — 397h —
—218h— 298h CCPR2L
SSP2BUF
SSP2ADD
SSP2MASK
— 19Ch SPBRGH 21Ch SSP2STAT
SSP2CON
—11Fh— 19Fh BAUDCON 21Fh SSP2CON3
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h General
(1)
Purpose
Register
48 Bytes
Unimplemented
Read as ‘0’
170h
Accesses
70h – 7Fh
1F0h
Accesses
70h – 7Fh
270h
Accesses
70h – 7Fh
280h
Core Registers
(Table 3-2)
300h
Core Registers
(Table 3-2)
— 30Ch — 38Ch —
— 30Dh — 38Dh —
(1)
(1)
(1)
— 395h IOCBN
— 396h IOCBF
(1)
318h CCPR4L
Read as ‘0’
(1)
319h CCPR4H
(1)
31Ah CCP4CON
(1)
31Bh —39Bh—
(1)
31Ch — 39Ch MDCON
(1)
31Dh
(1)
31Eh
320h
Unimplemented
(1)
299h CCPR2H
(1)
29Ah CCP2CON
(1)
29Bh PWM2CON
(1)
29Ch CCP2AS
(1)
29Dh PSTR2CON
(1)
29Eh CCPTMRS
(1)
29Fh —31Fh—39Fh
2A0h
(1)
Unimplemented
(1)
(1)
(1)
—
—
Read as ‘0’
36Fh 3EFh
2F0h
Accesses
70h – 7Fh
370h
Accesses
70h – 7Fh
380h
Core Registers
(Table 3-2)
391h —
392h —
393h —
398h —
399h —
39Ah CLKRCON
39Dh
39Eh
3A0h
MDSRC
MDCARL
MDCARH
Unimplemented
Read as ‘0’
3F0h
Accesses
70h – 7Fh
PIC16(L)F1826/27
DS41391D-page 24 2011 Microchip Technology Inc.
Legend: = Unimplemented data memory locations, read as ‘0’
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Ta bl e 3 -2 )
480h
48Bh
Core Registers
(Ta bl e 3 -2 )
500h
50Bh
Core Registers
(Ta bl e 3 -2 )
580h
58Bh
Core Registers
(Ta bl e 3 -2 )
600h
60Bh
Core Registers
(Ta bl e 3 -2 )
680h
68Bh
Core Registers
(Ta bl e 3 -2 )
700h
70Bh
Core Registers
(Ta bl e 3 -2 )
780h
78Bh
Core Registers
(Ta bl e 3 -2 )
40Ch
—
48Ch
—
50Ch
—
58Ch
—
60Ch
—
68Ch
—
70Ch
—
78Ch
—
40Dh
—
48Dh
—
50Dh
—
58Dh
—
60Dh
—
68Dh
—
70Dh
—
78Dh
—
40Eh
—
48Eh
—
50Eh
—
58Eh
—
60Eh
—
68Eh
—
70Eh
—
78Eh
—
40Fh
—
48Fh
—
50Fh
—
58Fh
—
60Fh
—
68Fh
—
70Fh
—
78Fh
—
410h
—
490h
—
510h
—
590h
—
610h
—
690h
—
710h
—
790h
—
411h
—
491h
—
511h
—
591h
—
611h
—
691h
—
711h
—
791h
—
412h
—
492h
—
512h
—
592h
—
612h
—
692h
—
712h
—
792h
—
413h
—
493h
—
513h
—
593h
—
613h
—
693h
—
713h
—
793h
—
414h
—
494h
—
514h
—
594h
—
614h
—
694h
—
714h
—
794h
—
415h
TMR4
(1)
495h
—
515h
—
595h
—
615h
—
695h
—
715h
—
795h
—
416h
PR4
(1)
496h
—
516h
—
596h
—
616h
—
696h
—
716h
—
796h
—
417h
T4CON
(1)
497h
—
517h
—
597h
—
617h
—
697h
—
717h
—
797h
—
418h
—
498h
—
518h
—
598h
—
618h
—
698h
—
718h
—
798h
—
419h
—
499h
—
519h
—
599h
—
619h
—
699h
—
719h
—
799h
—
41Ah
—
49Ah
—
51Ah
—
59Ah
—
61Ah
—
69Ah
—
71Ah
—
79Ah
—
41Bh
—
49Bh
—
51Bh
—
59Bh
—
61Bh
—
69Bh
—
71Bh
—
79Bh
—
41Ch
TMR6
(1)
49Ch
—
51Ch
—
59Ch
—
61Ch
—
69Ch
—
71Ch
—
79Ch
—
41Dh
PR6
(1)
49Dh
—
51Dh
—
59Dh
—
61Dh
—
69Dh
—
71Dh
—
79Dh
—
41Eh
T6CON
(1)
49Eh
—
51Eh
—
59Eh
—
61Eh
—
69Eh
—
71Eh
—
79Eh
—
41Fh
—
49Fh
—
51Fh
—
59Fh
—
61Fh
—
69Fh
—
71Fh
—
79Fh
—
420h
Unimplemented
Read as ‘0’
4A0h
Unimplemented
Read as ‘0’
520h
Unimplemented
Read as ‘0’
5A0h
Unimplemented
Read as ‘0’
620h
Unimplemented
Read as ‘0’
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h – 7Fh
4F0h
Accesses
70h – 7Fh
570h
Accesses
70h – 7Fh
5F0h
Accesses
70h – 7Fh
670h
Accesses
70h – 7Fh
6F0h
Accesses
70h – 7Fh
770h
Accesses
70h – 7Fh
7F0h
Accesses
70h – 7Fh
47Fh
4FFh 57Fh
5FFh 67Fh 6FFh 77Fh 7FFh
TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED)
PIC16(L)F1826/27
2011 Microchip Technology Inc. DS41391D-page 25
BANK16 BANK17 BANK18 BANK19 BANK20 BANK21 BANK22 BANK23
800h
80Bh
Core Registers
(Ta bl e 3 -2 )
880h
88Bh
Core Registers
(Ta bl e 3 -2 )
900h
90Bh
Core Registers
(Ta bl e 3 -2 )
980h
98Bh
Core Registers
(Ta bl e 3 -2 )
A00h
A0Bh
Core Registers
(Ta bl e 3 -2 )
A80h
A8Bh
Core Registers
(Ta bl e 3 -2 )
B00h
B0Bh
Core Registers
(Ta bl e 3 -2 )
B80h
B8Bh
Core Registers
(Ta bl e 3 -2 )
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh
9EFh
A6Fh
AEFh
B6Fh
BEFh
870h
Common RAM
(Accesses
70h – 7Fh)
8F0h
Common RAM
(Accesses
70h – 7Fh)
970h
Common RAM
(Accesses
70h – 7Fh)
9F0h
Common RAM
(Accesses
70h – 7Fh)
A70h
Common RAM
(Accesses
70h – 7Fh)
AF0h
Common RAM
(Accesses
70h – 7Fh)
B70h
Common RAM
(Accesses
70h – 7Fh)
BF0h
Common RAM
(Accesses
70h – 7Fh)
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta bl e 3 -2 )
C80h
C8Bh
Core Registers
(Ta bl e 3 -2 )
D00h
D0Bh
Core Registers
(Ta bl e 3 -2 )
D80h
D8Bh
Core Registers
(Ta bl e 3 -2 )
E00h
E0Bh
Core Registers
(Ta bl e 3 -2 )
E80h
E8Bh
Core Registers
(Ta bl e 3 -2 )
F00h
F0Bh
Core Registers
(Ta bl e 3 -2 )
F80h
F8Bh
Core Registers
(Ta bl e 3 -2 )
C0Ch
C6Fh
Unimplemented
Read as ‘0’
C8Ch
CEFh
Unimplemented
Read as ‘0’
D0Ch
D6Fh
Unimplemented
Read as ‘0’
D8Ch
DEFh
Unimplemented
Read as ‘0’
E0Ch
E6Fh
Unimplemented
Read as ‘0’
E8Ch
EEFh
Unimplemented
Read as ‘0’
F0Ch
F6Fh
Unimplemented
Read as ‘0’
F8Ch
F9Fh
Unimplemented
Read as ‘0’
FA0h
See Tab l e 3 - 4 for
more information
FEFh
C70h
Accesses
70h – 7Fh
CF0h
Accesses
70h – 7Fh
D70h
Accesses
70h – 7Fh
DF0h
Accesses
70h – 7Fh
E70h
Accesses
70h – 7Fh
EF0h
Accesses
70h – 7Fh
F70h
Common RAM
(Accesses
70h – 7Fh)
FF0h
Common RAM
(Accesses
70h – 7Fh)
C7Fh
CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED)
PIC16(L)F1826/27
PIC16(L)F1826/27
= Unimplemented data memory locations, read as ‘0’,
Bank 31
F80h
F8Bh
Core Registers
(Ta bl e 3 -2 )
F8Ch
FE3h
Unimplemented
Read as ‘0’
FE4h
STATUS_SHAD
FE5h
WREG_SHAD
FE6h
BSR_SHAD
FE7h
PCLATH_SHAD
FE8h
FSR0L_SHAD
FE9h
FSR0H_SHAD
FEAh
FSR1L_SHAD
FEBh
FSR1H_SHAD
FECh
—
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
FF0h
Common RAM
(Accesses
70h – 7Fh)
FFFh
TABLE 3-4: PIC16(L)F1826/27 MEMORY MAP (CONTINUED)
DS41391D-page 26 2011 Microchip Technology Inc.
PIC16(L)F1826/27
3.2.6 CORE FUNCTION REGISTERS SUMMARY
The Core Function registers listed in Ta bl e 3 - 5 can be
addressed from any Bank.
TABLE 3-5: CORE FUNCTION REGISTERS SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0-31
x00h or
INDF0
x80h
x01h or
INDF1
x81h
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
— — —TOPD ZDCC---1 1000 ---q quuu
— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
Shaded locations are unimplemented, read as ‘0’.
Value on
POR, BOR
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on all
other Resets
2011 Microchip Technology Inc. DS41391D-page 27
PIC16(L)F1826/27
TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Bank 0
00Ch PORTA
00Dh PORTB
00Eh
00Fh
010h
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF
013h PIR3
014h PIR4
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON
01Dh
01Eh CPSCON0 CPSON
01Fh CPSCON1
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
(1)
(1)
— Unimplemented — —
RA7
RB7 RB6 RB5 RB4 RB3 RB2
— — CCP4IF CCP3IF TMR6IF —
— — — — — — BCL2IF SSP2IF ---- --00 ---- --00
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
— — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000
RA6 RA5 RA4 RA3 RA2
— —CCP2IF
DONE
— — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000
T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
RA1
RB1 RB0
TMR4IF
—TMR1ON0000 00-0 uuuu uu-u
RA0
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
(1)
0000 0--0 0000 0--0
— --00 0-0- --00 0-0-
Bank 1
08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
08Eh
08Fh
090h
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE
093h PIE3
094h PIE4
095h
096h PCON STKOVF STKUNF
097h WDTCON
098h OSCTUNE
099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0
09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0
09Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
(1)
(1)
OPTION_REG
— Unimplemented — —
Shaded locations are unimplemented, read as ‘0’.
— — CCP4IE CCP3IE TMR6IE —
— — — — — — BCL2IE SSP2IE ---- --00 ---- --00
WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
— —RMCLRRI POR BOR 00-- 11qq qq-- qquu
— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000
— CHS4 CHS3 CHS2 CHS1 CHS0
— ADNREF
— — CCP2IE
TMR4IE
— SCS1 SCS0 0011 1-00 0011 1-00
GO/DONE
ADPREF1
(1)
0000 0--0 0000 0--0
— --00 0-0- --00 0-0-
ADON -000 0000 -000 0000
ADPREF0 0000 -000 0000 -000
Value on all
other
Resets
DS41391D-page 28 2011 Microchip Technology Inc.
PIC16(L)F1826/27
TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Bank 2
10Ch LATA LATA7 LATA6 — L ATA4 LATA3 LATA2 LATA1 L ATA0 xx-x xxxx uu-u uuuu
10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu
10Eh
10Fh
110h
111h CM1CON0 C1ON C1OUT C1OE C1POL
112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0
113h CM2CON0 C2ON C2OUT C2OE C2POL
114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0
115h CMOUT
116h BORCON SBOREN
117h FVRCON FVREN FVRRDY
118h DACCON0 DACEN DACLPS DACOE
119h DACCON1
11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
11Ch
11Dh APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL
11Eh APFCON1
11Fh
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— C1SP C1HYS C1SYNC 0000 -100 0000 -100
— — C1NCH<1:0> 0000 --00 0000 --00
— C2SP C2HYS C2SYNC 0000 -100 0000 -100
— — C2NCH1 C2NCH0 0000 --00 0000 --00
— — — — — — MC2OUT MC1OUT ---- --00 ---- --00
— — — — — — BORRDY 1--- ---q u--- ---u
Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0qrr 0000 0qrr 0000
— DACPSS1 DACPSS0 — DACNSS 000- 00-0 000- 00-0
— — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000
— Unimplemented — —
— — — — — — — TXCKSEL ---- ---0 ---- ---0
— Unimplemented — —
(1)
CCP2SEL
(1)
P1DSEL P1CSEL CCP1SEL 0000 0000 0000 0000
Bank 3
18Ch ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 ---1 1111 ---1 1111
18Dh ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1
18Eh
18Fh
190h
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000
197h
198h
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Note 1: PIC16(L)F1827 only.
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000
— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
— Unimplemented — —
— Unimplemented — —
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Shaded locations are unimplemented, read as ‘0’.
— 1111 111- 1111 111-
Value on all
other
Resets
2011 Microchip Technology Inc. DS41391D-page 29
PIC16(L)F1826/27
TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Bank 4
20Ch WPUA — —WPUA5— — — — — --1- ---- --1- ----
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh
20Fh
210h
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000
213h SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
219h SSP2BUF
21Ah SSP2ADD
21Bh SSP2MSK
21Ch SSP2STAT
21Dh SSP2CON1
21Eh SSP2CON2
21Fh SSP2CON3
— Unimplemented — —
(1)
Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
(1)
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000
(1)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111
(1)
SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
(1)
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
(1)
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
(1)
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
Bank 5
28Ch — Unimplemented — —
28Dh
28Eh
28Fh
290h
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
294h PWM1CON P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 0000 0000
295h CCP1AS CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000
296h PSTR1CON
297h
298h CCPR2L
299h CCPR2H
29Ah CCP2CON
— Unimplemented — —
(1)
(1)
(1)
29Bh PWM2CON
29Ch CCP2AS
(1)
29Dh PSTR2CON
29Eh CCPTMRS
29Fh
— Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
(1)
Shaded locations are unimplemented, read as ‘0’.
— — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001
Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
(1)
P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000
CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000
(1)
— — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001
C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
Note 1: PIC16(L)F1827 only.
Value on all
other
Resets
DS41391D-page 30 2011 Microchip Technology Inc.
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