Datasheet PIC16F1782, PIC16LF1782, PIC16F1783, PIC16LF1783 Datasheet

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PIC16(L)F1782/3

Data Sheet

28-Pin 8-Bit Advanced Analog

Flash Microcontrollers

 2011-2012 Microchip Technology Inc. Preliminary DS41579C

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC

logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

QUALITY MANAGEMENT S

DS41579C-page 2 Preliminary  2011-2012 Microchip Technology Inc.

ISBN: 9781620761304

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

PIC16(L)F1782/3

28-Pin 8-Bit Advanced Analog Flash Microcontroller

High-Performance RISC CPU:

• Only 49 Instructions

• Operating Speed:

- DC – 32 MHz clock input

- DC – 125 ns instruction cycle

• Interrupt Capability with Automatic Context Saving

• 16-Level Deep Hardware Stack with optional Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Memory Features:

• Up to 4 KW Flash Program Memory:

- Self-programmable under software control

- Programmable code protection

- Programmable write protection

• 256 Bytes of Data EEPROM

• Up to 512 Bytes of RAM

High Performance PWM Controller:

• Two Programmable Switch Mode Controller (PSMC) modules:

- Digital and/or analog feedback control of

PWM frequency and pulse begin/end times

- 16-bit Period, Duty Cycle and Phase

- 16 ns clock resolution

- Supports Single PWM, Complementary, Push-

Pull and 3-phase modes of operation

- Dead-band control with 8-bit counter

- Auto-shutdown and restart

- Leading and falling edge blanking

-Burst mode

Extreme Low-Power Management PIC16LF1782/3 with XLP:

• Sleep mode: 50 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Secondary Oscillator: 500 nA @ 32 kHz

• Operating Current:

-8A @ 32 kHz, 1.8V, typical

-32A/MHz @ 1.8V, typical

Analog Peripheral Features:

• Analog-to-Digital Converter (ADC):

- Fully differential 12-bit converter

- 100 ksps conversion rate

- 11 single-ended channels

- 5 differential channels

- Positive and negative reference selection

• 8-bit Digital-to-Analog Converter (DAC):

- Output available externally

- Positive and negative reference selection

- Internal connections to comparators, op amps, Fixed Voltage Reference (FVR) and ADC

• Three High-Speed Comparators:

- 50 ns response time @ V

- Rail-to-rail inputs

- Software selectable hysteresis

- Internal connection to op amps, FVR and DAC

• Two Operational Amplifiers:

- Rail-to-rail inputs/outputs

- High/Low selectable Gain Bandwidth Product

- Internal connection to DAC and FVR

• Fixed Voltage Reference (FVR):

- 1.024V, 2.048V and 4.096V output levels

- Internal connection to ADC, comparators and DAC

DD = 5V

I/O Features:

• Up to 24 I/O Pins and 1 Input-only Pin:

- High current sink/source for LED drivers

- Individually programmable interrupt-onchange pins

- Individually programmable weak pull-ups

- Individual input level selection

- Individually programmable slew rate control

- Individually programmable open drain outputs

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 3

PIC16(L)F1782/3

Digital Peripheral Features:

• Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated low-power 32 kHz oscillator driver

• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

• Two Capture/Compare/PWM modules (CCP):

- 16-bit capture, maximum resolution 12.5 ns

- 16-bit compare, max resolution 31.25 ns

- 10-bit PWM, max frequency 32 kHz

• Master Synchronous Serial Port (SSP) with SPI

CTM with:

and I

- 7-bit address masking

- SMBus/PMBus

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART):

- RS-232, RS-485 and LIN compatible

- Auto-baud detect

- Auto-wake-up on start

compatibility

Oscillator Features:

• Operate up to 32 MHz from Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range from

32 MHz to 31 kHz

• 31 kHz Low-Power Internal Oscillator

• 32.768 kHz Timer1 Oscillator:

- Available as system clock

- Low-power RTC

• External Oscillator Block with:

- 4 crystal/resonator modes up to 32 MHz using 4x PLL

- 3 external clock modes up to 32 MHz

• 4x Phase-Locked Loop (PLL)

• Fail-Safe Clock Monitor:

- Detect and recover from external oscillator failure

• Two-Speed Start-up:

- Minimize latency between code execution and external oscillator start-up

General Microcontroller Features:

• Power-Saving Sleep mode

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• Brown-out Reset (BOR) with Selectable Trip Point

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming

• In-Circuit Debug (ICD)

• Enhanced Low-Voltage Programming (LVP)

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1782/3)

- 2.3V to 5.5V (PIC16F1782/3)

(ICSPTM)

PIC16(L)F178X Family Types

Device

(bytes)

Flash (words)

Data Sheet Index

Program Memory

PIC16(L)F1782 (1) 2048 256 256 25 11 3 2 1 2/1 2 2 1 1 I Y PIC16(L)F1783 (1) 4096 256 512 25 11 3 2 1 2/1 2 2 1 1 I Y PIC16(L)F1784 (2) 4096 256 512 36 14 4 3 1 2/1 3 3 1 1 I Y PIC16(L)F1786 (2) 8192 256 1024 25 11 4 2 1 2/1 3 3 1 1 I Y PIC16(L)F1787 (2) 8192 256 1024 36 14 4 3 1 2/1 3 3 1 1 I Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS41579 PIC16(L)F1782/3 Data Sheet, 28-Pin Flash, 8-bit Advanced Analog MCUs. 2: Future Release PIC16(L)F1784/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs.

Data EEPROM

(2)

Mode Controllers

(PSMC)

CCP

EUSART

I/O’s

(bytes)

Data SRAM

12-bit ADC (ch)

Amplifiers

Operational

Comparators

Timers

8-bit DAC

(8/16-bit)

Programmable Switch

C™/SPI)

MSSP (I

(1)

Debug

XLP

DS41579C-page 4 Preliminary  2011-2012 Microchip Technology Inc.

FIGURE 1: 28-PIN DIAGRAM FOR PIC16(L)F1782/3

SPDIP, SOIC, SSOP

1 2 3 4 5 6 7

8 9

VPP/MCLR/RE3

RA0 RA1 RA2

RA3 RA4

RA5

RB6/ICSPCLK

RB5

RB4 RB3 RB2 RB1

RB0

VDD

VSS 11 12

13 14

28 27 26 25 24 23

RA7

RA6 RC0 RC1 RC2 RC3

RC5 RC4

RC7 RC6

RB7/ICSPDAT

Note: See Table 1 for the location of all peripheral functions.

PIC16(L)F1782/3

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 5

PIC16(L)F1782/3

2 3

RC0

RB7/ICSPDAT

RB6/ICSPCLK

RB5

RB4

RB3 RB2

RB1 RB0 V

VSS RC7

RC6

RC5

RC4

RE3/MCLR

/VPP

RA0

RA1

RA2 RA3 RA4 RA5 VSS RA7 RA6

RC1

RC2

RC3

13814

232822

PIC16(L)F1782/3

QFN, UQFN

Note: See Ta bl e 1 for the location of all peripheral functions.

FIGURE 2: 28-PIN DIAGRAM FOR PIC16(L)F1782/3

DS41579C-page 6 Preliminary  2011-2012 Microchip Technology Inc.

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1782/3)

PIC16(L)F1782/3

I/O

ADC

28-Pin QFN, UQFN

ADC Reference

Comparator

Operation Amplifiers

8-bit DAC

Timers

PSMC

CCP

EUSART

MSSP

Pull-up

Interrupt

28-Pin SPDIP, SOIC, SSOP

RA0 2 27 AN0 — C1IN0-

C2IN0C3IN0-

RA1 3 28 AN1 — C1IN1-

C2IN1C3IN1-

RA2 4 1 AN2 VREF- C1IN0+

C2IN0+

— — — — — — — IOC Y —

OPA1OUT — — — — — — IOC Y —

— DACOUT1

REF-

DACV

— — — — — IOC Y —

C3IN0+

RA3 5 2 AN3

REF1+

C1IN1+ — DACV

REF+— — — — —IOCY —

RA4 6 3 — — C1OUT OPA1IN+ — T0CKI — — — — IOC Y —

C2IN3-

(1)

OPA1IN- — — — — — SS IOC Y —

(2)

— — — — — — — IOC Y OSC2/

PSMC1CLK PSMC2CLK

PSMC1IN PSMC2IN

———IOCYOSC1/

(2)

CCP1

— — INT/

IOC

OPA2OUT — — — — — — IOC Y —

CLKOUT

CLKIN

Y —

RA5 7 4 AN4 — C2OUT

RA6 10 7 — — C2OUT

RA7 9 6 — V

REF2+ — — — —

RB0 21 18 AN12 — C2IN1+ — — —

RB1 22 19 AN10 — C1IN3-

C3IN3-

RB2 23 20 AN8 — — OPA2IN- — — — — — — IOC Y CLKR

(2)

RB3 24 21 AN9 —

C1IN2-

OPA2IN+ — — — CCP2

——IOCY—

C2IN2C3IN2-

RB4 25 22 AN11 — C3IN1+ — — — — — — — IOC Y —

SDI

SDA

SCK

SCL

(2)

IOC Y —

(2)

IOC Y ICSPCLK

(2)

IOC Y ICSPDAT

(2)

RB5 26 23 AN13 — C3OUT — — T1G — — — SDO

RB6 27 24 — — — — — — — — TX

RB7 28 25 — — — — DACOUT2 — — — RX

RC0 11 8 — — — — — T1OSO

PSMC1A — — — IOC Y —

(2) (2)

T1CKI

(1)

RC1 12 9 — — — — — T1OSI PSMC1B CCP2

RC2 13 10 — — — — — — PSMC1C CCP1

RC3 14 11 — — — — — — PSMC1D — — SCK

RC4 15 12 — — — — — — PSMC1E — — SDI

RC5 16 13 — — — — — — PSMC1F — — SDO

RC6 17 14 — — — — — — PSMC2A — TX

RC7 18 15 — — — — — — PSMC2B — RX

——IOCY—

(1)

— — IOC Y —

(1) (1)

(1)

IOC Y —

(1)

SCL

(1)

IOC Y —

(1)

SDA

(1)

IOC Y —

— IOC Y —

—IOCY —

RE3 1 26 — — — — — — — — — — IOC Y MCLR

VDD 20 17 — — — — — — — — — — — — VDD

VSS 8,195, 16—— — — — — — —————VSS

Basic

Note 1: Default pin assignment.

2: Alternate pin assignment that can be selected via software.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 7

PIC16(L)F1782/3

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 17

3.0 Memory Organization ................................................................................................................................................................. 19

4.0 Device Configuration .................................................................................................................................................................. 43

5.0 Resets ........................................................................................................................................................................................ 49

6.0 Oscillator Module........................................................................................................................................................................ 57

7.0 Reference Clock Module ............................................................................................................................................................ 75

8.0 Interrupts .................................................................................................................................................................................... 79

9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 93

10.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 97

11.0 Watchdog Timer (WDT) ............................................................................................................................................................. 99

12.0 Date EEPROM and Flash Program Memory Control ............................................................................................................... 103

13.0 I/O Ports ................................................................................................................................................................................... 117

14.0 Interrupt-on-Change ................................................................................................................................................................. 139

15.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 143

16.0 Temperature Indicator .............................................................................................................................................................. 147

17.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 149

18.0 Operational Amplifier (OPA) Module ........................................................................................................................................ 163

19.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 167

20.0 Comparator Module.................................................................................................................................................................. 171

21.0 Timer0 Module ......................................................................................................................................................................... 181

22.0 Timer1 Module ......................................................................................................................................................................... 185

23.0 Timer2 Module ......................................................................................................................................................................... 197

24.0 Programmable Switch Mode Control (PSMC) Module ............................................................................................................. 201

25.0 Capture/Compare/PWM Module .............................................................................................................................................. 255

26.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 265

27.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 317

28.0 In-Circuit Serial Programming

29.0 Instruction Set Summary .......................................................................................................................................................... 349

30.0 Electrical Specifications............................................................................................................................................................ 363

31.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 397

32.0 Development Support............................................................................................................................................................... 415

33.0 Packaging Information.............................................................................................................................................................. 419

Appendix A: Revision History............................................................................................................................................................. 431

Index .................................................................................................................................................................................................. 433

The Microchip Web Site..................................................................................................................................................................... 441

Customer Change Notification Service .............................................................................................................................................. 441

Customer Support .............................................................................................................................................................................. 441

Reader Response .............................................................................................................................................................................. 441

Product Identification System............................................................................................................................................................. 443

™ (ICSP™) ................................................................................................................................ 347

DS41579C-page 8 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 9

PIC16(L)F1782/3

NOTES:

DS41579C-page 10 Preliminary  2011-2012 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16(L)F1782/3 are described within this data sheet. They are available in 28-pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1782/3 devices. Table 1-2 shows the pinout descriptions.

Reference Ta bl e 1 -1 for peripherals available per device.

PIC16(L)F1782/3

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1782

Analog-to-Digital Converter (ADC) ●● Digital-to-Analog Converter (DAC) ●● Fixed Voltage Reference (FVR) ●● Reference Clock Module ●● Temperature Indicator ●● Capture/Compare/PWM (CCP/ECCP) Modules

CCP1 ●● CCP2 ●●

Comparators

C1 ●● C2 ●● C3 ●●

Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)

EUSART ●●

Master Synchronous Serial Ports

MSSP ●●

Op Amp

Op Amp 1 ●● Op Amp 2 ●●

Programmable Switch Mode Controller (PSMC)

PSMC1 ●● PSMC2 ●●

Timers

Timer0 ●● Timer1 ●● Timer2 ●●

PIC16(L)F1783

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 11

PIC16(L)F1782/3

PORTA

PORTB

PORTC

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

LFINTOSC

Oscillator

MCLR

Figure 2-1

CLKIN

CLKOUT

ADC

12-Bit

FVR

Te mp .

Indicator

EUSART

Comparators

MSSPTimer2Timer1Timer0

DAC

CCPs

PSMCsOp Amps

PORTE

HFINTOSC/

FIGURE 1-1: PIC16(L)F1782/3 BLOCK DIAGRAM

DS41579C-page 12 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/C1IN0-/C2IN0-/C3IN0- RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

C1IN0-

C2IN0-

C3IN0-

RA1/AN1/C1IN1-/C2IN1-/ C3IN1-/OPA1OUT

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

C1IN1-

C2IN1-

C3IN1-

OPA1OUT

RA2/AN2/C1IN0+/C2IN0+/ C3IN0+/DACOUT1/V

REF-

DACV

REF-/

RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

C1IN0+

C2IN0+

C3IN0+

DACOUT — AN Digital-to-Analog Converter output.

REF- AN — A/D Negative Voltage Reference input.

REF- AN — Digital-to-Analog Converter negative reference.

DACV

RA3 TTL/ST CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

REF+ AN — A/D Voltage Reference input.

RA3/AN3/V DACV

REF+

(1)

/C1IN1+/

C1IN1+

DACVREF+ AN — Digital-to-Analog Converter positive reference.

RA4/C1OUT/OPA1IN+/T0CKI RA4 TTL/ST CMOS General purpose I/O.

C1OUT

OPA1IN+

T0CKI ST — Timer0 clock input.

RA5/AN4/C2OUT SS

/OP1INA-/

RA5 TTL/ST CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

(1)

C2OUT

OPA1IN-

RA6/C2OUT/OSC2/CLKOUT RA6 TTL/ST CMOS General purpose I/O.

C2OUT

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

2: All pins have Interrupt-on-Change functionality.

Output

Typ e

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

—AN

AN — Comparator C1 positive input.

AN — Comparator C2 positive input.

AN — Comparator C3 positive input.

AN — Comparator C1 positive input.

—

CMOS

AN —

—

CMOS

AN —

Operational Amplifier 1 output.

Comparator C1 output.

Operational Amplifier 1 non-inverting input.

Comparator C2 output.

Operational Amplifier 1 inverting input.

Description

ST — Slave Select input.

—

CMOS

Comparator C2 output.

OSC/4 output.

C™ = Schmitt Trigger input with I2C

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 13

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)

Name Function

RA7/V PSMC2CLK/OSC1/CLKIN

RB0/AN12/C2IN1+/PSMC1IN/ PSMC2IN/CCP1

RB1/AN10/C1IN3-/C2IN3-/ C3IN3-/OPA2OUT

RB2/AN8/OPA2IN-/CLKR RB2 TTL/ST CMOS General purpose I/O.

RB3/AN9/C1IN2-/C2IN2-/ C3IN2-/OPA2IN+/CCP2

RB4/AN11/C3IN1+ RB4 TTL/ST CMOS General purpose I/O.

RB5/AN13/C3OUT/T1G/SDO

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

(1)

REF+

/PSMC1CLK/

(1)

/INT

(1)

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: All pins have Interrupt-on-Change functionality.

RA7 TTL/ST CMOS General purpose I/O.

REF+ AN — A/D Voltage Reference input.

PSMC1CLK

PSMC2CLK ST — PSMC2 clock input.

OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKIN st — External clock input (EC mode).

RB0 TTL/ST CMOS General purpose I/O.

AN12 AN — A/D Channel 12 input.

C2IN1+

PSMC1IN ST — PSMC1 Event Trigger input.

PSMC2IN ST — PSMC2 Event Trigger input.

CCP1 ST CMOS Capture/Compare/PWM1.

INT ST — External interrupt.

RB1 TTL/ST CMOS General purpose I/O.

AN10 AN — A/D Channel 10 input.

C1IN3-

C2IN3-

C3IN3-

OPA2OUT

AN8 AN — A/D Channel 8 input.

OPA2IN-

CLKR

RB3 TTL/ST CMOS General purpose I/O.

AN9 AN — A/D Channel 9 input.

C1IN2-

C2IN2-

C3IN2-

OPA2IN+

CCP2 ST CMOS Capture/Compare/PWM2.

AN11 AN — A/D Channel 11 input.

C3IN1+

RB5 TTL/ST CMOS General purpose I/O.

AN13 AN — A/D Channel 13 input.

C3OUT — CMOS Comparator C3 output.

T1G ST — Timer1 gate input.

SDO — CMOS SPI data output.

Input

Output

Typ e

ST — PSMC1 clock input.

AN — Comparator C2 positive input.

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

—AN

AN —

—CMOS

AN — Comparator C1 negative input.

AN — Comparator C2 negative input.

AN — Comparator C3 negative input.

AN —

AN — Comparator C3 positive input.

Operational Amplifier 2 output.

Operational Amplifier 2 inverting input.

Clock output.

Operational Amplifier 2 non-inverting input.

Description

C™ = Schmitt Trigger input with I2C

DS41579C-page 14 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

(1)

RB6/TX ICSPCLK

/CK

/SDI

/SDA

(1)

RB6 TTL/ST CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

SDI ST — SPI data input.

SDA I

ICSPCLK ST — Serial Programming Clock.

RB7/DACOUT2/RX

(1)

/SCL

(1)

/ICSPDAT

SCK

RB7 TTL/ST CMOS General purpose I/O.

DACOUT2 — AN Voltage Reference output.

(1)

/DT

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

SCK ST CMOS SPI clock.

SCL I

ICSPDAT ST CMOS ICSP™ Data I/O.

RC0/T1OSO/T1CKI/PSMC1A RC0 TTL/ST CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

PSMC1A — CMOS PSMC1 output A.

RC1/T1OSI/PSMC1B/CCP2

(1)

RC1 TTL/ST CMOS General purpose I/O.

T1OSI XTAL XTAL Timer1 oscillator connection.

PSMC1B — CMOS PSMC1 output B.

CCP2 ST CMOS Capture/Compare/PWM2.

RC2/PSMC1C/CCP1

(1)

RC2 TTL/ST CMOS General purpose I/O.

PSMC1C — CMOS PSMC1 output C.

CCP1 ST CMOS Capture/Compare/PWM1.

RC3/PSMC1D/SCK

/SCL

RC3 TTL/ST CMOS General purpose I/O.

(1)

PSMC1D — CMOS PSMC1 output D.

SCK ST CMOS SPI clock.

SCL I

(1)

RC4/PSMC1E/SDI

/SDA

(1)

RC4 TTL/ST CMOS General purpose I/O.

PSMC1E — CMOS PSMC1 output E.

SDI ST — SPI data input.

SDA I

RC5/PSMC1F/SDO

(1)

RC5 TTL/ST CMOS General purpose I/O.

PSMC1F — CMOS PSMC1 output F.

SDO — CMOS SPI data output.

RC6/PSMC2A/TX

/CK

RC6 TTL/ST CMOS General purpose I/O.

(1)

PSMC2A — CMOS PSMC2 output A.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC7/PSMC2B/RX

/DT

RC7 TTL/ST CMOS General purpose I/O.

(1)

PSMC2B — CMOS PSMC2 output B.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

2: All pins have Interrupt-on-Change functionality.

Output

Typ e

CODI2C™ data input/output.

CODI2C™ clock.

CODI2C™ data input/output.

Description

C™ = Schmitt Trigger input with I2C

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 15

PIC16(L)F1782/3

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)

Name Function

RE3/MCLR

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.

/VPP

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: All pins have Interrupt-on-Change functionality.

RE3 TTL/ST — General purpose input.

MCLR

PP HV — Programming voltage.

Input

Output

Typ e

ST — Master Clear with internal pull-up.

Description

C™ = Schmitt Trigger input with I2C

DS41579C-page 16 Preliminary  2011-2012 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See 8.5 “Automatic Context Saving”, for more information.

PIC16(L)F1782/3

2.2 16-level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See Section 3.5 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary” for more

details.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 17

PIC16(L)F1782/3

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Brown-out

Reset

VSS

Internal

Oscillator

Block

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

VSS

Internal

Oscillator

Block

Data Bus

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VSS

Internal

Oscillator

Block

RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

ConfigurationConfigurationConfiguration

Flash

Program

Memory

FIGURE 2-1: CORE BLOCK DIAGRAM

DS41579C-page 18 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

• Data EEPROM memory

Note 1: The Data EEPROM Memory and the

method to access Flash memory through the EECON registers is described in

Section 12.0 “Data EEPROM and Flash Program Memory Control”.

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1782 2,048 07FFh PIC16(L)F1783 4,096 0FFFh

(1)

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1782/3 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1, and 3-2).

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 19

PIC16(L)F1782/3

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip Program Memory

Page 0

07FFh

Wraps to Page 0

0800h

CALL, CALLW RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

7FFFh

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh 1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16F1782

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR PIC16F1783

DS41579C-page 20 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

constants

BRW ;Add Index in W to

;program counter to

;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W

constants

retlw DATA0 ;Index0 data retlw DATA1 ;Index1 data retlw DATA2 retlw DATA3

my_function

;… LOTS OF CODE… movlw LOW constants movwf FSR1L movlw HIGH constants movwf FSR1H moviw 0[INDF1]

;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a location in program memory.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 21

PIC16(L)F1782/3

Addresses BANKx

x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR

x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

Data Memory uses a 12-bit address. The upper 7-bits of the address define the Bank address and the lower 5-bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta b l e 3 - 2 . For detailed information, see Tab le 3 -7 .

TABLE 3-2: CORE REGISTERS

DS41579C-page 22 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”).

Note: The C and DC bits operate as Borrow and

Digit Borrow subtraction.

out bits, respectively, in

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —TOPD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

(1)

bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

(1)

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 23

PIC16(L)F1782/3

0Bh 0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.3.1 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

3.3.3 COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

DS41579C-page 24 Preliminary  2011-2012 Microchip Technology Inc.

3.3.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown in Table 3-3.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 25

TABLE 3-3: PIC16(L)F1782/3 MEMORY MAP (BANKS 0-7)

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 - 2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh 00Fh 010h PORTE 090h TRISE 110h 011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h 012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h 013h 014h PIR4 094h PIE4 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h 015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON 295h 016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSPCON3 297h 018h T1CON 098h OSCTUNE 118h DACCON0 198h 019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h 01Ah TMR2 09Ah OSCSTAT 11Ah 01Bh PR2 09Bh ADRESL 11Bh 01Ch T2CON 09Ch ADRESH 11Ch 01Dh 01Eh 01Fh 020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—093h— 113h CM2CON0 193h EEDATL 213h SSPMSK 293h CCPR1CON 313h — 393h IOCAF

— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh IOCEP — 09Eh ADCON1 11Eh CM3CON0 19Eh TXSTA 21Eh —29Eh—31Eh—39EhIOCEN — 09Fh ADCON2 11Fh CM3CON1 19Fh BAUDCON 21Fh —29Fh—31Fh—39FhIOCEF

General Purpose Register 80 Bytes

Common RAM

70h – 7Fh

080h

0A0h

0F0h

Core Registers

(Ta bl e 3 - 2)

General Purpose Register 80 Bytes

Accesses

70h – 7Fh

100h

120h

13Fh 140h

170h

Core Registers

(Table 3-2)

—190h— 210h WPUE 290h — 310h — 390h INLVLE

— 19Ah TXREG 21Ah — 29Ah CCPR2CON 31Ah —39Ah— — 19Bh SPBRG 21Bh —29Bh—31Bh—39Bh— — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —

General Purpose Register

80 Bytes

Accesses 70h – 7Fh

180h

1A0h

1F0h

Core Registers

(Table 3-2)

— 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC

—218h— 298h CCPR2L 318h — 398h IOCCN

General Purpose Register

80 Bytes

Accesses

70h – 7Fh

200h

Core Registers

(Table 3-2)

— 299h CCPR2H 319h — 399h IOCCF

220h

General Purpose

(1)

270h

80 Bytes

Accesses

70h – 7Fh

280h

Core Registers

(Table 3-2)

— 314h — 394h IOCBP — 315h — 395h IOCBN — 316h — 396h IOCBF — 317h — 397h IOCCP

2A0h

General Purpose

(1)

2F0h

80 Bytes

Accesses

70h – 7Fh

300h

Core Registers

(Table 3-2)

320h

General Purpose

(1)

36Fh 3EFh 370h

32 Bytes

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

380h

— 391h IOCAP — 392h IOCAN

3A0h

(1)

3F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

PIC16(L)F1782/3

DS41579C-page 26 Preliminary  2011-2012 Microchip Technology Inc.

Legend: = Unimplemented data memory locations, read as ‘0’

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

40Bh

Core Registers

(Ta bl e 3 - 2)

480h

48Bh

Core Registers

(Ta bl e 3 - 2)

500h

50Bh

Core Registers

(Ta bl e 3 - 2)

580h

58Bh

Core Registers

(Ta bl e 3 - 2)

600h

60Bh

Core Registers

(Ta bl e 3 - 2)

680h

68Bh

Core Registers

(Ta bl e 3 - 2)

700h

70Bh

Core Registers

(Ta bl e 3 - 2)

780h

78Bh

Core Registers

(Ta bl e 3 - 2)

40Ch

Unimplemented

Read as ‘0’

48Ch

Unimplemented

Read as ‘0’

50Ch

Unimplemented

Read as ‘0’

58Ch

Unimplemented

Read as ‘0’

60Ch

Unimplemented

Read as ‘0’

68Ch

Unimplemented

Read as ‘0’

70Ch

Unimplemented

Read as ‘0’

78Ch

Unimplemented

Read as ‘0’

510h 511h

OPA1CON

512h

—

513h

OPA2CON

514h

Unimplemented

Read as ‘0’

519h 51Ah

CLKRCON

51Bh

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h

Common RAM

(Accesses

70h – 7Fh)

4F0h

Common RAM

(Accesses

70h – 7Fh)

570h

Common RAM

(Accesses

70h – 7Fh)

5F0h

Common RAM

(Accesses 70h – 7Fh)

670h

Common RAM

(Accesses

70h – 7Fh)

6F0h

Common RAM

(Accesses 70h – 7Fh)

770h

Common RAM

(Accesses

70h – 7Fh)

7F0h

Common RAM

(Accesses 70h – 7Fh)

47Fh

4FFh 57Fh

5FFh 67Fh 6FFh 77Fh 7FFh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

80Bh

Core Registers

(Ta bl e 3 - 2)

880h

88Bh

Core Registers

(Ta bl e 3 - 2)

900h

90Bh

Core Registers

(Ta bl e 3 - 2)

980h

98Bh

Core Registers

(Ta bl e 3 - 2)

A00h

A0Bh

Core Registers

(Ta bl e 3 - 2)

A80h

A8Bh

Core Registers

(Ta bl e 3 - 2)

B00h

B0Bh

Core Registers

(Ta bl e 3 - 2)

B80h

B8Bh

Core Registers

(Ta bl e 3 - 2)

80Ch

See Ta bl e 3 - 5

88Ch

Unimplemented

Read as ‘0’

90Ch

Unimplemented

Read as ‘0’

98Ch

Unimplemented

Read as ‘0’

A0Ch

Unimplemented

Read as ‘0’

A8Ch

Unimplemented

Read as ‘0’

B0Ch

Unimplemented

Read as ‘0’

B8Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh

9EFh

A6Fh

AEFh

B6Fh

BEFh

870h

Common RAM

(Accesses

70h – 7Fh)

8F0h

Common RAM

(Accesses

70h – 7Fh)

970h

Common RAM

(Accesses

70h – 7Fh)

9F0h

Common RAM

(Accesses 70h – 7Fh)

A70h

Common RAM

(Accesses

70h – 7Fh)

AF0h

Common RAM

(Accesses 70h – 7Fh)

B70h

Common RAM

(Accesses

70h – 7Fh)

BF0h

Common RAM

(Accesses 70h – 7Fh)

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3 - 2)

C80h

C8Bh

Core Registers

(Ta bl e 3 - 2)

D00h

D0Bh

Core Registers

(Ta bl e 3 - 2)

D80h

D8Bh

Core Registers

(Ta bl e 3 - 2)

E00h

E0Bh

Core Registers

(Ta bl e 3 - 2)

E80h

E8Bh

Core Registers

(Ta bl e 3 - 2)

F00h

F0Bh

Core Registers

(Ta bl e 3 - 2)

F80h

F8Bh

Core Registers

(Ta bl e 3 - 2)

C0Ch

C6Fh

Unimplemented

Read as ‘0’

C8Ch

CEFh

Unimplemented

Read as ‘0’

D0Ch

D6Fh

Unimplemented

Read as ‘0’

D8Ch

DEFh

Unimplemented

Read as ‘0’

E0Ch

E6Fh

Unimplemented

Read as ‘0’

E8Ch

EEFh

Unimplemented

Read as ‘0’

F0Ch

F6Fh

Unimplemented

Read as ‘0’

F8Ch

FEFh

See Ta bl e 3 -6

C70h

Common RAM

(Accesses

70h – 7Fh)

CF0h

Common RAM

(Accesses

70h – 7Fh)

D70h

Common RAM

(Accesses

70h – 7Fh)

DF0h

Common RAM

(Accesses 70h – 7Fh)

E70h

Common RAM

(Accesses

70h – 7Fh)

EF0h

Common RAM

(Accesses 70h – 7Fh)

F70h

Common RAM

(Accesses

70h – 7Fh)

FF0h

Common RAM

(Accesses 70h – 7Fh)

C7Fh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-4: PIC16(L)F1782/3 MEMORY MAP (BANKS 8-31)

PIC16(L)F1782/3

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 16 BANK 16

811h

PSMC1CON

831h

PSMC2CON

812h

PSMC1MDL

832h

PSMC2MDL

813h

PSMC1SYNC

833h

PSMC2SYNC

814h

PSMC1CLK

834h

PSMC2CLK

815h

PSMC1OEN

835h

PSMC2OEN

816h

PSMC1POL

836h

PSMC2POL

817h

PSMC1BLNK

837h

PSMC2BLNK

818h

PSMC1REBS

838h

PSMC2REBS

819h

PSMC1FEBS

839h

PSMC2FEBS

81Ah

PSMC1PHS

83Ah

PSMC2PHS

81Bh

PSMC1DCS

83Bh

PSMC2DCS

81Ch

PSMC1PRS

83Ch

PSMC2PRS

81Dh

PSMC1ASDC

83Dh

PSMC2ASDC

81Eh

PSMC1ASDD

83Eh

PSMC2ASDD

81Fh

PSMC1ASDS

83Fh

PSMC2ASDS

820h

PSMC1INT

840h

PSMC2INT

821h

PSMC1PHL

841h

PSMC2PHL

822h

PSMC1PHH

842h

PSMC2PHH

823h

PSMC1DCL

843h

PSMC2DCL

824h

PSMC1DCH

844h

PSMC2DCH

825h

PSMC1PRL

845h

PSMC2PRL

826h

PSMC1PRH

846h

PSMC2PRH

827h

PSMC1TMRL

847h

PSMC2TMRL

828h

PSMC1TMRH

848h

PSMC2TMRH

829h

PSMC1DBR

849h

PSMC2DBR

82Ah

PSMC1DBF

84Ah

PSMC2DBF

82Bh

PSMC1BLKR

84Bh

PSMC2BLKR

82Ch

PSMC1BLKF

84Ch

PSMC2BLKF

82Dh

PSMC1FFA

84Dh

PSMC1FFA

82Eh

PSMC1STR0

84Eh

PSMC2STR0

82Fh

PSMC1STR1

84Fh

PSMC2STR1

830h

—

840h

86Fh

Unimplemented

Read as ‘0’

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 31

F8Ch

Unimplemented

Read as ‘0’

FE3h FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

TABLE 3-5: PIC16(L)F1782/3 MEMORY

MAP (BANK 16 DETAILS)

TABLE 3-6: PIC16(L)F1782/3 MEMORY

MAP (BANK 31 DETAILS)

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 27

PIC16(L)F1782/3

3.3.5 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3- 7 can be addressed from any Bank.

TABLE 3-7: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

Value on all

other Resets

DS41579C-page 28 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu

00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

00Fh

— Unimplemented — —

010h PORTE

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF

013h

— Unimplemented — —

014h PIR4

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

016h TMR2 Holding Register for the Least Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu

017h PR2 Holding Register for the Most Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu

018h T2CON

01Dh

— Unimplemented — —

01Fh

Bank 1

08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111

08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111

08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111

08Fh

— Unimplemented — —

090h TRISE

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE

093h

— Unimplemented — —

094h PIE4

095h

OPTION_REG

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0

09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR

09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu

09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0

09Fh ADCON2 TRIGSEL3 TRIGSEL2 TRIGSEL1 TRIGSEL0 CHSN3 CHSN2 CHSN1 CHSN0 000- -000 000- -000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — —RE3— — — ---- x--- ---- u---

— C3IF CCP2IF 0000 0-00 0000 0-00

— — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF --00 --00 --00 --00

—TMR1ON0000 00-0 uuuu uu-u

DONE

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

— — — — —

— — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC2SIE --00 --00 --00 --00

WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu

— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000

— CHS4 CHS3 CHS2 CHS1 CHS0

(2)

HFIOFL MFIOFR LFIOFR HFIOFS 00q0 --00 qqqq --0q

— ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000

T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

— — — ---- 1--- ---- 1---

— C3IE CCP2IE 0000 0-00 0000 0-00

— SCS1 SCS0 0011 1-00 0011 1-00

GO/DONE

ADON -000 0000 -000 0000

Val ue o n

POR, BOR

Valu e o n

all other

Resets

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 29

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu

10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu

10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu

10Fh

— Unimplemented — —

110h

— Unimplemented — —

111h

CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100

112h

CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000

113h

CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100

114h

CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000

115h

CMOUT — — — — — MC3OUT MC2OUT MC1OUT ---- -000 ---- -000

116h BORCON SBOREN BORFS

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0q00 0000 0q00 0000

118h DACCON0 DACEN

119h DACCON1 DACR<7:0> 0000 0000 0000 0000

11A h

— Unimplemented — —

11C h

11Dh APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 0000 0000 0000 0000

11Eh

CM3CON0 C3ON C3OUT C3OE C3POL C3ZLF C3SP C3HYS C3SYNC 0000 0100 0000 0100

11Fh

CM3CON1 C3INTP C3INTN C3PCH<2:0> C3NCH<2:0> 0000 0000 0000 0000

Bank 3

18Ch

ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1-11 1111 1-11 1111

18Dh ANSELB

18Eh

— Unimplemented — —

190h

191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000

192h EEADRH

193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h EEDATH

195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000

196h EECON2 EEPROM / Program Memory Control Register 2 0000 0000 0000 0000

197h VREGCON

198h

— Unimplemented — —

199h RCREG USART Receive Data Register 0000 0000 0000 0000

19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000

19Bh SPBRG BRG<7:0> 0000 0000 0000 0000

19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

(2)

—

— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— — — — — —VREGPMReserved ---- --01 ---- --01

--- DACOE1 DACOE2 DACPSS<1:0> --- DACNSS 0-00 00-0 0-00 00-0

EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000

— — — — — BORRDY 1x-- ---q uu-- ---u

— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

Value on

POR, BOR

Valu e o n all other

Resets

DS41579C-page 30 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 4

20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111

20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111

20Fh

— Unimplemented — —

210h WPUE

211h SSPBUF

212h SSPADD

213h SSPMSK

214h SSPSTAT SMP CKE D/A

215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

—

— Unimplemented — —

21Fh

Bank 5

28Ch ODCONA Open Drain Control for PORTA 0000 0000 0000 0000

28Dh ODCONB Open Drain Control for PORTB 0000 0000 0000 0000

28Eh ODCONC Open Drain Control for PORTC 0000 0000 0000 0000

28Fh

— Unimplemented — —

290h

— Unimplemented — —

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000

294h

—

— Unimplemented — —

297h

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

29Ah CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000 0000 0000

29Bh

—

— Unimplemented — —

29Fh

Bank 6

30Ch SLRCONA Slew Rate Control for PORTA 0000 0000 0000 0000

30Dh SLRCONB Slew Rate Control for PORTB 0000 0000 0000 0000

30Eh SLRCONC Slew Rate Control for PORTC 0000 0000 0000 0000

30Fh —

— Unimplemented — —

31Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — WPUE3 — — — ---- 1--- ---- 1---

Synchronous Serial Port Receive Buffer/Transmit Register

ADD<7:0>

MSK<7:0>

PSR/WUA BF 0000 0000 0000 0000

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

Valu e o n

all other

Resets

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 31

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 7

38Ch INLVLA Input Type Control for PORTA 0000 0000 0000 0000

38Dh INLVLB Input Type Control for PORTB 0000 0000 0000 0000

38Eh INLVLC Input Type Control for PORTC 1111 1111 1111 1111

38Fh

— Unimplemented — —

390h

INLVLE — — — — INLVLE3 — — — ---- 1--- ---- 1---

391h IOCAP IOCAP<7:0> 0000 0000 0000 0000

392h IOCAN IOCAN<7:0> 0000 0000 0000 0000

393h IOCAF IOCAF<7:0> 0000 0000 0000 0000

394h IOCBP IOCBP<7:0> 0000 0000 0000 0000

395h IOCBN IOCBN<7:0> 0000 0000 0000 0000

396h IOCBF IOCBF<7:0> 0000 0000 0000 0000

397h IOCCP IOCCP<7:0> 0000 0000 0000 0000

398h IOCCN IOCCN<7:0> 0000 0000 0000 0000

399h IOCCF IOCCF<7:0> 0000 0000 0000 0000

39Ah —

— Unimplemented — —

39Ch

39Dh IOCEP

39Eh IOCEN

39Fh IOCEF

Bank 8-9

40Ch

41Fh

and

— Unimplemented — —

48Ch

49Fh

Bank 10

50Ch —

— Unimplemented — —

510h

511h OPA1CON OPA1EN OPA1SP

512h

— Unimplemented — —

513h OPA2CON OPA2EN OPA2SP

514h

— — 519h

51Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000

51Bh —

— Unimplemented — — 51Fh

Bank 11-15

x0Ch

x8Ch

— Unimplemented — —

x6Fh

xEFh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — IOCEP3 — — — ---- 0--- ---- 0---

— — — —IOCEN3— — — ---- 0--- ---- 0---

— — — —IOCEF3— — — ---- 0--- ---- 0---

— — — —OPA1PCH<1:0>00-- --00 00-- --00

— — — —OPA2PCH<1:0>00-- --00 00-- --00

Unimplemented — —

Value on

POR, BOR

Valu e o n all other

Resets

DS41579C-page 32 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 16

80Ch —

— Unimplemented — —

810h

811h PSMC1CON PSMC1EN PSMC1LD PSMC1DBFE PSMC1DBRE P1MODE<3:0> 0000 0000 0000 0000

812h PSMC1MDL P1MDLEN P1MDLPOL P1MDLBIT

813h PSMC1SYNC

814h PSMC1CLK

815h PSMC1OEN

816h PSMC1POL

817h PSMC1BLNK

818h PSMCIREBS P1REBIN

819h PSMCIFEBS P1FEBIN

81Ah PSMC1PHS P1PHSIN

81Bh PSMC1DCS P1DCSIN

81Ch PSMC1PRS P1PRSIN

81Dh PSMC1ASDC P1ASE P1ASDEN P1ARSEN

81Eh PSMC1ASDL

81Fh PSMC1ASDS P1ASDSIN

820h PSMC1INT P1TOVIE P1TPHIE P1TDCIE P1TPRIE P1TOVIF P1TPHIF P1TDCIF P1TPRIF 0000 0000

821h PSMC1PHL Phase Low Count 0000 0000 0000 0000

822h PSMC1PHH Phase High Count 0000 0000 0000 0000

823h PSMC1DCL Duty Cycle Low Count 0000 0000 0000 0000

824h PSMC1DCH Duty Cycle High Count 0000 0000 0000 0000

825h PSMC1PRL Period Low Count 0000 0000 0000 0000

826h PSMC1PRH Period High Count 0000 0000 0000 0000

827h PSMC1TMRL Time base Low Counter 0000 0001 0000 0001

828h PSMC1TMRH Time base High Counter 0000 0000 0000 0000

829h PSMC1DBR rising Edge Dead-band Counter 0000 0000 0000 0000

82Ah PSMC1DBF Falling Edge Dead-band Counter 0000 0000 0000 0000

82Bh PSMC1BLKR rising Edge Blanking Counter 0000 0000 0000 0000

82Ch PSMC1BLKF Falling Edge Blanking Counter 0000 0000 0000 0000

82Dh PSMC1FFA

82Eh PSMC1STR0

82Fh PSMC1STR1 P1SYNC

830h

— Unimplemented — —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — — — P1SYNC<1:0> ---- --00 ---- --00

— — P1CPRE<1:0> — — P1CSRC<1:0> --00 --00 --00 --00

— — P1OEF P1OEE P1OED P1OEC P1OEB P1OEA --00 0000 --00 0000

— P1INPOL P1POLF P1POLE P1POLD P1POLC P1POLB P1POLA -000 0000 -000 0000

— — P1FEBM<1:0> — — P1REBM<1:0> --00 --00 --00 --00

— — — P1REBSC3 P1REBSC2 P1REBSC1 — 0--- 000- 0000 000-

— — — P1FEBSC3 P1FEBSC2 P1FEBSC1 — 0--- 000- 0000 000-

— — — P1PHSC3 P1PHSC2 P1PHSC1 P1PHST 0--- 0000 0--- 0000

— — — P1DCSC3 P1DCSC2 P1DCSC1 P1DCST 0--- 0000 0--- 0000

— — — P1PRSC3 P1PRSC2 P1PRSC1 P1PRST 0--- 0000 0--- 0000

— — P1ASDLF P1ASDLE P1ASDLD P1ASDLC P1ASDLB P1ASDLA --00 0000 --00 0000

— — — P1ASDSC3 P1ASDSC2 P1ASDSC1 — 0--- 000- 0--- 000-

— — — — Fractional Frequency Adjust Register ---- 0000 ---- 0000

— — P1STRF P1STRE P1STRD P1STRC P1STRB P1STRA --00 0001 --00 0001

— — — — — P1LSMEN P1HSMEN 0--- --00 0--- --00

— P1MSRC<3:0> 000- 0000 000- 0000

— — — — P1ASDOV 000- ---0 000- ---0

Val ue o n

POR, BOR

Valu e o n

all other

Resets

0000 0000

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 33

PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 16 (Continued)

831h PSMC2CON PSMC2EN PSMC2LD PSMC2DBFE PSMC2DBRE P2MODE<3:0> 0000 0000 0000 0000

832h PSMC2MDL P2MDLEN P2MDLPOL P2MDLBIT

833h PSMC2SYNC

834h PSMC2CLK

835h PSMC2OEN

836h PSMC2POL

837h PSMC2BLNK

838h PSMC2REBS P2REBIN

839h PSMC2FEBS P2FEBIN

83Ah PSMC2PHS P2PHSIN

83Bh PSMC2DCS P2DCSIN

83Ch PSMC2PRS P2PRSIN

83Dh PSMC2ASDC P2ASE P2ASDEN P2ARSEN

83Eh PSMC2ASDL

83Fh PSMC2ASDS P2ASDSIN

840h PSMC2INT P2TOVIE P2TPHIE P2TDCIE P2TPRIE P2TOVIF P2TPHIF P2TDCIF P2TPRIF 0000 0000

841h PSMC2PHL Phase Low Count 0000 0000 0000 0000

842h PSMC2PHH Phase High Count 0000 0000 0000 0000

843h PSMC2DCL Duty Cycle Low Count 0000 0000 0000 0000

844h PSMC2DCH Duty Cycle High Count 0000 0000 0000 0000

845h PSMC2PRL Period Low Count 0000 0000 0000 0000

846h PSMC2PRH Period High Count 0000 0000 0000 0000

847h PSMC2TMRL Time base Low Counter 0000 0001 0000 0001

848h PSMC2TMRH Time base High Counter 0000 0000 0000 0000

849h PSMC2DBR rising Edge Dead-band Counter 0000 0000 0000 0000

84Ah PSMC2DBF Falling Edge Dead-band Counter 0000 0000 0000 0000

84Bh PSMC2BLKR rising Edge Blanking Counter 0000 0000 0000 0000

84Ch PSMC2BLKF Falling Edge Blanking Counter 0000 0000 0000 0000

84Dh PSMC2FFA

84Eh PSMC2STR0

84Fh PSMC2STR1 P2SYNC

850h —

— Unimplemented — — 86Fh

Bank 17-30

x0Ch

x8Ch

— Unimplemented — —

x1Fh

x9Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — — — P2SYNC<1:0> ---- --00 ---- --00

— — P2CPRE<1:0> — — P2CSRC<1:0> --00 --00 --00 --00

— — — — — — P2OEB P2OEA ---- --00 ---- --00

—P2INPOL— — — — P2POLB P2POLA -0-- --00 -0-- --00

— — P2FEBM<1:0> — — P2REBM<1:0> --00 --00 --00 --00

— — — P2REBSC3 P2REBSC2 P2REBSC1 — 0--- 000- 0000 000-

— — — P2FEBSC3 P2FEBSC2 P2FEBSC1 — 0--- 000- 0000 000-

— — — P2PHSC3 P2PHSC2 P2PHSC1 P2PHST 0--- 0000 0--- 0000

— — — P2DCSC3 P2DCSC2 P2DCSC1 P2DCST 0--- 0000 0--- 0000

— — — P2PRSC3 P2PRSC2 P2PRSC1 P2PRST 0--- 0000 0--- 0000

— — P2ASDLF P2ASDLE P2ASDLD P2ASDLC P2ASDLB P2ASDLA --00 0000 --00 0000

— — — P2ASDSC3 P2ASDSC2 P2ASDSC1 — 0--- 000- 0--- 000-

— — — — Fractional Frequency Adjust Register ---- 0000 ---- 0000

— — — — — — P2STRB P2STRA ---- --01 ---- --01

— — — — — P2LSMEN P2HSMEN 0--- --00 0--- --00

— P2MSRC<3:0> 000- 0000 000- 0000

— — — — P2ASDOV 000- ---0 000- ---0

Value on

POR, BOR

Valu e o n all other

Resets

0000 0000

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PIC16(L)F1782/3

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 31

F8Ch

— Unimplemented — —

FE3h

FE4h STATUS_

SHAD

FE5h WREG_SHAD Working Register Shadow xxxx xxxx uuuu uuuu

FE6h BSR_SHAD

FE7h PCLATH_

SHAD

FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu

FE9h FSR0H_

SHAD

FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu

FEBh FSR1H_

SHAD

FECh

— Unimplemented — —

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’.

— — — — —ZDCC---- -xxx ---- -uuu

— — — Bank Select Register Shadow ---x xxxx ---u uuuu

— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu

— — — Current Stack Pointer ---1 1111 ---1 1111

Top of Stack Low byte xxxx xxxx uuuu uuuu

— Top of Stack High byte -xxx xxxx -uuu uuuu

Val ue o n

POR, BOR

Valu e o n

all other

Resets

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PCLPCH

ALU Result

PCLATH

PCLPCH

OPCODE <10:0>

PCLATH

PCLPCH

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH

PC + W

BRW

PCLPCH

PC + OPCODE <8:0>

BRA

3.4 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN

DIFFERENT SITUATIONS

3.4.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.

3.4.4 BRANCHING

The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction.

3.4.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

3.4.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).

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PIC16(L)F1782/3

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled (STVREN = 0)

Stack Reset Enabled (STVREN = 1)

TOSH:TOSL

3.5 Stack

All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-3 and 3-3). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled.

Note: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

3.5.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR.

Reference Figure 3-5 through Figure 3-8 for examples of accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

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0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00

STKPTR = 0x00

This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack.

TOSH:TOSL

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

DS41579C-page 38 Preliminary  2011-2012 Microchip Technology Inc.

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten.

Return Address

TOSH:TOSL

PIC16(L)F1782/3

3.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register.

3.6 Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

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PIC16(L)F1782/3

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000

Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

FIGURE 3-9: INDIRECT ADDRESSING

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3.6.1 TRADITIONAL DATA MEMORY

Indirect AddressingDirect Addressing

Bank Select

Location Select

4BSR 6

From Opcode

FSRxL70

Bank Select

Location Select

00000 00001 00010 11111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

FSRxH70

0000

The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

PIC16(L)F1782/3

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PIC16(L)F1782/3

Location Select

0x2000

FSRnH

FSRnL

0x020

Bank 0

0x06F 0x0A0

Bank 1 0x0EF 0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

Location Select

0x8000

FSRnH

FSRnL

0x0000

0x7FFF

0xFFFF

Program Flash Memory (low 8 bits)

3.6.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

3.6.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH

MEMORY MAP

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4.0 DEVICE CONFIGURATION

Device Configuration consists of Configuration Words, Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Words is

managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

PIC16(L)F1782/3

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PIC16(L)F1782/3

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FCMEN IESO CLKOUTEN BOREN<1:0> CPD

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

bit 12 IESO: Internal External Switchover bit

bit 11 CLKOUTEN

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

bit 8 CPD

bit 7 CP

bit 6 MCLRE: MCLR

bit 5 PWRTE

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

1 = Fail-Safe Clock Monitor and internal/external switchover are both enabled. 0 = Fail-Safe Clock Monitor is disabled

1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled

: Clock Out Enable bit

FOSC configuration bits are set to LP, XT, HS modes:

This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.

All other FOSC modes:

1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin

11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled

: Data Code Protection bit

1 = Data memory code protection is disabled 0 = Data memory code protection is enabled

: Code Protection bit

1 = Program memory code protection is disabled 0 = Program memory code protection is enabled

/VPP Pin Function Select bit

If LVP bit =

This bit is ignored.

If LVP bit = 0:

1 =MCLR 0 =MCLR

1 = PWRT disabled 0 = PWRT enabled

11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled

/VPP pin function is MCLR; Weak pull-up enabled. /VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

: Power-up Timer Enable bit

(1)

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PIC16(L)F1782/3

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 =LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase.Once the

Data Code Protection bit is enabled, (CPD ICSP) can disable the Data Code Protection (CPD is executed, the entire Program Flash Memory, Data EEPROM and configuration memory will be erased.

= 0), the Bulk Erase Program Memory Command (through

=1). When a Bulk Erase Program Memory Command

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PIC16(L)F1782/3

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

LVP DE BUG

bit 13 bit 8

U-1 U-1 R/P-1 U-1 U-1 U-1 R/P-1 R/P-1

— —

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

VCAPEN

— — —WRT<1:0>

LPBOR BORV STVREN PLLEN

bit 13 LVP: Low-Voltage Programming Enable bit

bit 12

bit 11

bit 10 BORV: Brown-out Reset Voltage Selection bit

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

bit 8 PLLEN: PLL Enable bit

bit 7-6 Unimplemented: Read as ‘1’

bit 5 VCAPEN

bit 4-2 Unimplemented: Read as ‘1’

bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

1 = Low-voltage programming enabled 0 = High-voltage on MCLR

: In-Circuit Debugger Mode bit

DEBUG

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

: Low-Power BOR Enable bit

LPBOR

1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled

1 = Brown-out Reset voltage (Vbor), low trip point selected. 0 = Brown-out Reset voltage (Vbor), high trip point selected.

1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset

1 = 4xPLL enabled 0 = 4xPLL disabled

1 = VCAP functionality is disabled on RA6 0 = V

4 kW Flash memory (PIC16(L)F1782 only)

8 kW Flash memory (PIC16(L)F1783 only)

: Voltage Regulator Capacitor Enable bit

CAP functionality is enabled on RA6

11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control

11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control

must be used for programming

(1)

(3)

(4)

(2)

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: Not implemented on PIC16LF1782/3. 3: The DEBUG

and programmers. For normal device operation, this bit should be maintained as a '1'.

4: See Vbor parameter for specific trip point voltages.

DS41579C-page 46 Preliminary  2011-2012 Microchip Technology Inc.

bit in Configuration Words is managed automatically by device development tools including debuggers

4.3 Code Protection

Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting.

4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP Words. When CP program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write

Protection” for more information.

= 0, external reads and writes of

4.3.2 DATA EEPROM PROTECTION

The entire data EEPROM is protected from external reads and writes by the CPD external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings.

bit in Configuration

bit. When CPD = 0,

PIC16(L)F1782/3

4.4 Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected.

4.5 User ID

Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 12.5 “User ID, Device ID and Configuration Word Access”for more information on accessing

these memory locations. checksum calculation, see the “PIC16(L)F178X Memory Programming Specification” (DS41457).

For more information on

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 47

PIC16(L)F1782/3

Device

DEVICEID<13:0> Values

DEV<8:0> REV<4:0>

PIC16F1782 10 1010 000 x xxxx

PIC16LF1782 10 1010 101 x xxxx

PIC16F1783 10 1010 001 x xxxx

PIC16LF1783 10 1010 110 x xxxx

4.6 Device ID and Revision ID

The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See

Section 12.5 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.

4.7 Register Definitions: Device ID

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

RRRRRR

DEV<8:3>

bit 13 bit 8

RRRRRRRR

DEV<2:0> REV<4:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared -n = Value when blank or after Bulk Erase

bit 13-5 DEV<8:0>: Device ID bits

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

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Note 1: See Table 5-1 for BOR active conditions.

Device

Reset

Power-on

Reset

WDT

Time-out

Brown-out

Reset

LPBOR

Reset

RESET Instruction

MCLRE

Sleep

BOR

Active

(1)

PWRT

Done

PWRTE

LFINTOSC

VDD

ICSP Programming Mode Exit

Stack

Pointer

5.0 RESETS

A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1.

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low Power Brown-out Reset (LPBOR)

•MCLR Reset

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To a ll o w V DD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

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5.1 Power-On Reset (POR)

The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising V performance may require greater than minimum V The PWRT, BOR or MCLR extend the start-up period until all device operation conditions have been met.

5.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the V rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 5-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

DD, fast operating speeds or analog

DD.

features can be used to

DD to

11 X X Active Waits for BOR ready

5.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 5 -1 for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words.

DD noise rejection filter prevents the BOR from trig-

A V gering on small events. If V duration greater than parameter T will reset. See Figure 5-2 for more information.

Instruction Execution upon:

Release of POR or Wake-up from Sleep

DD falls below VBOR for a

BORDC, the device

(1)

(BORRDY = 1)

10 X

00 X XDisabled

Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits.

1 X Active Waits for BOR ready

0 XDisabled

5.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and V is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

5.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready

DD is higher than the BOR threshold.

and V

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

Awake Active

Sleep Disabled

5.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBO-

REN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the V level.

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

Waits for BOR ready (BORRDY = 1)

(1)

(BORRDY = 1)

Begins immediately (BORRDY = x)

DS41579C-page 50 Preliminary  2011-2012 Microchip Technology Inc.

FIGURE 5-2: BROWN-OUT SITUATIONS

TPWRT

(1)

VBOR

Internal

Reset

VBOR

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

PIC16(L)F1782/3

5.3 Register Definitions: BOR Control

REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN BORFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Words =

1 = BOR Enabled 0 = BOR Disabled

bit 6 BORFS: Brown-out Reset Fast Start bit

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect.

If BOREN <1:0> =

1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off

bit 5-1 Unimplemented: Read as ‘0’

bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive

— — — — —BORRDY

 01:

01:

(1)

10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

Note 1: BOREN<1:0> bits are located in Configuration Words.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 51

PIC16(L)F1782/3

5.4 Low-Power Brown-Out Reset (LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to

Figure 5-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2.

DD pin.

5.4.1 ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled.

5.4.1.1 LPBOR Module Output

The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR the PCON register and to the power control block.

signal, which goes to

5.5 MCLR

The MCLR is an optional external input that can reset the device. The MCLR MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 5-2).

TABLE 5-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled 10Enabled x1Enabled

5.5.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR V

DD through an internal weak pull-up.

The device has a noise filter in the MCLR The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR

5.5.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 13.9 “PORTE Regis-

ters” for more information.

function is controlled by the

pin is connected to

Reset path.

pin low.

5.6 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO changed to indicate the WDT Reset. See Section 11.0

“Watchdog Timer (WDT)” for more information.

and PD bits in the STATUS register are

5.7 RESET Instruction

A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Ta b le 5 -4 for default conditions after a RESET instruction has occurred.

5.8 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 5.8 “Stack Overflow/Underflow

Reset” for more information.

5.9 Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

5.10 Power-up Timer

The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running.

The Power-up Timer is controlled by the PWRTE Configuration Words.

bit of

5.11 Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if required for oscillator source).

3. MCLR

The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See

Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information.

The Power-up Timer and oscillator start-up timer run independently of MCLR long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR device will begin execution immediately (see

Figure 5-3). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

must be released (if enabled).

Reset. If MCLR is kept low

high, the

DS41579C-page 52 Preliminary  2011-2012 Microchip Technology Inc.

FIGURE 5-3: RESET START-UP SEQUENCE

TOST

TMCLR

TPWRT

VDD

Internal POR

Power-up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-up Timer

Oscillator

OSC

Internal Oscillator

Oscillator

OSC

External Clock (EC)

CLKIN

OSC

External Crystal

PIC16(L)F1782/3

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 53

PIC16(L)F1782/3

5.12 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Ta b le 5 - 3 and Ta b le 5 - 4 show the Reset conditions of these registers.

TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition

0 0 1 1 10 x11Power-on Reset

0 0 1 1 10 x0xIllegal, TO

0 0 1 1 10 xx0Illegal, PD is set on POR

0 0 u 1 1u 011Brown-out Reset

u u 0 u uu u0uWDT Reset

u u u u uu u00WDT Wake-up from Sleep

u u u u uu u10Interrupt Wake-up from Sleep

u u u 0 uu uuuMCLR

u u u 0 uu u10MCLR

u u u u 0 u u u u RESET Instruction Executed

1 u u u uu uuuStack Overflow Reset (STVREN = 1)

u 1 u u uu uuuStack Underflow Reset (STVREN = 1)

is set on POR

Reset during normal operation

Reset during Sleep

TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-1 110x

MCLR

Reset during normal operation 0000h ---u uuuu uu-u 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-u 0uuu

WDT Reset 0000h ---0 uuuu uu-0 uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu

Brown-out Reset 0000h ---1 1uuu 00-1 11u0

Interrupt Wake-up from Sleep PC + 1

RESET Instruction Executed 0000h ---u uuuu uu-u u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

Program Counter

(1)

STATUS

---1 0uuu uu-u uuuu

PCON

DS41579C-page 54 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

5.13 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI

•MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

)

The PCON register bits are shown in Register 5-2.

5.14 Register Definitions: Power Control

REGISTER 5-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF —

bit 7 bit 0

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

WDT RMCLR RI POR BOR

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware

bit 5 Unimplemented: Read as ‘0’ bit 4 R

bit 3 RMCLR

bit 2 RI: RESET Instruction Flag bit

bit 1 POR

bit 0 BOR

WDT: Watchdog Timer Reset Flag bit

1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware)

: MCLR Reset Flag bit

1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR

1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware)

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

Reset has occurred (cleared by hardware)

: Power-on Reset Status bit

: Brown-out Reset Status bit

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 55

PIC16(L)F1782/3

TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BORCON SBOREN BORFS

PCON STKOVF STKUNF

STATUS

WDTCON Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

— — —TOPD Z DC C 23

— — WDTPS<4:0> SWDTEN 101

— — — — — BORRDY 51

—RWDTRMCLR RI POR BOR 55

DS41579C-page 56 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

6.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

6.1 Overview

The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

The oscillator module can be configured in one of eight clock modes.

1. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode (0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode (4 MHz to 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 32 MHz).

Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered.

The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency.

The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these three clock sources.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 57

PIC16(L)F1782/3

Oscillator

T1OSCEN Enable Oscillator

T1OSO

T1OSI

Timer1 Clock Source Option for other modules

OSC1

OSC2

Sleep

LP, XT, HS, RC, EC

T1OSC

To CPU and

Postscaler

MUX

16 MHz

8 MHz 4 MHz 2 MHz 1 MHz

250 kHz

500 kHz

IRCF<3:0>

31 kHz

500 kHz

Source

Internal

Oscillator

Block

WDT, PWRT, Fail-Safe Clock Monitor

16 MHz

INTOSC

(HFINTOSC)

SCS<1:0>

HFPLL

31 kHz (LFINTOSC)

Two-Speed Start-up and other modules

Oscillator

31 kHz Source

500 kHz

(MFINTOSC)

125 kHz

31.25 kHz

62.5 kHz

Peripherals

Sleep

External

Timer 1

4 x PLL

÷ 2

PSMC 64 MHz

PRIMUX

PSMCMUX

PLLMUX

0000

1111

SCS FOSC<2:0>

PLLEN or

SPLLEN

PRIMUX PSMCMUX PLLMUX

=00

=100

01110

11101

≠100

00110

(1)

0000

≠00 XXX X X 1 XX

Note 1: This selection should not be made when the PSMC is using the 64 MHz clock option.

FOSC

FIGURE 6-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS41579C-page 58 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

OSC1/CLKIN

OSC2/CLKOUT

Clock from Ext. System

PIC

MCU

FOSC/4 or

I/O

(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

6.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.

Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 6.3

“Clock Switching” for additional information.

6.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to:

- Timer1 oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 6.3 “Clock Switching”for more informa- tion.

6.2.1.1 EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 6-2 shows the pin connections for EC mode.

EC mode has 3 power modes to select from through Configuration Words:

• High power, 4-32 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low power, 0-0.5 MHz (FOSC = 101)

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC

MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

FIGURE 6-2: EXTERNAL CLOCK (EC)

MODE OPERATION

6.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 6-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 6-3 and Figure 6-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 59

PIC16(L)F1782/3

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Quartz

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

Ceramic

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

(3)

Resonator

OSC2/CLKOUT

FIGURE 6-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC Devices” (DS00826)

• AN849, “Basic PIC (DS00849)

• AN943, “Practical PIC Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

and PIC®

Oscillator Design”

Oscillator

FIGURE 6-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

6.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module.

In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 6.4

“Two-Speed Clock Start-up Mode”).

DS41579C-page 60 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

32.768 kHz

T1OSI

To Internal Logic

PIC® MCU

Crystal

T1OSO

Quartz

6.2.1.4 4x PLL

The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Section 30.0

“Electrical Specifications”.

The 4x PLL may be enabled for use by one of two methods:

1. Program the PLLEN bit in Configuration Words to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored.

6.2.1.5 TIMER1 Oscillator

The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.

The Timer1 Oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 6.3 “Clock

Switching” for more information.

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

and PIC®

Devices” (DS00826)

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for Low-Power External Oscillators”

(DS01288)

FIGURE 6-5: QUARTZ CRYSTAL

OPERATION (TIMER1 OSCILLATOR)

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 61

PIC16(L)F1782/3

OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  R

EXT  100 k, 3-5V

EXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

I/O

(1)

6.2.1.6 External RC Mode

The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required.

The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

bit in Configuration Words.

Figure 6-6 shows the external RC mode connections.

FIGURE 6-6: EXTERNAL RC MODES

The RC oscillator frequency is a function of the supply voltage, the resistor (R and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due to tolerance of external RC components used.

EXT) and capacitor (CEXT) values

6.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 6.3

“Clock Switching”for more information.

In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL that can produce one of three internal system clock sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3).

2. The MFINTOSC (Medium-Frequency Internal

Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3).

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at 31 kHz.

bit in Configuration Words.

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6.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 6-3).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’.

A fast startup oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC.

The High Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running.

The High Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value.

The High Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.

6.2.2.2 MFINTOSC

The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 6-3).

The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The MFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’

The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running.

6.2.2.3 Internal Oscillator Frequency Adjustment

The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 6-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency.

When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.

6.2.2.4 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a multiplexer (see Figure 6-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See

Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also

the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled:

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.

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6.2.2.5 Internal Oscillator Frequency Selection

The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software:

- 32 MHz (requires 4x PLL)

-16 MHz

-8 MHz

-4 MHz

-2 MHz

-1 MHz

- 500 kHz (Default after Reset)

- 250 kHz

- 125 kHz

- 62.5 kHz

- 31.25 kHz

- 31 kHz (LFINTOSC)

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency.

6.2.2.6 32 MHz Internal Oscillator Frequency Selection

The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source:

• The FOSC bits in Configuration Words must be

set to use the INTOSC source as the device system clock (FOSC<2:0> = 100).

• The SCS bits in the OSCCON register must be

cleared to use the clock determined by FOSC<2:0> in Configuration Words (SCS<1:0> = 00).

• The IRCF bits in the OSCCON register must be

set to the 8 MHz or 16 MHz HFINTOSC set to use (IRCF<3:0> = 111x).

• The SPLLEN bit in the OSCCON register must be

set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a ‘1’.

Note: When using the PLLEN bit of the

Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN option will not be available.

The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4x PLL with the internal oscillator.

The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.

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6.2.2.7 Internal Oscillator Clock Switch Timing

When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 6-7 for more details.

If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 6-1.

Start-up delay specifications are located in the oscillator tables of Section 30.0 “Electrical

Specifications”.

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HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

0 0

Start-up Time

2-cycle Sync Running

HFINTOSC/ LFINTOSC (FSCM and WDT disabled)

HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC/

IRCF <3:0>

System Clock

= 0  0

Start-up Time 2-cycle Sync

Running

LFINTOSC HFINTOSC/MFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

MFINTOSC

FIGURE 6-7: INTERNAL OSCILLATOR SWITCH TIMING

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6.3 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits:

• Default system oscillator determined by FOSC

bits in Configuration Words

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

6.3.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the Timer1 oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source.

6.3.3 TIMER1 OSCILLATOR

The Timer1 oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.

The Timer1 oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 22.0

“Timer1 Module with Gate Control” for more

information about the Timer1 peripheral.

6.3.4 TIMER1 OSCILLATOR READY

(T1OSCR) BIT

The user must ensure that the Timer1 oscillator is ready to be used before it is selected as a system clock source. The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator.

When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 6-1.

6.3.2 OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 oscillator.

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6.4 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.

If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.

6.4.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO (of the Configuration Words) = 1; Inter-

nal/External Switchover bit (Two-Speed Start-up mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

TABLE 6-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay

(1)

31 kHz

31.25 kHz-500 kHz

Oscillator Warm-up Delay (T

31.25kHz-16MHz DC – 32 MHz 2 cycles DC – 32 MHz 1 cycle of each

32 kHz-20 MHz 1024 Clock Cycles (OST)

31.25 kHz-500 kHz

31.25kHz-16MHz

2 s (approx.)

31 kHz 1 cycle of each

WARM)

LFINTOSC

Sleep/POR

MFINTOSC

HFINTOSC Sleep/POR EC, RC LFINTOSC EC, RC

Sleep/POR

Any clock source

Timer1 Oscillator

LP, XT, HS

MFINTOSC

HFINTOSC Any clock source LFINTOSC Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32 MHz 2 ms (approx.) Note 1: PLL inactive.

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0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N

6.4.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 6-8: TWO-SPEED START-UP

6.4.3 CHECKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator.

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External

LFINTOSC

÷ 64

31 kHz

(~32 s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

6.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC).

FIGURE 6-9: FSCM BLOCK DIAGRAM

6.5.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 6-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.

6.5.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flage will again become set by hardware.

6.5.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed.

6.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation.

The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.

DS41579C-page 70 Preliminary  2011-2012 Microchip Technology Inc.

FIGURE 6-10: FSCM TIMING DIAGRAM

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te st

Test Test

Clock Monitor Output

PIC16(L)F1782/3

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6.6 Register Definitions: Oscillator Control

REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF<3:0>

bit 7 bit 0

Legend:

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz HF or 32 MHz HF 1110 = 8 MHz or 32 MHz HF 1101 =4MHz HF 1100 =2MHz HF 1011 =1MHz HF 1010 = 500 kHz HF 1001 = 250 kHz HF 1000 = 125 kHz HF 0111 = 500 kHz MF (default upon Reset) 0110 = 250 kHz MF 0101 = 125 kHz MF 0100 = 62.5 kHz MF 0011 = 31.25 kHz HF 0010 = 31.25 kHz MF 000x =31kHz LF

bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words.

(1)

(2)

—

SCS<1:0>

Note 1: Duplicate frequency derived from HFINTOSC.

2: 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency

Selection”.

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REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q

T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS

bit 7 bit 0

Legend:

bit 7 T1OSCR: Timer1 Oscillator Ready bit

If T1OSCEN =

1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready

If T1OSCEN = 0 1 = Timer1 clock source is always ready

bit 6 PLLR 4x PLL Ready bit

1 = 4x PLL is ready 0 = 4x PLL is not ready

bit 5 OSTS: Oscillator Start-up Time-out Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready 0 = HFINTOSC is not ready

bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit

1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate

bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit

1 = MFINTOSC is ready 0 = MFINTOSC is not ready

bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready 0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate

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REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — TUN<5:0>

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits

100000 = Minimum frequency

•

111111 = 000000 = Oscillator module is running at the factory-calibrated frequency. 000001 =

•

011110 = 011111 = Maximum frequency

TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON SPLLEN IRCF<3:0>

OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 73

OSCTUNE

PIR2 OSFIF

PIE2 OSFIE

T1CON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

— —TUN<5:0>74

C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 89

C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 86

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON

—SCS<1:0>72

TABLE 6-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16F1782/3 only.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN<1:0> CPD

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

193

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7.0 REFERENCE CLOCK MODULE

The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR). This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. The reference clock module includes the following features:

• System clock is the source

• Available in all oscillator configurations

• Programmable clock divider

• Output enable to a port pin

• Selectable duty cycle

• Slew rate control

The reference clock module is controlled by the CLKRCON register (Register 7-1) and is enabled when setting the CLKREN bit. To output the divided clock signal to the CLKR port pin, the CLKROE bit must be set. The CLKRDIV<2:0> bits enable the selection of 8 different clock divider options. The CLKRDC<1:0> bits can be used to modify the duty cycle of the output

(1)

. The CLKRSLR bit controls slew rate limiting.

clock

Note 1: If the base clock rate is selected without

a divider, the output clock will always have a duty cycle equal to that of the source clock, unless a 0% duty cycle is selected. If the clock divider is set to base clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock.

7.3 Conflicts with the CLKR Pin

There are two cases when the reference clock output signal cannot be output to the CLKR pin, if:

• LP, XT or HS Oscillator mode is selected.

• CLKOUT function is enabled.

7.3.1 OSCILLATOR MODES

If LP, XT or HS oscillator modes are selected, the OSC2/CLKR pin must be used as an oscillator input pin and the CLKR output cannot be enabled. See

Section 6.2 “Clock Source Types”for more informa-

tion on different oscillator modes.

7.3.2 CLKOUT FUNCTION

The CLKOUT function has a higher priority than the reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configuration Words, F Reference Section 4.0 “Device Configuration” for more information.

OSC/4 will always be output on the port pin.

7.4 Operation During Sleep

As the reference clock module relies on the system clock as its source, and the system clock is disabled in Sleep, the module does not function in Sleep, even if an external clock source or the Timer1 clock source is configured as the system clock. The module outputs will remain in their current state until the device exits Sleep.

7.1 Slew Rate

The slew rate limitation on the output port pin can be disabled. The slew rate limitation is removed by clearing the CLKRSLR bit in the CLKRCON register.

7.2 Effects of a Reset

Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.

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7.5 Register Definition: Reference Clock Control

REGISTER 7-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0>

bit 7 bit 0

Legend:

bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference clock module is enabled 0 = Reference clock module is disabled

bit 6 CLKROE: Reference Clock Output Enable bit

1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin

bit 5 CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit

1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled

bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits

11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0%

bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits

111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2 000 = Base clock value

(2)

(1)

Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.

2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%

is selected.

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TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0>

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

CLKRDIV<2:0>

TABLE 7-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN<1:0> CPD

CP MCLRE PWRTE WDTE1<:0> FOSC<2:0>

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NOTES:

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8.0 INTERRUPTS

TMR0IF

TMR0IE

INTF

INTE

IOCIF

IOCIE

Interrupt to CPU

Wake-up (If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7>

PIEn<7>

PEIE

Peripheral Interrupts

(TMR1IF) PIR1<0>

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.

This chapter contains the following information for Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 8-1.

FIGURE 8-1: INTERRUPT LOGIC

PIC16(L)F1782/3

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8.1 Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt event(s)

• PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers)

The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the stack

• Critical registers are automatically saved to the shadow registers (See “Section 8.5 “Automatic

Context Saving”.”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

8.2 Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. See Figure 8-2 and Figure 8.3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKR

PC 0004h 0005h

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC)

Interrupt Sampled during Q1

Inst(PC)

PC-1 PC+1

NOP

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(00 05h)

Execute

PIC16(L)F1782/3

FIGURE 8-2: INTERRUPT LATENCY

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Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

Instruction Fetched

Instruction Executed

Interrupt Latency

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Forced NOP

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Forced NOP

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 T

CY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 30.0 “Electrical Specifications””.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

FIGURE 8-3: INT PIN INTERRUPT TIMING

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8.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 9.0

“Power-Down Mode (Sleep)” for more details.

8.4 INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.

PIC16(L)F1782/3

8.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.

and PD)

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8.6 Register Definitions: Interrupt Control

REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

bit 7 bit 0

Legend:

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt 0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed 0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state

(1)

Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register

Note: Interrupt flag bits are set when an interrupt

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have been cleared by software.

condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PIC16(L)F1782/3

REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

OSFIE C2IE C1IE EEIE BCLIE

bit 7 bit 0

Legend:

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt

bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit

1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt

bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt

bit 2 Unimplemented: Read as ‘0’ bit 1 C3IE: Comparator C3 Interrupt Enable bit

1 = Enables the Comparator C3 Interrupt 0 = Disables the Comparator C3 Interrupt

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt

— C3IE CCP2IE

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 8-4: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0

— — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5 PSMC2TIE: PSMC2 Time Base Interrupt Enable bit

1 = Enables PSMC2 time base generated interrupts 0 = Disables PSMC2 time base generated interrupts

bit 4 PSMC1TIE: PSMC1 Time Base Interrupt Enable bit

1 = Enables PSMC1 time base generated interrupts 0 = Disables PSMC1 time base generated interrupts

bit 3-2 Unimplemented: Read as ‘0’ bit 1 PSMC2SIE: PSMC2 Auto-Shutdown Interrupt Enable bit

1 = Enables PSMC2 auto-shutdown interrupts 0 = Disables PSMC2 auto-shutdown interrupts

bit 0 PSMC1SIE: PSMC1 Auto-Shutdown Interrupt Enable bit

1 = Enables PSMC1 auto-shutdown interrupts 0 = Disables PSMC1 auto-shutdown interrupts

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 8-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2 CCP1IF: CCP1 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending

Note: Interrupt flag bits are set when an interrupt

0 = Interrupt is not pending

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REGISTER 8-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

OSFIF C2IF C1IF EEIF BCLIF

bit 7 bit 0

Legend:

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 C2IF: Comparator C2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2 Unimplemented: Read as ‘0’ bit 1 C3IF: Comparator C3 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 CCP2IF: CCP2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

— C3IF CCP2IF

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REGISTER 8-7: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER42

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0

— — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5 PSMC2TIF: PSMC2 Time Base Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 PSMC1TIF: PSMC1 Time Base Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3-2 Unimplemented: Read as ‘0’ bit 1 PSMC2SIF: PSMC2 Auto-shutdown Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 PSMC1SIF: PSMC1 Auto-shutdown Flag bit

1 = Interrupt is pending

Note: Interrupt flag bits are set when an interrupt

0 = Interrupt is not pending

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TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84

OPTION_REG

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IFE TMR1IE

PIE2 OSFIE C2IE C1IE EEIE BCL1IE

PIE4

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF

PIR2 OSFIF C2IF C1IF EEIF BCL1IF

PIR4

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 183

— C3IE CCP2IE

— — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC2SIE 87

— C3IF CCP2IF

— — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF 90

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NOTES:

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9.0 POWER-DOWN MODE (SLEEP)

The Power-down mode is entered by executing a SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running, if enabled for operation during Sleep.

2. PD

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals

6. ADC is unaffected, if the dedicated FRC clock is

7. I/O ports maintain the status they had before

8. Resets other than WDT are not affected by

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 19.0 “Digital-to-Analog Con-

verter (DAC) Module” and Section 15.0 “Fixed Voltage Reference (FVR)” for more information on these

modules.

bit of the STATUS register is cleared.

that operate from it may continue operation in Sleep.

selected.

SLEEP was executed (driving high, low or high-impedance).

Sleep mode.

9.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

1. External Reset input on MCLR

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)

The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 5.12

“Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.

pin, if enabled

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(1)

CLKOUT

(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction Fetched

Instruction Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced

NOP

PC + 2 0004h 0005h

Forced

NOP

T1OSC

(3)

PC + 2

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference. 3: T1OSC; See Section 25.0 “Electrical Specifications”. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

9.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a SLEEP instruction

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

bit of the STATUS register will not be set

-TO

-PD

bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the execu- tion of a SLEEP instruction

- SLEEP instruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared.

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD was executed as a NOP.

FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

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9.2 Low-Power Sleep Mode

The PIC16(L)F1783 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16(L)F1783 allows the user to optimize the operating current in Sleep, depending on the application requirements.

A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep.

9.2.1 SLEEP CURRENT VS. WAKE-UP TIME

In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize.

The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.

9.2.2 PERIPHERAL USAGE IN SLEEP

Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the normal power mode when those peripherals are enabled. The Low-Power Sleep mode is intended for use with these peripherals:

• Brown-Out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-on-change pins

• Timer1 (with external clock source)

Note: The PIC16LF1782 does not have a con-

figurable Low-Power Sleep mode. PIC16LF1782 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum

DD and I/O voltage than the

V PIC16(L)F1783. See Section 29.0 “Elec- trical Specifications” for more information.

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 95

PIC16(L)F1782/3

9.3 Register Definitions: Voltage Regulator Control

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1

— — — — — —VREGPMReserved

bit 7 bit 0

Legend:

bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit

1 = Low-Power Sleep mode enabled in Sleep

Draws lowest current in Sleep, slower wake-up

0 = Normal Power mode enabled in Sleep

Draws higher current in Sleep, faster wake-up

bit 0 Reserved: Read as ‘1’. Maintain this bit set.

(2)

(1)

Note 1: PIC16F1782/3 only.

2: See Section 30.0 “Electrical Specifications”.

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF RAIF 84

IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 142

IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 141

IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 141

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IFE TMR1IE 85

PIE2 OSFIE C2IE C1IE EEIE BCL1IE

PIE4

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88

PIR2 OSFIF C2IF C1IF EEIF BCL1IF

PIR4

STATUS

VREGCON

WDTCON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.

— — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC2SIE 87

— — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF 90

— — —TOPD ZDCC 23

— — — — — —VREGPMReserved 96

— — WDTPS<4:0> SWDTEN 101

— C3IE CCP2IE 86

— C3IF CCP2IF 89

Page

DS41579C-page 96 Preliminary  2011-2012 Microchip Technology Inc.

PIC16(L)F1782/3

10.0 LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The PIC16F1782/3 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the V at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The PIC16LF1782/3 operates at a maximum V and does not incorporate an LDO.

A device I/O pin may be configured as the LDO voltage output, identified as the V required, an external low-ESR capacitor may be connected to the VCAP pin for additional regulator stability.

The VCAPEN

bit of Configuration Words determines if which pin is assigned as the V

Table 10-1.

TABLE 10-1: VCAPEN

VCAPEN Pin

0 RA6 1 No V

DD and I/O pins to operate

DD of 3.6V

CAP pin. Although not

CAP pin. Refer to

SELECT BIT

CAP

On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information on the constant current rate, refer to the LDO Regulator Characteristics Table in Section 30.0

“Electrical Specifications”.

TABLE 10-2: SUMMARY OF CONFIGURATION WORD WITH LDO

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG2

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO. Note 1: Not implemented on PIC16LF1782/3.

13:8

7:0

— — LVP DEBUG LPBOR BORV STVREN PLLEN

— — VCAPEN

(1)

— — — WRT<1:0>

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 97

PIC16(L)F1782/3

NOTES:

DS41579C-page 98 Preliminary  2011-2012 Microchip Technology Inc.

11.0 WATCHDOG TIMER (WDT)

LFINTOSC

23-bit Programmable

Prescaler WDT

WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 11-1: WATCHDOG TIMER BLOCK DIAGRAM

PIC16(L)F1782/3

 2011-2012 Microchip Technology Inc. Preliminary DS41579C-page 99

PIC16(L)F1782/3

11.1 Independent Clock Source

The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1ms. See

Section 30.0 “Electrical Specifications” for the

LFINTOSC tolerances.

11.2 WDT Operating Modes

The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Ta bl e 11 - 1 .

11.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on.

WDT protection is active during Sleep.

11.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

11.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register.

WDT protection is unchanged by Sleep. See

Table 11-1 for more details.

TABLE 11-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN

11 X XActive

10 X

Device

Mode

Awake Active

Sleep Disabled

WDT

Mode

11.3 Time-Out Period

The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds.

11.4 Clearing the WDT

The WDT is cleared when any of the following conditions occur:

•Any Reset

• CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail

• WDT is disabled

• Oscillator Start-up TImer (OST) is running

See Table 11-2 for more information.

11.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting.

When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 6.0 “Oscillator

Module (with Fail-Safe Clock Monitor)” for more

information on the OST.

When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO in the STATUS register are changed to indicate the event. See Section 3.0 “Memory Organization” and Status Register (Register 3-1) for more information.

and PD bits

00 X X Disabled

0 Disabled

Active

TABLE 11-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected

DS41579C-page 100 Preliminary  2011-2012 Microchip Technology Inc.

Cleared

Datasheet PIC16F1782, PIC16LF1782, PIC16F1783, PIC16LF1783 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance RISC CPU:

Memory Features:

High Performance PWM Controller:

Extreme Low-Power Management PIC16LF1782/3 with XLP:

Analog Peripheral Features:

I/O Features:

Digital Peripheral Features:

Oscillator Features:

General Microcontroller Features:

PIC16(L)F178X Family Types

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC16(L)F1782/3 BLOCK DIAGRAM

TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION

2.0 ENHANCED MID-RANGE CPU

2.1 Automatic Interrupt Context Saving

2.2 16-level Stack with Overflow and Underflow

2.3 File Select Registers

2.4 Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

3.0 MEMORY ORGANIZATION

TABLE 3-1: DEVICE SIZES AND ADDRESSES

3.1 Program Memory Organization

3.1.1 READING PROGRAM MEMORY AS DATA

EXAMPLE 3-1: RETLW INSTRUCTION

3.2 Data Memory Organization

3.2.1 CORE REGISTERS

TABLE 3-2: CORE REGISTERS

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

3.3.1 SPECIAL FUNCTION REGISTER

3.3.2 GENERAL PURPOSE RAM

3.3.3 COMMON RAM

3.3.4 DEVICE MEMORY MAPS

TABLE 3-3: PIC16(L)F1782/3 MEMORY MAP (BANKS 0-7)

TABLE 3-4: PIC16(L)F1782/3 MEMORY MAP (BANKS 8-31)

3.3.5 CORE FUNCTION REGISTERS SUMMARY

TABLE 3-7: CORE FUNCTION REGISTERS SUMMARY

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

3.4 PCL and PCLATH

3.4.3 COMPUTED FUNCTION CALLS

3.4.4 BRANCHING

3.4.1 MODIFYING PCL

3.4.2 COMPUTED GOTO

3.5 Stack

3.5.1 ACCESSING THE STACK

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

3.5.2 OVERFLOW/UNDERFLOW RESET

3.6 Indirect Addressing

FIGURE 3-9: INDIRECT ADDRESSING

3.6.1 TRADITIONAL DATA MEMORY

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

3.6.2 LINEAR DATA MEMORY

3.6.3 PROGRAM FLASH MEMORY

4.0 DEVICE CONFIGURATION

4.1 Configuration Words

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

4.3 Code Protection

4.3.1 PROGRAM MEMORY PROTECTION

4.3.2 DATA EEPROM PROTECTION

4.4 Write Protection

4.5 User ID

4.6 Device ID and Revision ID

4.7 Register Definitions: Device ID

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

5.0 RESETS