Datasheet PIC16LF1713, PIC16F1713, PIC16F1716, PIC16LF1716 Datasheet

PIC16(L)F1713/6

Cost Effective 8-Bit Intelligent Analog Flash Microcontrollers

Description:

PIC16(L)F1713/6 microcontrollers combine Intelligent Analog integration with low cost and extreme low power (XLP) to suit a variety of general purpose applications. These 28-pin devices deliver on-chip op amps, Core Independent Peripherals (CLC, NCO and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased design flexibility.

Core Features:

• C Compiler Optimized RISC Architecture

• Only 49 Instructions

• Operating Speed:

- 0-32 MHz clock input

- 125 ns minimum instruction cycle

• Interrupt Capability

• 16-Level Deep Hardware Stack

• Up to Four 8-bit Timers

• One 16-bit Timer

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Low-Power Brown-Out Reset (LPBOR)

• Programmable Watchdog Timer (WDT) up to 256s

• Programmable Code Protection

Memory:

• Up to 8 Kwords Flash Program Memory

• Up to 1024 Bytes Data SRAM Memory

• Direct, Indirect and Relative Addressing modes

Operating Characteristics:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1713/6)

- 2.3V to 5.5V (PIC16F1713/6)

• Temperature Range:

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features:

• Sleep mode: 50 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Secondary Oscillator: 500 nA @ 32 kHz

• Operating Current:

- 8 uA @ 32 kHz, 1.8V, typical

- 32 uA/MHz @ 1.8V, typical

Digital Peripherals:

• Configurable Logic Cell (CLC):

- Integrated combinational and sequential logic

• Complementary Output Generator (COG):

- Rising/falling edge dead-band control/ blanking

• Numerically Controlled Oscillator (NCO):

- Generates true linear frequency control and increased frequency resolution

- Input Clock: 0Hz < F

- Resolution: F

• Capture/Compare/PWM (CCP) module

• PWM: Two 10-bit Pulse-Width Modulators

• Serial Communications:

- SPI, I

- Auto-Baud Detect, auto-wake-up on start

• Up to 35 I/O Pins and One Input Pin:

- Individually programmable pull-ups

- Slew rate control

- Interrupt-on-change with edge-select

• Peripheral Pin Select (PPS):

- Enables pin mapping of digital I/O

C™, RS-232, RS-485, LIN compatible

NCO < 32 MHz

NCO/220

Intelligent Analog Peripherals:

• Operational Amplifiers:

- Two configurable rail-to-rail op amps

- Selectable internal and external channels

- 2 MHz gain bandwidth product

• High-Speed Comparators:

- Up to two comparators

- 50 ns response time

- Rail-to-rail inputs

• 10-Bit Analog-to-Digital Converter (ADC):

- Up to 28 external channels

- Conversion available during Sleep

- Temperature indicator

• Zero-Cross Detector (ZCD):

- Detect when AC signal on pin crosses ground

• 8-Bit Digital-to-Analog Converter (DAC):

- Output available externally

- Internal connections to comparators, op amps, Fixed Voltage Reference (FVR) and ADC

• Internal Voltage Reference module

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 1

PIC16(L)F1713/6

Clocking Structure:

• 16 MHz Internal Oscillator Block:

- ±1% at calibration

- Selectable frequency range from 0 to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- Three crystal/resonator modes up to 20 MHz

Programming/Debug Features:

• In-Circuit Debug Integrated On-Chip

• Emulation Header for Advanced Debug:

- Provides trace, background debug and up to 32 hardware break points

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

- Two external clock modes up to 20 MHz

• Fail-Safe Clock Monitor

• Two-Speed Oscillator Start-up

• Oscillator Start-up Timer (OST)

PIC16(L)F1713/6 Family Types

(1)

PPS

XLP

Debug

Device

Flash (words)

Data Sheet Index

Program Memory

PIC16(L)F1713(1)409651225171/1 2 214/12211141YI/EY PIC16(L)F1716 (1) 8192 1024 17 25 1/1 2 2 1 4/1 2211141YI/EY PIC16(L)F1717 (2) 8192 1024 36 28 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y PIC16(L)F1718 (2) 16384 2048 25 17 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y PIC16(L)F1719 (2) 16384 2048 36 28 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y

Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS40001726 PIC16(L)F1713/6 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers. 2: Future Release PIC16(L)F1717/8/9 Data Sheet, 28/40-Pin Flash, 8-bit Microcontrollers.

(bytes)

Data SRAM

(2)

I/Os

CCP

5/8-bit DAC

10-bit ADC (ch)

Op Amp

High-Speed/

Comparators

Timers

(8/16-bit)

Zero Cross

PWM

COG

C™/SPI)

CLC

EUSART

MSSP (I

NCO

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

DS40001726B-page 2 Preliminary  2013-2014 Microchip Technology Inc.

Pin Diagrams

PIC16(L)F1713/6

8 9

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RB6

RB5

RB4

RB3

RB2

RB1 RB0

VSS

24 23

RA7

RA6

RC0

RC1

RC2

RC3

RC5

RC4

RC7

RC6

RB7

Note: See Ta bl e 1 for the pin allocation table.

2 3

RC0

RB7

RB6

RB5

RB4

RB0 V

VSS RC7

RC6

RC5

RC4

RE3/MCLR

/VPP

RA0

RA1

RA2 RA3 RA4 RA5

RA7 RA6

RC1

RC2

RC3

13814

232822

PIC16(L)F1713/6

RB3 RB2 RB1

Note: See Ta bl e 1 for the pin allocation table.

FIGURE 1: 28-PIN PDIP, SOIC, SSOP

PIC16(L)F1713/6

FIGURE 2: 28-PIN (U)QFN

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DS40001726B-page 4 Preliminary  2013-2014 Microchip Technology Inc.

I/O

(2)

PDIP, SOIC,

SSOP

QFN, UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pull-up

Basic

RA0 2 27 AN0

CLCIN0

(1)

IOC Y

RA1 3 28 AN1 OPA1OUT

CLCIN1

(1)

IOC Y

RA2 4 1 AN2 Vref- DAC1OUT1 IOC Y

RA3 5 2 AN3 Vref+ IOC Y

RA4 6 3 OPA1IN+

IOC Y

RA5 7 4 AN4 OPA1IN- DAC2OUT1

RA6 10 7 IOC Y

OSC2

CLKOUT

RA7 9 6 IOC Y

OSC1

CLKIN

RB0 21 18 AN12 ZCD

INT

(1)

IOC

RB1 22 19 AN10 OPA2OUT IOC Y

RB2 23 20 AN8 OPA2IN- IOC Y

RB3 24 21 AN9 OPA2IN+ IOC Y

RB4 25 22 AN11 IOC Y

RB5 26 23 AN13

IOC Y

RB6 27 24

(1)

IOC Y ICSPCLK

RB7 28 25

DAC1OUT2 DAC2OUT2

CLCIN3

(1)

IOC Y ICSPDAT

SOSCO

RC1 12 9 SOSCI IOC Y

RC2 13 10 AN14 IOC Y

RC3 14 11 AN15

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

5: Alternate inputs are excluded from dot shaded areas.

IOC Y

CCP2

(1)

C2IN1+

COG1IN

(1)

C1IN3C2IN3-

C1IN2C2IN2-

RC0 11 8

EUSART

CLC

C1IN0C2IN0-

C1IN1C2IN1-

C1IN0+ C2IN0+

COG

MSSP

C1IN1+

Comparator

Timers

CCP

PWM

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1713/6)

PIC16(L)F1713/6

T0CKI

(1)

nSS

(1)

T1G

T1CKI

CLCIN2

(1)

CCP1

(1)

SCL/ SCK

(1)

IOC Y

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 5

I/O

(2)

PDIP, SOIC,

SSOP

QFN, UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pull-up

Basic

RC5 16 13 AN17 IOC Y

RC6 17 14 AN18 IOC Y

RC7 18 15 AN19 IOC Y

RE3 1 26 IOC Y

MCLR

Vpp

Vdd 20 17 Vdd

85 Vss

19 16

OUT

(4)

C1OUT

C2OUT

CCP1

CCP2

NCO1OUT

PWM3OUT

PWM4OUT

COG1A

COG1B

COG1C

COG1D

SDA

(3)

SCK/SCL

(3)

SDO

TX/CK

DT(3)

CLC4OUT

CLC3OUT

CLC2OUT

CLC1OUT

(5)

T1G

T1CKI

T0CKI

CCP1

CCP2

SDI

SCK/SCL

(3)

RX(3)

CLCIN0

CLCIN1

CLCIN2

CLCIN3

INT

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

IOC

Vss

RC4 15 12 AN16

COG1IN

Comparator

Timers

CCP

PWM

COG

MSSP

EUSART

CLC

SDI

SDA

(1)

(3)

5: Alternate inputs are excluded from dot shaded areas.

PIC16(L)F1713/6

1.0 Device Overview ......................................................................................................................................................................... 8

2.0 Enhanced Mid-Range CPU ....................................................................................................................................................... 13

3.0 Memory Organization ................................................................................................................................................................ 15

4.0 Device Configuration................................................................................................................................................................. 42

5.0 Resets ....................................................................................................................................................................................... 48

6.0 Oscillator Module (with Fail-Safe Clock Monitor) ...................................................................................................................... 56

7.0 Interrupts ................................................................................................................................................................................... 74

8.0 Power-Down Mode (Sleep) ....................................................................................................................................................... 87

9.0 Watchdog Timer (WDT) ............................................................................................................................................................ 91

10.0 Flash Program Memory Control ................................................................................................................................................ 96

11.0 I/O Ports .................................................................................................................................................................................. 112

12.0 Peripheral Pin Select (PPS) Module ....................................................................................................................................... 130

13.0 Interrupt-On-Change ............................................................................................................................................................... 136

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................. 145

15.0 Temperature Indicator Module ................................................................................................................................................ 148

16.0 Comparator Module................................................................................................................................................................. 150

17.0 Pulse Width Modulation (PWM) .............................................................................................................................................. 159

18.0 Complementary Output Generator (COG) Module.................................................................................................................. 165

19.0 Configurable Logic Cell (CLC)................................................................................................................................................. 197

20.0 Numerically Controlled Oscillator (NCO) Module .................................................................................................................... 214

21.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 221

22.0 Operational Amplifier (OPA) Modules ..................................................................................................................................... 235

23.0 8-Bit Digital-to-Analog Converter (DAC1) Module................................................................................................................... 238

24.0 5-Bit Digital-to-Analog Converter (DAC2) Module................................................................................................................... 242

25.0 Timer0 Module ........................................................................................................................................................................ 246

26.0 Timer1 Module with Gate Control............................................................................................................................................ 249

27.0 Timer2/4/6 Module .................................................................................................................................................................. 260

28.0 Zero-Cross Detection (ZCD) Module....................................................................................................................................... 265

29.0 Capture/Compare/PWM Modules ........................................................................................................................................... 269

30.0 Master Synchronous Serial Port (MSSP) Module ................................................................................................................... 277

31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................................................. 329

32.0 In-Circuit Serial Programming™ (ICSP™) .............................................................................................................................. 360

33.0 Instruction Set Summary......................................................................................................................................................... 362

34.0 Electrical Specifications........................................................................................................................................................... 376

35.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 409

36.0 Development Support.............................................................................................................................................................. 423

37.0 Packaging Information............................................................................................................................................................. 427

The Microchip Web Site.................................................................................................................................................................... 441

Customer Change Notification Service ............................................................................................................................................. 442

Customer Support ............................................................................................................................................................................. 441

Product Identification System............................................................................................................................................................ 442

Worldwide Sales and Service ........................................................................................................................................................... 444

DS40001726B-page 6 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TO OUR VALUED CUSTOMERS

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 7

PIC16(L)F1713/6

1.0 DEVICE OVERVIEW

The PIC16(L)F1713/6 are described within this data sheet. They are available in 28-pin SPDIP, SSOP, SOIC, QFN, and UQFN packages. Figure 1-1 shows a block diagram of the PIC16(L)F1713/6 devices.

Table 1-2 shows the pinout descriptions.

Reference Table 1-1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1713

PIC16(L)F1716

Analog-to-Digital Converter (ADC) ●● Complementary Output Generator (COG) ●● Fixed Voltage Reference (FVR) ●● Zero-Cross Detection (ZCD) ●● Temperature Indicator ●● Numerically Controlled Oscillator (NCO) ●● Digital-to-Analog Converter (DAC)

DAC1 ●● DAC2 ●●

Capture/Compare/PWM (CCP/ECCP) Modules

CCP1 ●● CCP2 ●●

Comparators

C1 ●● C2 ●●

Configurable Logic Cell (CLC)

CLC1 ●● CLC2 ●● CLC3 ●● CLC4 ●●

Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)

EUSART ●●

Master Synchronous Serial Ports

MSSP ●●

Op Amp

Op Amp 1 ●● Op Amp 2 ●●

Pulse Width Modulator (PWM)

PWM3 ●● PWM4 ●●

Timers

Timer0 ●● Timer1 ●● Timer2 ●●

DS40001726B-page 8 Preliminary  2013-2014 Microchip Technology Inc.

FIGURE 1-1: PIC16(L)F1713/6 BLOCK DIAGRAM

PORTA

PORTB

PORTC

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

LFINTOSC

Oscillator

MCLR

Figure 2-1

CLKIN

CLKOUT

ADC

10-Bit

FVR

Te mp .

Indicator

EUSART

Comparators

MSSPTimer2Timer1Timer0

DACs

CCPs

PWMOp Amps

HFINTOSC/

CLCs

COG

ZCD

NCO

PIC16(L)F1713/6

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 9

PIC16(L)F1713/6

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/C1IN0-/C2IN0-/

(1)

CLCIN0

RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — ADC Channel 0 input.

C1IN0- AN — Comparator C2 negative input.

C2IN0- AN — Comparator C3 negative input.

CLCIN0 TTL/ST — Configurable Logic Cell source input.

RA1/AN1/C1IN1-/C2IN1-/ OPA1OUT/CLCIN1

(1)

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — ADC Channel 1 input.

C1IN1- AN — Comparator C1 negative input.

C2IN1- AN — Comparator C2 negative input.

OPA1OUT — AN Operational Amplifier 1 output.

CLCIN1 TTL/ST — Configurable Logic Cell source input.

RA2/AN2/V DAC1OUT1

REF-/C1IN0+/C2IN0+/

RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — ADC Channel 2 input.

REF- AN — ADC Negative Voltage Reference input.

C1IN0+ AN — Comparator C2 positive input.

C2IN0+ AN — Comparator C3 positive input.

DAC1OUT1 — AN Digital-to-Analog Converter output.

RA3/AN3/V

REF+/C1IN1+ RA3 TTL/ST CMOS General purpose I/O.

AN3 AN — ADC Channel 3 input.

REF+ AN — ADC Voltage Reference input.

C1IN1+ AN — Comparator C1 positive input.

RA4/OPA1IN+/T0CKI

(1)

RA4 TTL/ST CMOS General purpose I/O.

OPA1IN+ AN — Operational Amplifier 1 non-inverting input.

T0CKI TTL/ST — Timer0 gate input.

RA5/AN4/OPA1IN-/DAC2OUT1/

(1)

RA5 TTL/ST CMOS General purpose I/O.

AN4 AN — ADC Channel 4 input.

OPA1IN- AN — Operational Amplifier 1 inverting input.

DAC2OUT1 — AN Digital-to-Analog Converter output.

TTL/ST — Slave Select enable input.

RA6/OSC2/CLKOUT RA6 TTL/ST CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

RA7/OSC1/CLKIN RA7 TTL/ST CMOS General purpose I/O.

OSC1

CLKIN TTL/ST

RB0/AN12/C2IN1+/ZCD/

(1)

COGIN

RB0 TTL/ST CMOS General purpose I/O.

AN12 AN — ADC Channel 12 input.

C2IN1+ AN — Comparator C2 positive input.

ZCD AN — Zero-Cross Detection Current Source/Sink.

COGIN TTL/ST — Complementary Output Generator input.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

Output

Typ e

OSC/4 output.

— XTAL Crystal/Resonator (LP, XT, HS modes).

— External clock input (EC mode).

Description

C™ = Schmitt Trigger input with I2C

DS40001726B-page 10 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB1/AN10/C1IN3-/C2IN3-/ OPA2OUT

RB2/AN8/OPA2IN- RB2 TTL/ST CMOS General purpose I/O.

RB3/AN9/C1IN2-/C2IN2-/ OPA2IN+

RB4/AN11 RB4 TTL/ST CMOS General purpose I/O.

RB5/AN13/T1G

RB6/CLCIN2

RB7/DAC1OUT2/DAC2OUT2/ CLCIN3

RC0/T1CKI

RC1/SOSCI/CCP2

RC2/AN14/CCP1

RC3/AN15/SCL/SCK

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

(1)

/ICSPCLK RB6 TTL/ST CMOS General purpose I/O.

(1)

/ICSPDAT

(1)

/SOSCO RC0 TTL/ST CMOS General purpose I/O.

(1)

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

RB1 TTL/ST CMOS General purpose I/O.

AN10 AN — ADC Channel 10 input.

C1IN3- AN — Comparator C1 negative input.

C2IN3- AN — Comparator C2 negative input.

OPA2OUT

AN8 AN — ADC Channel 8 input.

OPA2IN- AN — Operational Amplifier 2 inverting input.

RB3 TTL/ST CMOS General purpose I/O.

AN9 AN — ADC Channel 9 input.

C1IN2- AN — Comparator C1 negative input.

C2IN2- AN — Comparator C2 negative input.

OPA2IN+ AN — Operational Amplifier 2 non-inverting input.

AN11 AN — ADC Channel 11 input.

RB5 TTL/ST CMOS General purpose I/O.

AN13 AN — ADC Channel 13 input.

T1G TTL/ST — Timer1 gate input.

CLCIN2 TTL/ST — Configurable Logic Cell source input.

ICSPCLK ST — Serial Programming Clock.

RB7 TTL/ST CMOS General purpose I/O.

DAC1OUT2 — AN Digital-to-Analog Converter output.

DAC2OUT2 — AN Digital-to-Analog Converter output.

CLCIN3 TTL/ST — Configurable Logic Cell source input.

ICSPDAT ST CMOS ICSP™ Data I/O.

T1CKI TTL/ST — Timer1 clock input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

RC1 TTL/ST CMOS General purpose I/O.

SOSCI XTAL XTAL Secondary Oscillator Connection.

CCP2 TTL/ST — Capture input

RC2 TTL/ST CMOS General purpose I/O.

AN14 AN — ADC Channel 14 input.

CCP1 TTL/ST — Capture input

RC3 TTL/ST CMOS General purpose I/O.

AN15 AN — ADC Channel 15 input.

SCL/SCK I

Output

Typ e

—AN

C™ — I2C/SPI clock input.

Operational Amplifier 2 output.

Description

C™ = Schmitt Trigger input with I2C

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 11

PIC16(L)F1713/6

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

(1)

RC4/AN16/SDI

/SDA

(1)

RC4 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

SDI TTL/ST — SPI Data input

SDA I

RC5/AN17 RC5 TTL/ST CMOS General purpose I/O.

AN17 AN — ADC Channel 17 input.

RC6/AN18/CK

(1)

RC6 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

CK TTL/ST EUSART synchronous clock

RC7/AN19/RX

(1)

RC7 TTL/ST CMOS General purpose I/O.

AN18 AN — ADC Channel 18 input.

RX TTL/ST — EUSART receive

RE3/MCLR

DD VDD Power — Positive supply

SS Power — Ground reference

OUT

/VPP RE3 TTL/ST — General purpose input.

CLR ST — Master clear input

PP HV — Programming enable

(2)

C1OUT CMOS Comparator 1 output

C2OUT CMOS Comparator 2 output

CCP1 CMOS Compare/PWM1 output

CCP2 CMOS Compare/PWM2 output

NCO1OUT CMOS Numerically controlled oscillator output

PWM3OUT CMOS PWM3 output

PWM4OUT CMOS PWM4 output

COGA CMOS Complementary output generator output A

COGB CMOS Complementary output generator output B

COGC CMOS Complementary output generator output C

COGD CMOS Complementary output generator output D

(3)

SDA

SCK CMOS SPI clock output

(3)

SCL

SDO CMOS SPI data output

TX/CK CMOS EUSART asynchronous TX data/synchronous clock out

(3)

CLC1OUT CMOS Configurable logic cell 1 output

CLC2OUT CMOS Configurable logic cell 2 output

CLC3OUT CMOS Configurable logic cell 3 output

CLC4OUT CMOS Configurable logic cell 4 output

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

Output

Typ e

C™ — I2C Data input

OD I2C™ Data output

OD I2C™ clock output

CMOS EUSART synchronous data output

Description

C™ = Schmitt Trigger input with I2C

DS40001726B-page 12 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Brown-out

Reset

VSS

Internal

Oscillator

Block

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction Decode &

Control

Timing

Generation

VSS

Internal

Oscillator

Block

Data Bus

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

ConfigurationConfigurationConfiguration

Flash

Program

Memory

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and

FIGURE 2-1: CORE BLOCK DIAGRAM

Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

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PIC16(L)F1713/6

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving” for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See Section 3.5 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See

Section 33.0 “Instruction Set Summary” for more

details.

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PIC16(L)F1713/6

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

Note 1: The method to access Flash memory

through the PMCON registers is described in Section 10.0 “Flash Program Memory

Control”.

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1713/6 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1713 8,192 1FFFh PIC16(L)F1716 16,384 3FFFh

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PIC16(L)F1713/6

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh 1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh 1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

Page 2

Page 3

17FFh 1800h

1FFFh

2000h

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1713

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1716

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PIC16(L)F1713/6

constants

BRW ;Add Index in W to

;program counter to

;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.

The high directive will set bit<7> if a label points to a location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank.

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PIC16(L)F1713/6

Addresses BANKx

x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR

x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.2.1 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta bl e 3 - 2. For detailed information, see Ta bl e 3 -8 .

TABLE 3-2: CORE REGISTERS

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3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 33.0

“Instruction Set Summary”).

Note: The C and DC bits operate as Borrow and

Digit Borrow subtraction.

out bits, respectively, in

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —TOPD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

(1)

bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand.

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

(1)

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PIC16(L)F1713/6

0Bh 0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.3.1 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

3.3.3 COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

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3.3.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown in Tables 3-3 through 3-7.

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 21

TABLE 3-3: PIC16(L)F1713/6 MEMORY MAP (BANKS 0-7)

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 - 2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC 00Fh 010h PORTE 090h TRISE 110h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h 013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h

017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 018h T1CON 098h OSCTUNE 118h DAC1CON0 198h 019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h 01Ah TMR2 09Ah OSCSTAT 11Ah DAC2CON0 19Ah TX1REG 21Ah 01Bh PR2 09Bh ADRESL 11Bh DAC2CON1 19Bh SP1BRGL 21Bh 01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch 01Dh 01Eh 01Fh 020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Unimplemented on PIC16(L)F1713/6.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—094h— 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP

— 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh IOCEP — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh —39EhIOCEN — 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh —29Fh—31Fh—39FhIOCEF

General Purpose Register

80 Bytes

Common RAM

70h – 7Fh

080h

0A0h

0F0h

Core Registers

(Ta bl e 3 - 2)

General Purpose Register

80 Bytes

Accesses 70h – 7Fh

100h

120h

170h

Core Registers

(Table 3-2)

—190h— 210h WPUE 290h — 310h — 390h INLVLE

General Purpose Register 80 Bytes

Accesses

70h – 7Fh

180h

1A0h

1F0h

Core Registers

(Table 3-2)

—218h— 298h CCPR2L 318h — 398h IOCCN

General Purpose Register 80 Bytes

Accesses

70h – 7Fh

200h

Core Registers

(Table 3-2)

(1)

217h SSP1CON3 297h — 317h — 397h IOCCP

— 299h CCPR2H 319h — 399h IOCCF — 29Ah CCP2CON 31Ah —39Ah— —29Bh—31Bh—39Bh— — 29Ch — 31Ch — 39Ch —

220h

General Purpose Register

80 Bytes

270h

Accesses

70h – 7Fh

280h

2A0h

2F0h

Core Registers

(Table 3-2)

— 315h — 395h IOCBN — 316h — 396h IOCBF

General Purpose Register

80 Bytes

Accesses

70h – 7Fh

300h

Core Registers

(Table 3-2)

— 391h IOCAP — 392h IOCAN — 393h IOCAF

320h

General Purpose

32Fh 330h

36Fh 3EFh 370h

16 Bytes

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

380h

3A0h

3F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

PIC16(L)F1713/6

DS40001726B-page 22 Preliminary  2013-2014 Microchip Technology Inc.

TABLE 3-4: PIC16(L)F1713/6 MEMORY MAP, BANK 8-23

PIC16(L)F1713/6

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

Core Registers

(Ta bl e 3 - 2)

40Bh 40Ch 40Dh 40Eh 40Fh 410h

411h 412h 413h 414h 415h TMR4 495h 416h PR4 496h 417h T4CON 497h 418h 419h 41Ah 41Bh 41Ch TMR6 49Ch NCO1INCH 51Ch 41Dh PR6 49Dh NCO1INCU 51Dh 41Eh T6CON 49Eh NCO1CON 51Eh 41Fh

420h

— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh— —48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh— —490h—510h—590h—610h—690h— 710h — 790h — —491h— 511h OPA1CON 591h —611h—691h —492h—512h—592h—612h—692h —493h—513h—593h—613h—693h —494h—514h—594h—614h—694h

— 498h NCO1ACCL 518h —598h— 618h PWM3DCH 698h — 499h NCO1ACCH 519h —599h— 619h PWM3CON 699h — 49Ah NCO1ACCU 51Ah —59Ah— 61Ah PWM4DCL 69Ah — 49Bh NCO1INCL 51Bh —59Bh— 61Bh PWM4DCH 69Bh

— 49Fh NCO1CLK 51Fh —59Fh—61Fh—69Fh

480h

48Bh

4A0h

Core Registers

(Ta bl e 3 - 2)

— 515h OPA2CON 595h —615h—695h —516h—596h—616h—696h —517h—597h— 617h PWM3DCL 697h

500h

50Bh

520h

Core Registers

(Table 3-2)

— 59Ch — 61Ch PWM4CON 69Ch — 59Dh — 61Dh — 69Dh —59Eh—61Eh—69Eh

580h

58Bh

5A0h

Core Registers

(Table 3-2)

600h

60Bh

620h

Core Registers

(Table 3-2)

680h

68Bh

6A0h

Core Registers

(Table 3-2)

COG1PHR

COG1PHF COG1BLKR COG1BLKF

COG1DBR

COG1DBF COG1CON0 COG1CON1

COG1RIS

COG1RSIM

COG1FIS

COG1FSIM COG1ASD0 COG1ASD1

COG1STR

700h

Core Registers

(Table 3-2)

70Bh

711h — 791h — 712h — 792h — 713h — 793h — 714h — 794h — 715h — 795h — 716h — 796h — 717h — 797h — 718h — 798h — 719h — 799h — 71Ah —79Ah— 71Bh —79Bh— 71Ch — 79Ch — 71Dh — 79Dh — 71Eh —79Eh— 71Fh —79Fh—

720h

780h

78Bh

7A0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h

Accesses 70h – 7Fh

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

4F0h

Unimplemented

Read as ‘0’

Accesses 70h – 7Fh

570h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

5F0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

670h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

6F0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

770h

Unimplemented

Read as ‘0’

7F0h

Accesses

70h – 7Fh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

Core Registers

(Ta bl e 3 - 2) 80Bh 80Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh 870h

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Accesses 70h – 7Fh

880h

88Bh 88Ch

8F0h

Core Registers

(Ta bl e 3 - 2)

Unimplemented

Read as ‘0’

Accesses 70h – 7Fh

900h

90Bh 90Ch

970h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

980h

98Bh 98Ch

9EFh 9F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

A00h

A0Bh A0Ch

A6Fh

A70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

A80h

A8Bh A8Ch

AEFh AF0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

B00h

B0Bh B0Ch

B6Fh B70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

B80h

B8Bh B8Ch

BEFh BF0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3 - 2)

C80h

C8Bh

Core Registers

(Ta bl e 3 - 2)

D00h

D0Bh

Core Registers

(Ta bl e 3 - 2)

D80h

D8Bh

Core Registers

(Ta bl e 3 - 2)

E00h

E0Bh

Core Registers

(Ta bl e 3 - 2)

E80h

E8Bh

Core Registers

(Ta bl e 3 - 2)

F00h

F0Bh

Core Registers

(Ta bl e 3 - 2)

F80h

F8Bh

Core Registers

(Ta bl e 3 - 2)

C0Ch

—C8Ch—D0Ch—D8Ch—E0Ch

See Tab l e 3 -7 for

details

E8Ch

See Tab l e 3 -7 for register mapping

details

F0Ch

See Tab l e 3 -7 for register mapping

details

F8Ch

See Tab l e 3 -7 for register mapping

details

C0Dh

—C8Dh—D0Dh—D8Dh— E0Dh E8Dh F0Dh F8Dh

C0Eh

—C8Eh—D0Eh—D8Eh— E0Eh E8Eh F0Eh F8Eh

C0Fh

—C8Fh—D0Fh—D8Fh— E0Fh E8Fh F0Fh F8Fh

C10h

—C90h—D10h—D90h— E10h E90h F10h F90h

C11h

—C91h—D11h—D91h— E11h E91h F11h F91h

C12h

—C92h—D12h—D92h— E12h E92h F12h F92h

C13h

—C93h—D13h—D93h— E13h E93h F13h F93h

C14h

—C94h—D14h—D94h— E14h E94h F14h F94h

C15h

—C95h—D15h—D95h— E15h E95h F15h F95h

C16h

—C96h—D16h—D96h— E16h E96h F16h F96h

C17h

—C97h—D17h—D97h— E17h E97h F17h F97h

C18h

—C98h—D18h—D98h— E18h E98h F18h F98h

C19h

—C99h—D19h—D99h— E19h E99h F19h F99h

C1Ah

—C9Ah—D1Ah—D9Ah— E1Ah E9Ah F1Ah F9Ah

C1Bh

—C9Bh—D1Bh—D9Bh— E1Bh E9Bh F1Bh F9Bh

C1Ch

—C9Ch—D1Ch—D9Ch— E1Ch E9Ch F1Ch F9Ch

C1Dh

—C9Dh—D1Dh—D9Dh— E1Dh E9Dh F1Dh F9Dh

C1Eh

—C9Eh—D1Eh—D9Eh— E1Eh E9Eh F1Eh F9Eh

C1Fh

—C9Fh—D1Fh—D9Fh— E1Fh E9Fh F1Fh F9Fh

C20h

Unimplemented

Read as ‘0’

CA0h

Unimplemented

Read as ‘0’

D20h

Unimplemented

Read as ‘0’

DA0h

Unimplemented

Read as ‘0’

E20h EA0h F20h FA0h

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh C70h

Accesses 70h – 7Fh

CF0h

Accesses 70h – 7Fh

D70h

Accesses

70h – 7Fh

DF0h

Accesses

70h – 7Fh

E70h

Accesses

70h – 7Fh

EF0h

Accesses

70h – 7Fh

F70h

Accesses

70h – 7Fh

FF0h

Accesses

70h – 7Fh

CFFh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 23

TABLE 3-5: PIC16(L)F1713/6 MEMORY MAP, BANK 24-31

PIC16(L)F1713/6

Legend: = Unimplemented data memory locations, read as ‘0’,

Note 1: Only available on PIC16(L)F1713 devices

Bank 28 Bank 29 Bank 30

E0Ch —E8Ch—F0Ch — E0Dh

—E8Dh—F0Dh —

E0Eh

—E8Eh—F0Eh —

E0Fh PPSLOCK E8Fh

— F0Fh CLCDATA E10h INTPPS E90h RA0PPS F10h CLC1CON E11h T0CKIPPS E91h RA1PPS F11h CLC1POL E12h T1CKIPPS E92h RA2PPS F12h CLC1SEL0 E13h T1GPPS E93h RA3PPS F13h CLC1SEL1 E14h CCP1PPS E94h RA4PPS F14h CLC1SEL2 E15h CCP2PPS E95h RA5PPS F15h CLC1SEL3 E16h

— E96h RA6PPS F16h CLC1GLS0 E17h COGINPPS E97h RA7PPS F17h CLC1GLS1 E18h

— E98h RB0PPS F18h CLC1GLS2 E19h

— E99h RB1PPS F19h CLC1GLS3

E1Ah

—

E9Ah

RB2PPS

F1Ah

CLC2CON

E1Bh

— E9Bh RB3PPS F1Bh CLC2POL

E1Ch

—E9ChRB4PPS

(1)

F1Ch CLC2SEL0

E1Dh

—E9DhRB5PPS

(1)

F1Dh CLC2SEL1

E1Eh

—E9EhRB6PPS

(1)

F1Eh CLC2SEL2

E1Fh

—E9FhRB7PPS

(1)

F1Fh CLC2SEL3 E20h SSPCLKPPS EA0h RC0PPS F20h CLC2GLS0 E21h SSPDATPPS EA1h RC1PPS F21h CLC2GLS1 E22h SSPSSPPS EA2h RC2PPS F22h CLC2GLS2 E23h

— EA3h RC3PPS F23h CLC2GLS3 E24h RXPPS EA4h RC4PPS F24h CLC3CON E25h CKPPS EA5h RC5PPS F25h CLC3POL

E26h

— EA6h RC6PPS

(1)

F26h CLC3SEL0

E27h

— EA7h RC7PPS

(1)

F27h CLC3SEL1

E28h CLCIN0PPS EA8h

— F28h CLC3SEL2

E29h CLCIN1PPS EA9h

— F29h CLC3SEL3

E2Ah

CLCIN2PPS

EAAh

—

F2Ah

CLC3GLS0

E2Bh CLCIN3PPS EABh

— F2Bh CLC3GLS1

E2Ch

—EACh— F2Ch CLC3GLS2

E2Dh

—EADh— F2Dh CLC3GLS3

E2Eh

— EAEh — F2Eh CLC4CON

E2Fh

—EAFh— F2Fh CLC4POL E30h

— EB0h — F30h CLC4SEL0 E31h

— EB1h — F31h CLC4SEL1 E32h

—

EB2h

— F32h CLC4SEL2

E33h

— EB3h — F33h CLC4SEL3 E34h

— EB4h — F34h CLC4GLS0 E35h

— EB5h — F35h CLC4GLS1 E36h

— EB6h — F36h CLC4GLS2 E37h

— EB7h — F37h CLC4GLS3 E38h

— EB8h —F38h — E39h

— EB9h —F39h —

E3Ah

—

EBAh

—F3Ah —

E3Bh

— EBBh —F3Bh —

E3Ch

— EBCh —F3Ch —

E3Dh

—EBDh—F3Dh —

E3Eh

— EBEh —F3Eh —

E3Fh

— EBFh —F3Fh — E40h

—

EC0h

—

F40h

—

E6Fh EEFh F6Fh

TABLE 3-6: PIC16(L)F1713/6 MEMORY MAP, BANK 28-30

DS40001726B-page 24 Preliminary  2013-2014 Microchip Technology Inc.

TABLE 3-7: PIC16(L)F1713/6 MEMORY

Legend: = Unimplemented data memory locations,

read as ‘0’,

Bank 31

F8Ch

ICDIO

F8Dh

ICDCON0

F8Eh

—

F8Fh

—

F90h

—

F91h

ICDSTAT

F92h

—

F93h

—

F94h

—

F95h

—

F96h

ICDINSTL

F97h

ICDINSTH

F98h

—

F99h

—

F9Ah

—

F9Bh

—

F9Ch

ICDBK0CON

F9Dh

ICDBK0L

F9Eh

ICDBK0H

F9Fh

—

FE2h FE3h

BSRICDSHAD

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

FF0h

FFFh

—

MAP, BANK 31

PIC16(L)F1713/6

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 25

PIC16(L)F1713/6

3.3.5 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3- 8 can be addressed from any Bank.

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

Value on all

other Resets

DS40001726B-page 26 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx --uu uuuu

00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu ----

00Eh PORTC RC7

00Fh

— Unimplemented — —

010h

PORTE —

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0-00

012h PIR2 OSFIF C2IF C1IF

013h PIR3

014h

— Unimplemented — —

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM

01Ah TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 uuuu uuuu

01Bh PR2 Timer2 Period Register 1111 1111 uuuu uuuu

01Ch T2CON

01Dh

— Unimplemented — —

01Fh

Bank 1

08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 --11 1111

08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISA0 1111 1111 1111 ----

08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

08Fh

— Unimplemented — —

090h TRISE

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE C2IE C1IE

093h PIE3

094h

— Unimplemented — —

095h

OPTION_REG

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

099h OSCCON SPLLEN IRCF<3:0>

09Ah OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 0q0q qqqq --0q

09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu

09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS<2:0>

09Fh ADCON2 TRIGSEL<3:0>

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

(

RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

— — —

— BCL1IF TMR6IF TMR4IF CCP2IF 000- 0000 000- 00--

— NCOIF COGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF -000 0000 --00 -000

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

—

— NCOIE COGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE -000 0000 --00 -000

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111

— — WDTPS<4:0> SWDTEN --01 0110 --01 0110

— — TUN<5:0> --00 0000 --00 0000

—CHS<4:0>

— — —

— BCL1IE TMR6IE TMR4IE CCP2IE 000- 0000 000- 0000

—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu

RE3

T1GGO/

DONE

TRISE3

— ADNREF ADPREF<1:0> 0000 -000 0000 --00

— — — — 0000 ---- 0000 ----

— — —

—TMR1ON0000 00-0 uuuu uu-u

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

— — —

—SCS<1:0>0011 1-00 0011 1-00

GO/DONE

ADON -000 0000 -000 0000

Valu e o n

POR, BOR

---- x--- ---- u---

---- 1--- ---- 1---

Value on all

other

Resets

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 27

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

10Ch LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx --uu -uuu

10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu ----

10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu

10Fh

— Unimplemented — —

110 h

— Unimplemented — —

111h

CM1CON0 C1ON C1OUT — C1POL C1ZLF C1SP C1HYS C1SYNC 00-0 0100 00-0 0100

112 h

CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000

113 h

CM2CON0 C2ON C2OUT — C2POL C2ZLF C2SP C2HYS C2SYNC 00-0 0100 00-0 0100

114 h

CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000

115 h

CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00

116h BORCON SBOREN BORFS

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

118h DAC1CON0 DAC1EN

119h DAC1CON1 DAC1R<7:0> 0000 0000 0000 0000

11Ah DAC2CON0 DAC2EN

11Bh DAC2CON1 —

11Ch ZCD1CON ZCD1EN

11D h

— Unimplemented — —

11E h

— Unimplemented — —

11F h

— Unimplemented — —

Bank 3

18Ch

ANSELA — —ANSA5ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 ---1 1111

18Dh ANSELB

18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2

18Fh

— Unimplemented — —

190h

— Unimplemented — —

191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000

192h PMADRH

193h PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h PMDATH

195h PMCON1

196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000

197h VREGCON

198h

— Unimplemented — —

199h RC1REG USART Receive Data Register 0000 0000 0000 0000

19Ah TX1REG USART Transmit Data Register 0000 0000 0000 0000

19Bh SP1BRGL SP1BRG<7:0> 0000 0000 0000 0000

19Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000

19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000

19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUD1CON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 ----

— Program Memory Address Register High Byte 1000 0000 1000 0000

— — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— CFGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000

— — — — — —VREGPMReserved ---- --01 ---- --01

--- DAC1OE1 DAC1OE2 DAC1PSS<1:0> --- DAC1NSS 0-00 00-0 0-00 00-0

— — —

— ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 0-x0 --00 0-00 --00

— — — — — BORRDY 10-- ---q uu-- ---u

DAC2OE1 DAC2OE2 DAC2PSS<1:0> —DAC2NSS0-00 00-0 0-00 00-0

DAC2R<4:0> ---0 0000 ---0 0000

— — 1111 11-- 1111 1111

—SCKPBRG16—WUEABDEN01-0 0-00 01-0 0-00

Valu e o n

POR, BOR

Value on all

other

Resets

DS40001726B-page 28 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 4

20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 --11 1111

20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 ----

20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111

20Fh

— Unimplemented — —

210h WPUE

211h SSP1BUF

212h SSP1ADD

213h SSP1MSK

214h SSP1STAT SMP CKE D/A

215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

—

— Unimplemented — —

21Fh

Bank 5

28Ch ODCONA ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 0000 0000 --00 -000

28Dh ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 000- 0000 ----

28Eh ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000

28Fh

— Unimplemented — —

290h

— Unimplemented — —

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

293h CCP1CON

294h

—

— Unimplemented — —

297h

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

29Ah CCP2CON

29Bh

—

— Unimplemented — —

29Dh

29Eh CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0000 0000 0000 0000

29Fh

— Unimplemented — —

Bank 6

30Ch SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 1111 1111 --00 -000

30Dh SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 1111 1111 0000 ----

30Eh SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 0000 0000

30Fh —

— Unimplemented — —

31Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — — WPUE3 — — — ---- 1--- ---- 1---

Synchronous Serial Port Receive Buffer/Transmit Register

ADD<7:0>

MSK<7:0>

PSR/WUA BF 0000 0000 0000 0000

— — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000

— — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000

Valu e o n

POR, BOR

XXXX XXXX uuuu uuuu

XXXX XXXX 0000 0000

XXXX XXXX 1111 1111

Value on all

other

Resets

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 29

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 7

38Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 1111 1111 --11 1111

38Dh INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 1111 1111 1111 ----

38Eh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111

38Fh

— Unimplemented — —

390h INLVLE

391h IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0000 0000 --00 0000

392h IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0000 0000 --00 0000

393h IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0000 0000 --00 0000

394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 ----

395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 ----

396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 ----

397h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000

398h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000

399h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000

39Ah —

— Unimplemented — —

39Ch

39Dh IOCEP

39Eh IOCEN

39Fh IOCEF

Bank 8

40Ch —

— Unimplemented — —

414h

415h TMR4 Holding Register for the 8-bit TMR4 Register 0000 0000 uuuu uuuu

416h PR4 Timer4 Period Register 1111 1111 uuuu uuuu

417h T4CON

418h —

— Unimplemented — —

41Bh

41Ch TMR6 Holding Register for the 8-bit TMR6 Register 0000 0000 uuuu uuuu

41Dh PR6 Timer6 Period Register 1111 1111 uuuu uuuu

41Eh T6CON

41Fh

— Unimplemented — —

Bank 9

48Ch

— Unimplemented — —

497h

498h NCO1ACCL NCO1ACC 0000 0000 0000 0000

499h NCO1ACCH NCO1ACC 0000 0000 0000 0000

49Ah NCO1ACCU NCO1ACC ---- 0000 ---- 0000

49Bh NCO1INCL NCO1INC 0000 0001 0000 0001

49Ch NCO1INCH NCO1INC 0000 0000 0000 0000

49Dh NCO1INCU NCO1INC ---- 0000 ---- 0000

49Eh NCO1CON N1EN

49Fh NCO1CLK N1PWS<2:0>

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — —IOCEP3— — — ---- 0--- ---- 0---

— — — —IOCEN3— — — ---- 0--- ---- 0---

— — — — IOCEF3 — — — ---- 0--- ---- 0---

— T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000

— T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000

— N1OUT N1POL — — —N1PFM0-00 ---0 0-00 ---0

— — — N1CKS<1:0> 000- --00 000- --00

INLVLE3 ---- 1--- ---- 1---

Valu e o n

POR, BOR

Value on all

other

Resets

DS40001726B-page 30 Preliminary  2013-2014 Microchip Technology Inc.

+ 420 hidden pages

Datasheet PIC16LF1713, PIC16F1713, PIC16F1716, PIC16LF1716 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Description:

Core Features:

Memory:

Operating Characteristics:

eXtreme Low-Power (XLP) Features:

Digital Peripherals:

Intelligent Analog Peripherals:

Clocking Structure:

Programming/Debug Features:

Pin Diagrams

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1713/6)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC16(L)F1713/6 BLOCK DIAGRAM

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION

2.0 ENHANCED MID-RANGE CPU

FIGURE 2-1: CORE BLOCK DIAGRAM

2.1 Automatic Interrupt Context Saving

2.2 16-Level Stack with Overflow and Underflow

2.3 File Select Registers

2.4 Instruction Set

3.0 MEMORY ORGANIZATION

3.1 Program Memory Organization

TABLE 3-1: DEVICE SIZES AND ADDRESSES

3.1.1 READING PROGRAM MEMORY AS DATA

EXAMPLE 3-1: RETLW INSTRUCTION

3.2 Data Memory Organization

3.2.1 CORE REGISTERS

TABLE 3-2: CORE REGISTERS

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

3.3.1 SPECIAL FUNCTION REGISTER

3.3.2 GENERAL PURPOSE RAM

3.3.3 COMMON RAM

3.3.4 DEVICE MEMORY MAPS

TABLE 3-3: PIC16(L)F1713/6 MEMORY MAP (BANKS 0-7)

TABLE 3-4: PIC16(L)F1713/6 MEMORY MAP, BANK 8-23

TABLE 3-5: PIC16(L)F1713/6 MEMORY MAP, BANK 24-31

TABLE 3-6: PIC16(L)F1713/6 MEMORY MAP, BANK 28-30

3.3.5 CORE FUNCTION REGISTERS SUMMARY

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY