Datasheet PIC16LF1713, PIC16F1713, PIC16F1716, PIC16LF1716 Datasheet

PIC16(L)F1713/6

Cost Effective 8-Bit Intelligent Analog Flash Microcontrollers

Description:

PIC16(L)F1713/6 microcontrollers combine Intelligent Analog integration with low cost and extreme low power (XLP) to suit a variety of general purpose applications. These 28-pin devices deliver on-chip op amps, Core Independent Peripherals (CLC, NCO and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased design flexibility.

Core Features:

• C Compiler Optimized RISC Architecture

• Only 49 Instructions

• Operating Speed:

- 0-32 MHz clock input

- 125 ns minimum instruction cycle

• Interrupt Capability

• 16-Level Deep Hardware Stack

• Up to Four 8-bit Timers

• One 16-bit Timer

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Low-Power Brown-Out Reset (LPBOR)

• Programmable Watchdog Timer (WDT) up to 256s

• Programmable Code Protection

Memory:

• Up to 8 Kwords Flash Program Memory

• Up to 1024 Bytes Data SRAM Memory

• Direct, Indirect and Relative Addressing modes

Operating Characteristics:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1713/6)

- 2.3V to 5.5V (PIC16F1713/6)

• Temperature Range:

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features:

• Sleep mode: 50 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Secondary Oscillator: 500 nA @ 32 kHz

• Operating Current:

- 8 uA @ 32 kHz, 1.8V, typical

- 32 uA/MHz @ 1.8V, typical

Digital Peripherals:

• Configurable Logic Cell (CLC):

- Integrated combinational and sequential logic

• Complementary Output Generator (COG):

- Rising/falling edge dead-band control/ blanking

• Numerically Controlled Oscillator (NCO):

- Generates true linear frequency control and increased frequency resolution

- Input Clock: 0Hz < F

- Resolution: F

• Capture/Compare/PWM (CCP) module

• PWM: Two 10-bit Pulse-Width Modulators

• Serial Communications:

- SPI, I

- Auto-Baud Detect, auto-wake-up on start

• Up to 35 I/O Pins and One Input Pin:

- Individually programmable pull-ups

- Slew rate control

- Interrupt-on-change with edge-select

• Peripheral Pin Select (PPS):

- Enables pin mapping of digital I/O

C™, RS-232, RS-485, LIN compatible

NCO < 32 MHz

NCO/220

Intelligent Analog Peripherals:

• Operational Amplifiers:

- Two configurable rail-to-rail op amps

- Selectable internal and external channels

- 2 MHz gain bandwidth product

• High-Speed Comparators:

- Up to two comparators

- 50 ns response time

- Rail-to-rail inputs

• 10-Bit Analog-to-Digital Converter (ADC):

- Up to 28 external channels

- Conversion available during Sleep

- Temperature indicator

• Zero-Cross Detector (ZCD):

- Detect when AC signal on pin crosses ground

• 8-Bit Digital-to-Analog Converter (DAC):

- Output available externally

- Internal connections to comparators, op amps, Fixed Voltage Reference (FVR) and ADC

• Internal Voltage Reference module

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 1

PIC16(L)F1713/6

Clocking Structure:

• 16 MHz Internal Oscillator Block:

- ±1% at calibration

- Selectable frequency range from 0 to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- Three crystal/resonator modes up to 20 MHz

Programming/Debug Features:

• In-Circuit Debug Integrated On-Chip

• Emulation Header for Advanced Debug:

- Provides trace, background debug and up to 32 hardware break points

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

- Two external clock modes up to 20 MHz

• Fail-Safe Clock Monitor

• Two-Speed Oscillator Start-up

• Oscillator Start-up Timer (OST)

PIC16(L)F1713/6 Family Types

(1)

PPS

XLP

Debug

Device

Flash (words)

Data Sheet Index

Program Memory

PIC16(L)F1713(1)409651225171/1 2 214/12211141YI/EY PIC16(L)F1716 (1) 8192 1024 17 25 1/1 2 2 1 4/1 2211141YI/EY PIC16(L)F1717 (2) 8192 1024 36 28 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y PIC16(L)F1718 (2) 16384 2048 25 17 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y PIC16(L)F1719 (2) 16384 2048 36 28 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y

Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS40001726 PIC16(L)F1713/6 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers. 2: Future Release PIC16(L)F1717/8/9 Data Sheet, 28/40-Pin Flash, 8-bit Microcontrollers.

(bytes)

Data SRAM

(2)

I/Os

CCP

5/8-bit DAC

10-bit ADC (ch)

Op Amp

High-Speed/

Comparators

Timers

(8/16-bit)

Zero Cross

PWM

COG

C™/SPI)

CLC

EUSART

MSSP (I

NCO

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

DS40001726B-page 2 Preliminary  2013-2014 Microchip Technology Inc.

Pin Diagrams

PIC16(L)F1713/6

8 9

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RB6

RB5

RB4

RB3

RB2

RB1 RB0

VSS

24 23

RA7

RA6

RC0

RC1

RC2

RC3

RC5

RC4

RC7

RC6

RB7

Note: See Ta bl e 1 for the pin allocation table.

2 3

RC0

RB7

RB6

RB5

RB4

RB0 V

VSS RC7

RC6

RC5

RC4

RE3/MCLR

/VPP

RA0

RA1

RA2 RA3 RA4 RA5

RA7 RA6

RC1

RC2

RC3

13814

232822

PIC16(L)F1713/6

RB3 RB2 RB1

Note: See Ta bl e 1 for the pin allocation table.

FIGURE 1: 28-PIN PDIP, SOIC, SSOP

PIC16(L)F1713/6

FIGURE 2: 28-PIN (U)QFN

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DS40001726B-page 4 Preliminary  2013-2014 Microchip Technology Inc.

I/O

(2)

PDIP, SOIC,

SSOP

QFN, UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pull-up

Basic

RA0 2 27 AN0

CLCIN0

(1)

IOC Y

RA1 3 28 AN1 OPA1OUT

CLCIN1

(1)

IOC Y

RA2 4 1 AN2 Vref- DAC1OUT1 IOC Y

RA3 5 2 AN3 Vref+ IOC Y

RA4 6 3 OPA1IN+

IOC Y

RA5 7 4 AN4 OPA1IN- DAC2OUT1

RA6 10 7 IOC Y

OSC2

CLKOUT

RA7 9 6 IOC Y

OSC1

CLKIN

RB0 21 18 AN12 ZCD

INT

(1)

IOC

RB1 22 19 AN10 OPA2OUT IOC Y

RB2 23 20 AN8 OPA2IN- IOC Y

RB3 24 21 AN9 OPA2IN+ IOC Y

RB4 25 22 AN11 IOC Y

RB5 26 23 AN13

IOC Y

RB6 27 24

(1)

IOC Y ICSPCLK

RB7 28 25

DAC1OUT2 DAC2OUT2

CLCIN3

(1)

IOC Y ICSPDAT

SOSCO

RC1 12 9 SOSCI IOC Y

RC2 13 10 AN14 IOC Y

RC3 14 11 AN15

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

5: Alternate inputs are excluded from dot shaded areas.

IOC Y

CCP2

(1)

C2IN1+

COG1IN

(1)

C1IN3C2IN3-

C1IN2C2IN2-

RC0 11 8

EUSART

CLC

C1IN0C2IN0-

C1IN1C2IN1-

C1IN0+ C2IN0+

COG

MSSP

C1IN1+

Comparator

Timers

CCP

PWM

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1713/6)

PIC16(L)F1713/6

T0CKI

(1)

nSS

(1)

T1G

T1CKI

CLCIN2

(1)

CCP1

(1)

SCL/ SCK

(1)

IOC Y

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 5

I/O

(2)

PDIP, SOIC,

SSOP

QFN, UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pull-up

Basic

RC5 16 13 AN17 IOC Y

RC6 17 14 AN18 IOC Y

RC7 18 15 AN19 IOC Y

RE3 1 26 IOC Y

MCLR

Vpp

Vdd 20 17 Vdd

85 Vss

19 16

OUT

(4)

C1OUT

C2OUT

CCP1

CCP2

NCO1OUT

PWM3OUT

PWM4OUT

COG1A

COG1B

COG1C

COG1D

SDA

(3)

SCK/SCL

(3)

SDO

TX/CK

DT(3)

CLC4OUT

CLC3OUT

CLC2OUT

CLC1OUT

(5)

T1G

T1CKI

T0CKI

CCP1

CCP2

SDI

SCK/SCL

(3)

RX(3)

CLCIN0

CLCIN1

CLCIN2

CLCIN3

INT

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

IOC

Vss

RC4 15 12 AN16

COG1IN

Comparator

Timers

CCP

PWM

COG

MSSP

EUSART

CLC

SDI

SDA

(1)

(3)

5: Alternate inputs are excluded from dot shaded areas.

PIC16(L)F1713/6

1.0 Device Overview ......................................................................................................................................................................... 8

2.0 Enhanced Mid-Range CPU ....................................................................................................................................................... 13

3.0 Memory Organization ................................................................................................................................................................ 15

4.0 Device Configuration................................................................................................................................................................. 42

5.0 Resets ....................................................................................................................................................................................... 48

6.0 Oscillator Module (with Fail-Safe Clock Monitor) ...................................................................................................................... 56

7.0 Interrupts ................................................................................................................................................................................... 74

8.0 Power-Down Mode (Sleep) ....................................................................................................................................................... 87

9.0 Watchdog Timer (WDT) ............................................................................................................................................................ 91

10.0 Flash Program Memory Control ................................................................................................................................................ 96

11.0 I/O Ports .................................................................................................................................................................................. 112

12.0 Peripheral Pin Select (PPS) Module ....................................................................................................................................... 130

13.0 Interrupt-On-Change ............................................................................................................................................................... 136

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................. 145

15.0 Temperature Indicator Module ................................................................................................................................................ 148

16.0 Comparator Module................................................................................................................................................................. 150

17.0 Pulse Width Modulation (PWM) .............................................................................................................................................. 159

18.0 Complementary Output Generator (COG) Module.................................................................................................................. 165

19.0 Configurable Logic Cell (CLC)................................................................................................................................................. 197

20.0 Numerically Controlled Oscillator (NCO) Module .................................................................................................................... 214

21.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 221

22.0 Operational Amplifier (OPA) Modules ..................................................................................................................................... 235

23.0 8-Bit Digital-to-Analog Converter (DAC1) Module................................................................................................................... 238

24.0 5-Bit Digital-to-Analog Converter (DAC2) Module................................................................................................................... 242

25.0 Timer0 Module ........................................................................................................................................................................ 246

26.0 Timer1 Module with Gate Control............................................................................................................................................ 249

27.0 Timer2/4/6 Module .................................................................................................................................................................. 260

28.0 Zero-Cross Detection (ZCD) Module....................................................................................................................................... 265

29.0 Capture/Compare/PWM Modules ........................................................................................................................................... 269

30.0 Master Synchronous Serial Port (MSSP) Module ................................................................................................................... 277

31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................................................. 329

32.0 In-Circuit Serial Programming™ (ICSP™) .............................................................................................................................. 360

33.0 Instruction Set Summary......................................................................................................................................................... 362

34.0 Electrical Specifications........................................................................................................................................................... 376

35.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 409

36.0 Development Support.............................................................................................................................................................. 423

37.0 Packaging Information............................................................................................................................................................. 427

The Microchip Web Site.................................................................................................................................................................... 441

Customer Change Notification Service ............................................................................................................................................. 442

Customer Support ............................................................................................................................................................................. 441

Product Identification System............................................................................................................................................................ 442

Worldwide Sales and Service ........................................................................................................................................................... 444

DS40001726B-page 6 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TO OUR VALUED CUSTOMERS

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 7

PIC16(L)F1713/6

1.0 DEVICE OVERVIEW

The PIC16(L)F1713/6 are described within this data sheet. They are available in 28-pin SPDIP, SSOP, SOIC, QFN, and UQFN packages. Figure 1-1 shows a block diagram of the PIC16(L)F1713/6 devices.

Table 1-2 shows the pinout descriptions.

Reference Table 1-1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1713

PIC16(L)F1716

Analog-to-Digital Converter (ADC) ●● Complementary Output Generator (COG) ●● Fixed Voltage Reference (FVR) ●● Zero-Cross Detection (ZCD) ●● Temperature Indicator ●● Numerically Controlled Oscillator (NCO) ●● Digital-to-Analog Converter (DAC)

DAC1 ●● DAC2 ●●

Capture/Compare/PWM (CCP/ECCP) Modules

CCP1 ●● CCP2 ●●

Comparators

C1 ●● C2 ●●

Configurable Logic Cell (CLC)

CLC1 ●● CLC2 ●● CLC3 ●● CLC4 ●●

Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)

EUSART ●●

Master Synchronous Serial Ports

MSSP ●●

Op Amp

Op Amp 1 ●● Op Amp 2 ●●

Pulse Width Modulator (PWM)

PWM3 ●● PWM4 ●●

Timers

Timer0 ●● Timer1 ●● Timer2 ●●

DS40001726B-page 8 Preliminary  2013-2014 Microchip Technology Inc.

FIGURE 1-1: PIC16(L)F1713/6 BLOCK DIAGRAM

PORTA

PORTB

PORTC

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

LFINTOSC

Oscillator

MCLR

Figure 2-1

CLKIN

CLKOUT

ADC

10-Bit

FVR

Te mp .

Indicator

EUSART

Comparators

MSSPTimer2Timer1Timer0

DACs

CCPs

PWMOp Amps

HFINTOSC/

CLCs

COG

ZCD

NCO

PIC16(L)F1713/6

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 9

PIC16(L)F1713/6

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/C1IN0-/C2IN0-/

(1)

CLCIN0

RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — ADC Channel 0 input.

C1IN0- AN — Comparator C2 negative input.

C2IN0- AN — Comparator C3 negative input.

CLCIN0 TTL/ST — Configurable Logic Cell source input.

RA1/AN1/C1IN1-/C2IN1-/ OPA1OUT/CLCIN1

(1)

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — ADC Channel 1 input.

C1IN1- AN — Comparator C1 negative input.

C2IN1- AN — Comparator C2 negative input.

OPA1OUT — AN Operational Amplifier 1 output.

CLCIN1 TTL/ST — Configurable Logic Cell source input.

RA2/AN2/V DAC1OUT1

REF-/C1IN0+/C2IN0+/

RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — ADC Channel 2 input.

REF- AN — ADC Negative Voltage Reference input.

C1IN0+ AN — Comparator C2 positive input.

C2IN0+ AN — Comparator C3 positive input.

DAC1OUT1 — AN Digital-to-Analog Converter output.

RA3/AN3/V

REF+/C1IN1+ RA3 TTL/ST CMOS General purpose I/O.

AN3 AN — ADC Channel 3 input.

REF+ AN — ADC Voltage Reference input.

C1IN1+ AN — Comparator C1 positive input.

RA4/OPA1IN+/T0CKI

(1)

RA4 TTL/ST CMOS General purpose I/O.

OPA1IN+ AN — Operational Amplifier 1 non-inverting input.

T0CKI TTL/ST — Timer0 gate input.

RA5/AN4/OPA1IN-/DAC2OUT1/

(1)

RA5 TTL/ST CMOS General purpose I/O.

AN4 AN — ADC Channel 4 input.

OPA1IN- AN — Operational Amplifier 1 inverting input.

DAC2OUT1 — AN Digital-to-Analog Converter output.

TTL/ST — Slave Select enable input.

RA6/OSC2/CLKOUT RA6 TTL/ST CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

RA7/OSC1/CLKIN RA7 TTL/ST CMOS General purpose I/O.

OSC1

CLKIN TTL/ST

RB0/AN12/C2IN1+/ZCD/

(1)

COGIN

RB0 TTL/ST CMOS General purpose I/O.

AN12 AN — ADC Channel 12 input.

C2IN1+ AN — Comparator C2 positive input.

ZCD AN — Zero-Cross Detection Current Source/Sink.

COGIN TTL/ST — Complementary Output Generator input.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

Output

Typ e

OSC/4 output.

— XTAL Crystal/Resonator (LP, XT, HS modes).

— External clock input (EC mode).

Description

C™ = Schmitt Trigger input with I2C

DS40001726B-page 10 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB1/AN10/C1IN3-/C2IN3-/ OPA2OUT

RB2/AN8/OPA2IN- RB2 TTL/ST CMOS General purpose I/O.

RB3/AN9/C1IN2-/C2IN2-/ OPA2IN+

RB4/AN11 RB4 TTL/ST CMOS General purpose I/O.

RB5/AN13/T1G

RB6/CLCIN2

RB7/DAC1OUT2/DAC2OUT2/ CLCIN3

RC0/T1CKI

RC1/SOSCI/CCP2

RC2/AN14/CCP1

RC3/AN15/SCL/SCK

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

(1)

/ICSPCLK RB6 TTL/ST CMOS General purpose I/O.

(1)

/ICSPDAT

(1)

/SOSCO RC0 TTL/ST CMOS General purpose I/O.

(1)

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

RB1 TTL/ST CMOS General purpose I/O.

AN10 AN — ADC Channel 10 input.

C1IN3- AN — Comparator C1 negative input.

C2IN3- AN — Comparator C2 negative input.

OPA2OUT

AN8 AN — ADC Channel 8 input.

OPA2IN- AN — Operational Amplifier 2 inverting input.

RB3 TTL/ST CMOS General purpose I/O.

AN9 AN — ADC Channel 9 input.

C1IN2- AN — Comparator C1 negative input.

C2IN2- AN — Comparator C2 negative input.

OPA2IN+ AN — Operational Amplifier 2 non-inverting input.

AN11 AN — ADC Channel 11 input.

RB5 TTL/ST CMOS General purpose I/O.

AN13 AN — ADC Channel 13 input.

T1G TTL/ST — Timer1 gate input.

CLCIN2 TTL/ST — Configurable Logic Cell source input.

ICSPCLK ST — Serial Programming Clock.

RB7 TTL/ST CMOS General purpose I/O.

DAC1OUT2 — AN Digital-to-Analog Converter output.

DAC2OUT2 — AN Digital-to-Analog Converter output.

CLCIN3 TTL/ST — Configurable Logic Cell source input.

ICSPDAT ST CMOS ICSP™ Data I/O.

T1CKI TTL/ST — Timer1 clock input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

RC1 TTL/ST CMOS General purpose I/O.

SOSCI XTAL XTAL Secondary Oscillator Connection.

CCP2 TTL/ST — Capture input

RC2 TTL/ST CMOS General purpose I/O.

AN14 AN — ADC Channel 14 input.

CCP1 TTL/ST — Capture input

RC3 TTL/ST CMOS General purpose I/O.

AN15 AN — ADC Channel 15 input.

SCL/SCK I

Output

Typ e

—AN

C™ — I2C/SPI clock input.

Operational Amplifier 2 output.

Description

C™ = Schmitt Trigger input with I2C

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 11

PIC16(L)F1713/6

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

(1)

RC4/AN16/SDI

/SDA

(1)

RC4 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

SDI TTL/ST — SPI Data input

SDA I

RC5/AN17 RC5 TTL/ST CMOS General purpose I/O.

AN17 AN — ADC Channel 17 input.

RC6/AN18/CK

(1)

RC6 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

CK TTL/ST EUSART synchronous clock

RC7/AN19/RX

(1)

RC7 TTL/ST CMOS General purpose I/O.

AN18 AN — ADC Channel 18 input.

RX TTL/ST — EUSART receive

RE3/MCLR

DD VDD Power — Positive supply

SS Power — Ground reference

OUT

/VPP RE3 TTL/ST — General purpose input.

CLR ST — Master clear input

PP HV — Programming enable

(2)

C1OUT CMOS Comparator 1 output

C2OUT CMOS Comparator 2 output

CCP1 CMOS Compare/PWM1 output

CCP2 CMOS Compare/PWM2 output

NCO1OUT CMOS Numerically controlled oscillator output

PWM3OUT CMOS PWM3 output

PWM4OUT CMOS PWM4 output

COGA CMOS Complementary output generator output A

COGB CMOS Complementary output generator output B

COGC CMOS Complementary output generator output C

COGD CMOS Complementary output generator output D

(3)

SDA

SCK CMOS SPI clock output

(3)

SCL

SDO CMOS SPI data output

TX/CK CMOS EUSART asynchronous TX data/synchronous clock out

(3)

CLC1OUT CMOS Configurable logic cell 1 output

CLC2OUT CMOS Configurable logic cell 2 output

CLC3OUT CMOS Configurable logic cell 3 output

CLC4OUT CMOS Configurable logic cell 4 output

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

Output

Typ e

C™ — I2C Data input

OD I2C™ Data output

OD I2C™ clock output

CMOS EUSART synchronous data output

Description

C™ = Schmitt Trigger input with I2C

DS40001726B-page 12 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Brown-out

Reset

VSS

Internal

Oscillator

Block

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction Decode &

Control

Timing

Generation

VSS

Internal

Oscillator

Block

Data Bus

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

ConfigurationConfigurationConfiguration

Flash

Program

Memory

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and

FIGURE 2-1: CORE BLOCK DIAGRAM

Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

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PIC16(L)F1713/6

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving” for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See Section 3.5 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See

Section 33.0 “Instruction Set Summary” for more

details.

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PIC16(L)F1713/6

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

Note 1: The method to access Flash memory

through the PMCON registers is described in Section 10.0 “Flash Program Memory

Control”.

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1713/6 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1713 8,192 1FFFh PIC16(L)F1716 16,384 3FFFh

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PIC16(L)F1713/6

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh 1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh 1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

Page 2

Page 3

17FFh 1800h

1FFFh

2000h

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1713

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1716

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PIC16(L)F1713/6

constants

BRW ;Add Index in W to

;program counter to

;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.

The high directive will set bit<7> if a label points to a location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank.

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PIC16(L)F1713/6

Addresses BANKx

x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR

x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.2.1 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta bl e 3 - 2. For detailed information, see Ta bl e 3 -8 .

TABLE 3-2: CORE REGISTERS

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3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 33.0

“Instruction Set Summary”).

Note: The C and DC bits operate as Borrow and

Digit Borrow subtraction.

out bits, respectively, in

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —TOPD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

(1)

bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand.

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

(1)

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PIC16(L)F1713/6

0Bh 0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.3.1 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

3.3.3 COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

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3.3.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown in Tables 3-3 through 3-7.

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 21

TABLE 3-3: PIC16(L)F1713/6 MEMORY MAP (BANKS 0-7)

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 - 2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC 00Fh 010h PORTE 090h TRISE 110h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h 013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h

017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 018h T1CON 098h OSCTUNE 118h DAC1CON0 198h 019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h 01Ah TMR2 09Ah OSCSTAT 11Ah DAC2CON0 19Ah TX1REG 21Ah 01Bh PR2 09Bh ADRESL 11Bh DAC2CON1 19Bh SP1BRGL 21Bh 01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch 01Dh 01Eh 01Fh 020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Unimplemented on PIC16(L)F1713/6.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—094h— 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP

— 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh IOCEP — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh —39EhIOCEN — 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh —29Fh—31Fh—39FhIOCEF

General Purpose Register

80 Bytes

Common RAM

70h – 7Fh

080h

0A0h

0F0h

Core Registers

(Ta bl e 3 - 2)

General Purpose Register

80 Bytes

Accesses 70h – 7Fh

100h

120h

170h

Core Registers

(Table 3-2)

—190h— 210h WPUE 290h — 310h — 390h INLVLE

General Purpose Register 80 Bytes

Accesses

70h – 7Fh

180h

1A0h

1F0h

Core Registers

(Table 3-2)

—218h— 298h CCPR2L 318h — 398h IOCCN

General Purpose Register 80 Bytes

Accesses

70h – 7Fh

200h

Core Registers

(Table 3-2)

(1)

217h SSP1CON3 297h — 317h — 397h IOCCP

— 299h CCPR2H 319h — 399h IOCCF — 29Ah CCP2CON 31Ah —39Ah— —29Bh—31Bh—39Bh— — 29Ch — 31Ch — 39Ch —

220h

General Purpose Register

80 Bytes

270h

Accesses

70h – 7Fh

280h

2A0h

2F0h

Core Registers

(Table 3-2)

— 315h — 395h IOCBN — 316h — 396h IOCBF

General Purpose Register

80 Bytes

Accesses

70h – 7Fh

300h

Core Registers

(Table 3-2)

— 391h IOCAP — 392h IOCAN — 393h IOCAF

320h

General Purpose

32Fh 330h

36Fh 3EFh 370h

16 Bytes

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

380h

3A0h

3F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

PIC16(L)F1713/6

DS40001726B-page 22 Preliminary  2013-2014 Microchip Technology Inc.

TABLE 3-4: PIC16(L)F1713/6 MEMORY MAP, BANK 8-23

PIC16(L)F1713/6

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

Core Registers

(Ta bl e 3 - 2)

40Bh 40Ch 40Dh 40Eh 40Fh 410h

411h 412h 413h 414h 415h TMR4 495h 416h PR4 496h 417h T4CON 497h 418h 419h 41Ah 41Bh 41Ch TMR6 49Ch NCO1INCH 51Ch 41Dh PR6 49Dh NCO1INCU 51Dh 41Eh T6CON 49Eh NCO1CON 51Eh 41Fh

420h

— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh— —48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh— —490h—510h—590h—610h—690h— 710h — 790h — —491h— 511h OPA1CON 591h —611h—691h —492h—512h—592h—612h—692h —493h—513h—593h—613h—693h —494h—514h—594h—614h—694h

— 498h NCO1ACCL 518h —598h— 618h PWM3DCH 698h — 499h NCO1ACCH 519h —599h— 619h PWM3CON 699h — 49Ah NCO1ACCU 51Ah —59Ah— 61Ah PWM4DCL 69Ah — 49Bh NCO1INCL 51Bh —59Bh— 61Bh PWM4DCH 69Bh

— 49Fh NCO1CLK 51Fh —59Fh—61Fh—69Fh

480h

48Bh

4A0h

Core Registers

(Ta bl e 3 - 2)

— 515h OPA2CON 595h —615h—695h —516h—596h—616h—696h —517h—597h— 617h PWM3DCL 697h

500h

50Bh

520h

Core Registers

(Table 3-2)

— 59Ch — 61Ch PWM4CON 69Ch — 59Dh — 61Dh — 69Dh —59Eh—61Eh—69Eh

580h

58Bh

5A0h

Core Registers

(Table 3-2)

600h

60Bh

620h

Core Registers

(Table 3-2)

680h

68Bh

6A0h

Core Registers

(Table 3-2)

COG1PHR

COG1PHF COG1BLKR COG1BLKF

COG1DBR

COG1DBF COG1CON0 COG1CON1

COG1RIS

COG1RSIM

COG1FIS

COG1FSIM COG1ASD0 COG1ASD1

COG1STR

700h

Core Registers

(Table 3-2)

70Bh

711h — 791h — 712h — 792h — 713h — 793h — 714h — 794h — 715h — 795h — 716h — 796h — 717h — 797h — 718h — 798h — 719h — 799h — 71Ah —79Ah— 71Bh —79Bh— 71Ch — 79Ch — 71Dh — 79Dh — 71Eh —79Eh— 71Fh —79Fh—

720h

780h

78Bh

7A0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h

Accesses 70h – 7Fh

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

4F0h

Unimplemented

Read as ‘0’

Accesses 70h – 7Fh

570h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

5F0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

670h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

6F0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

770h

Unimplemented

Read as ‘0’

7F0h

Accesses

70h – 7Fh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

Core Registers

(Ta bl e 3 - 2) 80Bh 80Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh 870h

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Accesses 70h – 7Fh

880h

88Bh 88Ch

8F0h

Core Registers

(Ta bl e 3 - 2)

Unimplemented

Read as ‘0’

Accesses 70h – 7Fh

900h

90Bh 90Ch

970h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

980h

98Bh 98Ch

9EFh 9F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

A00h

A0Bh A0Ch

A6Fh

A70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

A80h

A8Bh A8Ch

AEFh AF0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

B00h

B0Bh B0Ch

B6Fh B70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

B80h

B8Bh B8Ch

BEFh BF0h

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3 - 2)

C80h

C8Bh

Core Registers

(Ta bl e 3 - 2)

D00h

D0Bh

Core Registers

(Ta bl e 3 - 2)

D80h

D8Bh

Core Registers

(Ta bl e 3 - 2)

E00h

E0Bh

Core Registers

(Ta bl e 3 - 2)

E80h

E8Bh

Core Registers

(Ta bl e 3 - 2)

F00h

F0Bh

Core Registers

(Ta bl e 3 - 2)

F80h

F8Bh

Core Registers

(Ta bl e 3 - 2)

C0Ch

—C8Ch—D0Ch—D8Ch—E0Ch

See Tab l e 3 -7 for

details

E8Ch

See Tab l e 3 -7 for register mapping

details

F0Ch

See Tab l e 3 -7 for register mapping

details

F8Ch

See Tab l e 3 -7 for register mapping

details

C0Dh

—C8Dh—D0Dh—D8Dh— E0Dh E8Dh F0Dh F8Dh

C0Eh

—C8Eh—D0Eh—D8Eh— E0Eh E8Eh F0Eh F8Eh

C0Fh

—C8Fh—D0Fh—D8Fh— E0Fh E8Fh F0Fh F8Fh

C10h

—C90h—D10h—D90h— E10h E90h F10h F90h

C11h

—C91h—D11h—D91h— E11h E91h F11h F91h

C12h

—C92h—D12h—D92h— E12h E92h F12h F92h

C13h

—C93h—D13h—D93h— E13h E93h F13h F93h

C14h

—C94h—D14h—D94h— E14h E94h F14h F94h

C15h

—C95h—D15h—D95h— E15h E95h F15h F95h

C16h

—C96h—D16h—D96h— E16h E96h F16h F96h

C17h

—C97h—D17h—D97h— E17h E97h F17h F97h

C18h

—C98h—D18h—D98h— E18h E98h F18h F98h

C19h

—C99h—D19h—D99h— E19h E99h F19h F99h

C1Ah

—C9Ah—D1Ah—D9Ah— E1Ah E9Ah F1Ah F9Ah

C1Bh

—C9Bh—D1Bh—D9Bh— E1Bh E9Bh F1Bh F9Bh

C1Ch

—C9Ch—D1Ch—D9Ch— E1Ch E9Ch F1Ch F9Ch

C1Dh

—C9Dh—D1Dh—D9Dh— E1Dh E9Dh F1Dh F9Dh

C1Eh

—C9Eh—D1Eh—D9Eh— E1Eh E9Eh F1Eh F9Eh

C1Fh

—C9Fh—D1Fh—D9Fh— E1Fh E9Fh F1Fh F9Fh

C20h

Unimplemented

Read as ‘0’

CA0h

Unimplemented

Read as ‘0’

D20h

Unimplemented

Read as ‘0’

DA0h

Unimplemented

Read as ‘0’

E20h EA0h F20h FA0h

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh C70h

Accesses 70h – 7Fh

CF0h

Accesses 70h – 7Fh

D70h

Accesses

70h – 7Fh

DF0h

Accesses

70h – 7Fh

E70h

Accesses

70h – 7Fh

EF0h

Accesses

70h – 7Fh

F70h

Accesses

70h – 7Fh

FF0h

Accesses

70h – 7Fh

CFFh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 23

TABLE 3-5: PIC16(L)F1713/6 MEMORY MAP, BANK 24-31

PIC16(L)F1713/6

Legend: = Unimplemented data memory locations, read as ‘0’,

Note 1: Only available on PIC16(L)F1713 devices

Bank 28 Bank 29 Bank 30

E0Ch —E8Ch—F0Ch — E0Dh

—E8Dh—F0Dh —

E0Eh

—E8Eh—F0Eh —

E0Fh PPSLOCK E8Fh

— F0Fh CLCDATA E10h INTPPS E90h RA0PPS F10h CLC1CON E11h T0CKIPPS E91h RA1PPS F11h CLC1POL E12h T1CKIPPS E92h RA2PPS F12h CLC1SEL0 E13h T1GPPS E93h RA3PPS F13h CLC1SEL1 E14h CCP1PPS E94h RA4PPS F14h CLC1SEL2 E15h CCP2PPS E95h RA5PPS F15h CLC1SEL3 E16h

— E96h RA6PPS F16h CLC1GLS0 E17h COGINPPS E97h RA7PPS F17h CLC1GLS1 E18h

— E98h RB0PPS F18h CLC1GLS2 E19h

— E99h RB1PPS F19h CLC1GLS3

E1Ah

—

E9Ah

RB2PPS

F1Ah

CLC2CON

E1Bh

— E9Bh RB3PPS F1Bh CLC2POL

E1Ch

—E9ChRB4PPS

(1)

F1Ch CLC2SEL0

E1Dh

—E9DhRB5PPS

(1)

F1Dh CLC2SEL1

E1Eh

—E9EhRB6PPS

(1)

F1Eh CLC2SEL2

E1Fh

—E9FhRB7PPS

(1)

F1Fh CLC2SEL3 E20h SSPCLKPPS EA0h RC0PPS F20h CLC2GLS0 E21h SSPDATPPS EA1h RC1PPS F21h CLC2GLS1 E22h SSPSSPPS EA2h RC2PPS F22h CLC2GLS2 E23h

— EA3h RC3PPS F23h CLC2GLS3 E24h RXPPS EA4h RC4PPS F24h CLC3CON E25h CKPPS EA5h RC5PPS F25h CLC3POL

E26h

— EA6h RC6PPS

(1)

F26h CLC3SEL0

E27h

— EA7h RC7PPS

(1)

F27h CLC3SEL1

E28h CLCIN0PPS EA8h

— F28h CLC3SEL2

E29h CLCIN1PPS EA9h

— F29h CLC3SEL3

E2Ah

CLCIN2PPS

EAAh

—

F2Ah

CLC3GLS0

E2Bh CLCIN3PPS EABh

— F2Bh CLC3GLS1

E2Ch

—EACh— F2Ch CLC3GLS2

E2Dh

—EADh— F2Dh CLC3GLS3

E2Eh

— EAEh — F2Eh CLC4CON

E2Fh

—EAFh— F2Fh CLC4POL E30h

— EB0h — F30h CLC4SEL0 E31h

— EB1h — F31h CLC4SEL1 E32h

—

EB2h

— F32h CLC4SEL2

E33h

— EB3h — F33h CLC4SEL3 E34h

— EB4h — F34h CLC4GLS0 E35h

— EB5h — F35h CLC4GLS1 E36h

— EB6h — F36h CLC4GLS2 E37h

— EB7h — F37h CLC4GLS3 E38h

— EB8h —F38h — E39h

— EB9h —F39h —

E3Ah

—

EBAh

—F3Ah —

E3Bh

— EBBh —F3Bh —

E3Ch

— EBCh —F3Ch —

E3Dh

—EBDh—F3Dh —

E3Eh

— EBEh —F3Eh —

E3Fh

— EBFh —F3Fh — E40h

—

EC0h

—

F40h

—

E6Fh EEFh F6Fh

TABLE 3-6: PIC16(L)F1713/6 MEMORY MAP, BANK 28-30

DS40001726B-page 24 Preliminary  2013-2014 Microchip Technology Inc.

TABLE 3-7: PIC16(L)F1713/6 MEMORY

Legend: = Unimplemented data memory locations,

read as ‘0’,

Bank 31

F8Ch

ICDIO

F8Dh

ICDCON0

F8Eh

—

F8Fh

—

F90h

—

F91h

ICDSTAT

F92h

—

F93h

—

F94h

—

F95h

—

F96h

ICDINSTL

F97h

ICDINSTH

F98h

—

F99h

—

F9Ah

—

F9Bh

—

F9Ch

ICDBK0CON

F9Dh

ICDBK0L

F9Eh

ICDBK0H

F9Fh

—

FE2h FE3h

BSRICDSHAD

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

FF0h

FFFh

—

MAP, BANK 31

PIC16(L)F1713/6

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 25

PIC16(L)F1713/6

3.3.5 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3- 8 can be addressed from any Bank.

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: These registers can be addressed from any bank.

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

Value on all

other Resets

DS40001726B-page 26 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx --uu uuuu

00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu ----

00Eh PORTC RC7

00Fh

— Unimplemented — —

010h

PORTE —

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0-00

012h PIR2 OSFIF C2IF C1IF

013h PIR3

014h

— Unimplemented — —

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM

01Ah TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 uuuu uuuu

01Bh PR2 Timer2 Period Register 1111 1111 uuuu uuuu

01Ch T2CON

01Dh

— Unimplemented — —

01Fh

Bank 1

08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 --11 1111

08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISA0 1111 1111 1111 ----

08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

08Fh

— Unimplemented — —

090h TRISE

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE C2IE C1IE

093h PIE3

094h

— Unimplemented — —

095h

OPTION_REG

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

099h OSCCON SPLLEN IRCF<3:0>

09Ah OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 0q0q qqqq --0q

09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu

09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS<2:0>

09Fh ADCON2 TRIGSEL<3:0>

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

(

RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

— — —

— BCL1IF TMR6IF TMR4IF CCP2IF 000- 0000 000- 00--

— NCOIF COGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF -000 0000 --00 -000

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

—

— NCOIE COGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE -000 0000 --00 -000

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111

— — WDTPS<4:0> SWDTEN --01 0110 --01 0110

— — TUN<5:0> --00 0000 --00 0000

—CHS<4:0>

— — —

— BCL1IE TMR6IE TMR4IE CCP2IE 000- 0000 000- 0000

—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu

RE3

T1GGO/

DONE

TRISE3

— ADNREF ADPREF<1:0> 0000 -000 0000 --00

— — — — 0000 ---- 0000 ----

— — —

—TMR1ON0000 00-0 uuuu uu-u

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

— — —

—SCS<1:0>0011 1-00 0011 1-00

GO/DONE

ADON -000 0000 -000 0000

Valu e o n

POR, BOR

---- x--- ---- u---

---- 1--- ---- 1---

Value on all

other

Resets

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 27

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

10Ch LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx --uu -uuu

10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu ----

10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu

10Fh

— Unimplemented — —

110 h

— Unimplemented — —

111h

CM1CON0 C1ON C1OUT — C1POL C1ZLF C1SP C1HYS C1SYNC 00-0 0100 00-0 0100

112 h

CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000

113 h

CM2CON0 C2ON C2OUT — C2POL C2ZLF C2SP C2HYS C2SYNC 00-0 0100 00-0 0100

114 h

CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000

115 h

CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00

116h BORCON SBOREN BORFS

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

118h DAC1CON0 DAC1EN

119h DAC1CON1 DAC1R<7:0> 0000 0000 0000 0000

11Ah DAC2CON0 DAC2EN

11Bh DAC2CON1 —

11Ch ZCD1CON ZCD1EN

11D h

— Unimplemented — —

11E h

— Unimplemented — —

11F h

— Unimplemented — —

Bank 3

18Ch

ANSELA — —ANSA5ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 ---1 1111

18Dh ANSELB

18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2

18Fh

— Unimplemented — —

190h

— Unimplemented — —

191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000

192h PMADRH

193h PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h PMDATH

195h PMCON1

196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000

197h VREGCON

198h

— Unimplemented — —

199h RC1REG USART Receive Data Register 0000 0000 0000 0000

19Ah TX1REG USART Transmit Data Register 0000 0000 0000 0000

19Bh SP1BRGL SP1BRG<7:0> 0000 0000 0000 0000

19Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000

19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000

19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUD1CON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 ----

— Program Memory Address Register High Byte 1000 0000 1000 0000

— — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

— CFGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000

— — — — — —VREGPMReserved ---- --01 ---- --01

--- DAC1OE1 DAC1OE2 DAC1PSS<1:0> --- DAC1NSS 0-00 00-0 0-00 00-0

— — —

— ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 0-x0 --00 0-00 --00

— — — — — BORRDY 10-- ---q uu-- ---u

DAC2OE1 DAC2OE2 DAC2PSS<1:0> —DAC2NSS0-00 00-0 0-00 00-0

DAC2R<4:0> ---0 0000 ---0 0000

— — 1111 11-- 1111 1111

—SCKPBRG16—WUEABDEN01-0 0-00 01-0 0-00

Valu e o n

POR, BOR

Value on all

other

Resets

DS40001726B-page 28 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 4

20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 --11 1111

20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 ----

20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111

20Fh

— Unimplemented — —

210h WPUE

211h SSP1BUF

212h SSP1ADD

213h SSP1MSK

214h SSP1STAT SMP CKE D/A

215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

—

— Unimplemented — —

21Fh

Bank 5

28Ch ODCONA ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 0000 0000 --00 -000

28Dh ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 000- 0000 ----

28Eh ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000

28Fh

— Unimplemented — —

290h

— Unimplemented — —

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

293h CCP1CON

294h

—

— Unimplemented — —

297h

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

29Ah CCP2CON

29Bh

—

— Unimplemented — —

29Dh

29Eh CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0000 0000 0000 0000

29Fh

— Unimplemented — —

Bank 6

30Ch SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 1111 1111 --00 -000

30Dh SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 1111 1111 0000 ----

30Eh SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 0000 0000

30Fh —

— Unimplemented — —

31Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — — WPUE3 — — — ---- 1--- ---- 1---

Synchronous Serial Port Receive Buffer/Transmit Register

ADD<7:0>

MSK<7:0>

PSR/WUA BF 0000 0000 0000 0000

— — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000

— — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000

Valu e o n

POR, BOR

XXXX XXXX uuuu uuuu

XXXX XXXX 0000 0000

XXXX XXXX 1111 1111

Value on all

other

Resets

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 29

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 7

38Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 1111 1111 --11 1111

38Dh INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 1111 1111 1111 ----

38Eh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111

38Fh

— Unimplemented — —

390h INLVLE

391h IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0000 0000 --00 0000

392h IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0000 0000 --00 0000

393h IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0000 0000 --00 0000

394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 ----

395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 ----

396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 ----

397h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000

398h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000

399h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000

39Ah —

— Unimplemented — —

39Ch

39Dh IOCEP

39Eh IOCEN

39Fh IOCEF

Bank 8

40Ch —

— Unimplemented — —

414h

415h TMR4 Holding Register for the 8-bit TMR4 Register 0000 0000 uuuu uuuu

416h PR4 Timer4 Period Register 1111 1111 uuuu uuuu

417h T4CON

418h —

— Unimplemented — —

41Bh

41Ch TMR6 Holding Register for the 8-bit TMR6 Register 0000 0000 uuuu uuuu

41Dh PR6 Timer6 Period Register 1111 1111 uuuu uuuu

41Eh T6CON

41Fh

— Unimplemented — —

Bank 9

48Ch

— Unimplemented — —

497h

498h NCO1ACCL NCO1ACC 0000 0000 0000 0000

499h NCO1ACCH NCO1ACC 0000 0000 0000 0000

49Ah NCO1ACCU NCO1ACC ---- 0000 ---- 0000

49Bh NCO1INCL NCO1INC 0000 0001 0000 0001

49Ch NCO1INCH NCO1INC 0000 0000 0000 0000

49Dh NCO1INCU NCO1INC ---- 0000 ---- 0000

49Eh NCO1CON N1EN

49Fh NCO1CLK N1PWS<2:0>

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — —IOCEP3— — — ---- 0--- ---- 0---

— — — —IOCEN3— — — ---- 0--- ---- 0---

— — — — IOCEF3 — — — ---- 0--- ---- 0---

— T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000

— T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000

— N1OUT N1POL — — —N1PFM0-00 ---0 0-00 ---0

— — — N1CKS<1:0> 000- --00 000- --00

INLVLE3 ---- 1--- ---- 1---

Valu e o n

POR, BOR

Value on all

other

Resets

DS40001726B-page 30 Preliminary  2013-2014 Microchip Technology Inc.

PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 10

50Ch —

— Unimplemented — —

510h

511h OPA1CON OPA1EN OPA1SP

512h —

— Unimplemented — —

514h

515h OPA2CON OPA2EN OPA2SP

516h —

— Unimplemented — —

51Fh

Bank 11

58Ch

— Unimplemented — —

59Fh

Bank 12

60Ch

— Unimplemented — —

616h

617h PWM3DCL PWM3DC<1:0>

618h PWM3DCH PWM3DCH<7:0> xxxx xxxx uuuu uuuu

619h PWM3CON PWM3EN

61Ah PWM4DCL PWM4DCL<1:0>

61Bh PWM4DCH PWM4DCH<7:0> xxxx xxxx uuuu uuuu

61Ch PWM4CON PWM4EN

61Dh

—

— Unimplemented — —

61Fh

Bank 13

68Ch

— Unimplemented — —

690h

691h COG1PHR

692h COG1PHF

693h COG1BLKR

694h COG1BLKF

695h COG1DBR

696h COG1DBF

697h COG1CON0 G1EN G1LD

698h COG1CON1 G1RDBS G1FDBS

699h COG1RIS G1RIS7

69Ah COG1RSIM G1RSIM7

69Bh COG1FIS G1FIS7

69Ch COG1FSIM G1FSIM7

69Dh COG1ASD0 G1ASE G1ARSEN G1ASDBD<1:0> G1ASDAC<1:0>

69Eh COG1ASD1

69Fh COG1STR

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: Unimplemented, read as ‘1’.

2: Unimplemented on PIC16(L)F1713/6.

— — COG Rising Edge Phase Delay Count Register --xx xxxx --uu uuuu

— — COG Falling Edge Phase Delay Count Register --xx xxxx --uu uuuu

— — COG Rising Edge Blanking Count Register --xx xxxx --uu uuuu

— — COG Falling Edge Blanking Count Register --xx xxxx --uu uuuu

— — COG Rising Edge Dead-band Count Register --xx xxxx --uu uuuu

— — COG Falling Edge Dead-band Count Register --xx xxxx --uu uuuu

— — — — G1AS3E G1AS2E G1AS1E G1AS0E ---- 0000 ---- 0000

G1SDATD G1SDATC G1SDATB G1SDATA G1STRD G1STRC G1STRB G1STRA

— PWM3OUT PWM3POL — — — — 0-x0 ---- u-uu ----

— PWM4OUT PWM4POL — — — — 0-x0 ---- u-uu ----

G1RIS6 G1RIS5 G1RIS4 G1RIS3 G1RIS2 G1RIS1 G1RIS0

G1RSIM6 G1RSIM5 G1RSIM4 G1RSIM3 G1RSIM2 G1RSIM1 G1RSIM0

G1FIS6 G1FIS5 G1FIS4 G1FIS3 G1FIS2 G1FIS1 G1FIS0

G1FSIM6 G1FSIM5 G1FSIM4 G1FSIM3 G1FSIM2 G1FSIM1 G1FSIM0

—OPA1UG— — OPA1PCH<1:0> 00-0 --00 00-0 --00

—OPA2UG— — OPA2PCH<1:0> 00-0 --00 00-0 --00

— — — — — — xx-- ---- uu-- ----

— G1CS<1:0> G1MD<2:0> 00-0 0000 00-0 0000

— — G1POLD G1POLC G1POLB G1POLA 00-- 0000 00-- 0000

— — 0001 01-- 0001 01--

Valu e o n

POR, BOR

0000 0000 -000 0000

0000 0001 0000 0001

Value on all

other

Resets

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TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 14-27

x0Ch/ x8Ch —

— Unimplemented — — x1Fh/ x9Fh

Bank 28

E0Ch —

— Unimplemented — — E0Eh

E0Fh

E10h

E11h

E12h

E13h

E14h

E15h

E16h

E17h

E18h

E19h

E1Ah

E1FH

E20h SSPCLKPPS

E21h SSPDATPPS

E22h SSPSSPPS

E23h

E24h RXPPS

E25h CKPPS

E26h

E27h

E28h

E29h

E2Ah

E2Bh

E2Ch

E6Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

PPSLOCK

INTPPS

T0CKIPPS

T1CKIPPS

T1GPPS

CCP1PPS

CCP2PPS

—

COGINPPS

— Unimplemented — —

—

CLCIN0PPS

CLCIN1PPS

CLCIN2PPS

CLCIN3PPS

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — — — — — PPSLOCKED ---- ---0 ---- ---0

— — —

Unimplemented — —

— — —

— — — SSPCLKPPS<4:0> ---1 0011 ---u uuuu

— — — SSPDATPPS<4:0> ---1 0100 ---u uuuu

— — — SSPSSPPS<4:0> ---0 0101 ---u uuuu

Unimplemented — —

— — — RXPPS<4:0> ---1 0111 ---u uuuu

— — — CKPPS<4:0> ---1 0110 ---u uuuu

Unimplemented — —

— — —

INTPPS<4:0>

T0CKIPPS<4:0>

T1CKIPPS<4:0>

T1GPPS<4:0>

CCP1PPS<4:0>

CCP2PPS<4:0>

COGINPPS<4:0>

CLCIN0PPS<4:0>

CLCIN1PPS<4:0>

CLCIN2PPS<4:0>

CLCIN3PPS<4:0>

Valu e o n

POR, BOR

---0 1000 ---u uuuu

---0 0100 ---u uuuu

---1 0000 ---u uuuu

---0 1101 ---u uuuu

---1 0010 ---u uuuu

---1 0001 ---u uuuu

---0 1000 ---u uuuu

---0 0000 ---u uuuu

---0 0001 ---u uuuu

---0 1110 ---u uuuu

---0 1111 ---u uuuu

Value on all

other

Resets

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PIC16(L)F1713/6

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 29

E8Ch —

— Unimplemented — —

E8Fh

E90h

E91h

E92h

E93h RA3PPS

E94h

E95h

E96h RA6PPS

E97h RA7PPS

E98h RB0PPS

E99h RB1PPS

E9Ah RB2PPS

E9Bh RB3PPS

E9Ch

E9Dh

E9Eh

E9Fh

EA0h

EA1h

EA2h

EA3h

EA4h

EA5h

EA6h

EA7h

EA8h — EEFh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

RA0PPS

RA1PPS

RA2PPS

RA4PPS

RA5PPS

RB4PPS

RB5PPS

RB6PPS

RB7PPS

RC0PPS

RC1PPS

RC2PPS

RC3PPS

RC4PPS

RC5PPS

RC6PPS

RC7PPS

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — RA0PPS<4:0> ---0 0000 ---u uuuu

— — — RA1PPS<4:0> ---0 0000 ---u uuuu

— — — RA2PPS<4:0> ---0 0000 ---u uuuu

— — — RA3PPS4:0> ---0 0000 ---u uuuu

— — — RA4PPS<4:0> ---0 0000 ---u uuuu

— — — RA5PPS<4:0> ---0 0000 ---u uuuu

— — — RA6PPS<4:0> ---0 0000 ---u uuuu

— — — RA7PPS<4:0> ---0 0000 ---u uuuu

— — — RB0PPS<4:0> ---0 0000 ---u uuuu

— — — RB1PPS<4:0> ---0 0000 ---u uuuu

— — — RB2PPS<4:0> ---0 0000 ---u uuuu

— — — RB3PPS<4:0> ---0 0000 ---u uuuu

— — — RB4PPS<4:0> ---0 0000 ---u uuuu

— — — RB5PPS<4:0> ---0 0000 ---u uuuu

— — — RB6PPS<4:0> ---0 0000 ---u uuuu

— — — RB7PPS<4:0> ---0 0000 ---u uuuu

— — — RC0PPS<4:0> ---0 0000 ---u uuuu

— — — RC1PPS<4:0> ---0 0000 ---u uuuu

— — — RC2PPS<4:0> ---0 0000 ---u uuuu

— — — RC3PPS<4:0> ---0 0000 ---u uuuu

— — — RC4PPS<4:0> ---0 0000 ---u uuuu

— — — RC5PPS<4:0> ---0 0000 ---u uuuu

— — — RC6PPS<4:0> ---0 0000 ---u uuuu

— — — RC7PPS<4:0> ---0 0000 ---u uuuu

Valu e o n

POR, BOR

Value on all

other

Resets

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TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 30

F0Ch —

— Unimplemented — — F0Eh

F0Fh CLCDATA

F10h CLC1CON LC1EN

F11h CLC1POL LC1POL

F12h CLC1SEL0

F13h CLC1SEL1

F14h CLC1SEL2

F15h CLC1SEL3

F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu

F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu

F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu

F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu

F1Ah CLC2CON LC2EN

F1Bh CLC2POL LC2POL

F1Ch CLC2SEL0

F1Dh CLC2SEL1

F1Eh CLC2SEL2

F1Fh CLC2SEL3

F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu

F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu

F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu

F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu

F24h CLC3CON LC3EN

F25h CLC3POL LC3POL

F26h CLC3SEL0

F27h CLC3SEL1

F28h CLC3SEL2

F29h CLC3SEL3

F2Ah CLC3GLS0

F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu

F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu

F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu

F2Eh CLC4CON LC4EN

F2Fh CLC4POL LC4POL

F30h CLC4SEL0

F31h CLC4SEL1

F32h CLC4SEL2

F33h CLC4SEL3

F34h CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu

F35h CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu

F36h CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu

F37h CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu

F38h —

— Unimplemented — — F6Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- 0000

— LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0-x0 0000 0-00 0000

— — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL x--- xxxx 0--- uuuu

— — — LC1D1S<4:0> ---x xxxx ---u uuuu

— — — LC1D2S<4:0> ---x xxxx ---u uuuu

— — — LC1D3S<4:0> ---x xxxx ---u uuuu

— — — LC1D4S<4:0> ---x xxxx ---u uuuu

— LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0-x0 0000 0-00 0000

— — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL x--- xxxx 0--- uuuu

— — — LC2D1S<4:0> ---x xxxx ---u uuuu

— — — LC2D2S<4:0> ---x xxxx ---u uuuu

— — — LC2D3S<4:0> ---x xxxx ---u uuuu

— — — LC2D4S<4:0> ---x xxxx ---u uuuu

— LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0-x0 0000 0-00 0000

— — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL x--- xxxx 0--- uuuu

— — — LC3D1S<4:0> ---x xxxx ---u uuuu

— — — LC3D2S<4:0> ---x xxxx ---u uuuu

— — — LC3D3S<4:0> ---x xxxx ---u uuuu

— — — LC3D4S<4:0> ---x xxxx ---u uuuu

— — — LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N ---x xxxx uuuu uuuu

— LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0-X0 0000 0-00 0000

— — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL x--- xxxx 0--- uuuu

— — — LC4D1S<4:0> ---x xxxx ---u uuuu

— — — LC4D2S<4:0> ---x xxxx ---u uuuu

— — — LC4D3S<4:0> ---x xxxx ---u uuuu

— — — LC4D4S<4:0> ---x xxxx ---u uuuu

Valu e o n

POR, BOR

Value on all

other

Resets

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TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 31

F8Ch

—

— Unimplemented — —

FE3h

FE4h STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSRIL_SHAD

FEBh

FSRIH_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented on PIC16(L)F1713/6.

— — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu

WREG_SHAD xxxx xxxx uuuu uuuu

— — — BSR_SHAD ---x xxxx ---u uuuu

— PCLATH_SHAD -xxx xxxx -uuu uuuu

FSR0L_SHAD xxxx xxxx uuuu uuuu

FSR0H_SHAD xxxx xxxx uuuu uuuu

FSRIL_SHAD xxxx xxxx uuuu uuuu

FSR1H_SHAD xxxx xxxx uuuu uuuu

Unimplemented —

— — —STKPTR---1 1111 ---1 1111

TOSL xxxx xxxx uuuu uuuu

—TOSH-xxx xxxx -uuu uuuu

Valu e o n

POR, BOR

Value on all

other

Resets

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PCLPCH

ALU Result

PCLATH

PCLPCH

OPCODE <10:0>

PCLATH

PCLPCH

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH

PC + W

BRW

PCLPCH

PC + OPCODE <8:0>

BRA

3.4 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN

DIFFERENT SITUATIONS

3.4.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.

3.4.4 BRANCHING

The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction.

3.4.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

3.4.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).

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0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled (STVREN = 0)

Stack Reset Enabled (STVREN = 1)

TOSH:TOSL

3.5 Stack

All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 3-1). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled.

Note: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

3.5.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR.

Reference Figure 3-5 through Figure 3-8 for examples of accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

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PIC16(L)F1713/6

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00

STKPTR = 0x00

This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack.

TOSH:TOSL

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

DS40001726B-page 38 Preliminary  2013-2014 Microchip Technology Inc.

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00

STKPTR = 0x10

When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten.

Return Address

TOSH:TOSL

PIC16(L)F1713/6

3.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register.

3.6 Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

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PIC16(L)F1713/6

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000

Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

FIGURE 3-9: INDIRECT ADDRESSING

DS40001726B-page 40 Preliminary  2013-2014 Microchip Technology Inc.

3.6.1 TRADITIONAL DATA MEMORY

Indirect AddressingDirect Addressing

Bank Select

Location Select

4BSR 6

From Opcode

FSRxL70

Bank Select

Location Select

00000 00001 00010 11111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

FSRxH70

0000

The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

PIC16(L)F1713/6

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Location Select

0x2000

FSRnH

FSRnL

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

Location Select

0x8000

FSRnH

FSRnL

0x0000

0x7FFF

0xFFFF

Program Flash Memory (low 8 bits)

3.6.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

3.6.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH

MEMORY MAP

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NOTES:

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4.0 DEVICE CONFIGURATION

Device configuration consists of Configuration Words, Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Words is

managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

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4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1

FCMEN IESO CLKOUTEN BOREN<1:0>

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

(1)

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

bit 12 IESO: Internal External Switchover bit

bit 11 CLKOUTEN

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

bit 8 Unimplemented: Read as ‘1’ bit 7 CP

bit 6 MCLRE: MCLR

bit 5 PWRTE

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

1 = Fail-Safe Clock Monitor and internal/external switchover are both enabled. 0 = Fail-Safe Clock Monitor is disabled

1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled

: Clock Out Enable bit

FOSC configuration bits are set to LP, XT, HS modes:

This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.

All other FOSC modes:

1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin

11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled

: Code Protection bit

1 = Program memory code protection is disabled 0 = Program memory code protection is enabled

/VPP Pin Function Select bit

If LVP bit =

This bit is ignored.

If LVP bit = 0:

1 =MCLR 0 =MCLR

1 = PWRT disabled 0 = PWRT enabled

11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled

/VPP pin function is MCLR; Weak pull-up enabled. /VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

: Power-up Timer Enable bit

(1)

—

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bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: The entire Flash program memory will be erased when the code protection is turned off during an erase.

When a Bulk Erase Program Memory Command is executed, the entire program Flash memory and configuration memory will be erased.

DS40001726B-page 46 Preliminary  2013-2014 Microchip Technology Inc.

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

(1)

LVP

bit 13 bit 8

DEBUG

(2)

LPBOR BORV

PIC16(L)F1713/6

(3)

STVREN PLLEN

R/P-1

ZCDDIS

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit

bit 12

bit 11

bit 10 BORV: Brown-out Reset Voltage Selection bit

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

bit 8 PLLEN: PLL Enable bit

bit 7 ZCDDIS: ZCD Disable bit

bit 6-3 Unimplemented: Read as ‘1’

bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit

bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

U-1 U-1 U-1 U-1 R/P-1 R/P-1 R/P-1

— — — —

(1)

1 = Low-voltage programming enabled 0 = High-voltage on MCLR

: In-Circuit Debugger Mode bit

DEBUG

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

LPBOR

: Low-Power BOR Enable bit

1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled

1 = Brown-out Reset voltage (VBOR), low trip point selected. 0 = Brown-out Reset voltage (V

1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset

1 = 4xPLL enabled 0 = 4xPLL disabled

1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 = ZCD always enabled

1 = The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all

future changes to PPS registers are prevented

0 = The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed)

Flash memory

4 kW

11 = Write protection off 10 = 000h to 1FFh write protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write protected, no addresses may be modified by PMCON control

must be used for programming

(2)

(3)

BOR), high trip point selected.

PPS1WAY

WRT<1:0>

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: The DEBUG

and programmers. For normal device operation, this bit should be maintained as a ‘1’.

3: See V

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 47

bit in Configuration Words is managed automatically by device development tools including debuggers

BOR parameter for specific trip point voltages.

PIC16(L)F1713/6

4.3 Code Protection

Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting.

4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP Words. When CP program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write

Protection” for more information.

= 0, external reads and writes of

4.4 Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected.

bit in Configuration

4.5 User ID

Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations. checksum calculation, see the “PIC16(L)F170X Memory Programming Specification” (DS41683).

For more information on

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Device DEVID<13:0> Values

PIC16F1713 11 0000 0100 0011 (3043h)

PIC16LF1713 11 0000 0100 0101 (3045h)

PIC16F1716 11 0000 0100 0010 (3042h)

PIC16LF1716 11 0000 0100 0100 (3044h)

4.6 Device ID and Revision ID

The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See

Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.

4.7 Register Definitions: Device and Revision

REGISTER 4-3: DEVID: DEVICE ID REGISTER

RRRRRR

DEV<13:8>

bit 13 bit 8

RRRRRRRR

DEV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 DEV<13:0>: Device ID bits

REGISTER 4-4: REVID: REVISION ID REGISTER

RRRRRR

REV<13:8>

bit 13 bit 8

RRRRRRRR

REV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 REV<13:0>: Revision ID bits

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Device

Reset

Power-on

Reset

WDT

Time-out

Brown-out

Reset

LPBOR

Reset

RESET Instruction

MCLRE

Sleep

BOR

Active

(1)

PWRTE

LFINTOSC

VDD

ICSP™ Programming Mode Exit

Stack Underflow

Stack Overlfow

VPP/MCLR

Power-up

Timer

Rev. 10-000006A

8/14/2013

Note 1: See Table 5-1 for BOR active conditions.

5.0 RESETS

A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1.

There are multiple ways to reset this device:

• Power-On Reset (POR)

• Brown-Out Reset (BOR)

• Low-Power Brown-Out Reset (LPBOR)

•MCLR Reset

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To a l l o w VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

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5.1 Power-On Reset (POR)

The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising V performance may require greater than minimum V The PWRT, BOR or MCLR extend the start-up period until all device operation conditions have been met.

5.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the V rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 5-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

DD, fast operating speeds or analog

DD.

features can be used to

DD to

11 X X Active Waits for BOR ready

5.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 5 - 1 for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words.

DD noise rejection filter prevents the BOR from

A V triggering on small events. If V a duration greater than parameter T will reset. See Figure 5-2 for more information.

Instruction Execution upon:

Release of POR or Wake-up from Sleep

DD falls below VBOR for

BORDC, the device

(1)

(BORRDY = 1)

10 X

00 X XDisabled

Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits.

1 X Active Waits for BOR ready

0 XDisabled

5.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and V is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

5.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and V

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

DD is higher than the BOR threshold.

Awake Active

Sleep Disabled

5.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the

SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the V

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

Waits for BOR ready (BORRDY = 1)

(1)

(BORRDY = 1)

Begins immediately (BORRDY = x)

DD level.

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TPWRT

(1)

VBOR

Internal

Reset

VBOR

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

FIGURE 5-2: BROWN-OUT SITUATIONS

5.3 Register Definitions: BOR Control

REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN BORFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Words =

1 = BOR Enabled 0 = BOR Disabled

bit 6 BORFS: Brown-out Reset Fast Start bit

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect.

If BOREN <1:0> =

1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off

bit 5-1 Unimplemented: Read as ‘0’

bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive

(1)

— — — — —BORRDY

 01:

01:

(1)

10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

Note 1: BOREN<1:0> bits are located in Configuration Words.

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5.4 Low-Power Brown-Out Reset (LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to

Figure 5-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2.

DD pin.

5.4.1 ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled.

5.4.1.1 LPBOR Module Output

The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR to the PCON register and to the power control block.

signal, which goes

5.5 MCLR

The MCLR is an optional external input that can reset the device. The MCLR MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 5-2).

TABLE 5-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled 10Enabled x1Enabled

5.5.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR V

DD through an internal weak pull-up.

The device has a noise filter in the MCLR The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR

5.5.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.1 “PORTA Regis-

ters” for more information.

function is controlled by the

pin is connected to

Reset path.

pin low.

5.6 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO changed to indicate the WDT Reset. See Section 9.0

“Watchdog Timer (WDT)” for more information.

and PD bits in the STATUS register are

5.7 RESET Instruction

A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Ta bl e 5 - 4 for default conditions after a RESET instruction has occurred.

5.8 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See 3.5.2 “Overflow/Underflow Reset” for more information.

5.9 Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

5.10 Power-Up Timer

The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running.

The Power-up Timer is controlled by the PWRTE Configuration Words.

bit of

5.11 Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if required for oscillator source).

3. MCLR

The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See

Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information.

The Power-up Timer and oscillator start-up timer run independently of MCLR long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR device will begin execution after 10 F

Figure 5-3). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

must be released (if enabled).

Reset. If MCLR is kept low

high, the

OSC cycles (see

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TOST

TMCLR

TPWRT

VDD

Internal POR

Power-up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-up Timer

Oscillator

OSC

Internal Oscillator

Oscillator

OSC

External Clock (EC)

CLKIN

OSC

External Crystal

FIGURE 5-3: RESET START-UP SEQUENCE

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5.12 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Ta bl e 5 -3 and Ta bl e 5 -4 show the Reset conditions of these registers.

TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition

001110x11Power-on Reset

001110x0xIllegal, TO

001110xx0Illegal, PD is set on POR

00u11u011Brown-out Reset

uu0uuuu0uWDT Reset

uuuuuuu00WDT Wake-up from Sleep

uuuuuuu10Interrupt Wake-up from Sleep

uuu0uuuuuMCLR

uuu0uuu10MCLR

u u u u 0 u u u u RESET Instruction Executed

1uuuuuuuuStack Overflow Reset (STVREN = 1)

u1uuuuuuuStack Underflow Reset (STVREN = 1)

is set on POR

Reset during normal operation

Reset during Sleep

TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-- 110x

MCLR

Reset during normal operation 0000h ---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu

WDT Reset 0000h ---0 uuuu uu-- uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu

Brown-out Reset 0000h ---1 1uuu 00-- 11u0

Interrupt Wake-up from Sleep PC + 1

RESET Instruction Executed 0000h ---u uuuu uu-- u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

Program

Counter

(1)

STATUS

---1 0uuu uu-- uuuu

PCON

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5.13 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI

•MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

)

The PCON register bits are shown in Register 5-2.

5.14 Register Definitions: Power Control

REGISTER 5-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF —

bit 7 bit 0

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

WDT RMCLR RI POR BOR

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware

bit 5 Unimplemented: Read as ‘0’ bit 4 R

bit 3 RMCLR

bit 2 RI: RESET Instruction Flag bit

bit 1 POR

bit 0 BOR

WDT: Watchdog Timer Reset Flag bit

1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware)

: MCLR Reset Flag bit

1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR

1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware)

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

Reset has occurred (cleared by hardware)

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TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BORCON SBOREN BORFS

PCON STKOVF STKUNF

STATUS

WDTCON Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

— — —TOPD Z DC C 19

— — WDTPS<4:0> SWDTEN 96

— — — — — BORRDY 52

—RWDTRMCLR RI POR BOR 56

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6.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

6.1 Overview

The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL or EXTRC modes) and switch automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources.

The oscillator module can be configured in one of the following clock modes.

1. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode (0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode (4 MHz to 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz)

7. EXTRC – External Resistor-Capacitor

8. INTOSC – Internal oscillator (31 kHz to 32 MHz)

Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered.

The ECH, ECM, and ECL clock modes rely on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The EXTRC clock mode requires an external resistor and capacitor to set the oscillator frequency.

The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these three clock sources.

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Secondary

T1OSCEN Enable Oscillator

SOSCO

SOSCI

Timer1 Clock Source Option for other modules

OSC1

OSC2

Sleep

LP, XT, HS, RC, EC

T1OSC

To CPU and

Postscaler

MUX

16 MHz

8 MHz 4 MHz 2 MHz 1 MHz

250 kHz

500 kHz

IRCF<3:0>

31 kHz

500 kHz

Source

Internal

Oscillator

Block

WDT, PWRT, Fail-Safe Clock Monitor

16 MHz

INTOSC

(HFINTOSC)

SCS<1:0>

HFPLL

31 kHz (LFINTOSC)

Two-Speed Start-up and other modules

Oscillator

31 kHz Source

500 kHz

(MFINTOSC)

125 kHz

31.25 kHz

62.5 kHz

Peripherals

Sleep

External

Timer1

4 x PLL

PRIMUX

PLLMUX

0000

1111

Inputs Outputs

SCS FOSC<2:0>

PLLEN or

SPLLEN

IRCF PRIMUX PLLMUX

=00

=100

0x10

=1110 1 1

≠1110 1 0

≠100

0x00

1x01

≠00 X X X X X

FOSC

Oscillator

FIGURE 6-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

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OSC1/CLKIN

OSC2/CLKOUT

Clock from Ext. System

PIC

MCU

FOSC/4 or

I/O

(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

6.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (EXTRC) mode circuits.

Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 6.3

“Clock Switching” for additional information.

6.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to:

- Secondary oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 6.3 “Clock Switching”for more informa- tion.

6.2.1.1 EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 6-2 shows the pin connections for EC mode.

EC mode has three power modes to select from through Configuration Words:

• ECH – High-power, 4-32 MHz

• ECM – Medium-power, 0.5-4 MHz

• ECL – Low-power, 0-0.5 MHz

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC

MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

FIGURE 6-2: EXTERNAL CLOCK (EC)

MODE OPERATION

6.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 6-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 6-3 and Figure 6-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

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Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Quartz

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

Ceramic

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

(3)

Resonator

OSC2/CLKOUT

FIGURE 6-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Application Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC Devices” (DS00826)

• AN849, “Basic PIC (DS00849)

• AN943, “Practical PIC Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

and PIC®

Oscillator Design”

Oscillator

FIGURE 6-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

6.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended, unless either FSCM or Two-Speed Start-Up are enabled. In this case, code will continue to execute at the selected INTOSC frequency while the OST is counting. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module.

In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 6.4

“Two-Speed Clock Start-up Mode”).

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32.768 kHz

SOSCI

To Internal Logic

PIC® MCU

Crystal

SOSCO

Quartz

6.2.1.4 4x PLL

The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Table 34-9.

The 4x PLL may be enabled for use by one of two methods:

1. Program the PLLEN bit in Configuration Words to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored.

6.2.1.5 Secondary Oscillator

The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.

The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 6.3

“Clock Switching” for more information.

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Application Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

and PIC®

Devices” (DS00826)

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for Low-Power External Oscillators”

(DS01288)

FIGURE 6-5: QUARTZ CRYSTAL

OPERATION (SECONDARY OSCILLATOR)

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OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  R

EXT  100 k, 3-5V

EXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

I/O

(1)

6.2.1.6 External RC Mode

The external Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required.

The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

bit in Configuration Words.

Figure 6-6 shows the external RC mode connections.

FIGURE 6-6: EXTERNAL RC MODES

The RC oscillator frequency is a function of the supply voltage, the resistor (R and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due to tolerance of external RC components used.

EXT) and capacitor (CEXT) values

6.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 6.3

“Clock Switching” for more information.

In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL that can produce one of three internal system clock sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3).

2. The MFINTOSC (Medium-Frequency Internal

Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3).

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at 31 kHz.

bit in Configuration Words.

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6.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 6-3).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’

A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running.

The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value.

The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.

6.2.2.2 MFINTOSC

The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 6-3).

The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The MFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’

The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running.

6.2.2.3 Internal Oscillator Frequency Adjustment

The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 6-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency.

When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.

6.2.2.4 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a multiplexer (see Figure 6-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See

Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also

the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled:

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.

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6.2.2.5 Internal Oscillator Frequency Selection

The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register.

The postscaled output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connect to a multiplexer (see Figure 6-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software:

- 32 MHz (requires 4x PLL)

-16 MHz

-8 MHz

-4 MHz

-2 MHz

-1 MHz

- 500 kHz (default after Reset)

- 250 kHz

- 125 kHz

- 62.5 kHz

- 31.25 kHz

- 31 kHz (LFINTOSC)

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency.

6.2.2.6 32 MHz Internal Oscillator Frequency Selection

The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source:

• The FOSC bits in Configuration Words must be

set to use the INTOSC source as the device system clock (FOSC<2:0> = 100).

• The SCS bits in the OSCCON register must be

cleared to use the clock determined by FOSC<2:0> in Configuration Words (SCS<1:0> = 00).

• The IRCF bits in the OSCCON register must be

set to the 8 MHz HFINTOSC set to use (IRCF<3:0> = 1110).

• The SPLLEN bit in the OSCCON register must be

set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a ‘1’.

Note: When using the PLLEN bit of the

Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN option will not be available.

The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4x PLL with the internal oscillator.

The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.

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6.2.2.7 Internal Oscillator Clock Switch Timing

When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 6-7 for more details.

If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 6-1.

Start-up delay specifications are located in the oscillator tables of Section 34.0 “Electrical

Specifications”.

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FIGURE 6-7: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

0 0

Start-up Time

2-cycle Sync Running

HFINTOSC/ LFINTOSC (FSCM and WDT disabled)

HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC/

IRCF <3:0>

System Clock

= 0  0

Start-up Time 2-cycle Sync

Running

LFINTOSC HFINTOSC/MFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

MFINTOSC

PIC16(L)F1713/6

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6.3 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits:

• Default system oscillator determined by FOSC

bits in Configuration Words

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

6.3.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by the value of the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the secondary oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source.

6.3.3 SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.

The secondary oscillator is enabled using the T1OSCEN control bit in the T1CON register. See

Section 26.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

6.3.4 SECONDARY OSCILLATOR READY

(SOSCR) BIT

The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator.

When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 6-1.

6.3.2 OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator.

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6.4 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.

If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT

external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.

6.4.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO (of the Configuration Words) = 1;

Internal/External Switchover bit (Two-Speed Start-up mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

TABLE 6-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay

(1)

31 kHz

31.25 kHz-500 kHz

Oscillator Warm-up Delay (T

31.25kHz-16MHz DC – 32 MHz 2 cycles DC – 32 MHz 1 cycle of each

32 kHz-20 MHz 1024 Clock Cycles (OST)

31.25 kHz-500 kHz

31.25kHz-16MHz

2 s (approx.)

31 kHz 1 cycle of each

WARM)

LFINTOSC

Sleep/POR

MFINTOSC

HFINTOSC Sleep/POR EC, RC LFINTOSC EC, RC

Sleep/POR

Any clock source

Secondary Oscillator

LP, XT, HS

MFINTOSC

HFINTOSC Any clock source LFINTOSC Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32 MHz 2 ms (approx.) Note 1: PLL inactive.

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0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N

6.4.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 6-8: TWO-SPEED START-UP

6.4.3 CHECKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator.

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External

LFINTOSC

÷ 64

31 kHz

(~32 s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

6.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Secondary Oscillator and RC).

FIGURE 6-9: FSCM BLOCK DIAGRAM

6.5.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 6-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.

6.5.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware.

6.5.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed.

6.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation.

The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.

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OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te st

Test Test

Clock Monitor Output

FIGURE 6-10: FSCM TIMING DIAGRAM

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6.6 Register Definitions: Oscillator Control

REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0

SPLLEN IRCF<3:0>

bit 7 bit 0

Legend:

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Words = 0:

1 = 4x PLL Is enabled 0 = 4x PLL is disabled

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz HF 1110 = 8 MHz or 32 MHz HF 1101 =4MHz HF 1100 =2MHz HF 1011 =1MHz HF 1010 =500kHz HF 1001 =250kHz HF 1000 =125kHz HF 0111 = 500 kHz MF (default upon Reset) 0110 =250kHz MF 0101 =125kHz MF 0100 =62.5kHz MF 0011 =31.25kHz HF 0010 =31.25kHz MF 000x =31kHz LF

bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words

(1)

(2)

—

SCS<1:0>

Note 1: Duplicate frequency derived from HFINTOSC.

2: 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency

Selection”.

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REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q

SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS

bit 7 bit 0

Legend:

bit 7 SOSCR: Secondary Oscillator Ready bit

If T1OSCEN =

1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready

If T1OSCEN = 1 = Secondary clock source is always ready

bit 6 PLLR 4x PLL Ready bit

1 = 4x PLL is ready 0 = 4x PLL is not ready

bit 5 OSTS: Oscillator Start-up Timer Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready 0 = HFINTOSC is not ready

bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit

1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate

bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit

1 = MFINTOSC is ready 0 = MFINTOSC is not ready

bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready 0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate

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REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — TUN<5:0>

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits

100000 = Minimum frequency

•

111111 = 000000 = Oscillator module is running at the factory-calibrated frequency 000001 =

•

011110 = 011111 = Maximum frequency

TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON SPLLEN IRCF<3:0>

OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 74

OSCTUNE

PIR2 OSFIF

PIE2 OSFIE

T1CON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

— —TUN<5:0>75

C2IF C1IF

C2IE C1IE

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON

—

BCL1IF TMR6IF TMR4IF CCP2IF 86

BCL1IE TMR6IE TMR4IE CCP2IE 83

—SCS<1:0>73

TABLE 6-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN<1:0> —

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

on Page

263

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TMR0IF TMR0IE

INTF

INTE

IOCIF

IOCIE

Interrupt to CPU

Wake-up (If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7>

PEIE

(TMR1IE) PIE1<0>

Peripheral Interrupts

PIEn<7>

7.0 INTERRUPTS

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.

This chapter contains the following information for Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 7-1.

FIGURE 7-1: INTERRUPT LOGIC

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7.1 Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt event(s)

• PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers)

The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the stack

• Critical registers are automatically saved to the shadow registers (See “Section 7.5 “Automatic

Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

7.2 Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKR

PC 0004h 0005h

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC)

Interrupt Sampled during Q1

Inst(PC)

PC-1 PC+1

NOP

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(0005h)

Execute

PIC16(L)F1713/6

FIGURE 7-2: INTERRUPT LATENCY

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FIGURE 7-3: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

Instruction Fetched

Instruction Executed

Interrupt Latency

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Forced

NOP

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Forced

NOP

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 34.0 “Electrical Specifications””.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

PIC16(L)F1713/6

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7.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0

“Power-Down Mode (Sleep)” for more details.

7.4 INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.

7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.

and PD)

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7.6 Register Definitions: Interrupt Control

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

bit 7 bit 0

Legend:

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt 0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed 0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state

(1)

Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers

Note: Interrupt flag bits are set when an interrupt

 2013-2014 Microchip Technology Inc. Preliminary DS40001726B-page 81

have been cleared by software.

condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PIC16(L)F1713/6

REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt

bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

OSFIE C2IE C1IE

bit 7 bit 0

Legend:

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt

bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt

bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

1 = Enables the Timer6 to PR6 match interrupt 0 = Disables the Timer6 to PR6 match interrupt

bit 1 TMR4IE: TMR4to PR4 Match Interrupt Enable bit

1 = Enables the Timer4 to PR4 match interrupt 0 = Disables the Timer4 to PR4 match interrupt

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt

—

BCL1IE TMR6IE TMR4IE CCP2IE

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— NCOIE

bit 7 bit 0

Legend:

COGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE

bit 7 bit 6 NCOIE: NCO Interrupt Enable bit

bit 5 COGIE: COG Auto-Shutdown Interrupt Enable bit

bit 4 ZCDIE: Zero-Cross Detection Interrupt Enable bit

bit 3 CLC4IE: CLC4 Interrupt Enable bit

bit 2 CLC3IE: CLC3 Interrupt Enable bit

bit 1 CLC2IE: CLC2 Interrupt Enable bit

bit 0 CLC1IE: CLC1 Interrupt Enable bit

Unimplemented: Read as ‘0’

1 = NCO interrupt enabled 0 = NCO interrupt disabled

1 = COG interrupt enabled 0 = COG interrupt disabled

1 = ZCD interrupt enabled 0 = ZCD interrupt disabled

1 = CLC4 interrupt enabled 0 = CLC4 interrupt disabled

1 = CLC3 interrupt enabled 0 = CLC3 interrupt disabled

1 = CLC2 interrupt enabled 0 = CLC2 interrupt disabled

1 = CLC1 interrupt enabled 0 = CLC1 interrupt disabled

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2 CCP1IF: CCP1 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending

Note: Interrupt flag bits are set when an interrupt

0 = Interrupt is not pending

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REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

OSFIF C2IF C1IF

bit 7 bit 0

Legend:

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 C2IF: Comparator C2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2 TMR6IF: Timer6 to PR6 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 1 TMR4IF: Timer4 to PR4 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 CCP2IF: CCP2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

—

BCL1IF TMR6IF TMR4IF CCP2IF

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REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—NCOIF

bit 7 bit 0

Legend:

COGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF

bit 7 bit 6 NCOIF: NCO Interrupt Flag bit

bit 5 COGIF: COG Auto-Shutdown Interrupt Flag bit

bit 4 ZCDIF: Zero-Cross Detection Interrupt Flag bit

bit 3 CLC4IF: CLC4 Interrupt Flag bit

bit 2 CLC3IF: CLC3 Interrupt Flag bit

bit 1 CLC2IF: CLC2 Interrupt Flag bit

bit 0 CLC1IF: CLC1 Interrupt Flag bit

Note: Interrupt flag bits are set when an interrupt

Unimplemented: Read as ‘0’

1 = Interrupt is pending 0 = Interrupt is not pending

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TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 81

OPTION_REG

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 82

PIE2 OSFIE C2IE C1IE

PIE3

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 85

PIR2 OSFIF C2IF C1IF

PIR3

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 254

— BCL1IE TMR6IE TMR4IE CCP2IE 83

— NCOIE COGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 84

— BCL1IF TMR6IF TMR4IF CCP2IF 86

— NCOIF COGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 87

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8.0 POWER-DOWN MODE (SLEEP)

The Power-down mode is entered by executing a SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

2. PD

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals

6. Timer1 and peripherals that operate from

7. ADC is unaffected, if the dedicated FRC

8. I/O ports maintain the status they had before

9. Resets other than WDT are not affected by

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using secondary oscillator

I/O pins that are high-impedance inputs should be pulled to V currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 22.0 “Operational Amplifier

(OPA) Modules” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these mod-

ules.

bit of the STATUS register is cleared.

that operate from it may continue operation in Sleep.

Timer1 continue operation in Sleep when the Timer1 clock source selected is:

•LFINTOSC

•T1CKI

• Secondary oscillator

oscillator is selected.

SLEEP was executed (driving high, low or high-impedance).

Sleep mode.

DD or VSS externally to avoid switching

8.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

1. External Reset input on MCLR

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)

The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to

Section 5.12 “Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.

pin, if enabled

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(1)

CLKOUT

(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction Fetched

Instruction Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2 0004h 0005h

Forced NOP

OST

(3)

PC + 2

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference. 3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 6.4

“Two-Speed Clock Start-up Mode”

4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

8.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a SLEEP instruction

- SLEEP instruction will execute as a NOP

- WDT and WDT prescaler will not be cleared

bit of the STATUS register will not be set

-TO

-PD

bit of the STATUS register will not be

cleared

• If the interrupt occurs during or after the execu- tion of a SLEEP instruction

- SLEEP instruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD was executed as a NOP.

FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

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8.2 Low-Power Sleep Mode

The PIC16F1713/6 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1713/6 allows the user to optimize the operating current in Sleep, depending on the application requirements.

A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep.

8.2.1 SLEEP CURRENT VS. WAKE-UP TIME

In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize.

The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.

8.2.2 PERIPHERAL USAGE IN SLEEP

Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the normal power mode when those peripherals are enabled. The Low-Power Sleep mode is intended for use with these peripherals:

• Brown-Out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-on-change pins

• Timer1 (with external clock source)

Note: The PIC16LF1713/6 does not have a

configurable Low-Power Sleep mode. PIC16LF1713/6 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum

DD and I/O voltage than the

V PIC16F1713/6. See Section 34.0

“Electrical Specifications” for more

information.

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8.3 Register Definitions: Voltage Regulator Control

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1

— — — — — —VREGPMReserved

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

(1)

bit 7-2

bit 1

bit 0

Note 1: PIC16F1713/6 only.

2: See Section 34.0 “Electrical Specifications”.

Unimplemented: Read as ‘0’

VREGPM: Voltage Regulator Power Mode Selection bit

1 = Low-Power Sleep mode enabled in Sleep

Draws lowest current in Sleep, slower wake-up

0 = Normal-Power mode enabled in Sleep

Draws higher current in Sleep, faster wake-up

Reserved: Read as ‘1’. Maintain this bit set.

(2)

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STATUS

VREGCON

WDTCON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. Note 1: PIC16F1713/6 only.

(1)

— — —TOPD ZDCC 19

— — — — — —VREGPMReserved 92

— —WDTPS<4:0>SWDTEN96

Page

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9.0 WATCHDOG TIMER (WDT)

LFINTOSC

23-bit Programmable

Prescaler WDT

WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM

PIC16(L)F1713/6

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9.1 Independent Clock Source

The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See

Table 34-8: Oscillator Parameters for the LFINTOSC

specification.

9.2 WDT Operating Modes

The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Ta bl e 9 - 1.

9.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on.

WDT protection is active during Sleep.

9.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

9.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register.

WDT protection is unchanged by Sleep. See Table 9-1 for more details.

9.4 Clearing the WDT

The WDT is cleared when any of the following conditions occur:

•Any Reset

• CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail

• WDT is disabled

• Oscillator Start-up Timer (OST) is running

See Table 9-2 for more information.

9.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting.

When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 6.0 “Oscillator

Module (with Fail-Safe Clock Monitor)” for more

information on the OST.

When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO in the STATUS register are changed to indicate the event. See STATUS Register (Register 3-1) for more information.

and PD bits

TABLE 9-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN

11 X XActive

10 X

00 X XDisabled

Device

Mode

Awake Active

Sleep Disabled

0 Disabled

WDT

Mode

Active

9.3 Time-Out Period

The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds.

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TABLE 9-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected

Cleared

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9.6 Register Definitions: Watchdog Control

REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

(1)

SWDTEN

— — WDTPS<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32)

•

10011 = Reserved. Results in minimum interval (1:32)

10010 = 1:8388608 (2 10001 = 1:4194304 (2 10000 = 1:2097152 (2 01111 = 1:1048576 (2 01110 = 1:524288 (2 01101 = 1:262144 (2 01100 = 1:131072 (2

) (Interval 256s nominal)

) (Interval 128s nominal)

) (Interval 64s nominal)

) (Interval 32s nominal)

) (Interval 16s nominal)

) (Interval 8s nominal)

) (Interval 4s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value) 01010 = 1:32768 (Interval 1s nominal) 01001 = 1:16384 (Interval 512 ms nominal) 01000 = 1:8192 (Interval 256 ms nominal) 00111 = 1:4096 (Interval 128 ms nominal) 00110 = 1:2048 (Interval 64 ms nominal) 00101 = 1:1024 (Interval 32 ms nominal) 00100 = 1:512 (Interval 16 ms nominal) 00011 = 1:256 (Interval 8 ms nominal) 00010 = 1:128 (Interval 4 ms nominal) 00001 = 1:64 (Interval 2 ms nominal) 00000 = 1:32 (Interval 1 ms nominal)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> =

1x: This bit is ignored. If WDTE<1:0> = 01:

1 = WDT is turned on 0 = WDT is turned off

If WDTE<1:0> =

00: This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON SPLLEN IRCF<3:0> —SCS<1:0>

STATUS

WDTCON

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

Watchdog Timer.

— — —TOPD Z DC C

— — WDTPS<4:0> SWDTEN

TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

on Page

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

13:8

7:0

— — FCMEN IESO CLKOUTEN BOREN<1:0> —

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

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10.0 FLASH PROGRAM MEMORY CONTROL

The Flash program memory is readable and writable during normal operation over the full V Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

• PMADRL

•PMADRH

When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read.

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device.

The Flash program memory can be protected in two ways; by code protection (CP and write protection (WRT<1:0> bits in Configuration Words).

Code protection (CP and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs.

Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device.

Note 1: Code protection of the entire Flash

program memory array is enabled by clearing the CP

bit in Configuration Words)

(1)

= 0)

, disables access, reading

bit of Configuration Words.

10.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register.

DD range.

10.1.1 PMCON1 AND PMCON2 REGISTERS

PMCON1 is the control register for Flash program memory accesses.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine.

The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory.

10.2 Flash Program Memory Overview

It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software.

After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair.

Note: If the user wants to modify only a portion

of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations.

See Table 10-1 for Erase Row size and the number of write latches for Flash program memory.

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Start

Read Operation

Select

Program or Configuration Memory

(CFGS)

Select

Word Address

(PMADRH:PMADRL)

End

Read Operation

Instruction Fetched ignored

NOP execution forced

Instruction Fetched ignored

NOP execution forced

Initiate Read operation

(RD = 1)

Data read now in

PMDATH:PMDATL

TABLE 10-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Write

Latches

(words)

Device

PIC16(L)F1713 PIC16(L)F1716

Row Erase

(words)

32 32

10.2.1 READING THE FLASH PROGRAM MEMORY

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

3. Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions.

PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user.

FIGURE 10-1: FLASH PROGRAM

MEMORY READ FLOWCHART

Note: The two instructions following a program

memory read are required to be NOPs. This prevents the user from executing a 2-cycle instruction on the next instruction after the RD bit is set.

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,RD

executed here

INSTR(PC + 1)

executed here

PC + 1 PMADRH,PMADRL

PC+3

PC + 5

Flash ADDR

RD bit

PMDATH,PMDATL

PC + 3 PC + 4

INSTR (PC + 1)

INSTR(PC - 1)

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

Flash Data

PMDATH

PMDATL

INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)

instruction ignored Forced NOP

INSTR(PC + 2)

executed here

instruction ignored Forced NOP

* This code block will read 1 word of program * memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;

MOVWF PMADRL ; Store LSB of address

MOVLW PROG_ADDR_HI ;

MOVWF PMADRH ; Store MSB of address

BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read

NOP ; Ignored (Figure 10-1)

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location

MOVF PMDATH,W ; Get MSB of word

MOVWF PROG_DATA_HI ; Store in user location

FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

EXAMPLE 10-1: FLASH PROGRAM MEMORY READ

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Datasheet PIC16LF1713, PIC16F1713, PIC16F1716, PIC16LF1716 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Description:

Core Features:

Memory:

Operating Characteristics:

eXtreme Low-Power (XLP) Features:

Digital Peripherals:

Intelligent Analog Peripherals:

Clocking Structure:

Programming/Debug Features:

Pin Diagrams

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1713/6)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC16(L)F1713/6 BLOCK DIAGRAM

TABLE 1-2: PIC16(L)F1713/6 PINOUT DESCRIPTION

2.0 ENHANCED MID-RANGE CPU

FIGURE 2-1: CORE BLOCK DIAGRAM

2.1 Automatic Interrupt Context Saving

2.2 16-Level Stack with Overflow and Underflow

2.3 File Select Registers

2.4 Instruction Set

3.0 MEMORY ORGANIZATION

3.1 Program Memory Organization

TABLE 3-1: DEVICE SIZES AND ADDRESSES

3.1.1 READING PROGRAM MEMORY AS DATA

EXAMPLE 3-1: RETLW INSTRUCTION

3.2 Data Memory Organization

3.2.1 CORE REGISTERS

TABLE 3-2: CORE REGISTERS

3.3 Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

3.3.1 SPECIAL FUNCTION REGISTER

3.3.2 GENERAL PURPOSE RAM

3.3.3 COMMON RAM

3.3.4 DEVICE MEMORY MAPS

TABLE 3-3: PIC16(L)F1713/6 MEMORY MAP (BANKS 0-7)

TABLE 3-4: PIC16(L)F1713/6 MEMORY MAP, BANK 8-23

TABLE 3-5: PIC16(L)F1713/6 MEMORY MAP, BANK 24-31

TABLE 3-6: PIC16(L)F1713/6 MEMORY MAP, BANK 28-30

3.3.5 CORE FUNCTION REGISTERS SUMMARY

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

3.4 PCL and PCLATH

3.4.3 COMPUTED FUNCTION CALLS

3.4.4 BRANCHING

3.4.1 MODIFYING PCL

3.4.2 COMPUTED GOTO

3.5 Stack

3.5.1 ACCESSING THE STACK

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

3.5.2 OVERFLOW/UNDERFLOW RESET

3.6 Indirect Addressing

FIGURE 3-9: INDIRECT ADDRESSING

3.6.1 TRADITIONAL DATA MEMORY

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

3.6.2 LINEAR DATA MEMORY

3.6.3 PROGRAM FLASH MEMORY

4.0 DEVICE CONFIGURATION

4.1 Configuration Words

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

4.3 Code Protection

4.3.1 PROGRAM MEMORY PROTECTION

4.4 Write Protection

4.5 User ID

4.6 Device ID and Revision ID

4.7 Register Definitions: Device and Revision

REGISTER 4-3: DEVID: DEVICE ID REGISTER

REGISTER 4-4: REVID: REVISION ID REGISTER