Datasheet PIC16F1512, PIC16LF1512, PIC16F1513, PIC16LF1513 Datasheet

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PIC16(L)F1512/3

28-Pin Flash Microcontrollers with XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• Up to 7 Kbytes Linear Program Memory Addressing

• Up to 256 Bytes Linear Data Memory Addressing

• Operating Speed:

- DC – 20 MHz clock input @ 2.5V

- DC – 16 MHz clock input @ 1.8V

- DC – 200 ns instruction cycle

• Interrupt Capability with Automatic Context Saving

• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%, typical

- Software selectable frequency range from

16 MHz to 31 kHz

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- Four crystal/resonator modes up to 20 MHz

- Three external clock modes up to 20 MHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

• Two-Speed Oscillator Start-up

• Oscillator Start-up Timer (OST)

Analog Features:

• Analog-to-Digital Converter (ADC):

- 10-bit resolution

- Up to 17 channels

- Special Event Triggers

- Conversion available during Sleep

• Hardware Capacitive Voltage Divider (CVD)

- Double sample conversions

- Two result registers

- Inverted acquisition

- 7-bit pre-charge timer

- 7-bit acquisition timer

- Two guard ring output drives

- Adjustable sample and hold capacitor array

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

• Integrated Temperature Indicator

Extreme Low-Power Management PIC16LF1512/3 with XLP:

• Sleep mode: 20 nA @ 1.8V, typical

• Watchdog Timer: 300 nA @ 1.8V, typical

• Secondary Oscillator: 600 nA @ 32 kHz, 1.8V, typical

• Operating Current: 30 A/MHz @ 1.8V, typical

Special Microcontroller Features:

• Operating Voltage Range:

- 2.3V-5.5V (PIC16F1512/3)

- 1.8V-3.6V (PIC16LF1512/3)

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Programmable Low-Power Brown-out Reset (LPBOR)

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Enhanced Low-Voltage Programming (LVP)

• Programmable Code Protection

• Low-Power Sleep mode

• 128 Bytes High-Endurance Flash:

- 100,000 write Flash endurance (minimum)

Peripheral Highlights:

• Up to 25 I/O Pins (1 input-only pin):

- High current sink/source 25 mA/25 mA

- Individually programmable weak pull-ups

- Individually programmable interrupt-on-change

(IOC) pins

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Low-power 32 kHz secondary oscillator driver

• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

• Two Capture/Compare (CCP) modules:

• Master Synchronous Serial Port (MSSP) with SPI

CTM with:

and I

- 7-bit address masking

- SMBus/PMBus

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module:

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

- Auto-wake-up on start

compatibility

 2012-2014 Microchip Technology Inc. DS40001624C-page 1

PIC16(L)F1512/3

28-Pin SPDIP, SOIC, SSOP

PIC16F1512/3

PIC16LF1512/3

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RB6/ICSPCLK/ICDCLK

RB5

RB4

RB3

RB2

RB1 RB0

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RC5

RC4

RC7

RC6

RB7/ICSPDAT/ICDDAT

PIC16(L)F151X/152X Family Types

ADC

(1)

CCP

Debug

(bytes)

(2)

I/O’s

10-bit (ch)

Timers

(8/16-bit)

Advanced Control

Device

Data SRAM

Data Sheet Index

PIC16(L)F1512 (1) 2048 128 25 17 Y 2/1 1 1 2 I Y PIC16(L)F1513 (1) 4096 256 25 17 Y 2/1 1 1 2 I Y PIC16(L)F1516 (2) 8192 512 25 17 N 2/1 1 1 2 I Y PIC16(L)F1517 (2) 8192 512 36 28 N 2/1 1 1 2 I Y PIC16(L)F1518 (2) 16384 1024 25 17 N 2/1 1 1 2 I Y PIC16(L)F1519 (2) 16384 1024 36 28 N 2/1 1 1 2 I Y PIC16(L)F1526 (3) 8192 768 54 30 N 6/3 2 2 10 I Y PIC16(L)F1527 (3) 16384 1536 54 30 N 6/3 2 2 10 I Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: Future Product PIC16(L)F1512/13 Data Sheet, 28-Pin Flash, 8-bit microcontrollers. 2: DS41452 PIC16(L)F1516/7/8/9 Data Sheet, 28/40/44-Pin Flash, 8-bit MCUs. 3: DS41458 PIC16(L)F1526/27 Data Sheet, 64-Pin Flash, 8-bit MCUs.

Program Memory

Flash (words)

C™/SPI)

EUSART

MSSP (I

FIGURE 1: 28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1512/3

XLP

DS40001624C-page 2  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

2 3

RC0

RB7/ICSPDAT/ICDDAT

RB6/ICSPCLK/ICDCLK

RB5

RB4

RB3 RB2 RB1 RB0 V

VSS RC7

RC6

RC5

RC4

RE3/MCLR/VPP

RA0

RA1

RA2 RA3 RA4 RA5

RA7 RA6

RC1

RC2

RC3

13814

232822

PIC16F1512/3 PIC16LF1512/3

28-Pin UQFN

FIGURE 2: 28-PIN UQFN (4X4) PACKAGE DIAGRAM FOR PIC16(L)F1512/3

 2012-2014 Microchip Technology Inc. DS40001624C-page 3

PIC16(L)F1512/3

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1512/3)

I/O

28-Pin UQFN

28-Pin SPDIP, SOIC, SSOP

RA0 2 27 AN0 — — — SS RA1328AN1 — ——— —— — RA2 4 1 AN2 — — — — — — — RA3 5 2 AN3/V RA4 6 3 — T0CKI — — — — — — RA5 7 4 AN4 — — — SS RA6 10 7 — — — — — — — OSC2/CLKOUT RA7 9 6 — — — — — — — OSC1/CLKIN RB0 21 18 AN12 — — — — INT/IOC Y — RB1 22 19 AN10 — — — — IOC Y — RB2 23 20 AN8 — — — — IOC Y — RB3 24 21 AN9 — CCP2 RB4 25 22 AN11

RB5 26 23 AN13 T1G — — — IOC Y — RB6 27 24 ADGRDA — — — — IOC Y ICSPCLK/ICDCLK RB7 28 25 ADGRDB — — — — IOC Y ICSPDAT/ICDDAT RC0 11 8 — SOSCO/T1CKI — — — — — — RC1 12 9 — SOSCI CCP2 RC2 13 10 AN14 — CCP1 — — — — — RC3 14 11 AN15 — — — SCK/SCL — — — RC4 15 12 AN16 — — — SDI/SDA — — — RC5 16 13 AN17 — — — SDO — — — RC6 17 14 AN18 — — TX/CK — — — — RC7 18 15 AN19 — — RX/DT — — — —

RE3 1 26 — — — — — — Y MCLR VDD 20 17 — — — — — — — —

SS 8,19 5,16 — — — — — — — —

NC — — — — — — — — — —

Note 1: Peripheral pin location selected using APFCON register. Default location.

2: Peripheral pin location selected using APFCON register. Alternate location.

A/D

REF+ — ——— —— —

ADOUT

Timers

— — — — IOC Y —

CCP

(2)

(1)

EUSART

——IOCY —

—— —— —

MSSP

(2)

(1)

Interrupt

— — —

—— VCAP

Pull-up

Basic

/VPP

DS40001624C-page 4  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 11

3.0 Memory Organization................................................................................................................................................................. 13

4.0 Device Configuration.................................................................................................................................................................. 35

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 41

6.0 Resets ........................................................................................................................................................................................ 56

7.0 Interrupts .................................................................................................................................................................................... 64

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 75

9.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 79

10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 80

11.0 Flash Program Memory Control ................................................................................................................................................. 84

12.0 I/O Ports ................................................................................................................................................................................... 100

13.0 Interrupt-On-Change ................................................................................................................................................................ 115

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 119

15.0 Temperature Indicator Module ................................................................................................................................................. 121

16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 123

17.0 Timer0 Module ......................................................................................................................................................................... 157

18.0 Timer1 Module with Gate Control............................................................................................................................................. 160

19.0 Timer2 Module ......................................................................................................................................................................... 171

20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 175

21.0 Capture/Compare/PWM Modules ............................................................................................................................................ 228

22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237

23.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 266

24.0 Instruction Set Summary.......................................................................................................................................................... 268

25.0 Electrical Specifications............................................................................................................................................................ 282

26.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 310

27.0 Development Support............................................................................................................................................................... 341

28.0 Packaging Information.............................................................................................................................................................. 345

The Microchip Web Site..................................................................................................................................................................... 357

Customer Change Notification Service .............................................................................................................................................. 357

Customer Support .............................................................................................................................................................................. 357

Product Identification System ............................................................................................................................................................ 358

 2012-2014 Microchip Technology Inc. DS40001624C-page 5

PIC16(L)F1512/3

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

DS40001624C-page 6  2012-2014 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16(L)F1512/3 are described within this data sheet. They are available in 28-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1512/3 devices.

Table 1-2 shows the pinout descriptions.

Reference Ta bl e 1 -1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1512

PIC16(L)F1513

Analog-to-Digital Converter (ADC) ●● Fixed Voltage Reference (FVR) ●● Temperature Indicator ●● Capture/Compare/PWM Modules

CCP1 ●● CCP2 ●●

EUSARTs

EUSART ●●

Master Synchronous Serial Ports

MSSP ●●

Timers

Timer0 ●● Timer1 ●● Timer2 ●●

PIC16(L)F1512/3

 2012-2014 Microchip Technology Inc. DS40001624C-page 7

PIC16(L)F1512/3

PORTB

Timer2MSSP

Timer0

CCP2

ADC

10-Bit

CCP1

Note 1: See applicable chapters for more information on peripherals.

2: See Ta bl e 1 -1 for peripherals available on specific devices.

CPU

Program

Flash Memory

PORTA

RAM

Timing

Generation

INTRC

Oscillator

MCLR

(Figure 2-1)

Timer1

OSC1/CLKIN

OSC2/CLKOUT

FVR

PORTC

PORTE

Te mp .

Indicator

EUSART

FIGURE 1-1: PIC16(L)F1512/3 BLOCK DIAGRAM

DS40001624C-page 8  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/SS

RA1/AN1 RA1 TTL CMOS General purpose I/O.

RA2/AN2 RA2 TTL CMOS General purpose I/O.

RA3/AN3/V

RA4/T0CKI RA4 TTL CMOS General purpose I/O.

RA5/AN4/SS

RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.

RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.

RB0/AN12/INT RB0 TTL CMOS General purpose I/O with IOC and WPU.

RB1/AN10 RB1 TTL CMOS General purpose I/O with IOC and WPU.

RB2/AN8 RB2 TTL CMOS General purpose I/O with IOC and WPU.

RB3/AN9/CCP2

RB4/AN11/ADOUT RB4 TTL CMOS General purpose I/O with IOC and WPU.

RB5/AN13/T1G RB5 TTL CMOS General purpose I/O with IOC and WPU.

RB6/ICSPCLK/ADGRDA RB6 TTL CMOS General purpose I/O with IOC and WPU.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.

(2)

REF+ RA3 TTL CMOS General purpose I/O.

(1)

/VCAP

(2)

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

AN1 AN — A/D Channel 1 input.

AN2 AN — A/D Channel 2 input.

AN3 AN — A/D Channel 3 input.

REF+ AN — A/D Positive Voltage Reference input.

T0CKI ST — Timer0 clock input.

RA5 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

CAP Power Power Filter capacitor for Voltage Regulator (PIC16(L)F1512/3 only).

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN ST — External clock input (EC mode).

AN12 AN — A/D Channel 12 input.

INT ST — External interrupt.

AN10 AN — A/D Channel 10 input.

AN8 AN — A/D Channel 8 input.

RB3 TTL CMOS General purpose I/O with IOC and WPU.

AN9 AN — A/D Channel 9 input.

CCP2 ST CMOS Capture/Compare/PWM 2.

AN11 AN — A/D Channel 11 input.

ADOUT CMOS — A/D with CVD output.

AN13 AN — A/D Channel 13 input.

T1G ST — Timer1 Gate input.

ICSPCLK ST CMOS In-Circuit Data I/O.

ADGRDA — CMOS Guard Ring output A.

Output

Typ e

ST — Slave Select input.

OSC/4 output.

Description

C™ = Schmitt Trigger input with I2C

 2012-2014 Microchip Technology Inc. DS40001624C-page 9

PIC16(L)F1512/3

TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB7/ICSPDAT/ADGRDB RB7 TTL CMOS General purpose I/O with IOC and WPU.

ICSPDAT ST CMOS ICSP™ Data I/O.

ADGRDB — CMOS Guard Ring output B.

RC0/SOSCO/T1CKI RC0 ST CMOS General purpose I/O.

SOSCO — XTAL Secondary oscillator connection.

RC1/SOSCI/CCP2

RC2/AN14/CCP1 RC2 ST CMOS General purpose I/O.

RC3/AN15/SCK/SCL

RC4/AN16/SDI/SDA

RC5/AN17/SDO RC5 ST CMOS General purpose I/O.

RC6/AN18/TX/CK

RC7/AN19/RX/DT

RE3/MCLR

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.

2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.

(1)

/VPP RE3 ST — General purpose input with WPU.

T1CKI ST — Timer1 clock input.

RC1 ST CMOS General purpose I/O.

SOSCI — XTAL Secondary oscillator connection.

CCP2 ST CMOS Capture/Compare/PWM 2.

AN14 AN — A/D Channel 14 input.

CCP1 ST CMOS Capture/Compare/PWM 1.

RC3 ST CMOS General purpose I/O.

AN15 AN — A/D Channel 15 input.

SCK ST CMOS SPI clock.

SCL I

RC4 ST CMOS General purpose I/O.

AN16 AN — A/D Channel 16 input.

SDI ST — SPI data input.

SDA I

AN17 AN — A/D Channel 17 input.

SDO — CMOS SPI data output.

RC6 ST CMOS General purpose I/O.

AN18 AN — A/D Channel 18 input.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC7 ST CMOS General purpose I/O.

AN19 AN — A/D Channel 19 input.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

MCLR

PP HV — Programming voltage.

Output

Typ e

C™ OD I2C™ clock.

C™ OD I2C™ data input/output.

ST — Master Clear with internal pull-up.

Description

C™ = Schmitt Trigger input with I2C

DS40001624C-page 10  2012-2014 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information.

PIC16(L)F1512/3

2.2 16-Level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register and, if enabled, will cause a software Reset. See Section 3.4 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See

Section 24.0 “Instruction Set Summary” for more

details.

 2012-2014 Microchip Technology Inc. DS40001624C-page 11

PIC16(L)F1512/3

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Brown-out

Reset

VSS

Internal

Oscillator

Block

Configuration

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction Decode &

Control

Timing

Generation

VSS

Internal

Oscillator

Block

Configuration

Data Bus

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory

RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

FIGURE 2-1: CORE BLOCK DIAGRAM

DS40001624C-page 12  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for these devices. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see

Figure 3-1 and Figure 3-2).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device

PIC16F1512 PIC16LF1512

PIC16F1513 PIC16LF1513

Note 1: High-endurance Flash applies to low byte of each address in the range.

Program Memory

Space (Words)

2,048 07FFh 0780h-07FFh

4,096 0FFFh 0F80h-0FFFh

Last Program Memory

Address

High-Endurance Flash

Memory Address Range

(1)

 2012-2014 Microchip Technology Inc. DS40001624C-page 13

PIC16(L)F1512/3

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Wraps to Page 0

0800h

CALL, CALLW RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

7FFFh

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip Program Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh 1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1512 PARTS

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1513 PARTS

DS40001624C-page 14  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

constants

BRW ;Add Index in W to

;program counter to

;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX CALL constants ;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.

The High directive will set bit<7> if a label points to a location in program memory.

 2012-2014 Microchip Technology Inc. DS40001624C-page 15

PIC16(L)F1512/3

Addresses BANKx

x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR

x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper seven bits of the address define the Bank address and the lower five bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta b le 3 - 2. For detailed information, see Tab le 3 -8 .

TABLE 3-2: CORE REGISTERS

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PIC16(L)F1512/3

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 24.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in subtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

PD ZDC

(1)

bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow

second operand.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

bit

(1)

 2012-2014 Microchip Technology Inc. DS40001624C-page 17

PIC16(L)F1512/3

0Bh 0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

DS40001624C-page 18  2012-2014 Microchip Technology Inc.

3.2.5 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1512/3 are as shown in Table 3-4 through Ta b le 3 -7 .

 2012-2014 Microchip Technology Inc. DS40001624C-page 19

TABLE 3-3: PIC16(L)F1512 MEMORY MAP (BANKS 0-7)

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 -2 )

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 00Fh 010h PORTE 090h TRISE 110h 011h PIR1 091h PIE1 111h 012h PIR2 092h PIE2 112h 013h 014h 015h TMR0 095h OPTION_REG 115h 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSPCON2 296h 017h TMR1H 097h WDTCON 117h FVRCON 197h 018h T1CON 098h 019h T1GCON 099h OSCCON 119h 01Ah TMR2 09Ah OSCSTAT 11Ah 01Bh PR2 09Bh ADRES0L 11Bh 01Ch T2CON 09Ch ADRES0H 11Ch 01Dh 01Eh 01Fh 020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’. Note 1: PIC16F1512 only.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—093h—113h— 193h PMDATL 213h SSPMSK 293h CCP1CON 313h — 393h — —094h—114h— 194h PMDATH 214h SSPSTAT 294h — 314h — 394h IOCBP

— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh — — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh —29Eh—31Eh—39Eh— —09Fh—11Fh— 19Fh BAUDCON 21Fh —29Fh—31Fh—39Fh—

General Purpose Register 80 Bytes

Common RAM

080h

0A0h

General Purpose

0BFh 0C0h

Unimplemented

0F0h

Core Registers

(Ta bl e 3 -2 )

—118h—198h—218h— 298h CCPR2L 318h — 398h —

32 Bytes

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

100h

120h

170h

Core Registers

(Table 3-2)

—190h— 210h WPUE 290h — 310h — 390h — — 191h PMADRL 211h SSPBUF 291h CCPR1L 311h — 391h — — 192h PMADRH 212h SSPADD 292h CCPR1H 312h — 392h —

— 195h PMCON1 215h SSPCON1 295h — 315h — 395h IOCBN

— 199h RCREG 219h — 299h CCPR2H 319h — 399h — — 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah —39Ah— — 19Bh SPBRGL 21Bh —29Bh—31Bh—39Bh— — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

180h

1A0h

1F0h

Core Registers

(Table 3-2)

VREGCON

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

(1)

200h

Core Registers

(Table 3-2)

— 28Ch — 30Ch — 38Ch —

—28Eh—30Eh—38Eh—

217h SSPCON3 297h — 317h — 397h —

220h

Unimplemented

Read as ‘0’

270h

Common RAM

(Accesses 70h – 7Fh)

280h

2A0h

2F0h

Core Registers

(Table 3-2)

— 30Dh — 38Dh —

— 316h — 396h IOCBF

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

300h

Core Registers

(Table 3-2)

320h

Unimplemented

Read as ‘0’

36Fh 3EFh 370h

Common RAM

(Accesses 70h – 7Fh)

380h

3A0h

3F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

PIC16(L)F1512/3

DS40001624C-page 20  2012-2014 Microchip Technology Inc.

TABLE 3-4: PIC16(L)F1513 MEMORY MAP (BANKS 0-7)

PIC16(L)F1512/3

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 -2 )

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’. Note 1: PIC16F1513 only.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

—093h—113h— 193h PMDATL 213h SSPMSK 293h CCP1CON 313h — 393h — —094h—114h— 194h PMDATH 214h SSPSTAT 294h — 314h — 394h IOCBP

General Purpose Register 80 Bytes

Common RAM

(Accesses

70h – 7Fh)

080h

0A0h

0F0h

Core Registers

(Ta bl e 3 -2 )

—118h—198h—218h— 298h CCPR2L 318h — 398h —

General Purpose Register 80 Bytes

Common RAM

(Accesses

70h – 7Fh)

100h

120h

170h

Core Registers

(Table 3-2)

—190h— 210h WPUE 290h — 310h — 390h — — 191h PMADRL 211h SSPBUF 291h CCPR1L 311h — 391h — — 192h PMADRH 212h SSPADD 292h CCPR1H 312h — 392h —

— 195h PMCON1 215h SSPCON1 295h — 315h — 395h IOCBN

— 199h RCREG 219h — 299h CCPR2H 319h — 399h — — 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah —39Ah— — 19Bh SPBRG 21Bh —29Bh—31Bh—39Bh— — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —

General Purpose Register 80 Bytes

Common RAM

(Accesses 70h – 7Fh)

180h

1A0h

1F0h

Core Registers

(Table 3-2)

VREGCON

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

(1)

200h

Core Registers

(Table 3-2)

— 28Ch — 30Ch — 38Ch —

—28Eh—30Eh—38Eh—

217h SSPCON3 297h — 317h — 397h —

220h

Unimplemented

Read as ‘0’

270h

Common RAM

(Accesses 70h – 7Fh)

280h

2A0h

2F0h

Core Registers

(Table 3-2)

— 30Dh — 38Dh —

— 316h — 396h IOCBF

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

300h

Core Registers

(Table 3-2)

320h

Unimplemented

Read as ‘0’

36Fh 3EFh 370h

Common RAM

(Accesses 70h – 7Fh)

380h

3A0h

3F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses 70h – 7Fh)

 2012-2014 Microchip Technology Inc. DS40001624C-page 21

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

40Bh

Core Registers

(Ta bl e 3 -2 )

480h

48Bh

Core Registers

(Ta bl e 3 -2 )

500h

50Bh

Core Registers

(Ta bl e 3 -2 )

580h

58Bh

Core Registers

(Ta bl e 3 -2 )

600h

60Bh

Core Registers

(Ta bl e 3 -2 )

680h

68Bh

Core Registers

(Ta bl e 3 -2 )

700h

70Bh

Core Registers

(Ta bl e 3 -2 )

780h

78Bh

Core Registers

(Ta bl e 3 -2 )

40Ch

Unimplemented

Read as ‘0’

48Ch

Unimplemented

Read as ‘0’

50Ch

Unimplemented

Read as ‘0’

58Ch

Unimplemented

Read as ‘0’

60Ch

Unimplemented

Read as ‘0’

68Ch

Unimplemented

Read as ‘0’

70Ch

See Ta bl e 3 -6

78Ch

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h

Common RAM

(Accesses

70h – 7Fh)

4F0h

Common RAM

(Accesses 70h – 7Fh)

570h

Common RAM

(Accesses 70h – 7Fh)

5F0h

Common RAM

(Accesses 70h – 7Fh)

670h

Common RAM

(Accesses 70h – 7Fh)

6F0h

Common RAM

(Accesses 70h – 7Fh)

770h

Common RAM

(Accesses 70h – 7Fh)

7F0h

Common RAM

(Accesses 70h – 7Fh)

47Fh

4FFh 57Fh

5FFh 67Fh 6FFh 77Fh 7FFh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

80Bh

Core Registers

(Ta bl e 3 -2 )

880h

88Bh

Core Registers

(Ta bl e 3 -2 )

900h

90Bh

Core Registers

(Ta bl e 3 -2 )

980h

98Bh

Core Registers

(Ta bl e 3 -2 )

A00h

A0Bh

Core Registers

(Ta bl e 3 -2 )

A80h

A8Bh

Core Registers

(Ta bl e 3 -2 )

B00h

B0Bh

Core Registers

(Ta bl e 3 -2 )

B80h

B8Bh

Core Registers

(Ta bl e 3 -2 )

80Ch

Unimplemented

Read as ‘0’

88Ch

Unimplemented

Read as ‘0’

90Ch

Unimplemented

Read as ‘0’

98Ch

Unimplemented

Read as ‘0’

A0Ch

Unimplemented

Read as ‘0’

A8Ch

Unimplemented

Read as ‘0’

B0Ch

Unimplemented

Read as ‘0’

B8Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh

9EFh

A6Fh

AEFh

B6Fh

BEFh

870h

Common RAM

(Accesses

70h – 7Fh)

8F0h

Common RAM

(Accesses 70h – 7Fh)

970h

Common RAM

(Accesses 70h – 7Fh)

9F0h

Common RAM

(Accesses 70h – 7Fh)

A70h

Common RAM

(Accesses 70h – 7Fh)

AF0h

Common RAM

(Accesses 70h – 7Fh)

B70h

Common RAM

(Accesses 70h – 7Fh)

BF0h

Common RAM

(Accesses 70h – 7Fh)

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3 -2 )

C80h

C8Bh

Core Registers

(Ta bl e 3 -2 )

D00h

D0Bh

Core Registers

(Ta bl e 3 -2 )

D80h

D8Bh

Core Registers

(Ta bl e 3 -2 )

E00h

E0Bh

Core Registers

(Ta bl e 3 -2 )

E80h

E8Bh

Core Registers

(Ta bl e 3 -2 )

F00h

F0Bh

Core Registers

(Ta bl e 3 -2 )

F80h

F8Bh

Core Registers

(Ta bl e 3 -2 )

C0Ch

C6Fh

Unimplemented

Read as ‘0’

C8Ch

CEFh

Unimplemented

Read as ‘0’

D0Ch

D6Fh

Unimplemented

Read as ‘0’

D8Ch

DEFh

Unimplemented

Read as ‘0’

E0Ch

E6Fh

Unimplemented

Read as ‘0’

E8Ch

EEFh

Unimplemented

Read as ‘0’

F0Ch

F6Fh

Unimplemented

Read as ‘0’

F8Ch

FEFh

See (Ta bl e 3 -7 )

C70h

Common RAM

(Accesses

70h – 7Fh)

CF0h

Common RAM

(Accesses 70h – 7Fh)

D70h

Common RAM

(Accesses 70h – 7Fh)

DF0h

Common RAM

(Accesses 70h – 7Fh)

E70h

Common RAM

(Accesses 70h – 7Fh)

EF0h

Common RAM

(Accesses 70h – 7Fh)

F70h

Common RAM

(Accesses 70h – 7Fh)

FE0h

Common RAM

(Accesses 70h – 7Fh)

C7Fh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FEFh

TABLE 3-5: PIC16(L)F1512/3 MEMORY MAP (BANKS 8-30)

PIC16(L)F1512/3

Bank 14

700h

70Bh

Core Registers

(Table 3-2)

70Ch

710h

Unimplemented

Read as ‘0’

711h

AADCON0

712h

AADCON1

713h

AADCON2

714h

AADCON3

715h

AADSTAT

716h

AADPRE

717h

AADACQ

718h

AADGRD

719h

AADCAP

71Ah

AADRES0L

71Bh

AADRES0H

71Ch

AADRES1L

71Dh

AADRES1H

71Eh

—

71Fh

—

720h

76Fh

Unimplemented

Read as ‘0’

770h

Common RAM

(Accesses 70h – 7Fh)

77Fh

Bank 31

F80h

F8Bh

Core Registers

(Table 3-2)

F8Ch

FE3h

Unimplemented

Read as ‘0’

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

FF0h

Common RAM

(Accesses 70h – 7Fh)

FFFh

TABLE 3-6: PIC16(L)F1512/3 MEMORY

MAP (BANK 14)

TABLE 3-7: PIC16(L)F1512/3 MEMORY

MAP (BANK 31)

Legend: = Unimplemented data memory locations,

DS40001624C-page 22  2012-2014 Microchip Technology Inc.

read as ‘0’.

PIC16(L)F1512/3

3.2.6 CORE FUNCTION REGISTERS SUMMARY

The Core Function Registers listed in Tab l e 3 -8 can be addressed from any Bank.

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

Value on all

other Resets

 2012-2014 Microchip Technology Inc. DS40001624C-page 23

PIC16(L)F1512/3

3.2.7 SPECIAL FUNCTION REGISTERS SUMMARY

The Special Function Registers are listed in Tab le 3 - 9.

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue o n

POR, BOR

Bank 0

00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu

00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

00Fh

— Unimplemented — —

010h PORTE

011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 OSFIF

013h

— Unimplemented — —

014h

— Unimplemented — —

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000

01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111

01Ch T2CON

01Dh

— Unimplemented — —

01Eh

— Unimplemented — —

01Fh

— Unimplemented — —

— — — —RE3— — — ---- x--- ---- u---

— — —BCLIF— — CCP2IF 0--- 0--0 0--- 0--0

—TMR1ON0000 00-0 uuuu uu-u

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

DONE

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

Bank 1

08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111

08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111

08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111

08Fh

— Unimplemented — —

090h TRISE

091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE

093h

— Unimplemented — —

094h

— Unimplemented — —

095h

OPTION_REG

096h PCON STKOVF STKUNF

097h WDTCON

098h

— Unimplemented — —

099h OSCCON

09Ah OSCSTAT SOSCR

09Bh ADRES0L

09Ch ADRES0H

09Dh ADCON0

09Eh ADCON1

09Fh

— Unimplemented — —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: PIC16F1512/3 only.

(3)

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.

— — — — —

— — —BCLIE— — CCP2IE 0--- 0--0 0--- 0--0

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111

—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu

— — WDTPS<4:0> SWDTEN --01 0110 --01 0110

—

—OSTSHFIOFR— — LFIOFR HFIOFS 0-q0 --00 q-qq --0q

A/D Result Register Low xxxx xxxx uuuu uuuu

A/D Result Register High xxxx xxxx uuuu uuuu

—CHS<4:0>

ADFM ADCS<2:0> — —

IRCF<3:0>

(2)

— — — ---- 1--- ---- 1---

—SCS<1:0>-011 1-00 -011 1-00

GO/DONE

ADON -000 0000 -000 0000

ADPREF<1:0>

0000 --00 0000 --00

Value on all

other

Resets

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PIC16(L)F1512/3

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue o n

POR, BOR

Bank 2

10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu

10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu

10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu

10Fh

— Unimplemented — —

115 h

116h BORCON SBOREN BORFS

117h FVRCON FVREN FVRRDY TSEN TSRNG

118 h

— Unimplemented — —

11C h

11Dh APFCON

11Eh

— Unimplemented — —

11Fh

— Unimplemented — —

— — — — — — SSSEL CCP2SEL ---- --00 ---- --00

— — — — — BORRDY 10-- ---q uu-- ---u

— —ADFVR<1:0>0q00 --00 0q00 --00

Bank 3

18Ch ANSELA — —ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --1- 1111

18Dh ANSELB

18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2

18Fh

— Unimplemented — —

190h

— Unimplemented — —

191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000

192h PMADRH

193h PMDATL Program Memory Data Register Low Byte xxxx xxxx uuuu uuuu

194h PMDATH

195h PMCON1

196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000

197h VREGCON

198h

— Unimplemented — —

199h RCREG USART Receive Data Register 0000 0000 0000 0000

19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000

19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000

19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: PIC16F1512/3 only.

2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.

(1)

Shaded locations are unimplemented, read as ‘0’.

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

— — 1111 1100 1111 1100

— Program Memory Address Register High Byte 1000 0000 1000 0000

— — Program Memory Data Register High Byte --xx xxxx --uu uuuu

(2)

—

— — — — — — VREGPM Reserved ---- --01 ---- --01

CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000

— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

Value on all

other

Resets

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PIC16(L)F1512/3

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue o n

POR, BOR

Bank 4

20Ch — Unimplemented — —

20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

20Eh

— Unimplemented — —

20Fh

— Unimplemented — —

210h WPUE

211h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

212h SSPADD Synchronous Serial Port (I

213h SSPMSK Synchronous Serial Port (I

214h SSPSTAT SMP CKE D/A

215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

— Unimplemented — —

21Fh

— — — — WPUE3 — — — ---- 1--- ---- 1---

C™ mode) Address Register 0000 0000 0000 0000

C™ mode) Address Mask Register 1111 1111 1111 1111

PSR/WUA BF 0000 0000 0000 0000

Bank 5

28Ch

— Unimplemented — —

290h

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

293h CCP1CON

294h

— Unimplemented — —

297h

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

29Ah CCP2CON

29Bh

— Unimplemented — —

29Fh

— — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000

— — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000

Bank 6

30Ch

— Unimplemented — —

31Fh

Bank 7

38Ch

— Unimplemented — —

393h

394h IOCBP IOCBP<7:0> 0000 0000 0000 0000

395h IOCBN IOCBN<7:0> 0000 0000 0000 0000

396h IOCBF IOCBF<7:0> 0000 0000 0000 0000

397h

— Unimplemented — —

39Fh

Bank 8-13

x0Ch

x8Ch

— Unimplemented — —

x1Fh

x9Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: PIC16F1512/3 only.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.

Value on all

other

Resets

DS40001624C-page 26  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue o n

POR, BOR

Bank 14

70ch

— Unimplemented — —

710h

711h AADCON0

712h AADCON1

713h AADCON2

714h AADCON3 ADEPPOL ADIPPOL ADOLEN ADOEN ADOOEN

715h AADSTAT

716h AADPRE

717h AADACQ

718h AADGRD GRDBOE GRDAOE GRDPOL

719h AADCAP

71Ah AADRES0L

71Bh AADRES0H

71Ch AADRES1L A/D Result 1 Register Low xxxx xxxx uuuu uuuu

71Dh AADRES1H A/D Result 1 Register High xxxx xxxx uuuu uuuu

71Eh

— Unimplemented — —

(3)

—CHS<4:0>

ADFM ADCS<2:0> — —

—TRIGSEL<2:0>— — — — -000 ---- -000 ----

— — — — — ADCONV ADSTG<1:0> ---- -000 ---- -000

— ADPRE<6:0> -000 0000 -000 0000

— ADACQ<6:0> -000 0000 -000 0000

— — — — — 000- ---- 000- ----

— — — — — ADDCAP<2:0> ---- -000 ---- -000

A/D Result 0 Register Low xxxx xxxx uuuu uuuu

A/D Result 0 Register High xxxx xxxx uuuu uuuu

GO/DONE

— ADIPEN ADDSEN 0000 0-00 0000 0-00

ADON -000 0000 -000 0000

ADPREF<1:0>

0000 --00 0000 --00

Bank 15-30

x0Ch

x8Ch

— Unimplemented — —

x1Fh

x9Fh

Bank 31

F8Ch

— Unimplemented — —

FE3h

FE4h STATUS_SHAD

FE5h WREG_SHAD Working Register Shadow xxxx xxxx uuuu uuuu

FE6h BSR_SHAD

FE7h PCLATH_SHAD

FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu

FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu

FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu

FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu

FECh

— Unimplemented — —

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: PIC16F1512/3 only.

Shaded locations are unimplemented, read as ‘0’.

2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.

— — — — —ZDCC---- -xxx ---- -uuu

— — — Bank Select Register Shadow ---x xxxx ---u uuuu

— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu

— — — Current Stack Pointer ---1 1111 ---1 1111

Top of Stack Low Byte xxxx xxxx uuuu uuuu

— Top of Stack High Byte -xxx xxxx -uuu uuuu

Value on all

other

Resets

 2012-2014 Microchip Technology Inc. DS40001624C-page 27

PIC16(L)F1512/3

PCLPCH

ALU Result

PCLATH

PCLPCH

OPCODE <10:0>

PCLATH

PCLPCH

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH

PC + W

BRW

PCLPCH

PC + OPCODE <8:0>

BRA

3.3 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN

DIFFERENT SITUATIONS

3.3.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.

3.3.4 BRANCHING

The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction.

3.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the PC to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the PC will change to the values contained in the PCLATH register and those being written to the PCL register.

3.3.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the PC (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556).

DS40001624C-page 28  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled (STVREN = 0)

Stack Reset Enabled (STVREN = 1)

TOSH:TOSL

3.4 Stack

All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the

CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to

an interrupt address.

3.4.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement STKPTR.

Reference Figure 3-5 through 3-8 for examples of accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

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PIC16(L)F1512/3

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00

STKPTR = 0x00

This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack.

TOSH:TOSL

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

DS40001624C-page 30  2012-2014 Microchip Technology Inc.

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten.

Return Address

TOSH:TOSL

PIC16(L)F1512/3

3.4.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register.

3.5 Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

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PIC16(L)F1512/3

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000

Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

FIGURE 3-9: INDIRECT ADDRESSING

DS40001624C-page 32  2012-2014 Microchip Technology Inc.

3.5.1 TRADITIONAL DATA MEMORY

Indirect AddressingDirect Addressing

Bank Select

Location Select

4BSR 6

From Opcode

FSRxL70

Bank Select

Location Select

00000 00001 00010 11111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

FSRxH70

0000

The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

PIC16(L)F1512/3

 2012-2014 Microchip Technology Inc. DS40001624C-page 33

PIC16(L)F1512/3

Location Select

0x2000

FSRnH

FSRnL

0x020

Bank 0

0x06F 0x0A0

Bank 1 0x0EF 0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

Location Select

0x8000

FSRnH

FSRnL

0x0000

0x7FFF

0xFFFF

Program Flash Memory (low 8 bits)

3.5.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

3.5.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH

MEMORY MAP

DS40001624C-page 34  2012-2014 Microchip Technology Inc.

4.0 DEVICE CONFIGURATION

Device Configuration consists of Configuration Words, Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Word 2 is

managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

PIC16(L)F1512/3

 2012-2014 Microchip Technology Inc. DS40001624C-page 35

PIC16(L)F1512/3

REGISTER 4-1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1

FCMEN IESO CLKOUTEN

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

bit 12 IESO: Internal External Switchover bit

bit 11 CLKOUTEN

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

bit 8 Unimplemented: Read as ‘1’ bit 7 CP: Code Protection bit

bit 6 MCLRE: MCLR/VPP Pin Function Select bit

bit 5 PWRTE

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled

1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled

: Clock Out Enable bit

FOSC Configuration bits are set to LP, XT, HS modes:

This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.

All other

11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled

1 = Program memory code protection is disabled 0 = Program memory code protection is enabled

If LVP bit =

1 = PWRT disabled 0 = PWRT enabled

11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled

FOSC modes:

1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin

This bit is ignored.

0: 1 =MCLR 0 =MCLR

/VPP pin function is MCLR; Weak pull-up enabled. /VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

: Power-up Timer Enable bit

BOREN<1:0> —

DS40001624C-page 36  2012-2014 Microchip Technology Inc.

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

PIC16(L)F1512/3

 2012-2014 Microchip Technology Inc. DS40001624C-page 37

PIC16(L)F1512/3

REGISTER 4-2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1

LVP DEBUG

bit 13 bit 8

U-1 U-1 U-1 R/P-1 U-1 U-1 R/P-1 R/P-1

— — — VCAPEN

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit

1 = Low-voltage programming enabled 0 = High-voltage on MCLR

bit 12 DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11 LPBOR: Low-Power BOR bit

1 = Low-Power BOR is disabled 0 = Low-Power BOR is enabled

bit 10 BORV: Brown-out Reset Voltage Selection bit

1 = Brown-out Reset voltage (VBOR), low trip point selected 0 = Brown-out Reset voltage (V

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset

bit 8-5 Unimplemented: Read as ‘1’ bit 4 VCAPEN

If PIC16LF1512/3 (regulator disabled):

bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

2 kW Flash memory (PIC16(L)F1512 only)

4 kW Flash memory (PIC16(L)F1513 only)

: Voltage Regulator Capacitor Enable bits

These bits are ignored. All V

PIC16F1512/3 (regulator enabled):

CAP functionality is enabled on RA5

0 =V 1 =All V

11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control 00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON control

11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control

CAP pin functions are disabled

must be used for programming

BOR), high trip point selected

CAP pin functions are disabled.

LPBOR BORV STVREN —

(1)

— —WRT<1:0>

(2)

(1)

Note 1: PIC16F1512/3 only.

2: See VBOR parameter for specific trip point voltages.

DS40001624C-page 38  2012-2014 Microchip Technology Inc.

4.2 Code Protection

Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting.

4.2.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP Words. When CP program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.3 “Write

Protection” for more information.

= 0, external reads and writes of

bit in Configuration

4.3 Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected.

PIC16(L)F1512/3

4.4 User ID

Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these

memory locations. calculation, see the “PIC16(L)F151X/152X Memory

Programming Specification” (DS41442).

For more information on checksum

 2012-2014 Microchip Technology Inc. DS40001624C-page 39

PIC16(L)F1512/3

Device

DEVICEID<13:0> Values

DEV<8:0> REV<4:0>

PIC16F1512 01 0111 000 x xxxx

PIC16F1513 01 0110 010 x xxxx

PIC16LF1512 01 0111 001 x xxxx

PIC16LF1513 01 0111 010 x xxxx

4.5 Device ID and Revision ID

The memory location 8006h is where the Device ID and

Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.

Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See

Section 11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations.

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

RRRRRR

DEV<8:3>

bit 13 bit 8

RRRRRRRR

DEV<2:0> REV<4:0>

bit 7 bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘1’

-n/n = Value at POR and BOR/Value at all other Resets

P = Programmable bit

bit 13-5 DEV<8:0>: Device ID bits

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

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PIC16(L)F1512/3

5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

5.1 Overview

The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption.

Figure 5-1 illustrates a block diagram of the oscillator

module.

Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

• Fast start-up oscillator allows internal circuits to

power up and stabilize before switching to the 16 MHz HFINTOSC

The oscillator module can be configured in one of eight clock modes.

1. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode (0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode (4 MHz to 20 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 16 MHz).

Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered.

The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency.

The INTOSC internal oscillator block produces a low and high frequency clock source, designated LFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these two clock sources.

 2012-2014 Microchip Technology Inc. DS40001624C-page 41

PIC16(L)F1512/3

OSC2

OSC1

Primary

Oscillator

(OSC)

SOSCO/

T1CKI

SOSCI

Secondary

Oscillator

(SOSC)

16 MHz

Primary Osc

Start-Up Osc

LF-INTOSC (31.25 kHz)

INTOSC

Divide Circuit

IRCF<3:0>

INTOSC

Primary Clock

Secondary Clock

Clock Switch MUX

Low-Power Mode

Event Switch

(SCS<1:0>)

Secondary Oscillator

Primary Oscillator

Internal Oscillator

HF-16 MHz

HF-4 MHz HF-2 MHz HF-1 MHz

HF-500 kHz

HF-250 kHz

HF-125 kHz

HF-62.5 kHz

HF-31.25 kH z

LF-31 kHz

HF-8 MHz

Internal Oscillator Mux

1111

1110

1101

1100

1011

1010/ 0111

1001/ 0110

1000/ 0101

0100

0011 0010

0001 0000

/1 /2 /4 /8

/16

/32

/64

/128

/256

/512

Start-up Control

Logic

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS40001624C-page 42  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

OSC1/CLKIN

OSC2/CLKOUT

Clock from Ext. System

PIC

MCU

FOSC/4 or

I/O

(1)

Note 1: Output depends upon the CLKOUTEN bit of

the Configuration Words.

5.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.

Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 MHz High-Frequency Internal Oscillator and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3

“Clock Switching” for additional information.

5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to:

- Secondary oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “Clock Switching”for more informa- tion.

5.2.1.1 EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode.

EC mode has three power modes to select from through Configuration Words:

• High power, 4-20 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low power, 0-0.5 MHz (FOSC = 101)

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC

MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

5.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

 2012-2014 Microchip Technology Inc. DS40001624C-page 43

PIC16(L)F1512/3

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Quartz

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

Ceramic

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

(3)

Resonator

OSC2/CLKOUT

FIGURE 5-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC Devices” (DS00826)

• AN849, “Basic PIC (DS00849)

• AN943, “Practical PIC Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

and PIC®

Oscillator Design”

Oscillator

FIGURE 5-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

5.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended unless either FSCM or Two-Speed Start-up are enabled, in which case code will continue to execute while the OST is counting. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module.

In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4

“Two-Speed Clock Start-up Mode”).

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PIC16(L)F1512/3

32.768 kHz

SOSCI

To Internal Logic

PIC® MCU

Crystal

SOSCO

Quartz

OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  R

EXT  100 k, 3-5V

EXT > 20 pF, 2-5V

Note 1: Output depends upon the CLKOUTEN bit of

the Configuration Words.

I/O

(1)

5.2.1.4 Secondary Oscillator

The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.

The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3

“Clock Switching” for more information.

FIGURE 5-5: QUARTZ CRYSTAL

OPERATION (SECONDARY OSCILLATOR)

5.2.1.5 External RC Mode

The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required.

The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

bit in Configuration Words.

Figure 5-6 shows the external RC mode connections.

FIGURE 5-6: EXTERNAL RC MODES

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC Devices” (DS00826)

• AN849, “Basic PIC (DS00849)

 2012-2014 Microchip Technology Inc. DS40001624C-page 45

• AN943, “Practical PIC Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for Low-Power External Oscillators”

(DS01288)

and PIC®

Oscillator Design”

Oscillator

The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due to tolerance of the external RC components used.

PIC16(L)F1512/3

5.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3

“Clock Switching”for more information.

In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

The internal oscillator block has two independent oscillators that provides the internal system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at 16 MHz.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at 31 kHz.

bit in Configuration Words.

5.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source.

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The frequency derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See

Section 5.2.2.4 “Internal Oscillator Clock Switch Timing” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’.

A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running.

The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.

5.2.2.2 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.4 “Internal Oscillator

Clock Switch Timing” for more information. The

LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.

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5.2.2.3 Internal Oscillator Frequency Selection

The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software:

•HFINTOSC

-16 MHz

-8 MHz

-4 MHz

-2 MHz

-1 MHz

- 500 kHz (default after Reset)

- 250 kHz

- 125 kHz

- 62.5 kHz

- 31.25 kHz

•LFINTOSC

•31 kHz

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.

5.2.2.4 Internal Oscillator Clock Switch Timing

When switching between the HFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1.

Start-up delay specifications are located in the oscillator tables of Section 25.0 “Electrical

Specifications”

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HFINTOSC

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC

LFINTOSC

IRCF <3:0>

System Clock

0 0

Start-up Time

2-cycle Sync Running

HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC

IRCF <3:0>

System Clock

= 0  0

Start-up Time 2-cycle Sync

Running

LFINTOSC HFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING

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5.3 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits:

• Default system oscillator determined by FOSC bits in Configuration Words

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

5.3.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator.

• When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source.

5.3.3 SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.

The secondary oscillator is enabled using the T1OSCEN control bit in the T1CON register. See

Section 18.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

5.3.4 SECONDARY OSCILLATOR READY

(SOSCR) BIT

The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator.

When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1.

5.3.2 OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator.

 2012-2014 Microchip Technology Inc. DS40001624C-page 49

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5.4 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.

If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short.

5.4.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO (of the Configuration Words) = 1;

Internal/External Switchover bit (Two-Speed Start-up mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

Note: If FSCM is enabled, Two-Speed Start-up

will automatically be enabled.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.

TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Oscillator Delay

LFINTOSC 1 cycle of each clock source HFINTOSC 2 s (approx.)

Any clock source

ECH, ECM, ECL, EXTRC 2 cycles

LP, XT, HS 1024 Clock Cycles (OST)

Secondary Oscillator 1024 Secondary Oscillator Cycles

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PIC16(L)F1512/3

0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N

5.4.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 5-8: TWO-SPEED START-UP

5.4.3 CHECKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator.

 2012-2014 Microchip Technology Inc. DS40001624C-page 51

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External

LFINTOSC

÷ 64

31 kHz

(~32 s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

5.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator).

FIGURE 5-9: FSCM BLOCK DIAGRAM

5.5.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.

5.5.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.

5.5.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed.

5.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation.

The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.

DS40001624C-page 52  2012-2014 Microchip Technology Inc.

FIGURE 5-10: FSCM TIMING DIAGRAM

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te st

Test Test

Clock Monitor Output

PIC16(L)F1512/3

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5.6 Oscillator Control Registers

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0

(1)

IRCF<3:0>

—

bit 7 bit 0

Legend:

bit 7 Unimplemented: Read as ‘0’ bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 =16MHz 1110 =8MHz 1101 =4MHz 1100 =2MHz 1011 =1MHz 1010 = 500 kHz 1001 = 250 kHz 1000 = 125 kHz 0111 = 500 kHz (default upon Reset) 0110 = 250 kHz 0101 = 125 kHz 0100 = 62.5 kHz 001x = 31.25 kHz 000x =31kHz LF

bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words.

SCS<1:0>

Note 1: Duplicate frequency derived from HFINTOSC.

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REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/0 R-0/q

SOSCR

—

OSTS HFIOFR

— —

bit 7 bit 0

Legend:

bit 7 SOSCR: Secondary Oscillator Ready bit

If T1OSCEN =

1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready

If T1OSCEN = 0:

1 = Timer1 clock source is always ready bit 6 Unimplemented: Read as ‘0’ bit 5 OSTS: Oscillator Start-up Timer Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words

0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready

0 = HFINTOSC is not ready

bit 3-2 Unimplemented: Read as ‘0’ bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready

0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC 16 MHz oscillator is stable and is driving the INTOSC

0 = HFINTOSC 16 MHz is not stable, the start-up oscillator is driving INTOSC

LFIOFR HFIOFS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

OSCSTAT SOSCR

PIE2 OSFIE

PIR2

T1CON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

— IRCF<3:0> —SCS<1:0>54

— OSTS HFIOFR — — LFIOFR HFIOFS 55

— — — BCLIE — — CCP2IE 71

OSFIF

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON

— — —

BCLIF — — CCP2IF

168

TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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13:8

7:0

—

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

FCMEN IESO CLKOUTEN BOREN<1:0>

—

PIC16(L)F1512/3

Note 1: See Table 6-1 for BOR active conditions.

Device

Reset

Power-on

Reset

WDT

Time-out

Brown-out

Reset

LPBOR

Reset

RESET Instruction

MCLRE

Sleep

BOR

Active

(1)

PWRT

Done

PWRTE

LFINTOSC

VDD

Exit

Stack

Pointer

6.0 RESETS

A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1.

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

•MCLR Reset

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To a l lo w VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.

FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

ICSP™ Programming Mode

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6.1 Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising V performance may require greater than minimum V The PWRT, BOR or MCLR extend the start-up period until all device operation conditions have been met.

6.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the V rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 6-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

DD, fast operating speeds or analog

DD.

features can be used to

DD to

11 X X Active Waits for BOR ready

6.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 6 -1 for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words.

DD noise rejection filter prevents the BOR from

A V triggering on small events. If V a duration greater than parameter T will reset. See Figure 6-2 for more information.

Instruction Execution upon:

Release of POR or Wake-up from Sleep

DD falls below VBOR for

BORDC, the device

(1)

(BORRDY = 1)

10 X

00 X XDisabled

Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits.

1 X Active Waits for BOR ready

0 XDisabled

6.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and V is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

6.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and V

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

DD is higher than the BOR threshold.

Awake Active

Sleep Disabled

6.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the

SBOREN bit of the BORCON register. The device startup is not delayed by the BOR ready condition or the

DD level.

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

Waits for BOR ready (BORRDY = 1)

(1)

(BORRDY = 1)

Begins immediately (BORRDY = x)

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TPWRT

(1)

VBOR

Internal

Reset

VBOR

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

FIGURE 6-2: BROWN-OUT SITUATIONS

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN BORFS

bit 7 bit 0

Legend:

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Words =

1 =BOR Enabled 0 =BOR Disabled

bit 6 BORFS: Brown-out Reset Fast Start bit

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect.

If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off

bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

— — — — — BORRDY

 01:

01:

(1)

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6.3 Low-Power Brown-out Reset (LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to

Figure 6-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2.

DD pin.

6.3.1 ENABLING LPBOR

The LPBOR is controlled by the LPBOREN bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled.

6.3.1.1 LPBOR Module Output

The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is to be OR’d together with the Reset signal of the BOR module to provide the generic B to the PCON register and to the power control block.

OR signal which goes

6.4 MCLR

The MCLR is an optional external input that can reset the device. The MCLR MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Register 4-2).

TABLE 6-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled 10Enabled x1Enabled

6.4.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR V

DD through an internal weak pull-up.

The device has a noise filter in the MCLR The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR

6.4.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.5 “PORTE Registers” for more information.

function is controlled by the

pin is connected to

Reset path.

pin low.

6.5 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO changed to indicate the WDT Reset. See Section 10.0 “Watchdog Timer (WDT)” for more information.

and PD bits in the STATUS register are

6.6 RESET Instruction

A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Ta b le 6 -4 for default conditions after a RESET instruction has occurred.

6.7 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 3.4.2 “Overflow/Underflow

Reset” for more information.

6.8 Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

6.9 Power-Up Timer

The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running.

The Power-up Timer is controlled by the PWRTE Configuration Words.

bit of

6.10 Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if required for oscillator source).

3. MCLR

The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for more information.

The Power-up Timer and oscillator start-up timer run independently of MCLR enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR will begin execution immediately (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel.

must be released (if enabled).

Reset. If MCLR is kept low long

high, the device

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TOST

TMCLR

TPWRT

VDD

Internal POR

Power-Up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-Up Timer

Oscillator

OSC

Internal Oscillator

Oscillator

OSC

External Clock (EC)

CLKIN

OSC

External Crystal

FIGURE 6-3: RESET START-UP SEQUENCE

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6.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Ta b le 6 - 3 and Tab le 6 - 4 show the Reset conditions of these registers.

TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition

0 0 1 1 10 x11Power-on Reset

0 0 1 1 10 x0xIllegal, TO

0 0 1 1 10 xx0Illegal, PD is set on POR

0 0 u 1 1u 011Brown-out Reset

u u 0 u uu u0uWDT Reset

u u u u uu u00WDT Wake-up from Sleep

u u u u uu u10Interrupt Wake-up from Sleep

u u u 0 uu uuuMCLR

u u u 0 uu u10MCLR

u u u u 0 u u u u RESET Instruction Executed

1 u u u uu uuuStack Overflow Reset (STVREN = 1)

u 1 u u uu uuuStack Underflow Reset (STVREN = 1)

is set on POR

Reset during normal operation

Reset during Sleep

(1)

(2)

STATUS

---1 0uuu uu-u uuuu

PCON

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-1 110x

MCLR

Reset during normal operation 0000h ---u uuuu uu-u 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-u 0uuu

WDT Reset 0000h ---0 uuuu uu-0 uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu

Brown-out Reset 0000h ---1 1uuu 00-1 11u0

Interrupt Wake-up from Sleep PC + 1

RESET Instruction Executed 0000h ---u uuuu uu-u u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program Counter

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6.12 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (PO

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI

•MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in Register 6-2.

REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF —

bit 7 bit 0

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

)

WDT RMCLR RI POR BOR

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware

bit 5 bit 4 RWDT: Watchdog Timer Reset Flag bit

bit 3 RMCLR

bit 2 RI: RESET Instruction Flag bit

bit 1 POR

bit 0 BOR

Unimplemented: Read as ‘0’

1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware)

: MCLR Reset Flag bit

1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR

1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware)

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

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TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BORCON SBOREN BORFS

PCON STKOVF STKUNF

STATUS

WDTCON

Legend: — = unimplemented, reads as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

— — —TOPD Z DC C

— — WDTPS<4:0> SWDTEN 82

— — — — — BORRDY 58

—

WDT

RMCLR RI POR BOR 62

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TMR0IF TMR0IE

INTF INTE

IOCIF IOCIE

Interrupt to CPU

Wake-up (If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7>

PIEn<7>

PEIE

Peripheral Interrupts

(TMR1IE) PIE1<0>

7.0 INTERRUPTS

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.

This chapter contains the following information for Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 7-1.

FIGURE 7-1: INTERRUPT LOGIC

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7.1 Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt event(s)

• PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register)

The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the stack

• Critical registers are automatically saved to the shadow registers (See Section 7.5 “Automatic

Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

7.2 Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

PC 0004h 0005h

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC )

Interrupt Sam pled during Q1

Inst(PC)

PC-1 PC+1

NOP

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(0005h)

Execute

PIC16(L)F1512/3

FIGURE 7-2: INTERRUPT LATENCY

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FIGURE 7-3: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

Instruction Fetched

Instruction Executed

Interrupt Latency

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 T

CY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

PIC16(L)F1512/3

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7.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 8.0 “Power-

Down Mode (Sleep)” for more details.

7.4 INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.

7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.

and PD)

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7.6 Interrupt Control Registers

7.6.1 INTCON REGISTER

The INTCON register is a readable and writable register that contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

bit 7 bit 0

Legend:

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt 0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit

1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed 0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state

(1)

Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register

have been cleared by software.

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7.6.2 PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as shown in Register 7-2.

REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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7.6.3 PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as shown in Register 7-3.

REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0

OSFIE — — —BCLIE — — CCP2IE

bit 7 bit 0

Legend:

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt

bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP bus collision interrupt 0 = Disables the MSSP bus collision interrupt

bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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7.6.4 PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as shown in Register 7-4.

REGISTER 7-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

Note: Interrupt flag bits are set when an interrupt

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2 CCP1IF: CCP1 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

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7.6.5 PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as shown in Register 7-5.

REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0

OSFIF — — —BCLIF — — CCP2IF

bit 7 bit 0

Legend:

Note: Interrupt flag bits are set when an interrupt

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

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TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69

OPTION_REG

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70

PIE2

PIR1

PIR2

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupts.

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 159

OSFIE

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

OSFIF

— — —BCLIE— — CCP2IE

— — —BCLIF— — CCP2IF

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8.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

bit of the STATUS register is cleared.

2. PD

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in Sleep.

6. Secondary oscillator is unaffected and peripherals

that operate from it may continue operation in Sleep.

7. ADC is unaffected, if the dedicated FRC clock is

selected.

8. I/O ports maintain the status they had before

SLEEP was executed (driving high, low or highimpedance).

9. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using secondary oscillator

I/O pins that are high-impedance inputs should be pulled to V currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include the FVR module. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information on this module.

DD or VSS externally to avoid switching

8.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

1. External Reset input on MCLR

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)

The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 6.11

“Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.

pin, if enabled

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(1)

CLKOUT

(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction Fetched

Instruction Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2 0004h 0005h

Forced NOP

OSC

(3)

PC + 2

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference. 3: T1OSC; See Section 25.0 “Electrical Specifications”. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

8.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a SLEEP instruction

- SLEEP instruction will execute as a NOP

- WDT and WDT prescaler will not be cleared

bit of the STATUS register will not be set

-TO

-PD

bit of the STATUS register will not be

cleared

• If the interrupt occurs during or after the execution of a SLEEP instruction

- SLEEP instruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD was executed as a NOP.

FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

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8.2 Low-Power Sleep Mode

The PIC16F1512/3 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1512/3 allows the user to optimize the operating current in Sleep, depending on the application requirements.

A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep.

8.2.1 SLEEP CURRENT VS. WAKE-UP TIME

In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize.

The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.

8.2.2 PERIPHERAL USAGE IN SLEEP

Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the Normal Power mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these peripherals:

• Brown-Out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/interrupt-on-change pins

• Timer1 (with external clock source)

• CCP (Capture mode)

Note: The PIC16LF1512/3 does not have a

configurable Low-Power Sleep mode. PIC16LF1512/3 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum

DD and I/O voltage than the

V PIC16F1512/3. See Section 25.0

“Electrical Specifications” for more

information.

8.3 Power Control Registers

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1

— — — — — —VREGPMReserved

bit 7 bit 0

Legend:

bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit

1 = Low-Power Sleep mode enabled in Sleep

Draws lowest current in Sleep, slower wake-up

0 = Normal-Power mode enabled in Sleep

Draws higher current in Sleep, faster wake-up

bit 0 Reserved: Read as ‘1’. Maintain this bit set.

Note 1: PIC16F1512/3 only.

2: See Section 25.0 “Electrical Specifications”.

(2)

(1)

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TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69

IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 117

IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 11 7

IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 117

PIE1 TMR1GIE ADIE RCIE

PIE2

PIR1 TMR1GIF ADIF RCIF

PIR2

STATUS

VREGCON

WDTCON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. Note 1: PIC16F1512/3 only.

OSFIE — — — BCLIE — — CCP2IE 71

OSFIF — — — BCLIF — — CCP2IF 73

(1)

— — —TOPD Z DC C 17

— — — — — —VREGPM

— —

TXIE SSPIE CCP1IE TMR2IE TMR1IE 70

TXIF SSPIF CCP1IF TMR2IF TMR1IF 72

Reserved

WDTPS<4:0>

SWDTEN 82

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9.0 LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The PIC16F1512/3 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the V at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The PIC16LF1512/3 operates at a maximum V and does not incorporate an LDO.

A device I/O pin may be configured as the LDO voltage output, identified as the V required, an external low-ESR capacitor may be connected to the VCAP pin for additional regulator stability.

The VCAPEN bit of Configuration Words determines which pin is assigned as the V

TABLE 9-1: VCAPEN

VCAPEN Pin

0 RA5

DD and I/O pins to operate

DD of 3.6V

CAP pin. Although not

CAP pin. Refer to Ta bl e 9 - 1.

SELECT BIT

On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information on the constant current rate, refer to the LDO Regulator Characteristics Table in Section 25.0

“Electrical Specifications”.

TABLE 9-2: SUMMARY OF CONFIGURATION WORD WITH LDO

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG2

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO. Note 1: PIC16F1512/3 only.

13:8

7:0

— — —

LVP DEBUG LPBOR BORV STVREN —

VCAPEN

— — WRT<1:0>

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LFINTOSC

23-bit Programmable

Prescaler WDT

WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

10.0 WATCHDOG TIMER (WDT)

The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256 seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM

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10.1 Independent Clock Source

The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See

Section 25.0 “Electrical Specifications” for the

LFINTOSC tolerances.

10.2 WDT Operating Modes

The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 10-1.

10.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on.

WDT protection is active during Sleep.

10.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register.

WDT protection is unchanged by Sleep. See

Table 10-1 for more details.

TABLE 10-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN

11 X XActive

10 X

Device

Mode

Awake Active

Sleep Disabled

WDT

Mode

10.3 Time-Out Period

The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds.

10.4 Clearing the WDT

The WDT is cleared when any of the following conditions occur:

•Any Reset

• CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail

• WDT is disabled

• Oscillator Start-up Timer (OST) is running

See Table 10-2 for more information.

10.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting.

When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 “Oscillator

Module (With Fail-Safe Clock Monitor)” for more

information on the OST.

When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO in the STATUS register are changed to indicate the event. See Section 3.0 “Memory Organization” and The STATUS register (Register 3-1) for more information.

and PD bits

00 X X Disabled

0 Disabled

Active

TABLE 10-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected

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Cleared

PIC16(L)F1512/3

10.6 Watchdog Control Register

REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

— — WDTPS<4:0> SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32)

•

10011 = Reserved. Results in minimum interval (1:32)

(1)

10010 = 1:8388608 (2 10001 = 1:4194304 (2 10000 = 1:2097152 (2 01111 = 1:1048576 (2 01110 = 1:524288 (2 01101 = 1:262144 (2 01100 = 1:131072 (2 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01010 = 1:32768 (Interval 1s nominal) 01001 = 1:16384 (Interval 512 ms nominal) 01000 = 1:8192 (Interval 256 ms nominal) 00111 = 1:4096 (Interval 128 ms nominal) 00110 = 1:2048 (Interval 64 ms nominal) 00101 = 1:1024 (Interval 32 ms nominal) 00100 = 1:512 (Interval 16 ms nominal) 00011 = 1:256 (Interval 8 ms nominal) 00010 = 1:128 (Interval 4 ms nominal) 00001 = 1:64 (Interval 2 ms nominal) 00000 = 1:32 (Interval 1 ms nominal)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = This bit is ignored. If WDTE<1:0> =

1 = WDT is turned on 0 = WDT is turned off

If WDTE<1:0> = This bit is ignored.

00:

01:

1x:

) (Interval 256s nominal)

) (Interval 128s nominal)

) (Interval 64s nominal)

) (Interval 32s nominal)

) (Interval 16s nominal)

) (Interval 8s nominal)

) (Interval 4s nominal)

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

STATUS — — —TOPD Z DC C

WDTCON — — WDTPS<4:0> SWDTEN

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

— IRCF<3:0> —SCS<1:0>

13:8

7:0

— FCMEN IESO CLKOUTEN BOREN<1:0> —

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

Watchdog Timer.

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11.0 FLASH PROGRAM MEMORY

CONTROL

The Flash program memory is readable and writable during normal operation over the full V Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

• PMADRL

•PMADRH

When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read.

The write time is controlled by an on-chip timer. The write/ erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device.

The Flash program memory can be protected in two ways; by code protection (CP and write protection (WRT<1:0> bits in Configuration Words).

Code protection (CP and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs.

Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device.

Note 1: Code protection of the entire Flash

program memory array is enabled by clearing the CP

bit in Configuration Words)

(1)

= 0)

, disables access, reading

bit of Configuration Words.

11.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register.

DD range.

11.1.1 PMCON1 AND PMCON2 REGISTERS

PMCON1 is the control register for Flash program memory accesses.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine.

The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory.

11.2 Flash Program Memory Overview

It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software.

After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair.

Note: If the user wants to modify only a portion

of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations.

See Table 11-1 for Erase Row size and the number of write latches for Flash program memory.

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Start

Read Operation

Select

Program or Configuration Memory

(CFGS)

Select

Word Address

(PMADRH:PMADRL)

End

Read Operation

Instruction Fetched ignored

NOP execution forced

Instruction Fetched ignored

NOP execution forced

Initiate Read operation

(RD = 1)

Data read now in

PMDATH:PMDATL

TABLE 11-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Device

PIC16(L)F1512/3 32 32

Row Erase

(words)

Write

Latches

(words)

11.2.1 READING THE FLASH PROGRAM MEMORY

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

3. Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions.

PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user.

Note: The two instructions following a program

memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set.

FIGURE 11-1: FLASH PROGRAM

MEMORY READ FLOWCHART

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,RD

executed here

INSTR(PC + 1)

executed here

PC + 1 PMADRH,PMADRL

PC+3

PC + 5

Flash ADDR

RD bit

PMDATH,PMDATL

PC + 3 PC + 4

INSTR (PC + 1)

INSTR(PC - 1)

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

Flash Data

PMDATH

PMDATL

INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)

instruction ignored Forced NOP

INSTR(PC + 2)

executed here

instruction ignored Forced NOP

* This code block will read 1 word of program * memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;

MOVWF PMADRL ; Store LSB of address

MOVLW PROG_ADDR_HI ;

MOVWL PMADRH ; Store MSB of address

BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read

NOP ; Ignored (Figure 11-2)

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location

MOVF PMDATH,W ; Get MSB of word

MOVWF PROG_DATA_HI ; Store in user location

FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

EXAMPLE 11-1: FLASH PROGRAM MEMORY READ

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Write 055h to

PMCON2

Start

Unlock Sequence

Write 0AAh to

PMCON2

Initiate

Write or Erase operation

(WR = 1)

Instruction Fetched ignored

NOP execution forced

End

Unlock Sequence

Instruction Fetched ignored

NOP execution forced

11.2.2 FLASH MEMORY UNLOCK SEQUENCE

The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations:

• Row Erase

• Load program memory write latches

• Write of program memory write latches to

program memory

• Write of program memory write latches to User

IDs

The unlock sequence consists of the following steps:

1. Write 55h to PMCON2

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4. NOP instruction

5. NOP instruction

Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction.

Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed.

FIGURE 11-3: FLASH PROGRAM

MEMORY UNLOCK SEQUENCE FLOWCHART

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Disable Interrupts

(GIE = 0)

Start

Erase Operation

Select

Program or Configuration Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

(FIGURE x-x)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

CPU stalls while

Erase operation completes

(2ms typical)

Figure 11-3

11.2.3 ERASING FLASH PROGRAM MEMORY

While executing code, program memory can only be erased by rows. To erase a row:

1. Load the PMADRH:PMADRL register pair with

any address within the row to be erased.

2. Clear the CFGS bit of the PMCON1 register.

3. Set the FREE and WREN bits of the PMCON1

4. Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

5. Set control bit WR of the PMCON1 register to

begin the erase operation.

See Example 11-2.

After the “BSF PMCON1,WR” instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions immediately following the WR bit set instruction. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction.

FIGURE 11-4: FLASH PROGRAM

MEMORY ERASE FLOWCHART

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; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF PMADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF PMADRH BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,FREE ; Specify an erase operation BSF PMCON1,WREN ; Enable writes

MOVLW 55h ; Start of required sequence to initiate erase MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write AAh BSF PMCON1,WR ; Set WR bit to begin erase NOP ; NOP instructions are forced as processor starts NOP ; row erase of program memory.

; ; The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction

BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts

Required

Sequence

EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY

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11.2.4 WRITING TO FLASH PROGRAM MEMORY

Program memory is programmed using the following steps:

1. Load the address in PMADRH:PMADRL of the

row to be programmed.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See

Figure 11-5 (row writes to program memory with 32

write latches) for more details.

The write latches are aligned to the Flash row address boundary defined by the upper 10-bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower 5-bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF.

The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory.

Note: The special unlock sequence is required

to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated.

1. Set the WREN bit of the PMCON1 register.

2. Clear the CFGS bit of the PMCON1 register.

3. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory.

4. Load the PMADRH:PMADRL register pair with the address of the location to be written.

5. Load the PMDATH:PMDATL register pair with the program memory data to be written.

6. Execute the unlock sequence (Section 11.2.2

“Flash Memory Unlock Sequence”). The write

latch is now loaded.

7. Increment the PMADRH:PMADRL register pair to point to the next location.

8. Repeat steps 5 through 7 until all but the last write latch has been loaded.

9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘0’, the write sequence will initiate the write to Flash program memory.

10. Load the PMDATH:PMDATL register pair with the program memory data to be written.

11. Execute the unlock sequence (Section 11.2.2

“Flash Memory Unlock Sequence”). The

entire program memory latch content is now written to Flash program memory.

Note: The program memory write latches are

reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state.

An example of the complete write sequence is shown in

Example 11-3. The initial address is loaded into the

PMADRH:PMADRL register pair; the data is loaded using indirect addressing.

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PMDATH PMDATL

7 5 0 7 0

6 8

1414

Write Latch #31

1Fh

1414

PMADRH PMADRL

7 6 0 7 5 4 0

Program Memory Write Latches

14 14 14

510

PMADRH<6:0>

:PMADRL<7:5>

Flash Program Memory

Row

Address

Decode

Addr

Write Latch #30

1Eh

Write Latch #1

01h

Write Latch #0

00h

Addr AddrAddr

000h 001Fh001Eh0000h 0001h

001h 003Fh003Eh0020h 0021h

002h 005Fh005Eh0040h 0041h

3FEh 7FDFh7FDEh7FC0h 7FC1h

3FFh 7FFFh7FFEh7FE0h 7FE1h

r9 r8 r7 r6 r5 r4 r3- r1 r0 c4 c3 c2 c1 c0r2

PMADRL<4:0>

400h 8009h-801Fh8000h-8003h

Configuration

Words

USER ID 0-3

8007h-8008h8006h

DEVICEID

REVID

reserved

8004h-8005h

reserved

Configuration Memory

CFGS = 0

CFGS = 1

FIGURE 11-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES

PIC16(L)F1512/3

Disable Interrupts

(GIE = 0)

Start

Write Operation

Select

Program or Config. Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Write Operation

(FREE = 0)

Enable Write/Erase

Operation (WREN = 1)

Unlock Sequence

(Figure x-x)

Disable

Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Write Operation

No delay when writing to

Program Memory Latches

Determine the number of

words to be written into the

Program or Configuration

Memory. The number of words cannot exceed the number of words

per row.

(word_cnt)

Load the value to write

(PMDATH:PMDATL)

Update the word counter

(word_cnt--)

Last word to

write ?

Increment Address

(PMADRH:PMADRL++)

Unlock Sequence

(Figure x-x)

CPU stalls while Write

operation completes

(2ms typical)

Load Write Latches Only

(LWLO = 1)

Write Latches to Flash

(LWLO = 0)

Yes

Figure 11-3

FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART

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; This write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) ;

BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,WREN ; Enable writes BSF PMCON1,LWLO ; Only Load Write Latches

LOOP

MOVIW FSR0++ ; Load first data byte into lower MOVWF PMDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF PMDATH ;

MOVF PMADRL,W ; Check if lower bits of address are '00000' XORLW 0x1F ; Check if we're on the last of 32 addresses ANDLW 0x1F ; BTFSC STATUS,Z ; Exit if last of 32 words, GOTO START_WRITE ;

MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write AAh BSF PMCON1,WR ; Set WR bit to begin write NOP ; NOP instructions are forced as processor

; loads program memory write latches

NOP ;

INCF PMADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches

START_WRITE

BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program

; memory write

MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write AAh BSF PMCON1,WR ; Set WR bit to begin write NOP ; NOP instructions are forced as processor writes

; all the program memory write latches simultaneously

NOP ; to program memory.

; After NOPs, the processor ; stalls until the self-write process in complete

; after write processor continues with 3rd instruction BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts

Required

Sequence

Required

Sequence

EXAMPLE 11-3: WRITING TO FLASH PROGRAM MEMORY

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Start

Modify Operation

Read Operation

(Figure x.x)

Erase Operation

(Figure x.x)

Modify Image

The words to be modified are

changed in the RAM image

End

Modify Operation

Write Operation

use RAM image

(Figure x.x)

An image of the entire row read

must be stored in RAM

Figure 11-2

Figure 11-4

Figure 11-5

11.3 Modifying Flash Program Memory

When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps:

1. Load the starting address of the row to be modified.

2. Read the existing data from the row into a RAM image.

3. Modify the RAM image to contain the new data to be written into program memory.

4. Load the starting address of the row to be rewritten.

5. Erase the program memory row.

6. Load the write latches with data from the RAM image.

7. Initiate a programming operation.

FIGURE 11-7: FLASH PROGRAM

MEMORY MODIFY FLOWCHART

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* This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF PMADRL ; Store LSB of address CLRF PMADRH ; Clear MSB of address

BSF PMCON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF PMCON1,RD ; Initiate read NOP ; Executed (See Figure 11-2) NOP ; Ignored (See Figure 11-2) BSF INTCON,GIE ; Restore interrupts

MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location

11.4 User ID, Device ID and

Configuration Word Access

Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2.

When read access is initiated on an address outside the parameters listed in Ta bl e 1 1- 2 , the PMDATH:PMDATL register pair is cleared, reading back ‘0’s.

TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)

Address Function Read Access Write Access

8000h-8003h User IDs Yes Yes

8006h Device ID/Revision ID Yes No

8007h-8008h Configuration Words 1 and 2 Yes No

EXAMPLE 11-4: CONFIGURATION WORD AND DEVICE ID ACCESS

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Start

Verify Operation

Read Operation

(Figure x.x)

End

Verify Operation

This routine assumes that the last row

of data written was from an image

saved in RAM. This image will be used

to verify the data currently stored in

Flash Program Memory.

PMDAT =

RAM image

Last

Word ?

Fail

Verify Operation

Yes

Figure 11-2

11.5 Write Verify

It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete.

FIGURE 11-8: FLASH PROGRAM

MEMORY VERIFY FLOWCHART

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11.6 Flash Program Memory Control Registers

REGISTER 11-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

PMDAT<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 11-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — PMDAT<13:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 11-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

PMADR<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 11-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— PMADR<14:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘1’

bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address

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REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

(1)

U-1

— CFGS LWLO FREE WRERR WREN WR RD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q

(2)

R/W-0/0 R/S/HC-0/0 R/S/HC-0/0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Note 1: Unimplemented bit, read as ‘1’.

2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1) . 3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

Unimplemented: Read as ‘1’

CFGS: Configuration Select bit

1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory

LWLO : Load Write Latches Only bit

1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches

will be initiated on the next WR command

FREE: Program Flash Erase Enable bit

1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command

WRERR: Program/Erase Error Flag bit

1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically

on any set attempt (write ‘

0 = The program or erase operation completed normally.

WREN: Program/Erase Enable bit

1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash

WR: Write Control bit

1 = Initiates a program Flash program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software.

0 = Program/erase operation to the Flash is complete and inactive.

RD: Read Control bit

1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set

(not cleared) in software.

0 = Does not initiate a program Flash read.

(3)

1’) of the WR bit).

DS40001624C-page 98  2012-2014 Microchip Technology Inc.

PIC16(L)F1512/3

REGISTER 11-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0

Program Memory Control Register 2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

PMCON1

PMCON2 Program Memory Control Register 2

PMADRL PMADRL<7:0>

PMADRH

PMDATL PMDATL<7:0>

PMDATH

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.

—

— PMADRH<6:0> 97

— — PMDATH<5:0> 97

CFGS LWLO FREE WRERR WREN WR RD

TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

CONFIG2

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

13:8

7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

13:8

7:0 — — — VCAPEN

— FCMEN IESO CLKOUTEN BOREN<1:0> —

— — LVP DEBUG LPBOR BORV STVREN —

(1)

— —WRT<1:0>

Page

 2012-2014 Microchip Technology Inc. DS40001624C-page 99

PIC16(L)F1512/3

Write LATx

Data Register

I/O pin

Read PORTx

Write PORTx

TRISx

Read LATx

Data Bus

To peripherals

ANSELx

VDD

VSS

; This code example illustrates ; initializing the PORTA register. The ; other ports are initialized in the same ; manner.

BANKSEL PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as

;outputs

12.0 I/O PORTS

Each port has three standard registers for its operation. These registers are:

• TRISx registers (data direction)

• PORTx registers (reads the levels on the pins of

the device)

• LATx registers (output latch)

Some ports may have one or more of the following additional registers. These registers are:

• ANSELx (analog select)

• WPUx (weak pull-up)

In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read.

TABLE 12-1: PORT AVAILABILITY PER

DEVICE

Device

PORTE

PORTA

PIC16(L)F1512 ●●●● PIC16(L)F1513 ●●●●

The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving.

A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value.

Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1.

PORTC

PORTB

FIGURE 12-1: GENERIC I/O PORT

OPERATION

EXAMPLE 12-1: INITIALIZING PORTA

DS40001624C-page 100  2012-2014 Microchip Technology Inc.

Datasheet PIC16F1512, PIC16LF1512, PIC16F1513, PIC16LF1513 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance RISC CPU:

Flexible Oscillator Structure:

Analog Features:

Extreme Low-Power Management PIC16LF1512/3 with XLP:

Special Microcontroller Features:

Peripheral Highlights:

PIC16(L)F151X/152X Family Types

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1512/3)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC16(L)F1512/3 BLOCK DIAGRAM

TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION

2.0 ENHANCED MID-RANGE CPU

2.1 Automatic Interrupt Context Saving

2.2 16-Level Stack with Overflow and Underflow

2.3 File Select Registers

2.4 Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

3.0 MEMORY ORGANIZATION

3.1 Program Memory Organization

TABLE 3-1: DEVICE SIZES AND ADDRESSES

3.1.1 READING PROGRAM MEMORY AS DATA

EXAMPLE 3-1: RETLW INSTRUCTION

3.2 Data Memory Organization

3.2.1 CORE REGISTERS

TABLE 3-2: CORE REGISTERS

REGISTER 3-1: STATUS: STATUS REGISTER

3.2.2 SPECIAL FUNCTION REGISTER

3.2.3 GENERAL PURPOSE RAM

3.2.4 COMMON RAM

3.2.5 DEVICE MEMORY MAPS

TABLE 3-3: PIC16(L)F1512 MEMORY MAP (BANKS 0-7)

TABLE 3-4: PIC16(L)F1513 MEMORY MAP (BANKS 0-7)

TABLE 3-5: PIC16(L)F1512/3 MEMORY MAP (BANKS 8-30)

3.2.6 CORE FUNCTION REGISTERS SUMMARY

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

3.2.7 SPECIAL FUNCTION REGISTERS SUMMARY

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

3.3 PCL and PCLATH

3.3.3 COMPUTED FUNCTION CALLS

3.3.4 BRANCHING

3.3.1 MODIFYING PCL

3.3.2 COMPUTED GOTO

3.4 Stack

3.4.1 ACCESSING THE STACK

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

3.4.2 OVERFLOW/UNDERFLOW RESET

3.5 Indirect Addressing

FIGURE 3-9: INDIRECT ADDRESSING

3.5.1 TRADITIONAL DATA MEMORY

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

3.5.2 LINEAR DATA MEMORY

3.5.3 PROGRAM FLASH MEMORY

4.0 DEVICE CONFIGURATION

4.1 Configuration Words

REGISTER 4-1: CONFIGURATION WORD 1

REGISTER 4-2: CONFIGURATION WORD 2

4.2 Code Protection

4.2.1 PROGRAM MEMORY PROTECTION

4.3 Write Protection

4.4 User ID

4.5 Device ID and Revision ID

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

5.1 Overview

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

5.2 Clock Source Types

5.2.1 EXTERNAL CLOCK SOURCES

FIGURE 5-6: EXTERNAL RC MODES

5.2.2 INTERNAL CLOCK SOURCES