PIC16(L)F1512/3
28-Pin Flash Microcontrollers with XLP Technology
High-Performance RISC CPU:
• C Compiler Optimized Architecture
• Only 49 Instructions
• Up to 7 Kbytes Linear Program Memory
Addressing
• Up to 256 Bytes Linear Data Memory Addressing
• Operating Speed:
- DC – 20 MHz clock input @ 2.5V
- DC – 16 MHz clock input @ 1.8V
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
Flexible Oscillator Structure:
• 16 MHz Internal Oscillator Block:
- Factory calibrated to ± 1%, typical
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• External Oscillator Block with:
- Four crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
• Two-Speed Oscillator Start-up
• Oscillator Start-up Timer (OST)
Analog Features:
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Up to 17 channels
- Special Event Triggers
- Conversion available during Sleep
• Hardware Capacitive Voltage Divider (CVD)
- Double sample conversions
- Two result registers
- Inverted acquisition
- 7-bit pre-charge timer
- 7-bit acquisition timer
- Two guard ring output drives
- Adjustable sample and hold capacitor array
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
• Integrated Temperature Indicator
Extreme Low-Power Management PIC16LF1512/3 with XLP:
• Sleep mode: 20 nA @ 1.8V, typical
• Watchdog Timer: 300 nA @ 1.8V, typical
• Secondary Oscillator: 600 nA @ 32 kHz, 1.8V,
typical
• Operating Current: 30 A/MHz @ 1.8V, typical
Special Microcontroller Features:
• Operating Voltage Range:
- 2.3V-5.5V (PIC16F1512/3)
- 1.8V-3.6V (PIC16LF1512/3)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-out Reset
(LPBOR)
• Extended Watchdog Timer (WDT)
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Enhanced Low-Voltage Programming (LVP)
• Programmable Code Protection
• Low-Power Sleep mode
• 128 Bytes High-Endurance Flash:
- 100,000 write Flash endurance (minimum)
Peripheral Highlights:
• Up to 25 I/O Pins (1 input-only pin):
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable interrupt-on-change
(IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Low-power 32 kHz secondary oscillator driver
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture/Compare (CCP) modules:
• Master Synchronous Serial Port (MSSP) with SPI
2
CTM with:
and I
- 7-bit address masking
- SMBus/PMBus
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
- Auto-wake-up on start
TM
compatibility
2012-2014 Microchip Technology Inc. DS40001624C-page 1
PIC16(L)F1512/3
28-Pin SPDIP, SOIC, SSOP
PIC16F1512/3
PIC16LF1512/3
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RB6/ICSPCLK/ICDCLK
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
VSS
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
V
SS
RA7
RA6
RC0
RC1
RC2
RC3
RC5
RC4
RC7
RC6
RB7/ICSPDAT/ICDDAT
PIC16(L)F151X/152X Family Types
ADC
(1)
CCP
Debug
(bytes)
(2)
I/O’s
10-bit (ch)
Timers
(8/16-bit)
Advanced Control
Device
Data SRAM
Data Sheet Index
PIC16(L)F1512 (1) 2048 128 25 17 Y 2/1 1 1 2 I Y
PIC16(L)F1513 (1) 4096 256 25 17 Y 2/1 1 1 2 I Y
PIC16(L)F1516 (2) 8192 512 25 17 N 2/1 1 1 2 I Y
PIC16(L)F1517 (2) 8192 512 36 28 N 2/1 1 1 2 I Y
PIC16(L)F1518 (2) 16384 1024 25 17 N 2/1 1 1 2 I Y
PIC16(L)F1519 (2) 16384 1024 36 28 N 2/1 1 1 2 I Y
PIC16(L)F1526 (3) 8192 768 54 30 N 6/3 2 2 10 I Y
PIC16(L)F1527 (3) 16384 1536 54 30 N 6/3 2 2 10 I Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: Future Product PIC16(L)F1512/13 Data Sheet, 28-Pin Flash, 8-bit microcontrollers.
2: DS41452 PIC16(L)F1516/7/8/9 Data Sheet, 28/40/44-Pin Flash, 8-bit MCUs.
3: DS41458 PIC16(L)F1526/27 Data Sheet, 64-Pin Flash, 8-bit MCUs.
Program Memory
Flash (words)
C™/SPI)
2
EUSART
MSSP (I
FIGURE 1: 28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1512/3
XLP
DS40001624C-page 2 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
2
3
6
1
18
19
20
21
15
7
16
17
RC0
5
4
RB7/ICSPDAT/ICDDAT
RB6/ICSPCLK/ICDCLK
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
VSS
RC7
RC6
RC5
RC4
RE3/MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
RC1
RC2
RC3
9
10
13814
12
11
27
26
232822
24
25
PIC16F1512/3
PIC16LF1512/3
28-Pin UQFN
FIGURE 2: 28-PIN UQFN (4X4) PACKAGE DIAGRAM FOR PIC16(L)F1512/3
2012-2014 Microchip Technology Inc. DS40001624C-page 3
PIC16(L)F1512/3
TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1512/3)
I/O
28-Pin UQFN
28-Pin SPDIP, SOIC, SSOP
RA0 2 27 AN0 — — — SS
RA1328AN1 — ——— —— —
RA2 4 1 AN2 — — — — — — —
RA3 5 2 AN3/V
RA4 6 3 — T0CKI — — — — — —
RA5 7 4 AN4 — — — SS
RA6 10 7 — — — — — — — OSC2/CLKOUT
RA7 9 6 — — — — — — — OSC1/CLKIN
RB0 21 18 AN12 — — — — INT/IOC Y —
RB1 22 19 AN10 — — — — IOC Y —
RB2 23 20 AN8 — — — — IOC Y —
RB3 24 21 AN9 — CCP2
RB4 25 22 AN11
RB5 26 23 AN13 T1G — — — IOC Y —
RB6 27 24 ADGRDA — — — — IOC Y ICSPCLK/ICDCLK
RB7 28 25 ADGRDB — — — — IOC Y ICSPDAT/ICDDAT
RC0 11 8 — SOSCO/T1CKI — — — — — —
RC1 12 9 — SOSCI CCP2
RC2 13 10 AN14 — CCP1 — — — — —
RC3 14 11 AN15 — — — SCK/SCL — — —
RC4 15 12 AN16 — — — SDI/SDA — — —
RC5 16 13 AN17 — — — SDO — — —
RC6 17 14 AN18 — — TX/CK — — — —
RC7 18 15 AN19 — — RX/DT — — — —
RE3 1 26 — — — — — — Y MCLR
VDD 20 17 — — — — — — — —
V
SS 8,19 5,16 — — — — — — — —
NC — — — — — — — — — —
Note 1: Peripheral pin location selected using APFCON register. Default location.
2: Peripheral pin location selected using APFCON register. Alternate location.
A/D
REF+ — ——— —— —
ADOUT
Timers
— — — — IOC Y —
CCP
(2)
(1)
EUSART
——IOCY —
—— —— —
MSSP
(2)
(1)
Interrupt
— — —
—— VCAP
Pull-up
Basic
/VPP
DS40001624C-page 4 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 11
3.0 Memory Organization................................................................................................................................................................. 13
4.0 Device Configuration.................................................................................................................................................................. 35
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 41
6.0 Resets ........................................................................................................................................................................................ 56
7.0 Interrupts .................................................................................................................................................................................... 64
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 75
9.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 79
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 80
11.0 Flash Program Memory Control ................................................................................................................................................. 84
12.0 I/O Ports ................................................................................................................................................................................... 100
13.0 Interrupt-On-Change ................................................................................................................................................................ 115
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 119
15.0 Temperature Indicator Module ................................................................................................................................................. 121
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 123
17.0 Timer0 Module ......................................................................................................................................................................... 157
18.0 Timer1 Module with Gate Control............................................................................................................................................. 160
19.0 Timer2 Module ......................................................................................................................................................................... 171
20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 175
21.0 Capture/Compare/PWM Modules ............................................................................................................................................ 228
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237
23.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 266
24.0 Instruction Set Summary.......................................................................................................................................................... 268
25.0 Electrical Specifications............................................................................................................................................................ 282
26.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 310
27.0 Development Support............................................................................................................................................................... 341
28.0 Packaging Information.............................................................................................................................................................. 345
The Microchip Web Site..................................................................................................................................................................... 357
Customer Change Notification Service .............................................................................................................................................. 357
Customer Support .............................................................................................................................................................................. 357
Product Identification System ............................................................................................................................................................ 358
2012-2014 Microchip Technology Inc. DS40001624C-page 5
PIC16(L)F1512/3
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS40001624C-page 6 2012-2014 Microchip Technology Inc.
1.0 DEVICE OVERVIEW
The PIC16(L)F1512/3 are described within this data
sheet. They are available in 28-pin packages. Figure 1-1
shows a block diagram of the PIC16(L)F1512/3 devices.
Table 1-2 shows the pinout descriptions.
Reference Ta bl e 1 -1 for peripherals available per
device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F1512
PIC16(L)F1513
Analog-to-Digital Converter (ADC) ●●
Fixed Voltage Reference (FVR) ●●
Temperature Indicator ●●
Capture/Compare/PWM Modules
CCP1 ●●
CCP2 ●●
EUSARTs
EUSART ●●
Master Synchronous Serial Ports
MSSP ●●
Timers
Timer0 ●●
Timer1 ●●
Timer2 ●●
PIC16(L)F1512/3
2012-2014 Microchip Technology Inc. DS40001624C-page 7
PIC16(L)F1512/3
PORTB
Timer2MSSP
Timer0
CCP2
ADC
10-Bit
CCP1
Note 1: See applicable chapters for more information on peripherals.
2: See Ta bl e 1 -1 for peripherals available on specific devices.
CPU
Program
Flash Memory
PORTA
RAM
Timing
Generation
INTRC
Oscillator
MCLR
(Figure 2-1)
Timer1
OSC1/CLKIN
OSC2/CLKOUT
FVR
PORTC
PORTE
Te mp .
Indicator
EUSART
FIGURE 1-1: PIC16(L)F1512/3 BLOCK DIAGRAM
DS40001624C-page 8 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION
Input
Name Function
RA0/AN0/SS
RA1/AN1 RA1 TTL CMOS General purpose I/O.
RA2/AN2 RA2 TTL CMOS General purpose I/O.
RA3/AN3/V
RA4/T0CKI RA4 TTL CMOS General purpose I/O.
RA5/AN4/SS
RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.
RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.
RB0/AN12/INT RB0 TTL CMOS General purpose I/O with IOC and WPU.
RB1/AN10 RB1 TTL CMOS General purpose I/O with IOC and WPU.
RB2/AN8 RB2 TTL CMOS General purpose I/O with IOC and WPU.
RB3/AN9/CCP2
RB4/AN11/ADOUT RB4 TTL CMOS General purpose I/O with IOC and WPU.
RB5/AN13/T1G RB5 TTL CMOS General purpose I/O with IOC and WPU.
RB6/ICSPCLK/ADGRDA RB6 TTL CMOS General purpose I/O with IOC and WPU.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
(2)
REF+ RA3 TTL CMOS General purpose I/O.
(1)
/VCAP
(2)
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
RA0 TTL CMOS General purpose I/O.
AN0 AN — A/D Channel 0 input.
SS
AN1 AN — A/D Channel 1 input.
AN2 AN — A/D Channel 2 input.
AN3 AN — A/D Channel 3 input.
REF+ AN — A/D Positive Voltage Reference input.
V
T0CKI ST — Timer0 clock input.
RA5 TTL CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
SS
CAP Power Power Filter capacitor for Voltage Regulator (PIC16(L)F1512/3 only).
V
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS F
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN ST — External clock input (EC mode).
AN12 AN — A/D Channel 12 input.
INT ST — External interrupt.
AN10 AN — A/D Channel 10 input.
AN8 AN — A/D Channel 8 input.
RB3 TTL CMOS General purpose I/O with IOC and WPU.
AN9 AN — A/D Channel 9 input.
CCP2 ST CMOS Capture/Compare/PWM 2.
AN11 AN — A/D Channel 11 input.
ADOUT CMOS — A/D with CVD output.
AN13 AN — A/D Channel 13 input.
T1G ST — Timer1 Gate input.
ICSPCLK ST CMOS In-Circuit Data I/O.
ADGRDA — CMOS Guard Ring output A.
Output
Typ e
Typ e
ST — Slave Select input.
ST — Slave Select input.
OSC/4 output.
Description
2
C™ = Schmitt Trigger input with I2C
2012-2014 Microchip Technology Inc. DS40001624C-page 9
PIC16(L)F1512/3
TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
RB7/ICSPDAT/ADGRDB RB7 TTL CMOS General purpose I/O with IOC and WPU.
ICSPDAT ST CMOS ICSP™ Data I/O.
ADGRDB — CMOS Guard Ring output B.
RC0/SOSCO/T1CKI RC0 ST CMOS General purpose I/O.
SOSCO — XTAL Secondary oscillator connection.
RC1/SOSCI/CCP2
RC2/AN14/CCP1 RC2 ST CMOS General purpose I/O.
RC3/AN15/SCK/SCL
RC4/AN16/SDI/SDA
RC5/AN17/SDO RC5 ST CMOS General purpose I/O.
RC6/AN18/TX/CK
RC7/AN19/RX/DT
RE3/MCLR
V
DD VDD Power — Positive supply.
SS VSS Power — Ground reference.
V
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
(1)
/VPP RE3 ST — General purpose input with WPU.
T1CKI ST — Timer1 clock input.
RC1 ST CMOS General purpose I/O.
SOSCI — XTAL Secondary oscillator connection.
CCP2 ST CMOS Capture/Compare/PWM 2.
AN14 AN — A/D Channel 14 input.
CCP1 ST CMOS Capture/Compare/PWM 1.
RC3 ST CMOS General purpose I/O.
AN15 AN — A/D Channel 15 input.
SCK ST CMOS SPI clock.
SCL I
RC4 ST CMOS General purpose I/O.
AN16 AN — A/D Channel 16 input.
SDI ST — SPI data input.
SDA I
AN17 AN — A/D Channel 17 input.
SDO — CMOS SPI data output.
RC6 ST CMOS General purpose I/O.
AN18 AN — A/D Channel 18 input.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RC7 ST CMOS General purpose I/O.
AN19 AN — A/D Channel 19 input.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
MCLR
PP HV — Programming voltage.
V
Output
Typ e
2
2
Typ e
C™ OD I2C™ clock.
C™ OD I2C™ data input/output.
ST — Master Clear with internal pull-up.
Description
2
C™ = Schmitt Trigger input with I2C
DS40001624C-page 10 2012-2014 Microchip Technology Inc.
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1 Automatic Interrupt Context Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
PIC16(L)F1512/3
2.2 16-Level Stack with Overflow and Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register and, if enabled, will cause a
software Reset. See Section 3.4 “Stack” for more
details.
2.3 File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 24.0 “Instruction Set Summary” for more
details.
2012-2014 Microchip Technology Inc. DS40001624C-page 11
PIC16(L)F1512/3
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
V
DD
8
8
Brown-out
Reset
12
3
VSS
Internal
Oscillator
Block
Configuration
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
15
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr
7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
V
DD
8
8
3
VSS
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
FIGURE 2-1: CORE BLOCK DIAGRAM
DS40001624C-page 12 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
3.0 MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
-User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for these devices. Accessing a location
above these boundaries will cause a wrap-around within
the implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (see
Figure 3-1 and Figure 3-2).
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device
PIC16F1512
PIC16LF1512
PIC16F1513
PIC16LF1513
Note 1: High-endurance Flash applies to low byte of each address in the range.
Program Memory
Space (Words)
2,048 07FFh 0780h-07FFh
4,096 0FFFh 0F80h-0FFFh
Last Program Memory
Address
High-Endurance Flash
Memory Address Range
(1)
2012-2014 Microchip Technology Inc. DS40001624C-page 13
PIC16(L)F1512/3
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Wraps to Page 0
Wraps to Page 0
Wraps to Page 0
0800h
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
Rollover to Page 0
Rollover to Page 0
7FFFh
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
CALL, CALLW
RETURN, RETLW
Stack Level 1
0005h
On-chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh
1000h
7FFFh
Page 1
Rollover to Page 1
Interrupt, RETFIE
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1512 PARTS
FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1513 PARTS
DS40001624C-page 14 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
CALL constants
;… THE CONSTANT IS IN W
constants
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.1.1 READING PROGRAM MEMORY AS DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The High directive will set bit<7> if a label points to a
location in program memory.
2012-2014 Microchip Technology Inc. DS40001624C-page 15
PIC16(L)F1512/3
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON
3.2 Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper seven
bits of the address define the Bank address and the
lower five bits select the registers/RAM in that bank.
3.2.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta b le 3 - 2. For detailed
information, see Tab le 3 -8 .
TABLE 3-2: CORE REGISTERS
DS40001624C-page 16 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 24.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TO
PD ZDC
(1)
(1)
C
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Digit Borrow
bit 0 C: Carry/Borrow
Note 1: For Borrow
second operand.
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
(1)
bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
bit
(1)
2012-2014 Microchip Technology Inc. DS40001624C-page 17
PIC16(L)F1512/3
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset
3.2.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
3.2.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-3: BANKED MEMORY
PARTITIONING
DS40001624C-page 18 2012-2014 Microchip Technology Inc.
3.2.5 DEVICE MEMORY MAPS
The memory maps for PIC16(L)F1512/3 are as shown
in Table 3-4 through Ta b le 3 -7 .
2012-2014 Microchip Technology Inc. DS40001624C-page 19
TABLE 3-3: PIC16(L)F1512 MEMORY MAP (BANKS 0-7)
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta bl e 3 -2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh
00Fh
010h PORTE 090h TRISE 110h
011h PIR1 091h PIE1 111h
012h PIR2 092h PIE2 112h
013h
014h
015h TMR0 095h OPTION_REG 115h
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSPCON2 296h
017h TMR1H 097h WDTCON 117h FVRCON 197h
018h T1CON 098h
019h T1GCON 099h OSCCON 119h
01Ah TMR2 09Ah OSCSTAT 11Ah
01Bh PR2 09Bh ADRES0L 11Bh
01Ch T2CON 09Ch ADRES0H 11Ch
01Dh
01Eh
01Fh
020h
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: PIC16F1512 only.
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
—093h—113h— 193h PMDATL 213h SSPMSK 293h CCP1CON 313h — 393h —
—094h—114h— 194h PMDATH 214h SSPSTAT 294h — 314h — 394h IOCBP
— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh —
— 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh —29Eh—31Eh—39Eh—
—09Fh—11Fh— 19Fh BAUDCON 21Fh —29Fh—31Fh—39Fh—
General
Purpose
Register
80 Bytes
Common RAM
080h
0A0h
General Purpose
0BFh
0C0h
Unimplemented
0F0h
Core Registers
(Ta bl e 3 -2 )
—118h—198h—218h— 298h CCPR2L 318h — 398h —
Register
32 Bytes
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
100h
120h
170h
Core Registers
(Table 3-2)
—190h— 210h WPUE 290h — 310h — 390h —
— 191h PMADRL 211h SSPBUF 291h CCPR1L 311h — 391h —
— 192h PMADRH 212h SSPADD 292h CCPR1H 312h — 392h —
— 195h PMCON1 215h SSPCON1 295h — 315h — 395h IOCBN
— 199h RCREG 219h — 299h CCPR2H 319h — 399h —
— 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah —39Ah—
— 19Bh SPBRGL 21Bh —29Bh—31Bh—39Bh—
— 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
180h
1A0h
1F0h
Core Registers
(Table 3-2)
VREGCON
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
(1)
200h
Core Registers
(Table 3-2)
— 28Ch — 30Ch — 38Ch —
—28Eh—30Eh—38Eh—
217h SSPCON3 297h — 317h — 397h —
220h
Unimplemented
Read as ‘0’
270h
Common RAM
(Accesses
70h – 7Fh)
280h
2A0h
2F0h
Core Registers
(Table 3-2)
— 30Dh — 38Dh —
— 316h — 396h IOCBF
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
300h
Core Registers
(Table 3-2)
320h
Unimplemented
Read as ‘0’
36Fh 3EFh
370h
Common RAM
(Accesses
70h – 7Fh)
380h
3A0h
3F0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
PIC16(L)F1512/3
DS40001624C-page 20 2012-2014 Microchip Technology Inc.
TABLE 3-4: PIC16(L)F1513 MEMORY MAP (BANKS 0-7)
PIC16(L)F1512/3
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta bl e 3 -2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh
00Fh
010h PORTE 090h TRISE 110h
011h PIR1 091h PIE1 111h
012h PIR2 092h PIE2 112h
013h
014h
015h TMR0 095h OPTION_REG 115h
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSPCON2 296h
017h TMR1H 097h WDTCON 117h FVRCON 197h
018h T1CON 098h
019h T1GCON 099h OSCCON 119h
01Ah TMR2 09Ah OSCSTAT 11Ah
01Bh PR2 09Bh ADRES0L 11Bh
01Ch T2CON 09Ch ADRES0H 11Ch
01Dh
01Eh
01Fh
020h
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: PIC16F1513 only.
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
—093h—113h— 193h PMDATL 213h SSPMSK 293h CCP1CON 313h — 393h —
—094h—114h— 194h PMDATH 214h SSPSTAT 294h — 314h — 394h IOCBP
— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh —
— 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh —29Eh—31Eh—39Eh—
—09Fh—11Fh— 19Fh BAUDCON 21Fh —29Fh—31Fh—39Fh—
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
080h
0A0h
0F0h
Core Registers
(Ta bl e 3 -2 )
—118h—198h—218h— 298h CCPR2L 318h — 398h —
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
100h
120h
170h
Core Registers
(Table 3-2)
—190h— 210h WPUE 290h — 310h — 390h —
— 191h PMADRL 211h SSPBUF 291h CCPR1L 311h — 391h —
— 192h PMADRH 212h SSPADD 292h CCPR1H 312h — 392h —
— 195h PMCON1 215h SSPCON1 295h — 315h — 395h IOCBN
— 199h RCREG 219h — 299h CCPR2H 319h — 399h —
— 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah —39Ah—
— 19Bh SPBRG 21Bh —29Bh—31Bh—39Bh—
— 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
180h
1A0h
1F0h
Core Registers
(Table 3-2)
VREGCON
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
(1)
200h
Core Registers
(Table 3-2)
— 28Ch — 30Ch — 38Ch —
—28Eh—30Eh—38Eh—
217h SSPCON3 297h — 317h — 397h —
220h
Unimplemented
Read as ‘0’
270h
Common RAM
(Accesses
70h – 7Fh)
280h
2A0h
2F0h
Core Registers
(Table 3-2)
— 30Dh — 38Dh —
— 316h — 396h IOCBF
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
300h
Core Registers
(Table 3-2)
320h
Unimplemented
Read as ‘0’
36Fh 3EFh
370h
Common RAM
(Accesses
70h – 7Fh)
380h
3A0h
3F0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
2012-2014 Microchip Technology Inc. DS40001624C-page 21
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Ta bl e 3 -2 )
480h
48Bh
Core Registers
(Ta bl e 3 -2 )
500h
50Bh
Core Registers
(Ta bl e 3 -2 )
580h
58Bh
Core Registers
(Ta bl e 3 -2 )
600h
60Bh
Core Registers
(Ta bl e 3 -2 )
680h
68Bh
Core Registers
(Ta bl e 3 -2 )
700h
70Bh
Core Registers
(Ta bl e 3 -2 )
780h
78Bh
Core Registers
(Ta bl e 3 -2 )
40Ch
Unimplemented
Read as ‘0’
48Ch
Unimplemented
Read as ‘0’
50Ch
Unimplemented
Read as ‘0’
58Ch
Unimplemented
Read as ‘0’
60Ch
Unimplemented
Read as ‘0’
68Ch
Unimplemented
Read as ‘0’
70Ch
See Ta bl e 3 -6
78Ch
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Common RAM
(Accesses
70h – 7Fh)
4F0h
Common RAM
(Accesses
70h – 7Fh)
570h
Common RAM
(Accesses
70h – 7Fh)
5F0h
Common RAM
(Accesses
70h – 7Fh)
670h
Common RAM
(Accesses
70h – 7Fh)
6F0h
Common RAM
(Accesses
70h – 7Fh)
770h
Common RAM
(Accesses
70h – 7Fh)
7F0h
Common RAM
(Accesses
70h – 7Fh)
47Fh
4FFh 57Fh
5FFh 67Fh 6FFh 77Fh 7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Ta bl e 3 -2 )
880h
88Bh
Core Registers
(Ta bl e 3 -2 )
900h
90Bh
Core Registers
(Ta bl e 3 -2 )
980h
98Bh
Core Registers
(Ta bl e 3 -2 )
A00h
A0Bh
Core Registers
(Ta bl e 3 -2 )
A80h
A8Bh
Core Registers
(Ta bl e 3 -2 )
B00h
B0Bh
Core Registers
(Ta bl e 3 -2 )
B80h
B8Bh
Core Registers
(Ta bl e 3 -2 )
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh
9EFh
A6Fh
AEFh
B6Fh
BEFh
870h
Common RAM
(Accesses
70h – 7Fh)
8F0h
Common RAM
(Accesses
70h – 7Fh)
970h
Common RAM
(Accesses
70h – 7Fh)
9F0h
Common RAM
(Accesses
70h – 7Fh)
A70h
Common RAM
(Accesses
70h – 7Fh)
AF0h
Common RAM
(Accesses
70h – 7Fh)
B70h
Common RAM
(Accesses
70h – 7Fh)
BF0h
Common RAM
(Accesses
70h – 7Fh)
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta bl e 3 -2 )
C80h
C8Bh
Core Registers
(Ta bl e 3 -2 )
D00h
D0Bh
Core Registers
(Ta bl e 3 -2 )
D80h
D8Bh
Core Registers
(Ta bl e 3 -2 )
E00h
E0Bh
Core Registers
(Ta bl e 3 -2 )
E80h
E8Bh
Core Registers
(Ta bl e 3 -2 )
F00h
F0Bh
Core Registers
(Ta bl e 3 -2 )
F80h
F8Bh
Core Registers
(Ta bl e 3 -2 )
C0Ch
C6Fh
Unimplemented
Read as ‘0’
C8Ch
CEFh
Unimplemented
Read as ‘0’
D0Ch
D6Fh
Unimplemented
Read as ‘0’
D8Ch
DEFh
Unimplemented
Read as ‘0’
E0Ch
E6Fh
Unimplemented
Read as ‘0’
E8Ch
EEFh
Unimplemented
Read as ‘0’
F0Ch
F6Fh
Unimplemented
Read as ‘0’
F8Ch
FEFh
See (Ta bl e 3 -7 )
C70h
Common RAM
(Accesses
70h – 7Fh)
CF0h
Common RAM
(Accesses
70h – 7Fh)
D70h
Common RAM
(Accesses
70h – 7Fh)
DF0h
Common RAM
(Accesses
70h – 7Fh)
E70h
Common RAM
(Accesses
70h – 7Fh)
EF0h
Common RAM
(Accesses
70h – 7Fh)
F70h
Common RAM
(Accesses
70h – 7Fh)
FE0h
Common RAM
(Accesses
70h – 7Fh)
C7Fh
CFFh D7Fh DFFh E7Fh EFFh F7Fh FEFh
TABLE 3-5: PIC16(L)F1512/3 MEMORY MAP (BANKS 8-30)
PIC16(L)F1512/3
PIC16(L)F1512/3
Bank 14
700h
70Bh
Core Registers
(Table 3-2)
70Ch
710h
Unimplemented
Read as ‘0’
711h
AADCON0
712h
AADCON1
713h
AADCON2
714h
AADCON3
715h
AADSTAT
716h
AADPRE
717h
AADACQ
718h
AADGRD
719h
AADCAP
71Ah
AADRES0L
71Bh
AADRES0H
71Ch
AADRES1L
71Dh
AADRES1H
71Eh
—
71Fh
—
720h
76Fh
Unimplemented
Read as ‘0’
770h
Common RAM
(Accesses
70h – 7Fh)
77Fh
Bank 31
F80h
F8Bh
Core Registers
(Table 3-2)
F8Ch
FE3h
Unimplemented
Read as ‘0’
FE4h
STATUS_SHAD
FE5h
WREG_SHAD
FE6h
BSR_SHAD
FE7h
PCLATH_SHAD
FE8h
FSR0L_SHAD
FE9h
FSR0H_SHAD
FEAh
FSR1L_SHAD
FEBh
FSR1H_SHAD
FECh
—
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
FF0h
Common RAM
(Accesses
70h – 7Fh)
FFFh
TABLE 3-6: PIC16(L)F1512/3 MEMORY
MAP (BANK 14)
TABLE 3-7: PIC16(L)F1512/3 MEMORY
MAP (BANK 31)
Legend: = Unimplemented data memory locations,
Legend: = Unimplemented data memory locations,
DS40001624C-page 22 2012-2014 Microchip Technology Inc.
read as ‘0’.
read as ‘0’.
PIC16(L)F1512/3
3.2.6 CORE FUNCTION REGISTERS SUMMARY
The Core Function Registers listed in Tab l e 3 -8 can be
addressed from any Bank.
TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0-31
x00h or
INDF0
x80h
x01h or
INDF1
x81h
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
— — —TOPD ZDCC---1 1000 ---q quuu
— — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
Shaded locations are unimplemented, read as ‘0’.
Val ue o n
POR, BOR
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on all
other Resets
2012-2014 Microchip Technology Inc. DS40001624C-page 23
PIC16(L)F1512/3
3.2.7 SPECIAL FUNCTION REGISTERS SUMMARY
The Special Function Registers are listed in Tab le 3 - 9.
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Val ue o n
POR, BOR
Bank 0
00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
00Fh
— Unimplemented — —
010h PORTE
011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF
013h
— Unimplemented — —
014h
— Unimplemented — —
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111
01Ch T2CON
01Dh
— Unimplemented — —
01Eh
— Unimplemented — —
01Fh
— Unimplemented — —
— — — —RE3— — — ---- x--- ---- u---
— — —BCLIF— — CCP2IF 0--- 0--0 0--- 0--0
—TMR1ON0000 00-0 uuuu uu-u
T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
Bank 1
08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111
08Fh
— Unimplemented — —
090h TRISE
091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE
093h
— Unimplemented — —
094h
— Unimplemented — —
095h
OPTION_REG
096h PCON STKOVF STKUNF
097h WDTCON
098h
— Unimplemented — —
099h OSCCON
09Ah OSCSTAT SOSCR
09Bh ADRES0L
09Ch ADRES0H
09Dh ADCON0
09Eh ADCON1
09Fh
— Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: PIC16F1512/3 only.
(3)
(3)
(3)
(3)
Shaded locations are unimplemented, read as ‘0’.
2: Unimplemented, read as ‘1’.
3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.
— — — — —
— — —BCLIE— — CCP2IE 0--- 0--0 0--- 0--0
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu
— — WDTPS<4:0> SWDTEN --01 0110 --01 0110
—
—OSTSHFIOFR— — LFIOFR HFIOFS 0-q0 --00 q-qq --0q
A/D Result Register Low xxxx xxxx uuuu uuuu
A/D Result Register High xxxx xxxx uuuu uuuu
—CHS<4:0>
ADFM ADCS<2:0> — —
IRCF<3:0>
(2)
— — — ---- 1--- ---- 1---
—SCS<1:0>-011 1-00 -011 1-00
GO/DONE
ADON -000 0000 -000 0000
ADPREF<1:0>
0000 --00 0000 --00
Value on all
other
Resets
DS40001624C-page 24 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Val ue o n
POR, BOR
Bank 2
10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu
10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu
10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu
10Fh
to
— Unimplemented — —
115 h
116h BORCON SBOREN BORFS
117h FVRCON FVREN FVRRDY TSEN TSRNG
118 h
to
— Unimplemented — —
11C h
11Dh APFCON
11Eh
— Unimplemented — —
11Fh
— Unimplemented — —
— — — — — — SSSEL CCP2SEL ---- --00 ---- --00
— — — — — BORRDY 10-- ---q uu-- ---u
— —ADFVR<1:0>0q00 --00 0q00 --00
Bank 3
18Ch ANSELA — —ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --1- 1111
18Dh ANSELB
18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2
18Fh
— Unimplemented — —
190h
— Unimplemented — —
191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH
193h PMDATL Program Memory Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH
195h PMCON1
196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON
198h
— Unimplemented — —
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000
19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: PIC16F1512/3 only.
2: Unimplemented, read as ‘1’.
3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.
(1)
Shaded locations are unimplemented, read as ‘0’.
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
— — 1111 1100 1111 1100
— Program Memory Address Register High Byte 1000 0000 1000 0000
— — Program Memory Data Register High Byte --xx xxxx --uu uuuu
(2)
—
— — — — — — VREGPM Reserved ---- --01 ---- --01
CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Value on all
other
Resets
2012-2014 Microchip Technology Inc. DS40001624C-page 25
PIC16(L)F1512/3
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Val ue o n
POR, BOR
Bank 4
20Ch — Unimplemented — —
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh
— Unimplemented — —
20Fh
— Unimplemented — —
210h WPUE
211h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSPADD Synchronous Serial Port (I
213h SSPMSK Synchronous Serial Port (I
214h SSPSTAT SMP CKE D/A
215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
to
— Unimplemented — —
21Fh
— — — — WPUE3 — — — ---- 1--- ---- 1---
2
C™ mode) Address Register 0000 0000 0000 0000
2
C™ mode) Address Mask Register 1111 1111 1111 1111
PSR/WUA BF 0000 0000 0000 0000
Bank 5
28Ch
— Unimplemented — —
to
290h
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON
294h
to
— Unimplemented — —
297h
298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON
29Bh
to
— Unimplemented — —
29Fh
— — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000
— — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000
Bank 6
30Ch
— Unimplemented — —
to
31Fh
Bank 7
38Ch
to
— Unimplemented — —
393h
394h IOCBP IOCBP<7:0> 0000 0000 0000 0000
395h IOCBN IOCBN<7:0> 0000 0000 0000 0000
396h IOCBF IOCBF<7:0> 0000 0000 0000 0000
397h
to
— Unimplemented — —
39Fh
Bank 8-13
x0Ch
or
x8Ch
— Unimplemented — —
to
x1Fh
or
x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: PIC16F1512/3 only.
Shaded locations are unimplemented, read as ‘0’.
2: Unimplemented, read as ‘1’.
3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.
Value on all
other
Resets
DS40001624C-page 26 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Val ue o n
POR, BOR
Bank 14
70ch
— Unimplemented — —
to
710h
711h AADCON0
712h AADCON1
713h AADCON2
714h AADCON3 ADEPPOL ADIPPOL ADOLEN ADOEN ADOOEN
715h AADSTAT
716h AADPRE
717h AADACQ
718h AADGRD GRDBOE GRDAOE GRDPOL
719h AADCAP
71Ah AADRES0L
71Bh AADRES0H
71Ch AADRES1L A/D Result 1 Register Low xxxx xxxx uuuu uuuu
71Dh AADRES1H A/D Result 1 Register High xxxx xxxx uuuu uuuu
71Eh
— Unimplemented — —
(3)
(3)
(3)
(3)
—CHS<4:0>
ADFM ADCS<2:0> — —
—TRIGSEL<2:0>— — — — -000 ---- -000 ----
— — — — — ADCONV ADSTG<1:0> ---- -000 ---- -000
— ADPRE<6:0> -000 0000 -000 0000
— ADACQ<6:0> -000 0000 -000 0000
— — — — — 000- ---- 000- ----
— — — — — ADDCAP<2:0> ---- -000 ---- -000
A/D Result 0 Register Low xxxx xxxx uuuu uuuu
A/D Result 0 Register High xxxx xxxx uuuu uuuu
GO/DONE
— ADIPEN ADDSEN 0000 0-00 0000 0-00
ADON -000 0000 -000 0000
ADPREF<1:0>
0000 --00 0000 --00
Bank 15-30
x0Ch
or
x8Ch
— Unimplemented — —
to
x1Fh
or
x9Fh
Bank 31
F8Ch
— Unimplemented — —
to
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD Working Register Shadow xxxx xxxx uuuu uuuu
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu
FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu
FECh
— Unimplemented — —
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: PIC16F1512/3 only.
Shaded locations are unimplemented, read as ‘0’.
2: Unimplemented, read as ‘1’.
3: This register is available in Bank 1 and Bank 14 under similar register names. See Table 16-4.
— — — — —ZDCC---- -xxx ---- -uuu
— — — Bank Select Register Shadow ---x xxxx ---u uuuu
— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
— — — Current Stack Pointer ---1 1111 ---1 1111
Top of Stack Low Byte xxxx xxxx uuuu uuuu
— Top of Stack High Byte -xxx xxxx -uuu uuuu
Value on all
other
Resets
2012-2014 Microchip Technology Inc. DS40001624C-page 27
PIC16(L)F1512/3
PCLPCH
0
14
PC
06
7
ALU Result
8
PCLATH
PCLPCH
0
14
PC
06
4
OPCODE <10:0>
11
PCLATH
PCLPCH
0
14
PC
06
7
W
8
PCLATH
Instruction with
PCL as
Destination
GOTO, CALL
CALLW
PCL
PCH
0
14
PC
PC + W
15
BRW
PCLPCH
0
14
PC
PC + OPCODE <8:0>
15
BRA
3.3 PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
FIGURE 3-4: LOADING OF PC IN
DIFFERENT SITUATIONS
3.3.3 COMPUTED FUNCTION CALLS
A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed calls by
combining PCLATH and W to form the destination
address. A computed CALLW is accomplished by
loading the W register with the desired address and
executing CALLW. The PCL register is loaded with the
value of W and PCH is loaded with PCLATH.
3.3.4 BRANCHING
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
3.3.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the PC to be changed by writing the desired
upper seven bits to the PCLATH register. When the
lower eight bits are written to the PCL register, all 15
bits of the PC will change to the values contained in the
PCLATH register and those being written to the PCL
register.
3.3.2 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to
the PC (ADDWF PCL). When performing a table read
using a computed GOTO method, care should be
exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, “Implementing a Table Read” (DS00556).
DS40001624C-page 28 2012-2014 Microchip Technology Inc.
PIC16(L)F1512/3
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x0000
STKPTR = 0x1F
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x1F STKPTR = 0x1F
Stack Reset Disabled
(STVREN = 0)
Stack Reset Enabled
(STVREN = 1)
TOSH:TOSL
TOSH:TOSL
3.4 Stack
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-5 through 3-8). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Word 2). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an
Overflow/Underflow, regardless of whether the Reset is
enabled.
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
3.4.1 ACCESSING THE STACK
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
Note: Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement STKPTR.
Reference Figure 3-5 through 3-8 for examples of
accessing the stack.
FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1
2012-2014 Microchip Technology Inc. DS40001624C-page 29
PIC16(L)F1512/3
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
Return Address0x00
STKPTR = 0x00
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
TOSH:TOSL
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
Return Address0x06
Return Address0x05
Return Address0x04
Return Address0x03
Return Address0x02
Return Address0x01
Return Address0x00
STKPTR = 0x06
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
TOSH:TOSL
FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2
FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3
DS40001624C-page 30 2012-2014 Microchip Technology Inc.
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