Datasheet PIC16F1508, PIC16F1509, PIC16LF1508, PIC16LF1509 Datasheet

PIC16(L)F1508/9

Data Sheet

20-Pin Flash, 8-Bit Microcontrollers

with nanoWatt XLP Technology

 2011 Microchip Technology Inc. Preliminary DS41609A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-726-3

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41609A-page 2 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• Up to 14 Kbytes Linear Program Memory
Addressing

• Up to 512 bytes Linear Data Memory Addressing

• Operating Speed:

- DC – 20 MHz clock input

- DC – 200 ns instruction cycle

• Interrupt Capability with Automatic Context
Saving

• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator Block:

- Factory calibrated to ±1%, typical

- Software selectable frequency range from

16 MHz to 31 kHz

• 31 kHz Low-Power Internal Oscillator

• Three External Clock modes up to 20 MHz

Special Microcontroller Features:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1508/9)

- 2.3V to 5.5V (PIC16F1508/9)

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Programmable Low-Power Brown-Out Reset
(LPBOR)

• Extended Watchdog Timer (WDT):

- Programmable period from 1 ms to 256s

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via Two
Pins

• Enhanced Low-Voltage Programming (LVP)

• In-Circuit Debug (ICD) via two pins

• Power-Saving Sleep mode:

- Low-Power Sleep mode

- Low-Power BOR (LPBOR)

• Integrated Temperature Indicator

• 128 Bytes High-Endurance Flash

- 100,000 write Flash endurance (minimum)

Extreme Low-Power Management with nanoWatt XLP (PIC16LF1508/9):

• Standby Current:

- 25 nA @ 1.8V, typical

• Watchdog Timer Current:

- 300 nA @ 1.8V, typical

• Operating Current:

-30 A/MHz @ 1.8V, typical

• Timer1 Oscillator Current:

- 600 nA @ 32 kHz, 1.8V, typical

Peripheral Features:

• Analog-to-Digital Converter (ADC):

- 10-bit resolution

- 12 external channels

- 3 internal channels:

- Fixed Voltage Reference

- Digital-to-Analog Converter

- Temperature Indicator channel

- Auto acquisition capability

- Conversion available during Sleep

• 2 Comparators:

- Rail-to-rail inputs

- Power mode control

- Software controllable hysteresis

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- Up to 1 rail-to-rail resistive 5-bit DAC with
positive reference selection

• 18 I/O Pins (1 Input-only Pin):

- High current sink/source 25 mA/25 mA

- Individually programmable weak pull-ups

- Individually programmable
interrupt-on-change (IOC) pins

• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler

• Four 10-bit PWM modules

• Master Synchronous Serial Port (MSSP) with SPI

2

C™ with:

and I

- 7-bit address masking

- SMBus/PMBus™ compatibility

 2011 Microchip Technology Inc. Preliminary DS41609A-page 3

PIC16(L)F1508/9

Peripheral Features (Continued):

• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

- Auto-wake-up on Start

• 4 Configurable Logic Cell (CLC) modules:

- 16 selectable input source signals

- Four inputs per module

- Software control of combinational/sequential

logic/state/clock functions

- AND/OR/XOR/D Flop/D Latch/SR/JK

- External or internal inputs/outputs

- Operation while in Sleep

• Numerically Controlled Oscillator (NCO):

- 20-bit accumulator

- 16-bit increment

- True linear frequency control

- High-speed clock input

- Selectable Output modes

- Fixed Duty Cycle (FDC) mode

- Pulse Frequency (PF) mode

• Complementary Waveform Generator (CWG):

- 8 selectable signal sources

- Selectable falling and rising edge dead-band
control

- Polarity control

- 4 auto-shutdown sources

- Multiple input sources: PWM, CLC, NCO

PIC12(L)F1501/PIC16(F)L150X Family Types

C/SPI)

2

CLC

EUSART

CWG

MSSP (I

(bytes)

Data SRAM

(2)

I/O’s

10-bit ADC (ch)

DAC

Timers

Comparators

PWM

(8/16-bit)

Device

Data Sheet Index

PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 — — 1 2 1 H —
PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 — 1 1 2 1 H —
PIC16(L)F1507 (3) 2048 128 18 12 — — 2/1 4 — — 1 2 1 H —
PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y
PIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: Future Product
2: DS41607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.
3: DS41586
4: DS41609 PIC16(L)F1508/1509 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.

Flash (words)

Program Memory

PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.

(1)

NCO

Debug

XLP

DS41609A-page 4 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

PIC16F1508/9

PIC16LF1508/9

1

2
3
4

14

13

12

11

5
6

7

10

9

8

VDD

RA5
RA4

MCLR/VPP/RA3

RC5

RC4

V

SS

RA0/ICSPDAT

RA1/ICSPCLK
RA2

RC0

RC1
RC2

RC3

PDIP, SOIC, SSOP

Note: See Tab le 1 for location of all peripheral functions.

18
17

16

15

20
19

RC6

RC7

RB7

RB4

RB5
RB6

PIC16F1508/9
PIC16LF1508/9

QFN 4x4

Note: See Tab le 1 for location of all peripheral functions.

15

RA1/ICSPCLK

RA2

RC0

RC1

RC2

11

12

13

14

6

7

RC7

RB7

RB4

RB5

RB6

8

9

10

2

3

1

18

1920

16

17

5

4

VDD

RA5

RA4

MCLR/VPP/RA3

RC5

RC4

RC3

RC6

VSS

RA0/ICSPDAT

FIGURE 1: 20-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1508/9

FIGURE 2: 20-PIN QFN PACKAGE DIAGRAM FOR PIC16(L)F1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 5

PIC16(L)F1508/9

TABLE 1: 20-PIN ALLOCATION TABLE (PIC16(L)F1508/9)

I/O

20-Pin PDIP/SOIC/SSOP

RA0 19 16 AN0 DACOUT1 C1IN+ — —

RA1 18 15 AN1 VREF+ C1IN0-

RA2 17 14 AN2 DACOUT2 C1OUT T0CKI

RA3 4 1 — — — T1G

RA4 3 20 AN3 — — SOSCO

RA5 2 19 — — — SOSCI

RB4 13 10 AN10 — — — — SDA/SDI — — CLC3IN0 — IOC Y —

RB5 12 9 AN11 — — —RX/DT— — — CLC4IN0 — IOC Y —

RB6 11 8 — — — — — SCL/SCK — — — — IOC Y —

RB7 10 7 — — — —TX/CK— — — CLC3 — IOC Y —

RC0 16 13 AN4 — C2IN+ — — — — — CLC2 — — — —

RC1 15 12 AN5 — C1IN1-

RC2 14 11 AN6 — C1IN2-

RC3 7 4 AN7 — C1IN3- ——— — — CLC2IN0 PWM2 — — —

RC4 6 3 — — C2OUT — — — CWG1B — CLC4

RC5 5 2 — — — ———CWG1A — CLC1

RC6 8 5 AN8 — — — — SS

RC7 9 6 AN9 — — ——SDO — — CLC1IN1 — — — —

VDD 1 18 — — — — — — — — — — — — VDD

VSS 2017—— — ——— — — — ———VSS

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

A/D

20-Pin QFN

Reference

Comparator

C2IN0-

C2IN1-

C2IN2-

Timers

——— — — CLC4IN1 — IOC Y ICSPCLK

(2)

(1)

T1G

T1CKI

——— — NCO1

— — — — — — — — — —

EUSART

— —

—SS

— — — — — — IOC Y CLKOUT

—— — NCO1CLK — — IOC Y CLKIN

MSSP

—

(2)

(1)

CWG

— — — — IOC Y ICSPDAT

CWG1FLT — CLC1

— — CLC1IN0 — IOC Y MCLR

— NCO1

NCO

(1)

(2)

CLC

(1)

— PWM4 — — —

CLC2IN1

(2)

CLC3IN1 — — — —

PWM

PWM3 INT/

IOC

— — — —

PWM1 — — —

Interrupt

Pull-up

ICDDAT

ICDCLK

Y —

OSC2

OSC1

Basic

VPP

DS41609A-page 6 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15

3.0 Memory Organization................................................................................................................................................................. 17

4.0 Device Configuration.................................................................................................................................................................. 43

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 49

6.0 Resets ........................................................................................................................................................................................ 65

7.0 Interrupts .................................................................................................................................................................................... 73

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 87

9.0 Watchdog Timer......................................................................................................................................................................... 91

10.0 Flash Program Memory Control ................................................................................................................................................. 95

11.0 I/O Ports ................................................................................................................................................................................... 111

12.0 Interrupt-On-Change ................................................................................................................................................................ 125

13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 131

14.0 Temperature Indicator Module ................................................................................................................................................. 133

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 135

16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 149

17.0 Comparator Module.................................................................................................................................................................. 153

18.0 Timer0 Module ......................................................................................................................................................................... 163

19.0 Timer1 Module with Gate Control............................................................................................................................................. 167

20.0 Timer2 Module ......................................................................................................................................................................... 179

21.0 Master Synchronous Serial Port Module.................................................................................................................................. 183

22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237

23.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 265

24.0 Configurable Logic Cell (CLC).................................................................................................................................................. 271

25.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 287

26.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 297

27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 313

28.0 Instruction Set Summary.......................................................................................................................................................... 315

29.0 Electrical Specifications............................................................................................................................................................ 329

30.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 357

31.0 Development Support............................................................................................................................................................... 359

32.0 Packaging Information.............................................................................................................................................................. 363

Appendix A: Data Sheet Revision History.......................................................................................................................................... 373

Index .................................................................................................................................................................................................. 375

The Microchip Web Site..................................................................................................................................................................... 381

Customer Change Notification Service .............................................................................................................................................. 381

Customer Support .............................................................................................................................................................................. 381

Reader Response .............................................................................................................................................................................. 382

Product Identification System ............................................................................................................................................................ 383

 2011 Microchip Technology Inc. Preliminary DS41609A-page 7

PIC16(L)F1508/9

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS41609A-page 8 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

1.0 DEVICE OVERVIEW

The PIC16(L)F1508/9 are described within this data
sheet. They are available in 14-pin packages. Figure 1-1
shows a block diagram of the PIC16(L)F1508/9 devices.
Tables 1-2 shows the pinout descriptions.

Reference Ta bl e 1 -1 for peripherals available per
device.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral

PIC16F1501

Analog-to-Digital Converter (ADC) ● ● ● ● ● ●●●
Complementary Wave Generator (CWG)
Digital-to-Analog Converter (DAC) ● ● ● ● ●●
Enhanced Universal

Synchronous/Asynchronous
Receiver/Transmitter (EUSART)

Fixed Voltage Reference (FVR) ● ● ● ● ● ●●●
Numerically Controlled Oscillator (NCO)
Temperature Indicator ● ● ● ● ● ●●●
Comparators

Configurable Logic Cell (CLC)

CLC1 ● ● ● ● ● ●●●
CLC2 ● ● ● ● ● ●●●
CLC3 ●●
CLC4

Master Synchronous Serial Ports

MSSP1 ● ● ●●

PWM Modules

PWM1 ● ● ● ● ● ●●●
PWM2 ● ● ● ● ● ●●●
PWM3
PWM4 ● ● ● ● ● ●●●

Timers

Timer0 ● ● ● ● ● ●●●
Timer1 ● ● ● ● ● ●●●
Timer2 ● ● ● ● ● ●●●

● ● ● ● ● ●●●

● ● ● ● ● ●●●

C1 ● ● ● ● ●●
C2 ● ● ●●

● ● ● ● ● ●●●

PIC16F1503

PIC16LF1501

PIC16F1507

PIC16LF1503

PIC16LF1507

●●

●●

PIC16F1508/9

PIC16LF1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 9

PIC16(L)F1508/9

PORTC

Note 1: See applicable chapters for more information on peripherals.

2: See Tab l e 1 - 1 for peripherals available on specific devices.

CPU

Program

Flash Memory

RAM

Timi ng

Generation

INTRC

Oscillator

MCLR

(Figure 2-1)

NCO1

PWM4

Timer2Timer1Timer0

CLC4

PWM1 PWM2

PWM3

PORTA

CWG1

CLC3

ADC

10-Bit

FVR

Te mp .

Indicator

OSC1/CLKIN

OSC2/CLKOUT

MSSP1

C2C1

DAC

PORTB

CLC2CLC1

EUSART

FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM

DS41609A-page 10 Preliminary  2011 Microchip Technology Inc.

TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION

Input

Name Function

Typ e

Output

Typ e

PIC16(L)F1508/9

Description

RA0/AN0/C1IN+/DACOUT1/
ICSPDAT/ICDDAT

RA1/AN1/CLC4IN1/V
C1IN0-/C2IN0-/ICSPCLK/
ICDCLK

RA2/AN2/C1OUT/DACOUT2/
T0CKI/INT/PWM3/CLC1
CWG1FLT

RA3/CLC1IN0/V
MCLR

RA4/AN3/SOSCO/
CLKOUT/T1G

RA5/CLKIN/T1CKI/NCO1CLK/
SOSCI

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

REF+/

PP/T1G

(1)

/

(2)

(2)

/SS

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel input.

C1IN+ AN — Comparator positive input.

DACOUT1 — AN Digital-to-Analog Converter output.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST CMOS In-Circuit Debug data.

RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel input.

CLC4IN1 ST — Configurable Logic Cell source input.

REF+ AN — A/D Positive Voltage Reference input.

V

C1IN0- AN — Comparator negative input.

C2IN0- AN — Comparator negative input.

ICSPCLK ST — ICSP Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

RA2 ST CMOS General purpose I/O.

AN2 AN — A/D Channel input.

C1OUT — CMOS Comparator output.

DACOUT2 — AN Digital-to-Analog Converter output.

T0CKI ST — Timer0 clock input.

INT ST — External interrupt.

PWM3 — CMOS PWM output.

CLC1 — CMOS Configurable Logic Cell source output.

CWG1FLT

/

RA3 TTL — General purpose input with IOC and WPU.

CLC1IN0 ST — Configurable Logic Cell source input.

PP HV — Programming voltage.

V

T1G ST — Timer1 Gate input.

SS

MCLR

RA4 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

CLKOUT — CMOS F

T1G ST — Timer1 Gate input.

RA5 TTL CMOS General purpose I/O.

CLKIN CMOS — External clock input (EC mode).

T1CKI ST — Timer1 clock input.

NCO1CLK ST — Numerically Controlled Oscillator Clock source input.

SOSCI XTAL XTAL Secondary Oscillator Connection.

ST — Complementary Waveform Generator Fault input.

ST — Slave Select input.

ST — Master Clear with internal pull-up.

OSC/4 output.

2

C™ = Schmitt Trigger input with I2C

 2011 Microchip Technology Inc. Preliminary DS41609A-page 11

PIC16(L)F1508/9

TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RB4/AN10/CLC3IN0/SDA/SDI RB4 TTL CMOS General purpose I/O.

AN10 AN — A/D Channel input.

CLC3IN0 ST — Configurable Logic Cell source input.

SDA I

SDI CMOS — SPI data input.

RB5/AN11/CLC4IN0/RX/DT RB5 TTL CMOS General purpose I/O.

AN11 AN — A/D Channel input.

CLC4IN0 ST — Configurable Logic Cell source input.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.

SCL I

SCK ST CMOS SPI clock.

RB7/CLC3/TX/CK RB7 TTL CMOS General purpose I/O.

CLC3 — CMOS Configurable Logic Cell source output.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC0/AN4/CLC2/C2IN+ RC0 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel input.

CLC2 — CMOS Configurable Logic Cell source output.

C2IN+ AN — Comparator positive input.

RC1/AN5/C1IN1-/C2IN1-/PWM4/

(1)

NCO1

RC2/AN6/C1IN2-/C2IN2- RC2 TTL CMOS General purpose I/O.

RC3/AN7/C1IN3-/PWM2/
CLC2IN0

RC4/C2OUT/CLC2IN1/CLC4/
CWG1B

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

HV = High Voltage XTAL = Crystal levels

2: Alternate location for peripheral pin function selected by the APFCON register.

RC1 TTL CMOS General purpose I/O.

AN5 AN — A/D Channel input.

C1IN1- AN — Comparator negative input.

C2IN1- AN — Comparator negative input.

PWM4 — CMOS PWM output.

NCO1 — CMOS Numerically Controlled Oscillator is source output.

AN6 AN — A/D Channel input.

C1IN2- AN — Comparator negative input.

C2IN2- AN — Comparator negative input.

RC3 TTL CMOS General purpose I/O.

AN7 AN — A/D Channel input.

C1IN3- AN — Comparator negative input.

PWM2 — CMOS PWM output.

CLC2IN0 ST — Configurable Logic Cell source input.

RC4 TTL CMOS General purpose I/O.

C2OUT — CMOS Comparator output.

CLC2IN1 ST — Configurable Logic Cell source input.

CLC4 — CMOS Configurable Logic Cell source output.

CWG1B — CMOS CWG complementary output.

Output

Typ e

Typ e

2

CODI2C data input/output.

2

CODI2C™ clock.

Description

2

C™ = Schmitt Trigger input with I2C

DS41609A-page 12 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RC5/PWM1/CLC1
CWG1A

RC6/AN8/NCO1

(1)

SS

RC7/AN9/CLC1IN1/SDO RC7 TTL CMOS General purpose I/O.

DD VDD Power — Positive supply.

V

SS VSS Power — Ground reference.

V

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

(2)

/

(2)

/CLC3IN1/

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

RC5 TTL CMOS General purpose I/O.

PWM1 — CMOS PWM output.

CLC1 — CMOS Configurable Logic Cell source output.

CWG1A — CMOS CWG primary output.

RC6 TTL CMOS General purpose I/O.

AN8 AN — A/D Channel input.

NCO1 — CMOS Numerically Controlled Oscillator source output.

CLC3IN1 ST — Configurable Logic Cell source input.

SS

AN9 AN — A/D Channel input.

CLC1IN1 ST — Configurable Logic Cell source input.

SDO — CMOS SPI data output.

Output

Typ e

Typ e

ST — Slave Select input.

Description

2

C™ = Schmitt Trigger input with I2C

 2011 Microchip Technology Inc. Preliminary DS41609A-page 13

PIC16(L)F1508/9

NOTES:

DS41609A-page 14 Preliminary  2011 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically
saved in Shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.

PIC16(L)F1508/9

2.2 16-Level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under­flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft­ware Reset. See section Section 3.4 “Stack” for more
details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See

Section 28.0 “Instruction Set Summary” for more

details.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 15

PIC16(L)F1508/9

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Instruction
Decode &

Control

Timing

Generation

CLKIN

CLKOUT

8

8

12

3

Internal

Oscillator

Block

Configuration

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction
Decode &

Control

Timing

Generation

8

8

3

Internal

Oscillator

Block

Configuration

15

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

8

8

3

Internal

Oscillator

Block

Configuration

Flash

Program

Memory

RAM

FSR regFSR reg

FSR1 Reg

15

15

MUX

15

Program Memory

Read (PMR)

12

FSR regFSR reg

BSR Reg

5

Power-up

Timer

Power-on

Reset

Watchdog

Timer

V

DD

Brown-out

Reset

VSSVDD VSSVDD VSS

FIGURE 2-1: CORE BLOCK DIAGRAM

DS41609A-page 16 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and
control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented. Accessing a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (See

Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device

PIC16F1508
PIC16LF1508

PIC16F1509
PIC16LF1509

Note 1: High-endurance Flash applies to low byte of each address in the range.

Program Memory

Space (Words)

4,096 0FFFh 0F80h-0FFFh

8,192 1FFFh 1F80h-1FFFh

Last Program Memory

Address

High-Endurance Flash

Memory Address Range

(1)

 2011 Microchip Technology Inc. Preliminary DS41609A-page 17

PIC16(L)F1508/9

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh
1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh
1000h

7FFFh

Page 1

Rollover to Page 3

Page 2

Page 3

17FFh
1800h

1FFFh
2000h

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR
PIC16(L)F1508

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR
PIC16(L)F1509

DS41609A-page 18 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

constants

BRW ;Add Index in W to

;program counter to

;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in pro­gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by set­ting bit 7 of the FSRxH register and reading the match­ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro­gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access­ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a
location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

The BRW instruction makes this type of table very sim­ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 19

PIC16(L)F1508/9

Addresses BANKx

x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR

x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper 7-bits
of the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta b l e 3 -2 . For detailed
information, see Tab le 3 -8 .

TABLE 3-2: CORE REGISTERS

DS41609A-page 20 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 28.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in
subtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

TO

PD ZDC

(1)

(1)

C

bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(1)

(1)

 2011 Microchip Technology Inc. Preliminary DS41609A-page 21

PIC16(L)F1508/9

0Bh

0Ch

1Fh

20h

6Fh
70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the appro­priate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all
banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

DS41609A-page 22 Preliminary  2011 Microchip Technology Inc.

3.2.5 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1508/9 are as shown
in Table 3-5 and Tab le 3 - 6.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 23

TABLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 1-7

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 -2 )

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh
00Fh
010h
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h
014h
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
—090h—110h—190h—210h—290h

—094h— 114h CM2CON1 194h PMDATH 214h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h
TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h
T1CON 098h

T1GCON 099h OSCCON 119h

TMR2 09Ah OSCSTAT 11Ah

PR2 09BhADRESL11Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON 19Dh
—
—

080h

Core Registers

(Ta bl e 3 -2 )

—118h

09Eh ADCON1 11Eh
09Fh ADCON2 11Fh

0A0h

100h

120h

Core Registers

(Table 3-2)

DACCON0
DACCON1

—19Ah
—19Bh
— 19Ch

—
—19Fh

180h

Core Registers

(Table 3-2)

198h —218h
199h

19Eh

1A0h

RCREG

TXREG
SPBRG

SPBRGH

RCSTA
TXSTA

BAUDCON

200h

Core Registers

(Table 3-2)

SSP1BUF
SSP1ADD
SSP1MSK

SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3

219h
21Ah —29Ah—31Ah—39Ah—
21Bh —29Bh—31Bh
21Ch — 29Ch — 31Ch
21Dh
21Eh
21Fh

220h

280h

Core Registers

(Table 3-2)

— 30Ch — 38Ch —

—28Eh—30Eh—38Eh—

291h
292h
293h
294h
295h
296h

297h
—
—299h— 319h — 399h —

—
—
—

298h

29Dh

29Eh

29Fh

2A0h

— 30Dh — 38Dh —

—
—
—
—
—
—
— 316h — 396h IOCBF
— 317h — 397h —
— 318h — 398h —

—
—
—

300h

310h
311h
312h
313h
314h
315h

31Dh
31Eh
31Fh

320h

Core Registers

(Table 3-2)

— 390h —
—
—
—
—
—

—
—
—
—
—

380h

Core Registers

(Table 3-2)

391h IOCAP
392h IOCAN
393h
394h IOCBP
395h IOCBN

39Bh
39Ch
39Dh
39Eh
39Fh

3A0h

IOCAF

—
—
—
—
—

General
Purpose
Register

80 Bytes

06Fh
070h

Common RAM

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

0EFh
0F0h

General
Purpose
Register

80 Bytes

Common RAM

(Accesses
70h – 7Fh)

General
Purpose
Register

80 Bytes

16Fh 1EFh 26Fh 2EFh
170h

Common RAM

(Accesses

70h – 7Fh)

1F0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

270h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

2F0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

Unimplemented

Read as ‘0’

36Fh 3EFh
370h

Common RAM

(Accesses
70h – 7Fh)

3F0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

PIC16(L)F1508/9

DS41609A-page 24 Preliminary  2011 Microchip Technology Inc.

TABLE 3-4: PIC16(L)F1509 MEMORY MAP, BANK 1-7

PIC16(L)F1508/9

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 -2 )

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh
00Fh
010h
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h
014h
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh

020h

06Fh
070h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
—090h—110h—190h—210h—290h

—094h— 114h CM2CON1 194h PMDATH 214h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h
TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h
T1CON 098h

T1GCON 099h OSCCON 119h

TMR2 09Ah OSCSTAT 11Ah

PR2 09BhADRESL11Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON 19Dh
—
—

General
Purpose
Register

80 Bytes

Common RAM

080h

Core Registers

(Ta bl e 3 -2 )

—118h

09Eh ADCON1 11Eh
09Fh ADCON2 11Fh
0A0h

General
Purpose
Register
80 Bytes

0EFh
0F0h

Common RAM

(Accesses
70h – 7Fh)

100h

120h

16Fh 1EFh 26Fh 2EFh
170h

Core Registers

(Table 3-2)

DACCON0
DACCON1

—19Ah
—19Bh
— 19Ch

—
—19Fh

General
Purpose
Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

180h

Core Registers

(Table 3-2)

198h —218h
199h

19Eh

1A0h

1F0h

RCREG

TXREG
SPBRG

SPBRGH

RCSTA
TXSTA

BAUDCON

General
Purpose
Register
80 Bytes

Common RAM

(Accesses
70h – 7Fh)

200h

Core Registers

(Table 3-2)

SSP1BUF
SSP1ADD
SSP1MSK

SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3

219h
21Ah —29Ah—31Ah—39Ah—
21Bh —29Bh—31Bh
21Ch — 29Ch — 31Ch
21Dh
21Eh
21Fh

220h

270h

General
Purpose
Register
80 Bytes

Common RAM

(Accesses
70h – 7Fh)

280h

Core Registers

(Table 3-2)

— 30Ch — 38Ch —

—28Eh—30Eh—38Eh—

291h
292h
293h
294h
295h
296h

297h
—
—299h— 319h — 399h —

—
—
—

298h

29Dh

29Eh

29Fh

2A0h

2F0h

— 30Dh — 38Dh —

—
—
—
—
—
—
— 316h — 396h IOCBF
— 317h — 397h —
— 318h — 398h —

—
—
—

General
Purpose
Register

80 Bytes

Common RAM

(Accesses
70h – 7Fh)

300h

Core Registers

(Table 3-2)

310h
311h
312h
313h
314h
315h

31Dh
31Eh
31Fh
320h General Purpose

36Fh 3EFh
370h

— 390h —
—
—
—
—
—

—
—
—
—
—

Register
16Bytes 3A0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

380h

391h IOCAP
392h IOCAN
393h
394h IOCBP
395h IOCBN

39Bh
39Ch
39Dh
39Eh
39Fh

3F0h

Core Registers

(Table 3-2)

IOCAF

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

—
—
—
—
—

 2011 Microchip Technology Inc. Preliminary DS41609A-page 25

TABLE 3-5: PIC16(L)F1508/9 MEMORY MAP, BANK 8-23

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh

420h

Core Registers

(Ta bl e 3 -2 )

— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
— 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —
—48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh—
—48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh—
—490h—510h—590h—610h—690h— 710h — 790h —
—491h—511h—591h— 611h PWM1DCL 691h CWG1DBR 711h — 791h —
—492h—512h—592h— 612h PWM1DCH 692h CWG1DBF 712h — 792h —
—493h—513h—593h— 613h PWM1CON 693h CWG1CON0 713h — 793h —
—494h—514h—594h— 614h PWM2DCL 694h CWG1CON1 714h — 794h —
—495h—515h—595h— 615h PWM2DCH 695h CWG1CON2 715h — 795h —
—496h—516h—596h— 616h PWM2CON 696h — 716h — 796h —
—497h—517h—597h— 617h PWM3DCL 697h — 717h — 797h —
— 498h NCO1ACCL 518h —598h— 618h PWM3DCH 698h — 718h — 798h —
— 499h NCO1ACCH 519h —599h— 619h PWM3CON 699h — 719h — 799h —
— 49Ah NCO1ACCU 51Ah —59Ah— 61Ah PWM4DCL 69Ah —71Ah—79Ah—
— 49Bh NCO1INCL 51Bh —59Bh— 61Bh PWM4DCH 69Bh —71Bh—79Bh—
— 49Ch NCO1INCH 51Ch — 59Ch — 61Ch PWM4CON 69Ch — 71Ch — 79Ch —
— 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh —
— 49Eh NCO1CON 51Eh —59Eh—61Eh—69Eh—71Eh—79Eh—
— 49Fh NCO1CLK 51Fh —59Fh—61Fh—69Fh—71Fh—79Fh—

480h

48Bh

4A0h

Core Registers

(Ta bl e 3 -2 )

500h

50Bh

520h

Core Registers

(Table 3-2)

580h

58Bh

5A0h

Core Registers

(Table 3-2)

600h

60Bh

620h

Core Registers

(Table 3-2)

680h

68Bh

6A0h

Core Registers

(Table 3-2)

700h

70Bh

720h

Core Registers

(Table 3-2)

780h

78Bh

7A0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 64Fh 6EFh 76Fh 7EFh
470h

Common RAM

(Accesses

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

70h – 7Fh)

4F0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

570h

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

5F0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

650h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

6F0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

770h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

7F0h

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

Core Registers

(Ta bl e 3 -2 )
80Bh
80Ch

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh
870h

Common RAM

(Accesses

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

70h – 7Fh)

880h

88Bh
88Ch

8F0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

900h

90Bh
90Ch

970h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

980h

98Bh
98Ch

9EFh
9F0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

A00h

A0Bh
A0Ch

A6Fh
A70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

A80h

A8Bh

A8Ch

AEFh
AF0h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

B00h

B0Bh
B0Ch

B6Fh
B70h

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

B80h

B8Bh
B8Ch

BEFh
BF0h

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses
70h – 7Fh)

PIC16(L)F1508/9

DS41609A-page 26 Preliminary  2011 Microchip Technology Inc.

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

C0Bh

Core Registers

(Ta bl e 3 -2 )

C80h

C8Bh

Core Registers

(Ta bl e 3 -2 )

D00h

D0Bh

Core Registers

(Ta bl e 3 -2 )

D80h

D8Bh

Core Registers

(Ta bl e 3 -2 )

E00h

E0Bh

Core Registers

(Ta bl e 3 -2 )

E80h

E8Bh

Core Registers

(Ta bl e 3 -2 )

F00h

F0Bh

Core Registers

(Ta bl e 3 -2 )

F80h

F8Bh

Core Registers

(Ta bl e 3 -2 )

C0Ch

—C8Ch—D0Ch—D8Ch—E0Ch—E8Ch—F0Ch

See Tab l e 3 - 7 for
register mapping

details

F8Ch

See Tab l e 3 - 7 for
register mapping

details

C0Dh

—C8Dh—D0Dh—D8Dh—E0Dh—E8Dh— F0Dh F8Dh

C0Eh

—C8Eh—D0Eh—D8Eh—E0Eh—E8Eh— F0Eh F8Eh

C0Fh

—C8Fh—D0Fh—D8Fh—E0Fh—E8Fh— F0Fh F8Fh

C10h

—C90h—D10h—D90h—E10h—E90h— F10h F90h

C11h

—C91h—D11h—D91h—E11h—E91h— F11h F91h

C12h

—C92h—D12h—D92h—E12h—E92h— F12h F92h

C13h

—C93h—D13h—D93h—E13h—E93h— F13h F93h

C14h

—C94h—D14h—D94h—E14h—E94h— F14h F94h

C15h

—C95h—D15h—D95h—E15h—E95h— F15h F95h

C16h

—C96h—D16h—D96h—E16h—E96h— F16h F96h

C17h

—C97h—D17h—D97h—E17h—E97h— F17h F97h

C18h

—C98h—D18h—D98h—E18h—E98h— F18h F98h

C19h

—C99h—D19h—D99h—E19h—E99h— F19h F99h

C1Ah

—C9Ah—D1Ah—D9Ah—E1Ah—E9Ah— F1Ah F9Ah

C1Bh

—C9Bh—D1Bh—D9Bh—E1Bh—E9Bh— F1Bh F9Bh

C1Ch

—C9Ch—D1Ch—D9Ch—E1Ch—E9Ch— F1Ch F9Ch

C1Dh

—C9Dh—D1Dh—D9Dh—E1Dh—E9Dh— F1Dh F9Dh

C1Eh

—C9Eh—D1Eh—D9Eh—E1Eh—E9Eh— F1Eh F9Eh

C1Fh

—C9Fh—D1Fh—D9Fh—E1Fh—E9Fh— F1Fh F9Fh

C20h

Unimplemented

Read as ‘0’

CA0h

Unimplemented

Read as ‘0’

D20h

Unimplemented

Read as ‘0’

DA0h

Unimplemented

Read as ‘0’

E20h

Unimplemented

Read as ‘0’

EA0h

Unimplemented

Read as ‘0’

F20h FA0h

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh

C70h

Common RAM

(Accesses

70h – 7Fh)

CF0h

Common RAM

(Accesses
70h – 7Fh)

D70h

Common RAM

(Accesses

70h – 7Fh)

DF0h

Common RAM

(Accesses
70h – 7Fh)

E70h

Common RAM

(Accesses

70h – 7Fh)

EF0h

Common RAM

(Accesses
70h – 7Fh)

F70h

Common RAM

(Accesses
70h – 7Fh)

FF0h

Common RAM

(Accesses
70h – 7Fh)

CFFh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-6: PIC16(L)F1508/9 MEMORY MAP, BANK 24-31

PIC16(L)F1508/9

TABLE 3-7: PIC16(L)F1508/9 MEMORY MAP, BANK 30-31

Bank 30

F0Ch

—

F0Dh

—

F0Eh

—

F0Fh

CLCDATA

F10h

CLC1CON

F11h

CLC1POL

F12h

CLC1SEL0

F13h

CLC1SEL1

F14h

CLC1GLS0

F15h

CLC1GLS1

F16h

CLC1GLS2

F17h

CLC1GLS3

F18h

CLC2CON

F19h

CLC2POL

F1Ah

CLC2SEL0

F1Bh

CLC2SEL1

F1Ch

CLC2GLS0

F1Dh

CLC2GLS1

F1Eh

CLC2GLS2

F1Fh

CLC2GLS3

F20h

CLC3CON

F21h

CLC3POL

F22h

CLC3SEL0

F23h

CLC3SEL1

F24h

CLC3GLS0

F25h

CLC3GLS1

F26h

CLC3GLS2

F27h

CLC3GLS3

F2Ah

CLC4CON

F2Bh

CLC4POL

F2Ch

CLC4SEL0

F2Dh

CLC4SEL1

F2Eh

CLC4GLS0

F2Fh

CLC4GLS1

F31h

CLC4GLS2

F31h

CLC4GLS3

F32h

Unimplemented

Read as ‘0’

F6Fh

Bank 31

F8Ch

FE3h

Unimplemented

Read as ‘0’

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

Legend: = Unimplemented data memory locations, read as ‘0’.

PIC16(L)F1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 27

PIC16(L)F1508/9

3.2.6 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3 -8 can be
addressed from any Bank.

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — —BSR<4:0>---0 0000 ---0 0000

— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

Shaded locations are unimplemented, read as ‘0’.

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Value on all

other Resets

DS41609A-page 28 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 0

00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx

00Dh PORTB RB7 RB6 RB5 RB4

00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx

00Fh

010h

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF

012h PIR2 OSFIF C2IF C1IF

013h PIR3

014h

015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu

018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000

01Bh PR2 Timer2 Period Register 1111 1111 1111 1111

01Ch T2CON

01Dh

01Eh

01Fh

— Unimplemented — —

— Unimplemented — —

— BCL1IF NCO1IF — — 000- -0-- 000- -0--

— — — — CLC4IF CLC3IF CLC2IF CLC1IF ---- 0000 ---- 0000

— Unimplemented — —

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— — — — xxxx ---- xxxx ----

— TMR2IF TMR1IF 0000 0-00 0000 0-00

—TMR1ON0000 00-0 uuuu uu-u

DONE

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

Bank 1

08Ch TRISA — — TRISA5 TRISA4 —

08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4

08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

08Fh

090h

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE

092h PIE2 OSFIE C2IE C1IE

093h PIE3

094h

095h

096h PCON STKOVF STKUNF

097h WDTCON

098h

099h OSCCON

09Ah OSCSTAT SOSCR

09Bh ADRESL xxxx xxxx uuuu uuuu

09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS<2:0>

09Fh ADCON2 TRIGSEL<3:0>

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.

— Unimplemented — —

— Unimplemented — —

— BCL1IE NCO1IE — — 000- 00-- 000- 00--

— — — — CLC4IE CLC3IE CLC2IE CLC1IE ---- 0000 ---- 0000

— Unimplemented — —

OPTION_REG

— Unimplemented — —

2: Unimplemented, read as ‘1’.

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111

—RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu

— — WDTPS<4:0> SWDTEN --01 0110 --01 0110

— IRCF<3:0> —SCS<1:0>-011 1-00 -011 1-00

—OSTSHFIOFR— — LFIOFR HFIOFS 0-q0 --00 q-qq --qq

— CHS<4:0>

(2)

TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

— — — — 1111 ---- 1111 ----

— TMR2IE TMR1IE 0000 0-00 0000 0-00

GO/DONE

— —

— — — — 0000 ---- 0000 ----

ADPREF<1:0>

ADON -000 0000 -000 0000

0000 --00 0000 --00

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41609A-page 29

PIC16(L)F1508/9

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 2

10Ch LATA — —LATA5LATA4— L ATA2 L ATA1 L ATA0 --xx -xxx --uu -uuu

10Dh LATB LATB7 LATB6 LATB5 LATB4

10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu

10Fh

110h

111h CM1CON0 C1ON C1OUT C1OE C1POL

112h CM1CON1 C1INTP C1INTN C1PCH<1:0>

113h CM2CON0 C2ON C2OUT C2OE C2POL

114h CM2CON1 C2INTP C2INTN C2PCH<1:0>

115h CMOUT

116h BORCON SBOREN BORFS

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

118h DACCON0 DACEN

119h DACCON1

11Dh APFCON

11Eh

11Fh

— Unimplemented — —

— Unimplemented — —

— — — — — —MC2OUT MC1OUT---- --00 ---- --00

— — — — — BORRDY 10-- ---q uu-- ---u

— DACOE1 DACOE2 — DACPSS — — 0-00 -0-- 0-00 -0--

— — DACR<4:0> ---0 0000 ---0 0000

11A h

to

— Unimplemented — —

11C h

— — — SSSEL T1GSEL — CLC1SEL NCO1SEL ---0 0-00 ---0 0-00

— Unimplemented — —

— Unimplemented — —

— — — — xxxx ---- uuuu ----

— C1SP C1HYS C1SYNC 0000 -100 0000 -100

— C1NCH<2:0> 0000 -000 0000 -000

— C2SP C2HYS C2SYNC 0000 -100 0000 -100

— C2NCH<2:0> 0000 -000 0000 -000

Bank 3

18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111

18Dh ANSELB

18Eh ANSELC ANSC7 ANSC6

18Fh

190h

191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000

192h PMADRH

193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h PMDATH

195h PMCON1

196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000

197h VREGCON

198h

199h RCREG USART Receive Data Register 0000 0000 0000 0000

19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000

19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000

19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

2: Unimplemented, read as ‘1’.

— — ANSB5 ANSB4 — — — — --11 ---- --11 ----

— — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111

— Flash Program Memory Address Register High Byte -000 0000 -000 0000

— — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

(2)

—

(1)

——————VREGPMReserved ---- --01 ---- --01

CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000

— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

Value on all

other

Resets

DS41609A-page 30 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 4

20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111

20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4

20Eh

to

— Unimplemented — —

210h

211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

212h SSP1ADD ADD<7:0> 0000 0000 0000 0000

213h SSP1MSK MSK<7:0> 1111 1111 1111 1111

214h SSP1STAT SMP CKE D/A

215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

to

— Unimplemented — —

21Fh

PSR/WUA BF 0000 0000 0000 0000

— — — — 1111 ---- 1111 ----

Value on

POR, BOR

Bank 5

28Ch

— Unimplemented — —

to

29Fh

Bank 6

30Ch

to

— Unimplemented — —

31Fh

Bank 7

38Ch

— Unimplemented — —

to

390h

391h IOCAP

392h IOCAN

393h IOCAF

394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4

395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4

396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4

397h

to

— Unimplemented — —

39Fh

— — IOCAP5 IOCAP4 IOCAP3

— — IOCAN5 IOCAN4 IOCAN3

— — IOCAF5 IOCAF4 IOCAF3

— — — — 0000 ---- 0000 ----

— — — — 0000 ---- 0000 ----

— — — — 0000 ---- 0000 ----

IOCAP2 IOCAP1 IOCAP0

IOCAN2 IOCAN1 IOCAN0

IOCAF2 IOCAF1 IOCAF0

--00 0000 --00 0000

--00 0000 --00 0000

--00 0000 --00 0000

Bank 8

40Ch

— Unimplemented — —

to

41Fh

Bank 9

48Ch

— Unimplemented — —

to

497h

498h NCO1ACCL NCO1ACC<7:0> 0000 0000 0000 0000

499h NCO1ACCH NCO1ACC<15:8> 0000 0000 0000 0000

49Ah NCO1ACCU NCO1ACC<19:16> 0000 0000 0000 0000

49Bh NCO1INCL NCO1INC<7:0> 0000 0000 0000 0000

49Ch NCO1INCH NCO1INC<15:8> 0000 0000 0000 0000

49Dh

49Eh NCO1CON N1EN N1OE N1OUT N1POL

49Fh NCO1CLK N1PWS<2:0>

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.

— Unimplemented — —

— — —N1PFM0000 ---0 0000 ---0

— — —N1CKS<1:0>0000 --00 0000 --00

2: Unimplemented, read as ‘1’.

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41609A-page 31

PIC16(L)F1508/9

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 10

50Ch

— Unimplemented — —

to

51Fh

Value on

POR, BOR

Bank 11

58Ch

to

— Unimplemented — —

59Fh

Bank 12

60Ch

— Unimplemented — —

to

610h

611h PWM1DCL PWM1DCL<7:6>

612h PWM1DCH PWM1DCH<7:0> xxxx xxxx uuuu uuuu

613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL

614h PWM2DCL PWM2DCL<7:6>

615h PWM2DCH PWM2DCH<7:0> xxxx xxxx uuuu uuuu

616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL

617h PWM3DCL PWM3DCL<7:6>

618h PWM3DCH PWM3DCH<7:0> xxxx xxxx uuuu uuuu

619h PWM3CON0 PWM3EN PWM3OE PWM3OUT PWM3POL

61Ah PWM4DCL PWM4DCL<7:6>

61Bh PWM4DCH PWM4DCH<7:0> xxxx xxxx uuuu uuuu

61Ch PWM4CON0 PWM4EN PWM4OE PWM4OUT PWM4POL

61Dh

to

— Unimplemented — —

61Fh

— — — — — — 00-- ---- 00-- ----

— — — — 0000 ---- 0000 ----

— — — — — — 00-- ---- 00-- ----

— — — — 0000 ---- 0000 ----

— — — — — — 00-- ---- 00-- ----

— — — — 0000 ---- 0000 ----

— — — — — — 00-- ---- 00-- ----

— — — — 0000 ---- 0000 ----

Bank 13

68Ch

— Unimplemented — —

to

690h

691h CWG1DBR

692h CWG1DBF

693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA

694h CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0>

695h CWG1CON2 G1ASE G1ARSEN

696h

— Unimplemented — —

to

69Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.

2: Unimplemented, read as ‘1’.

— —CWG1DBR<5:0>--00 0000 --00 0000

— —CWG1DBF<5:0>--xx xxxx --xx xxxx

— —G1CS00000 0--0 0000 0--0

— G1IS<2:0> 0000 -000 0000 -000

— — G1ASDC2 G1ASDC1 G1ASDSFLT G1ASDSCLC2 00-- --00 00-- --00

Value on all

other

Resets

DS41609A-page 32 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Banks 14-29

x0Ch/
x8Ch
—
x1Fh/
x9Fh

— Unimplemented — —

Bank 30

F0Ch

— Unimplemented — —

to

F0Eh

F0Fh CLCDATA

F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0000 0000 0000 0000

F11h CLC1POL LC1POL

F12h CLC1SEL0

F13h CLC1SEL1

F14h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu

F15h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu

F16h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu

F17h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu

F18h CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0000 0000 0000 0000

F19h CLC2POL LC2POL

F1Ah CLC2SEL0

F1Bh CLC2SEL1

F1Ch CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu

F1Dh CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu

F1Eh CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu

F1Fh CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu

F20h CLC3CON LC3EN LC3OE LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0000 0000 0000 0000

F21h CLC3POL LC3POL

F22h CLC3SEL0

F23h CLC3SEL1

F24h CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu

F25h CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu

F26h CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu

F27h CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu

F28h CLC4CON LC4EN LC4OE LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0000 0000 0000 0000

F29h CLC4POL LC4POL

F2Ah CLC4SEL0

F2Bh CLC4SEL1

F2Ch CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu

F2Dh CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu

F2Eh CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu

F2Fh CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu

F30h

to

— Unimplemented — —

F6Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.

2: Unimplemented, read as ‘1’.

— — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- 0000

— — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu

— LC1D2S<2:0> — LC1D1S<2:0> -xxx -xxx -uuu -uuu

— LC1D4S<2:0> — LC1D3S<2:0> -xxx -xxx -uuu -uuu

— — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu

— LC2D2S<2:0> — LC2D1S<2:0> -xxx -xxx -uuu -uuu

— LC2D4S<2:0> — LC2D3S<2:0> -xxx -xxx -uuu -uuu

— — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu

— LC3D2S<2:0> — LC3D1S<2:0> -xxx -xxx -uuu -uuu

— LC3D4S<2:0> — LC3D3S<2:0> -xxx -xxx -uuu -uuu

— — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- uuuu

— LC4D2S<2:0> — LC4D1S<2:0> -xxx -xxx -uuu -uuu

— LC4D4S<2:0> — LC4D3S<2:0> -xxx -xxx -uuu -uuu

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41609A-page 33

PIC16(L)F1508/9

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 31

F8Ch
—
FE3h

FE4h STATUS_

FE5h WREG_

FE6h BSR_

FE7h PCLATH_

FE8h FSR0L_

FE9h FSR0H_

FEAh FSR1L_

FEBh FSR1H_

FECh

FEDh

FEEh

FEFh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.

— Unimplemented — —

— — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu

SHAD

Working Register Shadow xxxx xxxx uuuu uuuu

SHAD

— — — Bank Select Register Shadow ---x xxxx ---u uuuu

SHAD

— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu

SHAD

— Unimplemented — —

STKPTR

TOSL

TOSH

2: Unimplemented, read as ‘1’.

— — — Current Stack Pointer ---1 1111 ---1 1111

Top-of-Stack Low byte xxxx xxxx uuuu uuuu

— Top-of-Stack High byte -xxx xxxx -uuu uuuu

Value on

POR, BOR

Value on all

other

Resets

DS41609A-page 34 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

PCL

PCH

0

14

PC

PCL

PCH

0

14

PC

ALU Result

8

7

6

PCLATH

0

Instruction with

PCL as

Destination

GOTO, CALL

OPCODE <10:0>

11

4

6

PCLATH

0

PCL

PCH

0

14

PC

W

8

7

6

PCLATH

0

CALLW

PCL

PCH

0

14

PC

PC + W

15

BRW

PCLPCH

0

14

PC

PC + OPCODE <8:0>

15

BRA

3.3 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN

DIFFERENT SITUATIONS

3.3.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).

3.3.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by com­bining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.

3.3.4 BRANCHING

The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.

If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will

3.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program Coun­ter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values con­tained in the PCLATH register and those being written
to the PCL register.

be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 35

PIC16(L)F1508/9

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled
(STVREN = 0)

Stack Reset Enabled
(STVREN = 1)

TOSH:TOSL

TOSH:TOSL

3.4 Stack

All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-5 through 3-8). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over­flow/Underflow, regardless of whether the Reset is
enabled.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the

CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to

an interrupt address.

3.4.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement the
STKPTR.

Reference Figure 3-5 through Figure 3-8 for examples
of accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

DS41609A-page 36 Preliminary  2011 Microchip Technology Inc.

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00

STKPTR = 0x00

This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.

TOSH:TOSL

PIC16(L)F1508/9

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

 2011 Microchip Technology Inc. Preliminary DS41609A-page 37

PIC16(L)F1508/9

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

TOSH:TOSL

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

3.4.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.

3.5 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

DS41609A-page 38 Preliminary  2011 Microchip Technology Inc.

FIGURE 3-9: INDIRECT ADDRESSING

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000

Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

PIC16(L)F1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 39

PIC16(L)F1508/9

Indirect AddressingDirect Addressing

Bank Select

Location Select

4BSR 6

0

From Opcode

FSRxL70

Bank Select

Location Select

00000 00001 00010 11111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

0

FSRxH70

0000

3.5.1 TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

DS41609A-page 40 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

7

0

1

7

0

0

Location Select

0x2000

FSRnH

FSRnL

0x020

Bank 0

0x06F
0x0A0

Bank 1
0x0EF
0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

0

7

1

7

0

0

Location Select

0x8000

FSRnH

FSRnL

0x0000

0x7FFF

0xFFFF

Program
Flash
Memory
(low 8
bits)

3.5.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.

The 16 bytes of common memory are not included in
the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

3.5.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH

MEMORY MAP

 2011 Microchip Technology Inc. Preliminary DS41609A-page 41

PIC16(L)F1508/9

NOTES:

DS41609A-page 42 Preliminary  2011 Microchip Technology Inc.

4.0 DEVICE CONFIGURATION

Device configuration consists of Configuration Words,
Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Words is

managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a '1'.

PIC16(L)F1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 43

PIC16(L)F1508/9

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1

FCMEN IESO CLKOUTEN

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CP

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

MCLRE PWRTE WDTE<1:0> FOSC<2:0>

BOREN<1:0>

—

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

bit 12 IESO: Internal External Switchover bit

bit 11 CLKOUTEN

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

bit 8 Unimplemented: Read as ‘1’

bit 7 CP: Code Protection bit

bit 6 MCLRE: MCLR/VPP Pin Function Select bit

bit 5 PWRTE

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bits

bit 2-0 FOSC<2:0>: Oscillator Selection bits

1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled

1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled

1 = CLKOUT function is disabled. I/O function on the CLKOUT pin
0 = CLKOUT function is enabled on the CLKOUT pin

11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled

1 = Program memory code protection is disabled
0 = Program memory code protection is enabled

If LVP bit =

If LVP bit =

1 = PWRT disabled
0 = PWRT enabled

11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled

111 = ECH:External clock, High-Power mode: on CLKIN pin
110 = ECM: External clock, Medium-Power mode: on CLKIN pin
101 = ECL: External clock, Low-Power mode: on CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

: Clock Out Enable bit

(2)

1:

This bit is ignored.

0:

1 =MCLR
0 =MCLR

/VPP pin function is MCLR; Weak pull-up enabled.
/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

: Power-Up Timer Enable bit

(1)

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: Once enabled, code-protect can only be disabled by bulk erasing the device.

DS41609A-page 44 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1

LVP

bit 13 bit 8

U-1U-1U-1U-1U-1U-1R/P-1R/P-1

— —

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

— —

DEBUG

(3)

LPBOR BORV STVREN —

— —WRT<1:0>

bit 13 LVP: Low-Voltage Programming Enable bit

1 = Low-voltage programming enabled
0 = High-voltage on MCLR

bit 12 DEBUG

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11

bit 10 BORV: Brown-out Reset Voltage Selection bit

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

bit 8-2 Unimplemented: Read as ‘1’
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: See Vbor parameter for specific trip point voltages.
3: The DEBUG bit in Configuration Words is managed automatically by device development tools including

LPBOR

1 = Low-Power Brown-out Reset is disabled
0 = Low-Power Brown-out Reset is enabled

1 = Brown-out Reset voltage (Vbor), low trip point selected.
0 = Brown-out Reset voltage (Vbor), high trip point selected.

1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset

2 k

debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.

: In-Circuit Debugger Mode bit

: Low-Power BOR Enable bit

W Flash memory:

11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified
01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified
00 = 000h to 7FFh write-protected, no addresses may be modified

must be used for programming

(1)

(3)

(2)

 2011 Microchip Technology Inc. Preliminary DS41609A-page 45

PIC16(L)F1508/9

4.2 Code Protection

Code protection allows the device to be protected from
unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.

4.2.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP
Words. When CP
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.3 “Write

Protection” for more information.

= 0, external reads and writes of

4.3 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.

bit in Configuration

4.4 User ID

Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See

Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing these

memory locations.
calculation, see the “PIC12(L)F1501/PIC16(L)F150X

Memory Programming Specification” (DS41573).

For more information on checksum

DS41609A-page 46 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

Device

DEVICEID<13:0> Values

DEV<8:0> REV<4:0>

PIC16F1508 10 1101 001 x xxxx

PIC16LF1508 10 1101 111 x xxxx

PIC16F1509 10 1101 010 x xxxx

PIC16LF1509 10 1101 000 x xxxx

4.5 Device ID and Revision ID

The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See

Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

RRRRRR

DEV<8:3>

bit 13 bit 8

RRRRRRRR

DEV<2:0> REV<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit

bit 13-5 DEV<8:0>: Device ID bits

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

 2011 Microchip Technology Inc. Preliminary DS41609A-page 47

PIC16(L)F1508/9

NOTES:

DS41609A-page 48 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

5.1 Overview

The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor­mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators, with a choice of speeds selectable via
software. Additional clock features include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and
code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

• Fast start-up oscillator allows internal circuits to

power-up and stabilize before switching to the 16
MHz HFINTOSC

The oscillator module can be configured in one of eight
clock modes.

1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode
(0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode
(4 MHz to 20 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC)

8. INTOSC – Internal oscillator (31 kHz to 16 MHz)

Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.

The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT, and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.

The INTOSC internal oscillator block produces a low
and high-frequency clock source, designated
LFINTOSC and HFINTOSC. (See Internal Oscillator
Block, Figure 5-1). A wide selection of device clock
frequencies may be derived from these two clock
sources.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 49

PIC16(L)F1508/9

Primary

Oscillator

(OSC)

Secondary

Oscillator

(SOSC)

Postscaler

MUX

16 MHz

8 MHz
4 MHz
2 MHz

1 MHz
500 kHz
250 kHz
125 kHz

62.5 kHz

31.25 kHz
31 kHz

WDT, PWRT and other Modules

MUX

Sleep

CPU and

Peripherals

Clock

Control

SCS<1:0>

FOSC<2:0>

CLKIN/ OSC1/
SOSCI/ T1CKI

CLKOUT / OSC2

SOSCO/ T1G

Primary Clock

Secondary Clock

INTOSC

IRCF<3:0>

16 MHz

Primary OSC

31 kHz

Source

Start-Up

OSC

Start-up

Control Logic

23

4

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS41609A-page 50 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

OSC1/CLKIN

OSC2/CLKOUT

Clock from
Ext. System

PIC

®

MCU

FOSC/4 or

I/O

(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

5.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator mod­ules (EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resis­tor-Capacitor (RC) mode circuits.

Internal clock sources are contained within the oscillator
module. The internal oscillator block has two internal
oscillators that are used to generate the internal system
clock sources: the 16 MHz High-Frequency Internal
Oscillator and the 31 kHz Low-Frequency Internal
Oscillator (LFINTOSC).

The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3

“Clock Switching” for additional information.

5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device
system clock by performing one of the following
actions:

• Program the FOSC<2:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.

• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:

- Secondary oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “Clock Switching”for more informa-
tion.

5.2.1.1 EC Mode

The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.

EC mode has 3 power modes to select from through
Configuration Words:

• High power, 4-20 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low power, 0-0.5 MHz (FOSC = 101)

The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC

®

MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

5.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.

LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).

XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.

HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 51

PIC16(L)F1508/9

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M

 to 10 M.

C1

C2

Quartz

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M

 to 10 M.

3: An additional parallel feedback resistor (R

P)

may be required for proper ceramic resonator
operation.

C1

C2

Ceramic

R

S

(1)

OSC1/CLKIN

RF

(2)

Sleep

To Internal
Logic

PIC® MCU

RP

(3)

Resonator

OSC2/CLKOUT

FIGURE 5-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR
HS MODE)

Note 1: Quartz crystal characteristics vary

according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC
Devices” (DS00826)

• AN849, “Basic PIC
(DS00849)

• AN943, “Practical PIC
Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”
(DS00949)

®

and PIC®

®

Oscillator Design”

®

Oscillator

FIGURE 5-4: CERAMIC RESONATOR

OPERATION
(XT OR HS MODE)

5.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.

In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4

“Two-Speed Clock Start-up Mode”).

DS41609A-page 52 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

C1

C2

32.768 kHz

SOSCI

To Internal
Logic

PIC® MCU

Crystal

SOSCO

Quartz

OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

F

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k

  REXT  100 k, 3-5V

C

EXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

I/O

(1)

5.2.1.4 Secondary Oscillator

The secondary oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is opti­mized for timekeeping operations with a 32.768 kHz
crystal connected between the SOSCO and SOSCI
device pins.

The secondary oscillator can be used as an alternate
system clock source and can be selected during
run-time using clock switching. Refer to Section 5.3

“Clock Switching” for more information.

FIGURE 5-5: QUARTZ CRYSTAL

OPERATION
(SECONDARY
OSCILLATOR)

5.2.1.5 External RC Mode

The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.

The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN

bit in Configuration Words.

Figure 5-6 shows the external RC mode connections.

FIGURE 5-6: EXTERNAL RC MODES

Note 1: Quartz crystal characteristics vary

according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC
Devices” (DS00826)

• AN849, “Basic PIC
(DS00849)

 2011 Microchip Technology Inc. Preliminary DS41609A-page 53

• AN943, “Practical PIC
Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”
(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for
Low-Power External Oscillators”

(DS01288)

®

and PIC®

®

Oscillator Design”

®

Oscillator

The RC oscillator frequency is a function of the supply
voltage, the resistor (R

EXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting
the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due
to tolerance of external RC components used.

PIC16(L)F1508/9

5.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscil­lator block as the system clock by performing one of the
following actions:

• Program the FOSC<2:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.

• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3

“Clock Switching”for more information.

In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN

The internal oscillator block has two independent
oscillators that provides the internal system clock
source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at
16 MHz.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at
31 kHz.

bit in Configuration Words.

5.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source.

The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). The frequency derived
from the HFINTOSC can be selected via software using
the IRCF<3:0> bits of the OSCCON register. See

Section 5.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.

A fast start-up oscillator allows internal circuits to
power-up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.

The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.

5.2.2.2 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). Select 31 kHz, via
software, using the IRCF<3:0> bits of the OSCCON
register. See Section 5.2.2.4 “Internal Oscillator

Clock Switch Timing” for more information. The

LFINTOSC is also the frequency for the Power-up Timer
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock
Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:

• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.

DS41609A-page 54 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

5.2.2.3 Internal Oscillator Frequency
Selection

The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 5-1). The Internal Oscillator Frequency
Select bits IRCF<3:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
the following frequencies can be selected via software:

•HFINTOSC

-16 MHz

-8 MHz

-4 MHz

-2 MHz

-1 MHz

- 500 kHz (default after Reset)

- 250 kHz

- 125 kHz

- 62.5 kHz

- 31.25 kHz

•LFINTOSC

-31 kHz

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli­cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi­tion times can be obtained between frequency changes
that use the same oscillator source.

5.2.2.4 Internal Oscillator Clock Switch
Timing

When switching between the HFINTOSC and the
LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-7). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new
clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.

Start-up delay specifications are located in the
oscillator tables of Section 29.0 “Electrical

Specifications”.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 55

PIC16(L)F1508/9

HFINTOSC

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC

LFINTOSC

IRCF <3:0>

System Clock

0 0

0 0

Start-up Time

2-cycle Sync Running

2-cycle Sync Running

HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC

IRCF <3:0>

System Clock

= 0  0

Start-up Time 2-cycle Sync

Running

LFINTOSC HFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING

DS41609A-page 56 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

5.3 Clock Switching

The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:

• Default system oscillator determined by FOSC
bits in Configuration Words

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

5.3.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary
oscillator.

• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.

5.3.3 SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the SOSCO and SOSCI device
pins.

The secondary oscillator is enabled using the
T1OSCEN control bit in the T1CON register. See

Section 19.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

5.3.4 SECONDARY OSCILLATOR READY

(SOSCR) BIT

The user must ensure that the secondary oscillator is
ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (SOSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
SOSCR bit is set, the SCS bits can be configured to
select the secondary oscillator.

When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil­lator delays are shown in Table 5-1.

5.3.2 OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Words, or from the internal clock source. In particular,
OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out for LP, XT or HS modes. The OST
does not reflect the status of the secondary oscillator.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 57

PIC16(L)F1508/9

5.4 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscil­lator module is configured for LP, XT, or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.

If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT reg­ister is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.

5.4.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the
following settings:

• IESO (of the Configuration Words) = 1; Inter-

nal/External Switchover bit (Two-Speed Start-up
mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay

Sleep/POR

Sleep/POR EC, RC DC – 20 MHz 2 cycles

LFINTOSC EC, RC DC – 20 MHz 1 cycle of each

Sleep/POR

Any clock source HFINTOSC 31.25 kHz-16 MHz 2 s (approx.)

Any clock source LFINTOSC 31 kHz 1 cycle of each

Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST)

DS41609A-page 58 Preliminary  2011 Microchip Technology Inc.

LFINTOSC
HFINTOSC

Secondary Oscillator,
LP, XT, HS

31 kHz

31.25kHz-16MHz

32 kHz-20 MHz 1024 Clock Cycles (OST)

Oscillator Warm-up Delay (T

WARM)

PIC16(L)F1508/9

0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N

PC

5.4.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 5-8: TWO-SPEED START-UP

5.4.3 CHECKING TWO-SPEED CLOCK STATUS

Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Words, or the
internal oscillator.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 59

PIC16(L)F1508/9

External

LFINTOSC

÷ 64

S

R

Q

31 kHz

(~32

s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Q

Sample Clock

5.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, RC and
secondary oscillator).

FIGURE 5-9: FSCM BLOCK DIAGRAM

5.5.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.

5.5.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared and the device
will be operating from the external clock source. The
Fail-Safe condition must be cleared before the OSFIF
flag can be cleared.

5.5.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.

5.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.

The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

DS41609A-page 60 Preliminary  2011 Microchip Technology Inc.

FIGURE 5-10: FSCM TIMING DIAGRAM

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator
Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te st

Test Test

Clock Monitor Output

PIC16(L)F1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 61

PIC16(L)F1508/9

5.6 Oscillator Control Registers

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0

(1)

(1)

(1)

IRCF<3:0>

—

—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’
bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 =16MHz
1110 =8MHz
1101 =4MHz
1100 =2MHz
1011 =1MHz
1010 = 500 kHz
1001 = 250 kHz
1000 = 125 kHz
0111 = 500 kHz (default upon Reset)
0110 = 250 kHz
0101 = 125 kHz
0100 = 62.5 kHz
001x = 31.25 kHz
000x =31kHz LF

bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.

SCS<1:0>

Note 1: Duplicate frequency derived from HFINTOSC.

DS41609A-page 62 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/q R-0/q

SOSCR

—

OSTS HFIOFR

— —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional

bit 7 SOSCR: Secondary Oscillator Ready bit

If T1OSCEN =

1:

1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready

If T1OSCEN = 0:

1 = Timer1 clock source is always ready
bit 6 Unimplemented: Read as ‘0’
bit 5 OSTS: Oscillator Start-up Time-out Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words

0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready

0 = HFINTOSC is not ready

bit 3-2 Unimplemented: Read as ‘0’
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready

0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC

0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC

LFIOFR HFIOFS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

OSCSTAT SOSCR

PIE2 OSFIE

PIR2

T1CON

Legend: — = unimplemented location, read as ‘

— IRCF<3:0> —SCS<1:0>62

—OSTSHFIOFR— — LFIOFR HFIOFS 63

C2IE C1IE — BCL1IE NCO1IE — — 80

OSFIF

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON

C2IF C1IF —

0’. Shaded cells are not used by clock sources.

BCL1IF

NCO1IF

—

— 83

Register
on Page

175

TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 63

13:8

7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

— — FCMEN IESO CLKOUTEN BOREN<1:0>

—

Register
on Page

44

PIC16(L)F1508/9

NOTES:

DS41609A-page 64 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

Note 1: See Table 6-1 for BOR active conditions.

Device

Reset

Power-on

Reset

WDT

Time-out

Brown-out

Reset

LPBOR

Reset

RESET Instruction

MCLRE

Sleep

BOR

Active

(1)

PWRT

R

Done

PWRTE

LFINTOSC

VDD

ICSP™ Programming Mode Exit

Stack

Pointer

MCLR

6.0 RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

•MCLR Reset

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.

A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.

FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

 2011 Microchip Technology Inc. Preliminary DS41609A-page 65

PIC16(L)F1508/9

6.1 Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising V
performance may require greater than minimum V
The PWRT, BOR or MCLR
extend the start-up period until all device operation
conditions have been met.

6.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time­out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the V
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.

The Power-up Timer starts after the release of the POR
and BOR.

For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).

DD, fast operating speeds or analog

DD.

features can be used to

DD to

6.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.

The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu­ration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 6 -1 for more information.

The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.

DD noise rejection filter prevents the BOR from trig-

A V
gering on small events. If V
duration greater than parameter T
will reset. See Figure 6-2 for more information.

DD falls below VBOR for a

BORDC, the device

TABLE 6-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

11 X X Active Waits for BOR ready

10 X

1

01

0 X Disabled Begins immediately

00 X XDisabled

Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.

Awake Active Waits for BOR ready

Sleep Disabled

X

Active Waits for BOR ready

Instruction Execution upon:

Release of POR or Wake-up from Sleep

(1)

(BORRDY = 1)

(BORRDY = 1)

(1)

(BORRDY = 1)

(BORRDY = x)

6.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are pro­grammed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.

6.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are pro­grammed to ‘10’, the BOR is on, except in Sleep. The
device start-up will be delayed until the BOR is ready

DD is higher than the BOR threshold.

and V

DS41609A-page 66 Preliminary  2011 Microchip Technology Inc.

BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.

6.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or

DD level.

the V

BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

FIGURE 6-2: BROWN-OUT SITUATIONS

TPWRT

(1)

VBOR

V

DD

Internal

Reset

VBOR

V

DD

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

V

DD

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

PIC16(L)F1508/9

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN BORFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Word
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Word

1 = BOR Enabled
0 = BOR Disabled

bit 6 BORFS: Brown-out Reset Fast Start bit

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.

If BOREN <1:0> =

1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off

bit 5-1 Unimplemented: Read as ‘0’

bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive

— — — — —BORRDY

s  01:

s = 01:

(1)

10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

Note 1: BOREN<1:0> bits are located in Configuration Words.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 67

PIC16(L)F1508/9

6.3 Low-Power Brown-out Reset (LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to

Figure 6-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external V
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.

DD pin.

6.3.1 ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.

6.3.1.1 LPBOR Module Output

The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR mod­ule to provide the generic BOR
the PCON register and to the power control block.

signal which goes to

6.4 MCLR

The MCLR is an optional external input that can reset
the device. The MCLR
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).

TABLE 6-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled
10Enabled
x1Enabled

6.4.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR
V

DD through an internal weak pull-up.

The device has a noise filter in the MCLR
The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR

6.4.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 11.2 “PORTA Regis-

ters” for more information.

function is controlled by the

pin is connected to

Reset path.

pin low.

6.5 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO
changed to indicate the WDT Reset. See Section 9.0

“Watchdog Timer” for more information.

and PD bits in the STATUS register are

6.6 RESET Instruction

A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Ta b le 6 - 4
for default conditions after a RESET instruction has
occurred.

6.7 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.4.2 “Overflow/Underflow

Reset” for more information.

6.8 Programming Mode Exit

Upon exit of Programming mode, the device will
behave as if a POR had just occurred.

6.9 Power-Up Timer

The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.

The Power-up Timer is controlled by the PWRTE
Configuration Words.

bit of

6.10 Start-up Sequence

Upon the release of a POR or BOR, the following must
occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. M

CLR must be released (if enabled).

The total time-out will vary based on oscillator configu­ration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for more information.

The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.

high, the device

DS41609A-page 68 Preliminary  2011 Microchip Technology Inc.

FIGURE 6-3: RESET START-UP SEQUENCE

TMCLR

TPWRT

VDD

Internal POR

Power-Up Timer

MCLR

Internal RESET

Internal Oscillator

Oscillator

F

OSC

External Clock (EC)

CLKIN

F

OSC

PIC16(L)F1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 69

PIC16(L)F1508/9

6.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Tab le 6- 3 and Tab le 6 -4 show the Reset
conditions of these registers.

TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition

0 0 1 1 10 x11Power-on Reset

0 0 1 1 10 x0xIllegal, TO

0 0 1 1 10 xx0Illegal, PD is set on POR

0 0 u 1 1u 011Brown-out Reset

u u 0 u uu u0uWDT Reset

u u u u uu u00WDT Wake-up from Sleep

u u u u uu u10Interrupt Wake-up from Sleep

u u u 0 uu uuuMCLR

u u u 0 uu u10MCLR

u u u u 0 u u u u RESET Instruction Executed

1 u u u uu uuuStack Overflow Reset (STVREN = 1)

u 1 u u uu uuuStack Underflow Reset (STVREN = 1)

is set on POR

Reset during normal operation

Reset during Sleep

(1)

(2)

STATUS

Register

---1 0uuu uu-- uuuu

PCON

Register

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-- 110x

MCLR

Reset during normal operation 0000h ---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu

WDT Reset 0000h ---0 uuuu uu-- uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu

Brown-out Reset 0000h ---1 1uuu 00-- 11u0

Interrupt Wake-up from Sleep PC + 1

RESET Instruction Executed 0000h ---u uuuu uu-- u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is

pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program
Counter

DS41609A-page 70 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

6.12 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits
to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI

•MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in Register 6-2.

REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF —

bit 7 bit 0

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

)

)

R

WDT RMCLR RI POR BOR

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware

bit 5 Unimplemented: Read as ‘0’
bit 4 RWDT

bit 3 RMCLR

bit 2 RI: RESET Instruction Flag bit

bit 1 POR

bit 0 BOR

: Watchdog Timer Reset Flag bit

1 = A Watchdog Timer Reset has not occurred or set by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)

: MCLR Reset Flag bit

1 = A MCLR Reset has not occurred or set by firmware
0 = A MCLR

1 = A RESET instruction has not been executed or set by firmware
0 = A RESET instruction has been executed (cleared by hardware)

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

Reset has occurred (cleared by hardware)

: Power-on Reset Status bit

: Brown-out Reset Status bit

 2011 Microchip Technology Inc. Preliminary DS41609A-page 71

PIC16(L)F1508/9

TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register
on Page

BORCON SBOREN BORFS

PCON STKOVF STKUNF

STATUS

WDTCON

— — —TOPD Z DC C 21

— — WDTPS<4:0> SWDTEN 93

— — — — — BORRDY 67

—RWDTRMCLR RI POR BOR 71

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR

Reset and Watchdog Timer Reset during normal operation.

TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

CONFIG2

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

13:8

7:0

13:8

7:0

— — — — CLKOUTEN BOREN<1:0> —

CP MCLRE PWRTE WDTE<1:0>

— — LV P DEBUG LPBOR BORV STVREN —

— — — — — — WRT<1:0>

FOSC<2:0>

Register
on Page

44

45

DS41609A-page 72 Preliminary  2011 Microchip Technology Inc.

7.0 INTERRUPTS

TMR0IF
TMR0IE

INTF
INTE

IOCIF
IOCIE

Interrupt
to CPU

Wake-up
(If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7>
PIEn<7>

PEIE

Peripheral Interrupts

(TMR1IF) PIR1<0>

The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.

This chapter contains the following information for
Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the
corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 7-1.

FIGURE 7-1: INTERRUPT LOGIC

PIC16(L)F1508/9

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7.1 Operation

Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)

The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.

The following events happen when an interrupt event
occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

Shadow registers (See “Section 7.5 “Automatic

Context Saving”.”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the Shadow registers and setting the GIE
bit.

For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.

7.2 Interrupt Latency

Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 7-2
and Figure 7.3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other
enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

DS41609A-page 74 Preliminary  2011 Microchip Technology Inc.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Fosc

CLKR

PC 0004h 0005h

PC

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

PC

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC )

Interrupt Sam pled
during Q1

Inst(PC)

PC-1 PC+1

NOP

PC

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

PC

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(0005h)

Execute

Execute

Execute

PIC16(L)F1508/9

FIGURE 7-2: INTERRUPT LATENCY

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Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

FOSC

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

PC

Instruction
Fetched

Instruction
Executed

Interrupt Latency

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Forced NOP

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Forced NOP

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”.

4: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(1)

FIGURE 7-3: INT PIN INTERRUPT TIMING

DS41609A-page 76 Preliminary  2011 Microchip Technology Inc.

7.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0 “Power-

Down Mode (Sleep)” for more details.

7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.

PIC16(L)F1508/9

7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis­ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica­tions to any of these registers are desired, the corre­sponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s appli­cation, other registers may also need to be saved.

and PD)

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7.6 Interrupt Control Registers

7.6.1 INTCON REGISTER

The INTCON register is a readable and writable
register, that contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt
0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed
0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state

(1)

(1)

Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register

have been cleared by software.

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PIC16(L)F1508/9

7.6.2 PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as
shown in Register 7-2.

REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt
0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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7.6.3 PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.

REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0

OSFIE C2IE C1IE — BCL1IE NCO1IE — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt

bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt

bit 2 NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit

1 = Enables the NCO interrupt
0 = Disables the NCO interrupt

bit 1-0 Unimplemented: Read as ‘0’

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS41609A-page 80 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

7.6.4 PIE3 REGISTER

The PIE3 register contains the interrupt enable bits, as
shown in Register 7-4.

REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — — CLC4IE CLC3IE CLC2IE CLC1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’
bit 3 CLC4IE: Configurable Logic Block 4 Interrupt Enable bit

1 = Enables the CLC 4 interrupt
0 = Disables the CLC 4 interrupt

bit 2 CLC3IE: Configurable Logic Block 3 Interrupt Enable bit

1 = Enables the CLC 3 interrupt
0 = Disables the CLC 3 interrupt

bit 1 CLC2IE: Configurable Logic Block 2 Interrupt Enable bit

1 = Enables the CLC 2 interrupt
0 = Disables the CLC 2 interrupt

bit 0 CLC1IE: Configurable Logic Block 1 Interrupt Enable bit

1 = Enables the CLC 1 interrupt
0 = Disables the CLC 1 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 81

PIC16(L)F1508/9

7.6.5 PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as
shown in Register 7-5.

REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

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PIC16(L)F1508/9

7.6.6 PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as
shown in Register 7-6.

REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0

OSFIF C2IF C1IF — BCL1IF NCO1IF — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 6 C2IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 5 C1IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 NCO1IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 1-0 Unimplemented: Read as ‘0’

 2011 Microchip Technology Inc. Preliminary DS41609A-page 83

PIC16(L)F1508/9

7.6.7 PIR3 REGISTER

The PIR3 register contains the interrupt flag bits, as
shown in Register 7-7.

REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — — CLC4IF CLC3IF CLC2IF CLC1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

bit 7-4 Unimplemented: Read as ‘0’
bit 3 CLC4IF: Configurable Logic Block 4 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 2 CLC3IF: Configurable Logic Block 3 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 1 CLC2IF: Configurable Logic Block 2 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

bit 0 CLC1IF: Configurable Logic Block 1 Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending

DS41609A-page 84 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78

OPTION_REG

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE

PIE2 OSFIE C2IE C1IE

PIE3

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF

PIR2 OSFIF C2IF C1IF

PIR3
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 165

— TMR2IE TMR1IE 79

— BCL1IE NCO1IE — — 80

— — — — CLC4IE CLC4IE CLC2IE CLC1IE 81

— TMR2IF TMR1IF 82

— BCL1IF NCO1IF — — 83

— — — — CLC4IF CLC3IF CLC2IF CLC1IF 84

Register
on Page

 2011 Microchip Technology Inc. Preliminary DS41609A-page 85

PIC16(L)F1508/9

NOTES:

DS41609A-page 86 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

8.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a
SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.

bit of the STATUS register is cleared.

2. PD

3. TO

bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.

6. ADC is unaffected, if the dedicated FRC clock is
selected.

7. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or high­impedance).

8. Resets other than WDT are not affected by
Sleep mode.

Refer to individual chapters for more details on
peripheral operation during Sleep.

To minimize current consumption, the following
conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• CWG, NCO and CLC modules using HFINTOSC

I/O pins that are high-impedance inputs should be
pulled to V
currents caused by floating inputs.

Examples of internal circuitry that might be sourcing
current include the FVR module. See Section 13.0

“Fixed Voltage Reference (FVR)” for more

information on this module.

DD or VSS externally to avoid switching

8.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the
following events:

1. External Reset input on MCLR

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running dur­ing Sleep (see individual peripheral for more
information)

The first three events will cause a device Reset. The
last three events are considered a continuation of pro­gram execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 6.11

“Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.

8.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared
bit of the STATUS register will not be set

-TO

-PD bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction

- SLEEP instruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

bit of the STATUS register will be set

-TO

-PD bit of the STATUS register will be cleared

pin, if enabled

 2011 Microchip Technology Inc. Preliminary DS41609A-page 87

PIC16(L)F1508/9

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(1)

CLKOUT

(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

PC

Instruction
Fetched

Instruction
Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2 0004h 0005h

Forced NOP

T1

OSC

(3)

PC + 2

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference.
3: T1OSC; See Section 29.0 “Electrical Specifications”.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD
was executed as a NOP.

FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

DS41609A-page 88 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

8.2 Low-Power Sleep Mode

The PIC16F1508/9 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16F1508/9 allows the user to optimize the
operating current in Sleep, depending on the
application requirements.

A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.

8.2.1 SLEEP CURRENT VS. WAKE-UP TIME

In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal con­figuration and stabilize.

The Low-Power Sleep mode is beneficial for applica­tions that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.

8.2.2 PERIPHERAL USAGE IN SLEEP

Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the Normal Power
mode when those peripherals are enabled. The Low­Power Sleep mode is intended for use with these
peripherals:

• Brown-Out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-on-change pins

• Timer1 (with external clock source)

The Complementary Waveform Generator (CWG), the
Numerically Controlled Oscillator (NCO) and the Con­figurable Logic Cell (CLC) modules can utilize the
HFINTOSC oscillator as either a clock source or as an
input source. Under certain conditions, when the
HFINTOSC is selected for use with the CWG, NCO or
CLC modules, the HFINTOSC will remain active
during Sleep. This will have a direct effect on the
Sleep mode current.

Please refer to sections 24.5 “Operation During

Sleep”, 25.7 “Operation In Sleep” and 26.10 “Oper­ation During Sleep” for more information.

Note: The PIC16LF1508/9 does not have a con-

figurable Low-Power Sleep mode.
PIC16LF1508/9 is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time pen­alty. This device has a lower maximum

DD and I/O voltage than the

V
PIC16F1508/9. See Section 29.0 “Elec-

trical Specifications” for more informa-

tion.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 89

PIC16(L)F1508/9

REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1

— — — — — —VREGPMReserved

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’
bit 1 VREGPM: Voltage Regulator Power Mode Selection bit

1 = Low-Power Sleep mode enabled in Sleep

Draws lowest current in Sleep, slower wake-up

0 = Normal Power mode enabled in Sleep

Draws higher current in Sleep, faster wake-up

bit 0 Reserved: Read as ‘1’. Maintain this bit set.

(1)

Note 1: PIC16F1508/9 only.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78

IOCAF

IOCAN

IOCAP
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4

IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4

IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE

PIE2 OSFIE C2IE C1IE

PIE3

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF

PIR2 OSFIF C2IF C1IF

PIR3

STATUS

WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.

— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 127

— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 127

— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 127

— — — —

— — — —

— — — —

— TMR2IE TMR1IE 79

— BCL1IE NCO1IE — — 80

— — — — CLC4IE CLC4IE CLC2IE CLC1IE 81

— TMR2IF TMR1IF 82

— BCL1IF NCO1IF — — 83

— — — — CLC4IF CLC3IF CLC2IF CLC1IF 84

— — —TOPD Z DC C 21

— — WDTPS<4:0> SWDTEN 93

Register on

Page

128

128

128

DS41609A-page 90 Preliminary  2011 Microchip Technology Inc.

9.0 WATCHDOG TIMER

LFINTOSC

23-bit Programmable

Prescaler WDT

WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (typical)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM

PIC16(L)F1508/9

 2011 Microchip Technology Inc. Preliminary DS41609A-page 91

PIC16(L)F1508/9

9.1 Independent Clock Source

The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See

Section 29.0 “Electrical Specifications” for the

LFINTOSC tolerances.

9.2 WDT Operating Modes

The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words. See Ta bl e 9 - 1 .

9.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always on.

WDT protection is active during Sleep.

9.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

9.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.

WDT protection is unchanged by Sleep. See Table 9-1
for more details.

TABLE 9-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN

11 X XActive

10 X

Device

Mode

Awake Active

Sleep Disabled

WDT

Mode

9.3 Time-Out Period

The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.

9.4 Clearing the WDT

The WDT is cleared when any of the following condi­tions occur:

•Any Reset

• CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail

• WDT is disabled

See Table 9-2 for more information.

9.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.

When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator

Module (With Fail-Safe Clock Monitor)” for more

information on the OST.

When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO
in the STATUS register are changed to indicate the
event. The RWDT
used. See Section 3.0 “Memory Organization” for
more information.

bit in the PCON register can also be

and PD bits

01

00 X X Disabled

1

X

0 Disabled

Active

TABLE 9-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = INTOSC, EXTCLK
Change INTOSC divider (IRCF bits) Unaffected

DS41609A-page 92 Preliminary  2011 Microchip Technology Inc.

Cleared

PIC16(L)F1508/9

9.6 Watchdog Control Register

REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

— — WDTPS<4:0> SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’
bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

00000 = 1:32 (Interval 1 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01010 = 1:32768 (Interval 1s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01100 = 1:131072 (2
01101 = 1:262144 (2
01110 = 1:524288 (2
01111 = 1:1048576 (2
10000 = 1:2097152 (2
10001 = 1:4194304 (2
10010 = 1:8388608 (2

17

) (Interval 4s nominal)

18

) (Interval 8s nominal)

19

) (Interval 16s nominal)

20

) (Interval 32s nominal)

21

) (Interval 64s nominal)

22

) (Interval 128s nominal)

23

) (Interval 256s nominal)

(1)

10011 = Reserved. Results in minimum interval (1:32)

•

•

•

11111 = Reserved. Results in minimum interval (1:32)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> =
This bit is ignored.
If WDTE<1:0> = 01:

1 = WDT is turned on
0 = WDT is turned off

If WDTE<1:0> =
This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

 2011 Microchip Technology Inc. Preliminary DS41609A-page 93

00:

1x:

PIC16(L)F1508/9

TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON — IRCF<3:0> —SCS<1:0>

PCON

STATUS

WDTCON

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

STKOVF STKUNF —RWDTRMCLR RI POR BOR

— — —TOPD Z DC C

— — WDTPS<4:0> SWDTEN

TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

13:8

7:0

— —

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

FCMEN IESO

CLKOUTEN BOREN<1:0> —

Register
on Page

62

71

21

93

Register

on Page

44

DS41609A-page 94 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

10.0 FLASH PROGRAM MEMORY

CONTROL

The Flash program memory is readable and writable
during normal operation over the full V
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

• PMADRL

•PMADRH

When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.

The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge
pump.

The Flash program memory can be protected in two
ways; by code protection (CP
and write protection (WRT<1:0> bits in Configuration
Words).

Code protection (CP
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.

Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.

Note 1: Code protection of the entire Flash

program memory array is enabled by
clearing the CP

= 0)

bit in Configuration Words)

(1)

, disables access, reading

bit of Configuration Words.

10.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up
to a maximum of 32K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.

10.1.1 PMCON1 AND PMCON2 REGISTERS

PMCON1 is the control register for Flash program
memory accesses.

DD range.

Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.

The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.

The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.

10.2 Flash Program Memory Overview

It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.

After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.

Note: If the user wants to modify only a portion

of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. How­ever, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.

See Table 10-1 for Erase Row size and the number of
write latches for Flash program memory.

TABLE 10-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Write

Latches

(words)

Device

PIC16(L)F1508
PIC16(L)F1509

Row Erase

(words)

32 32

 2011 Microchip Technology Inc. Preliminary DS41609A-page 95

PIC16(L)F1508/9

Start

Read Operation

Select

Program or Configuration Memory

(CFGS)

Select

Word Address

(PMADRH:PMADRL)

End

Read Operation

Instruction Fetched ignored

NOP execution forced

Instruction Fetched ignored

NOP execution forced

Initiate Read operation

(RD = 1)

Data read now in

PMDATH:PMDATL

10.2.1 READING THE FLASH PROGRAM MEMORY

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

3. Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.

PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.

Note: The two instructions following a program

memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.

FIGURE 10-1: FLASH PROGRAM

MEMORY READ
FLOWCHART

DS41609A-page 96 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,RD

executed here

INSTR(PC + 1)

executed here

PC

PC + 1 PMADRH,PMADRL

PC+3

PC + 5

Flash ADDR

RD bit

PMDATH,PMDATL

PC + 3 PC + 4

INSTR (PC + 1)

INSTR(PC - 1)

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

Flash Data

PMDATH

PMDATL

Register

INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)

instruction ignored
Forced NOP

INSTR(PC + 2)

executed here

instruction ignored
Forced NOP

* This code block will read 1 word of program
* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;

MOVWF PMADRL ; Store LSB of address

MOVLW PROG_ADDR_HI ;

MOVWF PMADRH ; Store MSB of address

BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read

NOP ; Ignored (Figure 10-2)

NOP ; Ignored (Figure 10-2)

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location

MOVF PMDATH,W ; Get MSB of word

MOVWF PROG_DATA_HI ; Store in user location

FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

EXAMPLE 10-1: FLASH PROGRAM MEMORY READ

 2011 Microchip Technology Inc. Preliminary DS41609A-page 97

PIC16(L)F1508/9

Write 055h to

PMCON2

Start

Unlock Sequence

Write 0AAh to

PMCON2

Initiate

Write or Erase operation

(WR = 1)

Instruction Fetched ignored

NOP execution forced

End

Unlock Sequence

Instruction Fetched ignored

NOP execution forced

10.2.2 FLASH MEMORY UNLOCK SEQUENCE

The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write pro­gramming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:

•Row Erase

• Load program memory write latches

• Write of program memory write latches to pro-

gram memory

• Write of program memory write latches to User

IDs

The unlock sequence consists of the following steps:

1. Write 55h to PMCON2

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4. NOP instruction

5. NOP instruction

Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.

Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.

FIGURE 10-3: FLASH PROGRAM

MEMORY UNLOCK
SEQUENCE FLOWCHART

DS41609A-page 98 Preliminary  2011 Microchip Technology Inc.

PIC16(L)F1508/9

Disable Interrupts

(GIE = 0)

Start

Erase Operation

Select

Program or Configuration Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

(FIGURE x-x)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

CPU stalls while

Erase operation completes

(2ms typical)

Figure 10-3

10.2.3 ERASING FLASH PROGRAM

While executing code, program memory can only be
erased by rows. To erase a row:

1. Load the PMADRH:PMADRL register pair with

2. Clear the CFGS bit of the PMCON1 register.

3. Set the FREE and WREN bits of the PMCON1

4. Write 55h, then AAh, to PMCON2 (Flash

5. Set control bit WR of the PMCON1 register to

See Example 10-2.

After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately fol­lowing the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.

MEMORY

any address within the row to be erased.

register.

programming unlock sequence).

begin the erase operation.

FIGURE 10-4: FLASH PROGRAM

MEMORY ERASE
FLOWCHART

 2011 Microchip Technology Inc. Preliminary DS41609A-page 99

PIC16(L)F1508/9

; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF PMADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF PMADRH
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,FREE ; Specify an erase operation
BSF PMCON1,WREN ; Enable writes

MOVLW 55h ; Start of required sequence to initiate erase
MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.

;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction

BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts

Required

Sequence

EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY

DS41609A-page 100 Preliminary  2011 Microchip Technology Inc.