Datasheet PIC12F752, PIC12HV752 Datasheet

PIC12F752/HV752

Data Sheet

8-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450.
Additional U.S. and foreign patents and applications may be issued or pending.

 2011 Microchip Technology Inc. Preliminary DS41576B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-798-0

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41576B-page 2 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU:

• Only 35 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 20 MHz clock input

- DC – 200 ns instruction cycle

• 1024 x 14 On-chip Flash Program Memory

• Self Read/Write Program Memory

• 64 x 8 General Purpose Registers (SRAM)

• Interrupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency:
8 MHz, 4 MHz, 1 MHz or 31 kHz

- Software tunable

• Power-Saving Sleep mode

• Voltage Range (PIC12F752):

- 2.0V to 5.5V

• Shunt Voltage Regulator (PIC12HV752)

- 2.0V to user defined

- 5 volt regulation

- 4 mA to 50 mA shunt range

• Multiplexed Master Clear with Pull-up/Input Pin

• Interrupt-on-Change Pins

• Individually Programmable Weak Pull-ups

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Brown-out Reset (BOR)

• Watchdog Timer (WDT) with Internal Oscillator for
Reliable Operation

• Industrial and Extended Temperature Range

• High Endurance Flash:

- 100,000 write Flash endurance

- Flash retention: >40 years

• Programmable Code Protection

• In-Circuit Debug (ICD) via Two Pins

• In-Circuit Serial Programming™ (ICSP™) via Two
Pins

Low-Power Features:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operating Current:

- 11 uA @ 32 kHz, 2.0V, typical

- 260 uA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

• <1 uA @ 2.0V, typical

Peripheral Features:

• 5 I/O Pins and 1 Input-only Pin

• High Current Source/Sink:

- 50 mA I/O, (2 pins)

- 25 mA I/O, (4 pins)

• 2 High-Speed Analog Comparator modules:

- 20 ns response time

- Fixed Voltage Reference (FVR)

- Programmable on-chip voltage reference via
integrated 5-bit DAC

- Internal/external inputs and outputs (select­able)

- Built-in Hysteresis (software selectable)

• A/D Converter:

- 10-bit resolution

- 4 external channels

- 2 internal reference voltage channels

• Dual Range Digital-to-Analog Converter (DAC):

- 5-bit resolution

- Full Range or Limited Range output

- 4 mV steps @ 2.0V (Limited Range)

- 65 mV steps @ 2.0V (Full Range)

• Fixed Voltage Reference (FVR), 1.2V reference

• Capture, Compare, PWM (CCP) module:

- 16-bit Capture, max. resolution = 12.5 ns

- Compare, max. resolution = 200 ns

- 10-bit PWM, max. frequency = 20 kHz

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit Timer/Counter with Prescaler

- External Timer1 Gate (count enable)

- 4 Selectable Clock sources

• Timer2: 8-Bit Timer/Counter with Prescaler

- 8-Bit Period Register and Postscaler

• Hardware Limit Timer (HLT):

- 8-bit Timer with Prescaler

- 8-bit period register and postscaler

- Asynchronous H/W Reset sources

• Complementary Output Generator (COG):

- Complementary Waveforms from selectable
sources

- 2 I/O (50 mA) for direct MOSFET drive

- Rising and/or Falling edge dead-band control

- Phase control, Blanking control

- Auto-shutdown

 2011 Microchip Technology Inc. Preliminary DS41576B-page 3

PIC12F752/HV752

1

2

3

4

5

6

7

8

PIC12F752/HV752

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2

MCLR/VPP/RA3

VDD

RA5

RA4

Note: See Tab le 2 for the location of all peripheral functions.

TABLE 1: PIC12F752/HV752 FEATURE SUMMARY

Device

PIC12F752 1024 Y 64 6 4 2 3/1 1 Y N

PIC12HV752 1024 Y 64 6 4 2 3/1 1 Y Y

Flash

Program

(User)

(words)

Memory

Self Read/Write

SRAM

Flash Memory

(bytes)

I/Os

10-bit A/D (ch)

Comparators

Timers

8/16-bit

CCP

(COG)

Complementary

Output Generator

FIGURE 1: 8-PIN DIAGRAM, PIC12F752/HV752 (PDIP, SOIC, DFN)

Shunt Regulator

DS41576B-page 4 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

TABLE 2: PIC12F752/HV752 PIN SUMMARY (PDIP, SOIC, DFN)

I/O

Pin

RA0

ADC

(5)

7 AN0 C1IN0+

Comparators

Timers

— — IOC Y COG1OUT1

C2IN0+

RA1 6 AN1 C1IN0-

——IOCY — V

C2IN0-

(5)

RA2

5 AN2 C1OUT

T0CKI CCP1 IOC

C2OUT

(1)

RA3

4— —

RA4 3 AN3 C1IN1- T1G

T1G

(3)

(2)

RA5 2 — C2IN1- T1CKI — IOC Y COG1OUT0

— 1 — — — — — — — — VDD

—8— — — — — — — — VSS

* Alternate pin function.

Note 1: Input only.

2: Default pin function via the APFCON register.
3: Alternate pin function via the APFCON register.
4: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.
5: The port pins for the primary COG1OUTx pins have High Power (HP) output drivers.

CCP

Interrupts

Pull-up

Output

Complementary

Y COG1OUT0

INT

—

IOC Y

(4)

COG1FLT

— IOC Y COG1FLT

COG1OUT1

Generator (COG)

(3)

(2)

(2)

(2)

(3)

(3)

Volt age

Reference

DACOUT
REFOUT

REF+ ICSPCLK

— —

—MCLR/VPP

— CLKOUT

—CLKIN

Basic

ICSPDAT

 2011 Microchip Technology Inc. Preliminary DS41576B-page 5

PIC12F752/HV752

Table of Contents

1.0 Device Overview ......................................................................................................................................................................... 9

2.0 Memory Organization ................................................................................................................................................................ 11

3.0 Flash Program Memory Self Read/Self Write Control ............................................................................................................... 29

4.0 Oscillator Module ....................................................................................................................................................................... 39

5.0 I/O Ports .................................................................................................................................................................................... 45

6.0 Timer0 Module .......................................................................................................................................................................... 55

7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57

8.0 Timer2 Module .......................................................................................................................................................................... 69

9.0 Hardware Limit Timer (HLT) Module ......................................................................................................................................... 73

10.0 Capture/Compare/PWM Modules ............................................................................................................................................. 77

11.0 Complementary Output Generator (COG) Module .................................................................................................................... 85

12.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 101

13.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 113

14.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 115

15.0 Comparator Module ................................................................................................................................................................. 121

16.0 Instruction Set Summary ......................................................................................................................................................... 131

17.0 Special Features of the CPU ................................................................................................................................................... 141

18.0 Shunt Regulator (PIC12HV752 Only) ...................................................................................................................................... 161

19.0 Development Support .............................................................................................................................................................. 163

20.0 Electrical Specifications ........................................................................................................................................................... 167

21.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 191

22.0 Packaging Information ............................................................................................................................................................. 193

Index ................................................................................................................................................................................................. 207

The Microchip Web Site .................................................................................................................................................................... 207

Customer Change Notification Service ............................................................................................................................................. 207

Customer Support ............................................................................................................................................................................. 207

Reader Response ............................................................................................................................................................................. 208

Product Identification System ............................................................................................................................................................ 209

DS41576B-page 6 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 7

PIC12F752/HV752

NOTES:

DS41576B-page 8 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

Flash

Program

Memory

13

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr

7

RAM Addr

9

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

CLKIN

CLKOUT

PORTA

8

8

8

3

8-Level Stack

64 Bytes

1K X 14

(13-Bit)

Power-up

Timer

Power-on

Reset

Watchdog

Timer

MCLR

VSS

Brown-out

Reset

Timer0 Timer1

RA0

RA1

RA2

RA3

RA4

RA5

Analog Comparator

T0CKI

INT

T1CKI

Configuration

Internal

Oscillator

and Reference

T1G

VDD

Block

C1IN0+/C2IN0+

C1IN0-/C2IN0-

C1IN1-

C2IN1-

C1OUT/C2OUT

Shunt Regulator

(PIC12HV752 only)

Capture/

Compare/

PWM

(CCP)

Hardware

Limit

Timer1

(HLT)

Complementary

Output

Generator

(COG)

Timer2

Fixed Voltage

Reference

(FVR)

Dual Range

DAC

1.0 DEVICE OVERVIEW

The PIC12F752/HV752 devices are covered by this
data sheet. They are available in 8-pin PDIP, SOIC and
DFN packages.

FIGURE 1-1: PIC12F752/HV752 BLOCK DIAGRAM

Block Diagrams and pinout descriptions of the devices
are in Figure 1-1 and Table 1-1.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 9

PIC12F752/HV752

TABLE 1-1: PIC12F752/HV752 PINOUT DESCRIPTION

Name Function

(2)

RA0/COG1OUT1

/C1IN0+/
C2IN0+/AN0/DACOUT/
REFOUT/
ICSPDAT

RA0 TTL HP General purpose I/O with IOC and WPU.

COG1OUT1 — HP COG output channel 1.

C1IN0+ AN — Comparator C1 positive input.

C2IN0+ AN — Comparator C2 positive input.

Input

Type

AN0 AN — A/D Channel 0 input.

DACOUT — AN DAC unbuffered Voltage Reference output.

REFOUT — AN DAC/FVR buffered Voltage Reference output.

ICSPDAT ST HP Serial Programming Data I/O.

RA1/C1IN0-/C2IN0-/AN1/

REF+/ICSPCLK

V

RA1 TTL CMOS General purpose I/O with IOC and WPU.

C1IN0- AN — Comparator C1 negative input.

C2IN0- AN — Comparator C2 negative input.

AN1 AN — A/D Channel 1 input.

REF+ AN — A/D Positive Voltage Reference input.

V

ICSPCLK ST — Serial Programming Clock.

RA2/INT/CCP1/C2OUT/
C1OUT/T0CKI/
COG1OUT0

(2)

/AN2

RA2 ST HP General purpose I/O with IOC and WPU.

INT ST — External interrupt.

CCP1 ST HP Capture/Compare/PWM 1.

C2OUT — HP Comparator C2 output.

C1OUT — HP Comparator C1 output.

T0CKI ST — Timer0 clock input.

COG1OUT0 — HP COG output channel 0.

AN2 AN — A/D Channel 2 input.

(1)

RA3
V

PP/MCLR

/T1G

(3)

/COG1FLT

(4)

(3)

/

RA3 TTL — General purpose input with WPU.

T1G ST — Timer1 Gate input.

COG1FLT ST — COG auto-shutdown fault input.

PP HV — Programming voltage.

V

MCLR

RA4/T1G
COG1FLT
CLKOUT

(2)

/COG1OUT1

(2)

/C1IN1-/AN3/

(3)

/

RA4 TTL CMOS General purpose I/O with IOC and WPU.

T1G ST — Timer1 Gate input.

COG1OUT1

COG1FLT

C1IN1- AN — Comparator C1 negative input.

AN3 AN — A/D Channel 3 input.

CLKOUT — CMOS F

RA5/T1CKI/COG1OUT0
C2IN1-/CLKIN

(3)

/

RA5 TTL CMOS General purpose I/O with IOC and WPU.

T1CKI ST — Timer1 clock input.

COG1OUT0 — CMOS COG output channel 0.

C2IN1- AN — Comparator C2 negative input.

CLKIN ST — External Clock input (EC mode).

DD VDD Power — Positive supply.

V

SS VSS Power — Ground reference.

V

Legend: AN = Analog input or output CMOS = CMOS compatible input or output

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HP = High Power HV = High Voltage

* Alternate pin function.

Note 1: Input only.

2: Default pin function via the APFCON register.
3: Alternate pin function via the APFCON register.
4: RA3 pull-up is enabled when pin is configured as MCLR

Output

Typ e

ST

—

Master Clear w/internal pull-up.

— CMOS COG output channel 1

ST — COG auto-shutdown fault input.

OSC/4 output.

in Configuration Word.

Description

DS41576B-page 10 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

PC<12:0>

13

0000h

0004h

0005h

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN
RETFIE, RETLW

Stack Level 2

Wraps to 0000h-03FFh

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F752/HV752 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. Only the first 1K x 14 (0000h-03FFh) is
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space for PIC12F752/HV752. The Reset
vector is at 0000h and the interrupt vector is at 0004h
(see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC12F752/HV752

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into four
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-6Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. Register locations 70h-7Fh in Bank 0 are
Common RAM and shared as the last 16 addresses in
all Banks. All other RAM is unimplemented and returns
‘0’ when read. The RP<1:0> bits of the STATUS register
are the bank select bits.

RP0

RP1

00  Bank 0 is selected
01  Bank 1 is selected
10  Bank 2 is selected
11  Bank 3 is selected

 2011 Microchip Technology Inc. Preliminary DS41576B-page 11

PIC12F752/HV752

2.2.1 GENERAL PURPOSE REGISTER
FILE

The register file is organized as 64 x 8 in the
PIC12F752/HV752. Each register is accessed, either
directly or indirectly, through the File Select Register
(FSR) (see Section 2.4 “Indirect Addressing, INDF

and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tab le 2 -1 ). These
registers are static RAM.

The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.

DS41576B-page 12 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 0 BANK 1 BANK 2 BANK 3

INDF 00h INDF 80h INDF 100h INDF 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h LATA 105h ANSELA 185h

— 06h — 86h — 106h — 186h
— 07h — 87h — 107h — 187h

IOCAF 08h IOCAP 88h IOCAN 108h APFCON 188h

— 09h — 89h — 109h OSCTUNE 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch WPUA 10Ch

PMCON1 18Ch

PIR2 0Dh PIE2 8Dh SLRCONA 10Dh PMCON2 18Dh

—0Eh —8Eh — 10Eh PMADRL 18Eh

TMR1L 0Fh OSCCON 8Fh PCON 10Fh PMADRH 18Fh
TMR1H 10h FVRCON 90h TMR2 110h PMDATL 190h
T1CON 11h DACCON0 91h

PR2 111h PMDATH 191h

T1GCON 12h DACCON1 92h T2CON 112h COG1PH 192h

CCPR1L 13h — 93h HLTMR1 113h COG1BLK 193h

CCPR1H 14h

— 94h HLTPR1 114h COG1DB 194h

CCP1CON 15h — 95h HLT1CON0 115h COG1CON0 195h

— 16h — 96h HLT1CON1 116h COG1CON1 196h

— 17h — 97h — 117h COG1ASD 197h

— 18h — 98h — 118h — 198h

— 19h — 99h — 119h — 199h

—1Ah —9Ah —11Ah — 19Ah

— 1Bh CM2CON0 9Bh —11Bh — 19Bh
ADRESL 1Ch CM2CON1 9Ch

—11Ch — 19Ch
ADRESH 1Dh CM1CON0 9Dh —11Dh — 19Dh
ADCON0 1Eh CM1CON1 9Eh —11Eh — 19Eh
ADCON1 1Fh CMOUT 9Fh

—11Fh — 19Fh

Unimplemented

20h

3Fh

Unimplemented

A0h

EFh

Unimplemented

120h

16Fh

Unimplemented

1A0h

1EFh

General
Purpose
Register

48 Bytes

40h

6Fh

Common RAM

16 Bytes

70h
7Fh

Common RAM

(Accesses

70h-7Fh)

F0h
FFh

Common RAM

(Accesses

70h-7Fh)

170h
17Fh

Common RAM

(Accesses

70h-7Fh)

1F0h
1FFh

FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F752/HV752

 2011 Microchip Technology Inc. Preliminary DS41576B-page 13

PIC12F752/HV752

TABLE 2-1: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 0

Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

01h TMR0 Holding register for the 8-bit TMR0 xxxx xxxx uuuu uuuu

02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS

04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

05h PORTA

06h

— Unimplemented — —

— Unimplemented — —

07h

08h IOCAF

— Unimplemented — —

09h

0Ah PCLATH

0Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

0Ch PIR1

0Dh PIR2

— Unimplemented — —

0Eh

0Fh

TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx

10h

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu

11h

T1CON

12h T1GCON

13h

CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx uuuu uuuu

14h

CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx uuuu uuuu

15h

CCP1CON

16h

to

— Unimplemented — —

1Bh

ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx uuuu uuuu

1Ch

1Dh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx uuuu uuuu

1Eh

ADCON0 ADFM VCFG CHS<3:0> GO/DONE

1Fh

ADCON1

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatch exists.

IRP RP1 RP0 TO

— —

— —

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 00---000 00---000

— — C2IF C1IF — COG1IF — CCP1IF --00 -0-0 --00 -0-0

TMR1CS<1:0> T1CKPS<1:0>

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

— —

— ADCS<2:0> — — — —

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the

RA5 RA4 RA3 RA2 RA1 RA0

IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

DC1B<1:0> CCP1M<3:0>

Reset and Watchdog Timer Reset during normal operation.

PD ZDCC

Reserved

DONE

T1SYNC

T1GVAL T1GSS<1:0>

—

TMR1ON 0000 00-0

ADON

Value on

POR/BOR

Reset

0001 1xxx 000q quuu

--xx xxxx --uu uuuu

--00 0000 --00 0000

(2)

0000 0000 0000 0000

0000 0x00 uuuu uxuu

--00 0000 --00 0000

0000 0000 0000 0000

-000 ---- -000 ----

Value o n

all other

Resets

uuuu uuuu

uuuu uu-u

(1)

DS41576B-page 14 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

TABLE 2-2: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

81h OPTION_REG

82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS

84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

85h TRISA — — TRISA5 TRISA4 TRISA3

86h — Unimplemented — —

87h — Unimplemented — —

88h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000

89h — Unimplemented — —

8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

8Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

8Ch PIE1 TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 00-- -000 00-- -000

8Dh PIE2 — — C2IE C1IE — COG1IE — CCP1IE --00 -0-0 --00 -0-0

8Eh — Unimplemented — —

8Fh OSCCON

90h FVRCON FVREN FVRRDY FVR-

91h DACCON0 DACEN DACRNG DACOE — — DAC PSS0 — — 000- -0-- 000- -0--

92h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000

93h

to

— Unimplemented — —

9Ah

9Bh CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100

9Ch CM2CON1 C2INTP C2INTN C2PCH<1:0> — — — C2NCH0 0000 ---0 0000 ---0

9Dh CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100

9Eh CM1CON1 C1INTP C1INTN C1PCH<1:0> — — — C1NCH0 0000 ---0 0000 ---0

9Fh CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatch exists.

3: TRISA3 always reads ‘1’.

RAPU

IRP RP1 RP0 TO

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the

INTEDG T0CS T0SE PSA PS<2:0>

PD ZDCC

(3)

TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

— —

IRCF<1:0>

BUFEN

FVR-

BUFSS

Reset and Watchdog Timer Reset during normal operation.

—

— — — —

HTS LTS

—

Valu e o n

POR/BOR

Reset

1111 1111 1111 1111

0001 1xxx 000q quuu

(2)

0000 0000 0000 0000

--01 -00- --uu -uu-

0000 ---- 0000 ----

Values on

all other

(1)

Resets

 2011 Microchip Technology Inc. Preliminary DS41576B-page 15

PIC12F752/HV752

TABLE 2-3: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 2

Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

101h TMR0 Holding Register for the 8-bit Timer0 Register xxxx xxxx uuuu uuuu

102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

103h STATUS

104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

105h LATA — —LATA5LATA4— LATA2 L ATA1 LATA 0 --xx -xxx --uu -uuu

106h — Unimplemented — —

107h — Unimplemented — —

108h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000

109h — Unimplemented — —

10Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

10Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

10Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --00 0000 --00 0000

10Dh SLRCONA — — — — —SLRA2 —SLRA0---- -0-0 ---- -0-0

10Eh — Unimplemented — —

10Fh PCON — — — — — —PORBOR ---- --qq ---- --uu

110h

TMR2 Holding Register for the 8-bit Timer2 Register 0000 0000 0000 0000

111h PR2 Timer2 Period Register 1111 1111 1111 1111

112 h T 2CO N — TOUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

113h HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Register 0000 0000 0000 0000

114h HLTPR1 Hardware Limit Timer1 Period Register 1111 1111 1111 1111

115h HLT1CON0 — H1OUTPS<3:0> H1ON H1CKPS<1:0> -000 0000 -000 0000

116h HLT1CON1 — — — H1ERS<2:0> H1FEREN H1REREN ---0 0000 ---0 0000

117 h

— Unimplemented — —

to

11F h

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatch exists.

IRP RP1

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the

RP0 TO PD ZDCC0001 1xxx 000q quuu

Reset and Watchdog Timer Reset during normal operation.

Value on

POR/BOR

Reset

(2)

0000 0000 0000 0000

Val ue o n

all other

Resets

(1)

DS41576B-page 16 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

TABLE 2-4: PIC12F752/HV752 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

181h OPTION_REG

182h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

183h STATUS

184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

185h ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 --11 -111 --11 -111

186h

— Unimplemented — —

187h

— Unimplemented — —

188h APFCON

189h OSCTUNE — — — TUN<4:0> ---0 0000 ---u uuuu

18Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

18Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

18Ch PMCON1 — — — — —WRENWR RD---- -000 ---- -000

18Dh PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----

18Eh PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000

18Fh PMADRH — — — — — — PMADRH<1:0> ---- --00 ---- --00

190h PMDATL Program Memory Data Register Low Byte 0000 0000 0000 0000

191h PMDATH — — Program Memory Data Register High Byte --00 0000 --00 0000

192h COG1PH

193h COG1BLK G1BLKR<3:0> G1BLKF<3:0> xxxx xxxx uuuu uuuu

194h COG1DB G1DBR<3:0> G1DBF<3:0> xxxx xxxx uuuu uuuu

195h COG1CON0

196h COG1CON1

197h COG1ASD

198h

— Unimplemented — —

to

19Fh

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

RAPU

IRP RP1 RP0 TO

— — —

— — — —

G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD G1CS<1:0>

G1FSIM G1RSIM

G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the mismatch exists.

INTEDG T0CS T0SE PSA PS<2:0>

PD ZDCC

T1GSEL

G1FS<2:0> G1RS<2:0>

Reset and Watchdog Timer Reset during normal operation.

— COG1FSEL COG1O1SEL COG1O0SEL ---0 -000 ---0 -000

G1PH<3:0> ---- xxxx ---- uuuu

Val ue on

POR/BOR

Reset

1111 1111 1111 1111

0001 1xxx 000q quuu

(2)

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

Values on

all other

(1)

Resets

 2011 Microchip Technology Inc. Preliminary DS41576B-page 17

PIC12F752/HV752

2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM)

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO

and PD bits are not

writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, see the Section 16.0

“Instruction Set Summary”.

REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)

bit 6 RP1: Register Bank Select bit (used for direct addressing)

00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)

bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h-FFh)
0 = Bank 0 (00h-7Fh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Borrow

bit 0 C: Carry/Borrow

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

bit

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(2)

bit

(ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed.

(2)

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

PD ZDC

(1)

(1)

C

Note 1: The C and DC bits operate as a Borrow

DS41576B-page 18 Preliminary  2011 Microchip Technology Inc.

instructions for examples.

2: For Borrow

For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.

and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF

PIC12F752/HV752

000

001

010

011

100

101

110

111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

BIT VALUE TIMER0 RATE WDT RATE

2.2.2.2 OPTION Register

The OPTION register is a readable and writable
register, which contains various control bits to
configure:

• Timer0/WDT prescaler

• External RA2/INT interrupt

•Timer0

• Weak pull-ups on PORTA

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG T0CS T0SE PSA PS<2:0>

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT
by setting PSA bit to ‘1’ of the OPTION
register. See Section 6.1.3 “Software
Programmable Prescaler”.

bit 7 RAPU

: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

OSC/4)

 2011 Microchip Technology Inc. Preliminary DS41576B-page 19

PIC12F752/HV752

2.2.2.3 INTCON Register

The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, IOCIE change and external
RA2/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit

1 = Enables the IOC change interrupt
0 = Disables the IOC change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit

1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = An IOC pin has changed state and generated an interrupt
0 = No pin interrupts have been generated

(2)

(1)

Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

DS41576B-page 20 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

2.2.2.4 PIE1 Register

The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-4.

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIE: ADC Interrupt Enable bit

1 = Enables the TMR1 gate interrupt
0 = Disables the TMR1 gate interrupt

bit 6 ADIE: ADC Interrupt Enable bit

1 = Enables the ADC interrupt
0 = Disables the ADC interrupt

bit 5-3 Unimplemented: Read as ‘0’

bit 2 HLTMR1IE: Hardware Limit Timer1 Interrupt Enable bit

1 = Enables the HLTMR1 interrupt
0 = Disables the HLTMR1 interrupt

bit 1 TMR2IE: Timer2 Interrupt Enable bit

1 = Enables the Timer2 interrupt
0 = Disables the Timer2 interrupt

bit 0 TMR1IE: Timer1 Interrupt Enable bit

1 = Enables the Timer1 interrupt
0 = Disables the Timer1 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 21

PIC12F752/HV752

2.2.2.5 PIE2 Register

The PIE2 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-5.

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0

— — C2IE C1IE —COG1IE — CCP1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt

bit 4 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt

bit 3 Unimplemented: Read as ‘0’

bit 2 COG1IE: COG 1 Interrupt Flag bit

1 = COG1 interrupt enabled
0 = COG1 interrupt disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS41576B-page 22 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

2.2.2.6 PIR1 Register

The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-6.

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

TMR1GIF ADIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIF: TMR1 Gate Interrupt Flag bit

1 = Timer1 gate interrupt is pending
0 = Timer1 gate interrupt is not pending

bit 6 ADIF: ADC Interrupt Flag bit

1 = ADC conversion complete
0 = ADC conversion has not completed or has not been started

bit 5-3 Unimplemented: Read as ‘0’

bit 2 HLTMR1IF: Hardware Limit Timer1 to HLTPR1 Match Interrupt Flag bit

1 = HLTMR1 to HLTPR1 match occurred (must be cleared in software)
0 = HLTMR1 to HLTPR1 match did not occur

bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match did not occur

bit 0 TMR1IF: Timer1 Interrupt Flag bit

1 = Timer1 rolled over (must be cleared in software)
0 = Timer1 has not rolled over

— — — HLTMR1IF TMR2IF TMR1IF

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 23

PIC12F752/HV752

2.2.2.7 PIR2 Register

The PIR2 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-7.

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0

— — C2IF C1IF COG1IF — CCP1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 C2IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed

bit 4 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed

bit 3 Unimplemented: Read as ‘0’

bit 2 COG1IF: COG 1 Interrupt Flag bit

1 = COG1 has generated an auto-shutdown interrupt
0 = COG1 has NOT generated an auto-shutdown interrupt

bit 1 Unimplemented: Read as ‘0’

bit 0 CCP1IF: ECCP Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode
Unused in this mode

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

DS41576B-page 24 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

2.2.2.8 PCON Register

The Power Control (PCON) register (see Tab le 1 7- 2)
contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR

The PCON register also controls the software enable of
the BOR

The PCON register bits are shown in Register 2-8.

.

REGISTER 2-8: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-q/u R/W-q/u

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = unchanged

)

Reset

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR

bit 0 BOR

: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

 2011 Microchip Technology Inc. Preliminary DS41576B-page 25

PIC12F752/HV752

PC

12 8 7 0

5

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE <10:0>

8

PC

12 11 10 0

11

PCLATH<4:3>

PCH PCL

87

2

PCLATH

PCH PCL

PCL as

Destination

MOVLW 0x40 ;initialize pointer
MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer
BTFSS FSR,7 ;all done?
GOTO NEXT ;no clear next

CONTINUE ;yes continue

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-3 shows the two
situations for the loading of the PC. The upper example
in Figure 2-3 shows how the PC is loaded on a write to
PCL (PCLATH<4:0>  PCH). The lower example in

Figure 2-3 shows how the PC is loaded during a CALL or

GOTO instruction (PCLATH<4:3>  PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.2 STACK

The PIC12F752/HV752 Family has an 8-level x 13-bit
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the
Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is exe­cuted or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.

The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.

2.4 Indirect Addressing, INDF and
FSR Registers

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
13 bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.

A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.

For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).

The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit of the
STATUS register, as shown in Figure 2-4.

A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

DS41576B-page 26 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

Data
Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1 RP0 6

0

From Opcode

IRP File Select Register

7

0

Bank Select

Location Select

00 01 10 11

180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

For memory map detail, see Figure 2-2.

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F752/HV752

 2011 Microchip Technology Inc. Preliminary DS41576B-page 27

PIC12F752/HV752

NOTES:

DS41576B-page 28 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL

The Flash program memory is readable and writable
during normal operation (full V
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers (see Registers 3-1 to 3-5). There
are six SFRs used to read and write this memory:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

• PMADRL

• PMADRH

When interfacing the program memory block, the
PMDATL and PMDATH registers form a two-byte word
which holds the 14-bit data for read/write, and the
PMADRL and PMADRH registers form a two-byte
word which holds the 10-bit address of the Flash loca­tion being accessed. These devices have 1K words of
program Flash with an address range from 0000h to
03FFh.

The program memory allows single word read and a
by four word write. A four word write automatically
erases the row of the location and writes the new data
(erase before write).

The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.

When the device is code-protected, the CPU may
continue to read and write the Flash program memory.

Depending on the settings of the Flash Program
Memory Enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory, however, reads of the program memory are
allowed.

When the Flash program memory Code Protection

) bit in the Configuration Word register is enabled,

(CP
the program memory is code-protected, and the
device programmer (ICSP™) cannot access data or
program memory.

DD range). This memory

3.1 PMADRH and PMADRL Registers

The PMADRH and PMADRL registers can address up
to a maximum of 1K words of program memory.

When selecting a program address value, the Most
Significant Byte (MSB) of the address is written to the
PMADRH register and the Least Significant Byte
(LSB) is written to the PMADRL register.

3.2 PMCON1 and PMCON2 Registers

PMCON1 is the control register for the data program
memory accesses.

Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
termination of a write operation.

The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.

PMCON2 is not a physical register. Reading PMCON2
will read all ‘0’s. The PMCON2 register is used
exclusively in the Flash memory write sequence.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 29

PIC12F752/HV752

3.3 Flash Program Memory Control Registers

REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMDATL<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMDATL<7:0>: 8 Least Significant Data bits to Write or Read from Program Memory

REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMADRL<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation

REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— —PMDATH<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 PMDATH<5:0>: 6 Most Significant Data bits from Program Memory

REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — PMADRH<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1-0 PMADRH<1:0>: Specifies the 2 Most Significant Address bits or High bits for Program Memory Reads.

DS41576B-page 30 Preliminary  2011 Microchip Technology Inc.