Datasheet PIC12F752, PIC12HV752 Datasheet

PIC12F752/HV752

Data Sheet

8-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.

 2011 Microchip Technology Inc. Preliminary DS41576B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC

logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-798-0

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

DS41576B-page 2 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU:

• Only 35 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 20 MHz clock input

- DC – 200 ns instruction cycle

• 1024 x 14 On-chip Flash Program Memory

• Self Read/Write Program Memory

• 64 x 8 General Purpose Registers (SRAM)

• Interrupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency: 8 MHz, 4 MHz, 1 MHz or 31 kHz

- Software tunable

• Power-Saving Sleep mode

• Voltage Range (PIC12F752):

- 2.0V to 5.5V

• Shunt Voltage Regulator (PIC12HV752)

- 2.0V to user defined

- 5 volt regulation

- 4 mA to 50 mA shunt range

• Multiplexed Master Clear with Pull-up/Input Pin

• Interrupt-on-Change Pins

• Individually Programmable Weak Pull-ups

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Brown-out Reset (BOR)

• Watchdog Timer (WDT) with Internal Oscillator for Reliable Operation

• Industrial and Extended Temperature Range

• High Endurance Flash:

- 100,000 write Flash endurance

- Flash retention: >40 years

• Programmable Code Protection

• In-Circuit Debug (ICD) via Two Pins

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

Low-Power Features:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operating Current:

- 11 uA @ 32 kHz, 2.0V, typical

- 260 uA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

• <1 uA @ 2.0V, typical

Peripheral Features:

• 5 I/O Pins and 1 Input-only Pin

• High Current Source/Sink:

- 50 mA I/O, (2 pins)

- 25 mA I/O, (4 pins)

• 2 High-Speed Analog Comparator modules:

- 20 ns response time

- Fixed Voltage Reference (FVR)

- Programmable on-chip voltage reference via integrated 5-bit DAC

- Internal/external inputs and outputs (selectable)

- Built-in Hysteresis (software selectable)

• A/D Converter:

- 10-bit resolution

- 4 external channels

- 2 internal reference voltage channels

• Dual Range Digital-to-Analog Converter (DAC):

- 5-bit resolution

- Full Range or Limited Range output

- 4 mV steps @ 2.0V (Limited Range)

- 65 mV steps @ 2.0V (Full Range)

• Fixed Voltage Reference (FVR), 1.2V reference

• Capture, Compare, PWM (CCP) module:

- 16-bit Capture, max. resolution = 12.5 ns

- Compare, max. resolution = 200 ns

- 10-bit PWM, max. frequency = 20 kHz

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit Timer/Counter with Prescaler

- External Timer1 Gate (count enable)

- 4 Selectable Clock sources

• Timer2: 8-Bit Timer/Counter with Prescaler

- 8-Bit Period Register and Postscaler

• Hardware Limit Timer (HLT):

- 8-bit Timer with Prescaler

- 8-bit period register and postscaler

- Asynchronous H/W Reset sources

• Complementary Output Generator (COG):

- Complementary Waveforms from selectable sources

- 2 I/O (50 mA) for direct MOSFET drive

- Rising and/or Falling edge dead-band control

- Phase control, Blanking control

- Auto-shutdown

 2011 Microchip Technology Inc. Preliminary DS41576B-page 3

PIC12F752/HV752

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2

MCLR/VPP/RA3

VDD

RA5

RA4

Note: See Tab le 2 for the location of all peripheral functions.

TABLE 1: PIC12F752/HV752 FEATURE SUMMARY

Device

PIC12F752 1024 Y 64 6 4 2 3/1 1 Y N

PIC12HV752 1024 Y 64 6 4 2 3/1 1 Y Y

Flash

Program

(User)

(words)

Memory

Self Read/Write

SRAM

Flash Memory

(bytes)

I/Os

10-bit A/D (ch)

Comparators

Timers

8/16-bit

CCP

(COG)

Complementary

Output Generator

FIGURE 1: 8-PIN DIAGRAM, PIC12F752/HV752 (PDIP, SOIC, DFN)

Shunt Regulator

DS41576B-page 4 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

TABLE 2: PIC12F752/HV752 PIN SUMMARY (PDIP, SOIC, DFN)

I/O

RA0

ADC

(5)

7 AN0 C1IN0+

Comparators

Timers

— — IOC Y COG1OUT1

C2IN0+

RA1 6 AN1 C1IN0-

——IOCY — V

C2IN0-

(5)

RA2

5 AN2 C1OUT

T0CKI CCP1 IOC

C2OUT

(1)

RA3

4— —

RA4 3 AN3 C1IN1- T1G

T1G

(3)

(2)

RA5 2 — C2IN1- T1CKI — IOC Y COG1OUT0

— 1 — — — — — — — — VDD

—8— — — — — — — — VSS

* Alternate pin function.

Note 1: Input only.

2: Default pin function via the APFCON register. 3: Alternate pin function via the APFCON register. 4: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word. 5: The port pins for the primary COG1OUTx pins have High Power (HP) output drivers.

CCP

Interrupts

Pull-up

Output

Complementary

Y COG1OUT0

INT

—

IOC Y

(4)

COG1FLT

— IOC Y COG1FLT

COG1OUT1

Generator (COG)

(3)

(2)

(3)

Volt age

Reference

DACOUT REFOUT

REF+ ICSPCLK

— —

—MCLR/VPP

— CLKOUT

—CLKIN

Basic

ICSPDAT

 2011 Microchip Technology Inc. Preliminary DS41576B-page 5

PIC12F752/HV752

Table of Contents

1.0 Device Overview ......................................................................................................................................................................... 9

2.0 Memory Organization ................................................................................................................................................................ 11

3.0 Flash Program Memory Self Read/Self Write Control ............................................................................................................... 29

4.0 Oscillator Module ....................................................................................................................................................................... 39

5.0 I/O Ports .................................................................................................................................................................................... 45

6.0 Timer0 Module .......................................................................................................................................................................... 55

7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57

8.0 Timer2 Module .......................................................................................................................................................................... 69

9.0 Hardware Limit Timer (HLT) Module ......................................................................................................................................... 73

10.0 Capture/Compare/PWM Modules ............................................................................................................................................. 77

11.0 Complementary Output Generator (COG) Module .................................................................................................................... 85

12.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 101

13.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 113

14.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 115

15.0 Comparator Module ................................................................................................................................................................. 121

16.0 Instruction Set Summary ......................................................................................................................................................... 131

17.0 Special Features of the CPU ................................................................................................................................................... 141

18.0 Shunt Regulator (PIC12HV752 Only) ...................................................................................................................................... 161

19.0 Development Support .............................................................................................................................................................. 163

20.0 Electrical Specifications ........................................................................................................................................................... 167

21.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 191

22.0 Packaging Information ............................................................................................................................................................. 193

Index ................................................................................................................................................................................................. 207

The Microchip Web Site .................................................................................................................................................................... 207

Customer Change Notification Service ............................................................................................................................................. 207

Customer Support ............................................................................................................................................................................. 207

Reader Response ............................................................................................................................................................................. 208

Product Identification System ............................................................................................................................................................ 209

DS41576B-page 6 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

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Customer Notification System

 2011 Microchip Technology Inc. Preliminary DS41576B-page 7

PIC12F752/HV752

NOTES:

DS41576B-page 8 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

Flash

Program

Memory

Data Bus

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

CLKIN

CLKOUT

PORTA

8-Level Stack

64 Bytes

1K X 14

(13-Bit)

Power-up

Timer

Power-on

Reset

Watchdog

Timer

MCLR

VSS

Brown-out

Reset

Timer0 Timer1

RA0

RA1

RA2

RA3

RA4

RA5

Analog Comparator

T0CKI

INT

T1CKI

Configuration

Internal

Oscillator

and Reference

T1G

VDD

Block

C1IN0+/C2IN0+

C1IN0-/C2IN0-

C1IN1-

C2IN1-

C1OUT/C2OUT

Shunt Regulator

(PIC12HV752 only)

Capture/

Compare/

PWM

(CCP)

Hardware

Limit

Timer1

(HLT)

Complementary

Output

Generator

(COG)

Timer2

Fixed Voltage

Reference

(FVR)

Dual Range

DAC

1.0 DEVICE OVERVIEW

The PIC12F752/HV752 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC and DFN packages.

FIGURE 1-1: PIC12F752/HV752 BLOCK DIAGRAM

Block Diagrams and pinout descriptions of the devices are in Figure 1-1 and Table 1-1.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 9

PIC12F752/HV752

TABLE 1-1: PIC12F752/HV752 PINOUT DESCRIPTION

Name Function

(2)

RA0/COG1OUT1

/C1IN0+/ C2IN0+/AN0/DACOUT/ REFOUT/ ICSPDAT

RA0 TTL HP General purpose I/O with IOC and WPU.

COG1OUT1 — HP COG output channel 1.

C1IN0+ AN — Comparator C1 positive input.

C2IN0+ AN — Comparator C2 positive input.

Input

Type

AN0 AN — A/D Channel 0 input.

DACOUT — AN DAC unbuffered Voltage Reference output.

REFOUT — AN DAC/FVR buffered Voltage Reference output.

ICSPDAT ST HP Serial Programming Data I/O.

RA1/C1IN0-/C2IN0-/AN1/

REF+/ICSPCLK

RA1 TTL CMOS General purpose I/O with IOC and WPU.

C1IN0- AN — Comparator C1 negative input.

C2IN0- AN — Comparator C2 negative input.

AN1 AN — A/D Channel 1 input.

REF+ AN — A/D Positive Voltage Reference input.

ICSPCLK ST — Serial Programming Clock.

RA2/INT/CCP1/C2OUT/ C1OUT/T0CKI/ COG1OUT0

(2)

/AN2

RA2 ST HP General purpose I/O with IOC and WPU.

INT ST — External interrupt.

CCP1 ST HP Capture/Compare/PWM 1.

C2OUT — HP Comparator C2 output.

C1OUT — HP Comparator C1 output.

T0CKI ST — Timer0 clock input.

COG1OUT0 — HP COG output channel 0.

AN2 AN — A/D Channel 2 input.

(1)

RA3 V

PP/MCLR

/T1G

(3)

/COG1FLT

(4)

(3)

RA3 TTL — General purpose input with WPU.

T1G ST — Timer1 Gate input.

COG1FLT ST — COG auto-shutdown fault input.

PP HV — Programming voltage.

MCLR

RA4/T1G COG1FLT CLKOUT

(2)

/COG1OUT1

(2)

/C1IN1-/AN3/

(3)

RA4 TTL CMOS General purpose I/O with IOC and WPU.

T1G ST — Timer1 Gate input.

COG1OUT1

COG1FLT

C1IN1- AN — Comparator C1 negative input.

AN3 AN — A/D Channel 3 input.

CLKOUT — CMOS F

RA5/T1CKI/COG1OUT0 C2IN1-/CLKIN

(3)

RA5 TTL CMOS General purpose I/O with IOC and WPU.

T1CKI ST — Timer1 clock input.

COG1OUT0 — CMOS COG output channel 0.

C2IN1- AN — Comparator C2 negative input.

CLKIN ST — External Clock input (EC mode).

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HP = High Power HV = High Voltage

* Alternate pin function.

Note 1: Input only.

2: Default pin function via the APFCON register. 3: Alternate pin function via the APFCON register. 4: RA3 pull-up is enabled when pin is configured as MCLR

Output

Typ e

—

Master Clear w/internal pull-up.

— CMOS COG output channel 1

ST — COG auto-shutdown fault input.

OSC/4 output.

in Configuration Word.

Description

DS41576B-page 10 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

PC<12:0>

0000h

0004h

0005h

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

Stack Level 2

Wraps to 0000h-03FFh

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F752/HV752 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space for PIC12F752/HV752. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC12F752/HV752

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 40h-6Fh in Bank 0 are General Purpose Registers, implemented as static RAM. Register locations 70h-7Fh in Bank 0 are Common RAM and shared as the last 16 addresses in all Banks. All other RAM is unimplemented and returns ‘0’ when read. The RP<1:0> bits of the STATUS register are the bank select bits.

RP0

RP1

00  Bank 0 is selected 01  Bank 1 is selected 10  Bank 2 is selected 11  Bank 3 is selected

 2011 Microchip Technology Inc. Preliminary DS41576B-page 11

PIC12F752/HV752

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file is organized as 64 x 8 in the PIC12F752/HV752. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF

and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tab le 2 -1 ). These registers are static RAM.

The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

DS41576B-page 12 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 0 BANK 1 BANK 2 BANK 3

INDF 00h INDF 80h INDF 100h INDF 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h LATA 105h ANSELA 185h

— 06h — 86h — 106h — 186h — 07h — 87h — 107h — 187h

IOCAF 08h IOCAP 88h IOCAN 108h APFCON 188h

— 09h — 89h — 109h OSCTUNE 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch WPUA 10Ch

PMCON1 18Ch

PIR2 0Dh PIE2 8Dh SLRCONA 10Dh PMCON2 18Dh

—0Eh —8Eh — 10Eh PMADRL 18Eh

TMR1L 0Fh OSCCON 8Fh PCON 10Fh PMADRH 18Fh TMR1H 10h FVRCON 90h TMR2 110h PMDATL 190h T1CON 11h DACCON0 91h

PR2 111h PMDATH 191h

T1GCON 12h DACCON1 92h T2CON 112h COG1PH 192h

CCPR1L 13h — 93h HLTMR1 113h COG1BLK 193h

CCPR1H 14h

— 94h HLTPR1 114h COG1DB 194h

CCP1CON 15h — 95h HLT1CON0 115h COG1CON0 195h

— 16h — 96h HLT1CON1 116h COG1CON1 196h

— 17h — 97h — 117h COG1ASD 197h

— 18h — 98h — 118h — 198h

— 19h — 99h — 119h — 199h

—1Ah —9Ah —11Ah — 19Ah

— 1Bh CM2CON0 9Bh —11Bh — 19Bh ADRESL 1Ch CM2CON1 9Ch

—11Ch — 19Ch ADRESH 1Dh CM1CON0 9Dh —11Dh — 19Dh ADCON0 1Eh CM1CON1 9Eh —11Eh — 19Eh ADCON1 1Fh CMOUT 9Fh

—11Fh — 19Fh

Unimplemented

20h

3Fh

Unimplemented

A0h

EFh

Unimplemented

120h

16Fh

Unimplemented

1A0h

1EFh

General Purpose Register

48 Bytes

40h

6Fh

Common RAM

16 Bytes

70h 7Fh

Common RAM

(Accesses

70h-7Fh)

F0h FFh

Common RAM

(Accesses

70h-7Fh)

170h 17Fh

Common RAM

(Accesses

70h-7Fh)

1F0h 1FFh

FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F752/HV752

 2011 Microchip Technology Inc. Preliminary DS41576B-page 13

PIC12F752/HV752

TABLE 2-1: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 0

Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

01h TMR0 Holding register for the 8-bit TMR0 xxxx xxxx uuuu uuuu

02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS

04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

05h PORTA

06h

— Unimplemented — —

07h

08h IOCAF

— Unimplemented — —

09h

0Ah PCLATH

0Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

0Ch PIR1

0Dh PIR2

— Unimplemented — —

0Eh

0Fh

TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx

10h

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu

11h

T1CON

12h T1GCON

13h

CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx uuuu uuuu

14h

CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx uuuu uuuu

15h

CCP1CON

16h

— Unimplemented — —

1Bh

ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx uuuu uuuu

1Ch

1Dh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx uuuu uuuu

1Eh

ADCON0 ADFM VCFG CHS<3:0> GO/DONE

1Fh

ADCON1

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatch exists.

IRP RP1 RP0 TO

— —

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 00---000 00---000

— — C2IF C1IF — COG1IF — CCP1IF --00 -0-0 --00 -0-0

TMR1CS<1:0> T1CKPS<1:0>

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

— —

— ADCS<2:0> — — — —

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the

RA5 RA4 RA3 RA2 RA1 RA0

IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

DC1B<1:0> CCP1M<3:0>

Reset and Watchdog Timer Reset during normal operation.

PD ZDCC

Reserved

DONE

T1SYNC

T1GVAL T1GSS<1:0>

—

TMR1ON 0000 00-0

ADON

Value on

POR/BOR

Reset

0001 1xxx 000q quuu

--xx xxxx --uu uuuu

--00 0000 --00 0000

(2)

0000 0000 0000 0000

0000 0x00 uuuu uxuu

--00 0000 --00 0000

0000 0000 0000 0000

-000 ---- -000 ----

Value o n

all other

Resets

uuuu uuuu

uuuu uu-u

(1)

DS41576B-page 14 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

TABLE 2-2: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

81h OPTION_REG

82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS

84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

85h TRISA — — TRISA5 TRISA4 TRISA3

86h — Unimplemented — —

87h — Unimplemented — —

88h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000

89h — Unimplemented — —

8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

8Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

8Ch PIE1 TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 00-- -000 00-- -000

8Dh PIE2 — — C2IE C1IE — COG1IE — CCP1IE --00 -0-0 --00 -0-0

8Eh — Unimplemented — —

8Fh OSCCON

90h FVRCON FVREN FVRRDY FVR-

91h DACCON0 DACEN DACRNG DACOE — — DAC PSS0 — — 000- -0-- 000- -0--

92h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000

93h

— Unimplemented — —

9Ah

9Bh CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100

9Ch CM2CON1 C2INTP C2INTN C2PCH<1:0> — — — C2NCH0 0000 ---0 0000 ---0

9Dh CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100

9Eh CM1CON1 C1INTP C1INTN C1PCH<1:0> — — — C1NCH0 0000 ---0 0000 ---0

9Fh CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatch exists.

3: TRISA3 always reads ‘1’.

RAPU

IRP RP1 RP0 TO

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the

INTEDG T0CS T0SE PSA PS<2:0>

PD ZDCC

(3)

TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

— —

IRCF<1:0>

BUFEN

FVR-

BUFSS

Reset and Watchdog Timer Reset during normal operation.

—

— — — —

HTS LTS

—

Valu e o n

POR/BOR

Reset

1111 1111 1111 1111

0001 1xxx 000q quuu

(2)

0000 0000 0000 0000

--01 -00- --uu -uu-

0000 ---- 0000 ----

Values on

all other

(1)

Resets

 2011 Microchip Technology Inc. Preliminary DS41576B-page 15

PIC12F752/HV752

TABLE 2-3: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 2

Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

101h TMR0 Holding Register for the 8-bit Timer0 Register xxxx xxxx uuuu uuuu

102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

103h STATUS

104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

105h LATA — —LATA5LATA4— LATA2 L ATA1 LATA 0 --xx -xxx --uu -uuu

106h — Unimplemented — —

107h — Unimplemented — —

108h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000

109h — Unimplemented — —

10Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

10Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

10Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --00 0000 --00 0000

10Dh SLRCONA — — — — —SLRA2 —SLRA0---- -0-0 ---- -0-0

10Eh — Unimplemented — —

10Fh PCON — — — — — —PORBOR ---- --qq ---- --uu

110h

TMR2 Holding Register for the 8-bit Timer2 Register 0000 0000 0000 0000

111h PR2 Timer2 Period Register 1111 1111 1111 1111

112 h T 2CO N — TOUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

113h HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Register 0000 0000 0000 0000

114h HLTPR1 Hardware Limit Timer1 Period Register 1111 1111 1111 1111

115h HLT1CON0 — H1OUTPS<3:0> H1ON H1CKPS<1:0> -000 0000 -000 0000

116h HLT1CON1 — — — H1ERS<2:0> H1FEREN H1REREN ---0 0000 ---0 0000

117 h

— Unimplemented — —

11F h

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatch exists.

IRP RP1

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the

RP0 TO PD ZDCC0001 1xxx 000q quuu

Reset and Watchdog Timer Reset during normal operation.

Value on

POR/BOR

Reset

(2)

0000 0000 0000 0000

Val ue o n

all other

Resets

(1)

DS41576B-page 16 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

TABLE 2-4: PIC12F752/HV752 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

181h OPTION_REG

182h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

183h STATUS

184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

185h ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 --11 -111 --11 -111

186h

— Unimplemented — —

187h

— Unimplemented — —

188h APFCON

189h OSCTUNE — — — TUN<4:0> ---0 0000 ---u uuuu

18Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

18Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

18Ch PMCON1 — — — — —WRENWR RD---- -000 ---- -000

18Dh PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----

18Eh PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000

18Fh PMADRH — — — — — — PMADRH<1:0> ---- --00 ---- --00

190h PMDATL Program Memory Data Register Low Byte 0000 0000 0000 0000

191h PMDATH — — Program Memory Data Register High Byte --00 0000 --00 0000

192h COG1PH

193h COG1BLK G1BLKR<3:0> G1BLKF<3:0> xxxx xxxx uuuu uuuu

194h COG1DB G1DBR<3:0> G1DBF<3:0> xxxx xxxx uuuu uuuu

195h COG1CON0

196h COG1CON1

197h COG1ASD

198h

— Unimplemented — —

19Fh

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

RAPU

IRP RP1 RP0 TO

— — —

— — — —

G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD G1CS<1:0>

G1FSIM G1RSIM

G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the mismatch exists.

INTEDG T0CS T0SE PSA PS<2:0>

PD ZDCC

T1GSEL

G1FS<2:0> G1RS<2:0>

Reset and Watchdog Timer Reset during normal operation.

— COG1FSEL COG1O1SEL COG1O0SEL ---0 -000 ---0 -000

G1PH<3:0> ---- xxxx ---- uuuu

Val ue on

POR/BOR

Reset

1111 1111 1111 1111

0001 1xxx 000q quuu

(2)

0000 0000 0000 0000

Values on

all other

(1)

Resets

 2011 Microchip Technology Inc. Preliminary DS41576B-page 17

PIC12F752/HV752

2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM)

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO

and PD bits are not

writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 16.0

“Instruction Set Summary”.

REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh)

bit 6 RP1: Register Bank Select bit (used for direct addressing)

00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh)

bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h-FFh) 0 = Bank 0 (00h-7Fh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Borrow

bit 0 C: Carry/Borrow

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

bit

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

(2)

bit

(ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed.

(2)

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

PD ZDC

(1)

Note 1: The C and DC bits operate as a Borrow

DS41576B-page 18 Preliminary  2011 Microchip Technology Inc.

instructions for examples.

2: For Borrow

For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.

and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF

PIC12F752/HV752

000

001

010

011

100

101

110

111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

BIT VALUE TIMER0 RATE WDT RATE

2.2.2.2 OPTION Register

The OPTION register is a readable and writable register, which contains various control bits to configure:

• Timer0/WDT prescaler

• External RA2/INT interrupt

•Timer0

• Weak pull-ups on PORTA

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG T0CS T0SE PSA PS<2:0>

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 6.1.3 “Software Programmable Prescaler”.

bit 7 RAPU

: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (F

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

OSC/4)

 2011 Microchip Technology Inc. Preliminary DS41576B-page 19

PIC12F752/HV752

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, IOCIE change and external RA2/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit

1 = Enables the IOC change interrupt 0 = Disables the IOC change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit

1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = An IOC pin has changed state and generated an interrupt 0 = No pin interrupts have been generated

(2)

(1)

Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

DS41576B-page 20 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

2.2.2.4 PIE1 Register

The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-4.

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIE: ADC Interrupt Enable bit

1 = Enables the TMR1 gate interrupt 0 = Disables the TMR1 gate interrupt

bit 6 ADIE: ADC Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5-3 Unimplemented: Read as ‘0’

bit 2 HLTMR1IE: Hardware Limit Timer1 Interrupt Enable bit

1 = Enables the HLTMR1 interrupt 0 = Disables the HLTMR1 interrupt

bit 1 TMR2IE: Timer2 Interrupt Enable bit

1 = Enables the Timer2 interrupt 0 = Disables the Timer2 interrupt

bit 0 TMR1IE: Timer1 Interrupt Enable bit

1 = Enables the Timer1 interrupt 0 = Disables the Timer1 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 21

PIC12F752/HV752

2.2.2.5 PIE2 Register

The PIE2 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-5.

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0

— — C2IE C1IE —COG1IE — CCP1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator 2 interrupt 0 = Disables the Comparator 2 interrupt

bit 4 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt

bit 3 Unimplemented: Read as ‘0’

bit 2 COG1IE: COG 1 Interrupt Flag bit

1 = COG1 interrupt enabled 0 = COG1 interrupt disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS41576B-page 22 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

2.2.2.6 PIR1 Register

The PIR1 register contains the Peripheral Interrupt flag bits, as shown in Register 2-6.

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

TMR1GIF ADIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIF: TMR1 Gate Interrupt Flag bit

1 = Timer1 gate interrupt is pending 0 = Timer1 gate interrupt is not pending

bit 6 ADIF: ADC Interrupt Flag bit

1 = ADC conversion complete 0 = ADC conversion has not completed or has not been started

bit 5-3 Unimplemented: Read as ‘0’

bit 2 HLTMR1IF: Hardware Limit Timer1 to HLTPR1 Match Interrupt Flag bit

1 = HLTMR1 to HLTPR1 match occurred (must be cleared in software) 0 = HLTMR1 to HLTPR1 match did not occur

bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match did not occur

bit 0 TMR1IF: Timer1 Interrupt Flag bit

1 = Timer1 rolled over (must be cleared in software) 0 = Timer1 has not rolled over

— — — HLTMR1IF TMR2IF TMR1IF

Note: Interrupt flag bits are set when an interrupt

 2011 Microchip Technology Inc. Preliminary DS41576B-page 23

PIC12F752/HV752

2.2.2.7 PIR2 Register

The PIR2 register contains the Peripheral Interrupt flag bits, as shown in Register 2-7.

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0

— — C2IF C1IF COG1IF — CCP1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 C2IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed

bit 4 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed

bit 3 Unimplemented: Read as ‘0’

bit 2 COG1IF: COG 1 Interrupt Flag bit

1 = COG1 has generated an auto-shutdown interrupt 0 = COG1 has NOT generated an auto-shutdown interrupt

bit 1 Unimplemented: Read as ‘0’

bit 0 CCP1IF: ECCP Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM mode Unused in this mode

Note: Interrupt flag bits are set when an interrupt

DS41576B-page 24 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

2.2.2.8 PCON Register

The Power Control (PCON) register (see Tab le 1 7- 2) contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR

The PCON register also controls the software enable of the BOR

The PCON register bits are shown in Register 2-8.

REGISTER 2-8: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-q/u R/W-q/u

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = unchanged

)

Reset

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR

bit 0 BOR

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

 2011 Microchip Technology Inc. Preliminary DS41576B-page 25

PIC12F752/HV752

12 8 7 0

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

MOVLW 0x40 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer BTFSS FSR,7 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0>  PCH). The lower example in

Figure 2-3 shows how the PC is loaded during a CALL or

GOTO instruction (PCLATH<4:3>  PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.2 STACK

The PIC12F752/HV752 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

2.4 Indirect Addressing, INDF and FSR Registers

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table.

For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556).

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-4.

A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

DS41576B-page 26 Preliminary  2011 Microchip Technology Inc.

PIC12F752/HV752

Data Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1 RP0 6

From Opcode

IRP File Select Register

Bank Select

Location Select

00 01 10 11

180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

For memory map detail, see Figure 2-2.

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F752/HV752

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3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL

The Flash program memory is readable and writable during normal operation (full V is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5). There are six SFRs used to read and write this memory:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

• PMADRL

• PMADRH

When interfacing the program memory block, the PMDATL and PMDATH registers form a two-byte word which holds the 14-bit data for read/write, and the PMADRL and PMADRH registers form a two-byte word which holds the 10-bit address of the Flash location being accessed. These devices have 1K words of program Flash with an address range from 0000h to 03FFh.

The program memory allows single word read and a by four word write. A four word write automatically erases the row of the location and writes the new data (erase before write).

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations.

When the device is code-protected, the CPU may continue to read and write the Flash program memory.

Depending on the settings of the Flash Program Memory Enable (WRT<1:0>) bits, the device may or may not be able to write certain blocks of the program memory, however, reads of the program memory are allowed.

When the Flash program memory Code Protection

) bit in the Configuration Word register is enabled,

(CP the program memory is code-protected, and the device programmer (ICSP™) cannot access data or program memory.

DD range). This memory

3.1 PMADRH and PMADRL Registers

The PMADRH and PMADRL registers can address up to a maximum of 1K words of program memory.

When selecting a program address value, the Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register.

3.2 PMCON1 and PMCON2 Registers

PMCON1 is the control register for the data program memory accesses.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear.

PMCON2 is not a physical register. Reading PMCON2 will read all ‘0’s. The PMCON2 register is used exclusively in the Flash memory write sequence.

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3.3 Flash Program Memory Control Registers

REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMDATL<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMDATL<7:0>: 8 Least Significant Data bits to Write or Read from Program Memory

REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMADRL<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation

REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— —PMDATH<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 PMDATH<5:0>: 6 Most Significant Data bits from Program Memory

REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — PMADRH<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1-0 PMADRH<1:0>: Specifies the 2 Most Significant Address bits or High bits for Program Memory Reads.

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REGISTER 3-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0

— — — — —WRENWR RD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7-3 Unimplemented: Read as ‘0’

bit 2 WREN: Program/Erase Enable bit

1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash

bit 1 WR: Write Control bit

1 = Initiates a program Flash program/erase operation

The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software.

0 = Program/erase operation to the Flash is complete and inactive

bit 0 RD: Read Control bit

1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can

only be set (not cleared) in software.

0 = Does not initiate a program Flash read

Note 1: Unimplemented bit, read as ‘1’.

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BANKSEL PM_ADR ; Change STATUS bits RP1:0 to select bank with PMADRL MOVLW MS_PROG_PM_ADDR ; MOVWF PMADRH ; MS Byte of Program Address to read MOVLW LS_PROG_PM_ADDR ; MOVWF PMADRL ; LS Byte of Program Address to read BANKSEL PMCON1 ; Bank to containing PMCON1 BSF PMCON1, RD ; PM Read

NOP ; First instruction after BSF PMCON1,RD executes normally

NOP ; Any instructions here are ignored as program

; memory is read in second cycle after BSF PMCON1,RD

; BANKSEL PMDATL ; Bank to containing PMADRL MOVF PMDATL, W ; W = LS Byte of Program PMDATL MOVF PMDATH, W ; W = MS Byte of Program PMDATL

3.4 Reading the Flash Program Memory

To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “

PMCON1,RD

” instruction to be ignored. The data is available in the very next cycle in the PMDATL and PMDATH registers; it can be read as two bytes in the following instructions. PMDATL and PMDATH registers will hold this value until another read or until it is written to by the user (during a write operation).

EXAMPLE 3-1: FLASH PROGRAM READ

BSF

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,RD

Executed here

INSTR (PC + 1)

Executed here

NOP

Executed here

PC PC + 1 PMADRH,PMADRL PC+3 PC + 5

Flash ADDR

RD bit

INSTR (PC)

PMDATH,PMDATL

INSTR (PC + 3)

PC + 3 PC + 4

INSTR (PC + 4)

INSTR (PC + 1)

INSTR (PC - 1)

Executed here

INSTR (PC + 3)

Executed here

INSTR (PC + 4)

Executed here

Flash DATA

PMDATH

PMDATL Register

PMRHLT

FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

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3.5 Writing the Flash Program

Memory

A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory.

Flash program memory must be written in four-word blocks. See Figure 3-2 and Figure 3-3 for more details. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where PMADRL<1:0> = 00. All block writes to program memory are done as 16-word erase by fourword write operations. The write operation is edgealigned and cannot occur across boundaries.

To write program data, it must first be loaded into the buffer registers (see Figure 3-2). This is accomplished by first writing the destination address to PMADRL and PMADRH and then writing the data to PMDATL and PMDATH. After the address and data have been set up, then the following sequence of events must be executed:

1. Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

2. Set the WR control bit of the PMCON1 register.

All four buffer register locations should be written to with correct data. If less than four words are being written to in the block of four words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the PMDATL and PMDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed.

To transfer data from the buffer registers to the program memory, the PMADRL and PMADRH must point to the last location in the four-word block (PMADRL<1:0> =

11). Then the following sequence of events must be executed:

1. Write 55h, then AAh, to PMCON2 (Flash pro-

gramming sequence).

2. Set control bit WR of the PMCON1 register to

begin the write operation.

The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (000, 001, 010, 011). When the write is performed on the last word (PMADRL<1:0> = 11), a block of sixteen words is automatically erased and the content of the four-word buffer registers are written into the program memory.

After the “BSF PMCON1,WR” instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buffer registers, the writing of the first three words of the block appears to occur immediately. The processor will halt internal operations for the typical 4 ms, only during the cycle in

which the erase takes place (i.e., the last word of the sixteen-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the four-word write cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. The above sequence must be repeated for the higher 12 words.

3.6 Protection Against Spurious Write

There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents program memory writes.

The write initiate sequence and the WREN bit help prevent an accidental write during brown-out, power glitch or software malfunction.

3.7 Operation During Code-Protect

When the device is code-protected, the CPU is able to read and write unscrambled data to the program memory.

3.8 Operation During Write Protect

When the program memory is write-protected, the CPU can read and execute from the program memory. The portions of program memory that are write protected can be modified by the CPU using the PMCON registers, but the protected program memory cannot be modified using ICSP mode.

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14 14 14

Program Memory

Buffer Register

PMADRL<1:0> = 00

Buffer Register

PMADRL<1:0> = 01

Buffer Register

PMADRL<1:0> = 10

Buffer Register

PMADRL<1:0> = 11

PMDATLPMDATH

First word of block to be written

If at a new row

to Flash automatically after this word is written

are transferred

Flash are erased, then four buffers

sixteen words of

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,WR

Executed here

INSTR (PC + 1)

Executed here

PC + 1

Flash

INSTR

PMDATH,PMDATL

INSTR (PC+3)

INSTR

NOP

Executed here

Flash

PMWHLT

WR bit

Processor halted PM Write Time

PMADRH,PMADRL

PC + 3 PC + 4

INSTR (PC + 3)

Executed here

ADDR

DATA

Memory

Location

ignored

read

PC + 2

INSTR (PC+2)

(INSTR (PC + 2)

NOP

Executed here

(PC)

(PC + 1)

FIGURE 3-2: BLOCK WRITES TO 1K FLASH PROGRAM MEMORY

FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This write routine assumes the following: ; A valid starting address (the least significant bits = '00') ; is loaded in ADDRH:ADDRL ; ADDRH, ADDRL and DATADDR are all located in data memory

; BANKSEL PMADRH MOVF ADDRH,W ;Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVF DATAADDR,W ;Load initial data address MOVWF FSR ;

LOOP MOVF INDF,W ;Load first data byte into lower

MOVWF PMDATL ; INCF FSR,F ;Next byte MOVF INDF,W ;Load second data byte into upper MOVWF PMDATH ; INCF FSR,F ; BANKSEL PMCON1 BSF PMCON1,WREN ;Enable writes BCF INTCON,GIE ;Disable interrupts (if using) BTFSC INTCON,GIE ;See AN576 GOTO $-2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Required Sequence MOVLW 55h ;Start of required write sequence: MOVWF PMCON2 ;Write 55h MOVLW 0AAh ; MOVWF PMCON2 ;Write 0AAh BSF PMCON1,WR ;Set WR bit to begin write NOP ;Required to transfer data to the buffer NOP ;registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; BCF PMCON1,WREN ;Disable writes BSF INTCON,GIE ;Enable interrupts (comment out if not using interrupts) BANKSEL PMADRL MOVF PMADRL, W INCF PMADRL,F ;Increment address ANDLW 0x03 ;Indicates when sixteen words have been programmed SUBLW 0x03 ;Change value for different size write blocks

;0x0F = 16 words ;0x0B = 12 words ;0x07 = 8 words

;0x03 = 4 words BTFSS STATUS,Z ;Exit on a match, GOTO LOOP ;Continue if more data needs to be written

An example of the complete four-word write sequence is shown in Example 3-2. The initial address is loaded into the PMADRH and PMADRL register pair; the four words of data are loaded using indirect addressing.

EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY

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TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PMCON1

PMCON2 Program Memory Control Register 2

PMADRL PMADRL<7:0>

PMADRH

PMDATL PMDATL<7:0>

PMDATH

INTCON GIE PEIE

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.

* Page provides register information.

— — — — —

— — — — — — PMADRH<1:0> 30

— — PMDATH<5:0> 30

T0IE INTE IOCIE T0IF INTF IOCIF

WREN WR RD

TABLE 3-2: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG

Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by Flash program memory.

13:8

7:0 —CPMCLRE PWRTE WDTE — — FOSC0

— — DEBUG CLKOUTEN WRT<1:0> BOREN<1:0>

Page

29*

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(CPU and

CLKIN

System Clock

MUX

FOSC

Internal Oscillator

HFINTOSC

8 MHz

LFINTOSC

31 kHz

Prescaler

÷1

÷2

÷8

IRCF<1:0>

COG Clock Source

HFINTOSC Enable

(Figure 4-2)

WDT Clock Source

LFINTOSC Enable

(Figure 4-2)

Peripherals)

EC Enable

(Figure 4-2)

FOSC0

Sleep

HFINTOSC Enable

IRCF<1:0>  00

FOSC0

Sleep

EC Enable

FOSC0

Sleep LFINTOSC Enable

IRCF<1:0> = 00

WDTE

4.0 OSCILLATOR MODULE

The internal oscillator module provides the following selectable system clock modes:

4.1 Overview

The oscillator module has a variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance

• 8 MHz (HFINTOSC)

• 4 MHz (HFINTOSC Postscaler)

• 1 MHz (HFINTOSC Postscaler)

• 31 kHz (LFINTOSC)

and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module.

The oscillator module can be configured in one of two clock modes.

1. EC (external clock)

2. INTOSC (internal oscillator)

Clock Source modes are configured by the FOSC bit in the Configuration Word register (CONFIG).

FIGURE 4-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

FIGURE 4-2: OSCILLATOR ENABLE

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CLKIN

CLKOUT

(1)

I/O

Clock from Ext. System

PIC

MCU

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

CLKOUT

(1)

I/O

PIC

MCU

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

I/O

CLKIN

(1)

4.2 Clock Source Modes

Clock Source modes can be classified as external or internal:

• The External Clock mode relies on an external clock for the clock source. For example, a clock module or clock output from another circuit.

• Internal clock sources are contained internally within the oscillator module. The oscillator module has four selectable clock frequencies:

-8MHz

-4MHz

-1MHz

-31kHz

The system clock can be selected between external or internal clock sources via the FOSC0 bit of the Configuration Word register (CONFIG).

4.2.1 EC MODE

The External Clock (EC) mode allows an externally generated logic as the system clock source. The EC clock mode is selected when the FOSC0 bit of the Configuration Word is set.

When operating in this mode, an external clock source must be connected to the CLKIN input. The CLKOUT is available for either general purpose I/O or system clock output. Figure 4-3 shows the pin connections for EC mode.

Because the PIC the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

MCU design is fully static, stopping

When one of the HFINTOSC frequencies is selected, the frequency of the internal oscillator can be trimmed by adjusting the TUN<4:0> bits of the OSCTUNE register.

Operation after a Power-on Reset (POR) or wake-up from Sleep is delayed by the oscillator start-up time. Delays are typically longer for the LFINTOSC than HFINTOSC because of the very low-power operation and relatively narrow bandwidth of the LF internal oscillator. However, when another peripheral keeps the oscillator running during Sleep, the start-up time is delayed to allow the memory bias to stabilize.

FIGURE 4-4: INTERNAL CLOCK MODE

OPERATION

4.2.2.1 Oscillator Ready Bits

The HTS and LTS bits of the OSCCON register indicate the status of the HFINTOSC and LFINTOSC, respectively. When either bit is set, it indicates that the corresponding oscillator is running and stable.

FIGURE 4-3: EXTERNAL CLOCK (EC)

MODE OPERATION

4.2.2 INTERNAL CLOCK MODE

Internal clock mode configures the internal oscillators as the system clock source. The internal clock mode is selected when the FOSC0 bit of the Configuration Word is cleared. The source and frequency are selected with the IRCF<1:0> bits of the OSCCON register.

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4.3 System Clock Output

The CLKOUT pin is available for general purpose I/O or system clock output. The CLKOUTEN Configuration Word controls the function of the CLKOUT pin.

When the CLKOUTEN is driven by the selected internal oscillator frequency divided by 4. The corresponding I/O pin always reads ‘0’ in this configuration.

The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements.

When the CLKOUTEN function is disabled and the CLKOUT pin is available for general purpose I/O.

bit is cleared, the CLKOUT pin

bit is set, the system clock out

bit of the

4.4 Oscillator Delay upon Wake-Up, Power-Up, and Base Frequency Change

In applications where the OSCTUNE register is used to shift the HFINTOSC frequency, the application should not expect the frequency to stabilize immediately. In this case, the frequency may shift gradually toward the new value. The time for this frequency shift is less than eight cycles of the base frequency.

A short delay is invoked upon power-up and when waking from sleep to allow the memory bias circuitry to stabilize. Table 4-1 shows examples where the oscillator delay is invoked.

TABLE 4-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR INTOSC 31 kHz to 8 MHz

Sleep/POR EC DC – 20 MHz

10 s internal delay to allow memory bias to stabilize.

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4.5 Oscillator Control Registers

REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 U-0 R/W-0/u R/W-1/u U-0 R-0/u R-0/u U-0

— —IRCF<1:0>—HTSLTS —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits

11 = 8 MHz 10 = 4 MHz 01 = 1 MHz (Reset default) 00 = 31 kHz (LFINTOSC)

bit 3 Unimplemented: Read as ‘0’

bit 2 HTS: HFINTOSC Status bit

1 = HFINTOSC is stable 0 = HFINTOSC is not stable

bit 1 LT S: LFINTOSC Status bit

1 = LFINTOSC is stable 0 = LFINTOSC is not stable

bit 0 Unimplemented: Read as ‘0’

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4.5.1 OSCTUNE REGISTER

The oscillator is factory calibrated, but can be adjusted in software by writing to the OSCTUNE register (Register 4-2).

The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number.

When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u

— — — TUN<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximum frequency 01110 =

•

00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 =

•

• 10000 = Minimum frequency

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

OSCTUNE

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word register (Register 17-1) for operation of all register bits.

— —IRCF<1:0>—HTSLTS— 42

— — —TUN<4:0> 43

oscillators.

TABLE 4-3: SUMMARY OF CONFIGURATION WORD CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG

Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by oscillator module.

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13:8

7:0

— — DEBUG CLKOUTEN WRT<1:0> BOREN<1:0>

— CP MCLRE PWRTE WDTE — —FOSC0

on Page

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Write LATA

Data Register

I/O pin

Read PORTA

Write PORTA

TRISA

Read LATA

Data Bus

To peripherals

ANSELA

VDD

VSS

; This code example illustrates ; initializing the PORTA register. The ; other ports are initialized in the same ; manner.

BANKSEL PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as

;outputs

5.0 I/O PORTS

For this device there is one port available, PORTA. In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read.

PORTA has three standard registers for its operation. These registers are:

• TRISA registers (data direction)

• PORTA registers (reads the levels on the pins of the device)

• LATA registers (output latch)

Some ports may have one or more of the following additional registers. These registers are:

• ANSELA (analog select)

• WPUA (weak pull-up)

The Data Latch (LATA register) is useful for readmodify-write operations on the value that the I/O pins are driving.

A write operation to the LATA register has the same effect as a write to the corresponding PORTA register. A read of the LATA register reads the values held in the I/O PORT latches, while a read of the PORTA register reads the actual I/O pin value.

Ports that support analog inputs have an associated ANSEL register. When an ANSELA bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 5-1.

EXAMPLE 5-1: INITIALIZING PORTA

FIGURE 5-1: GENERIC I/O PORTA

OPERATION

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5.1 Alternate Pin Function

The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 5-1. For this device family, the following functions can be moved between different pins.

•Timer1 Gate

• COG1

These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.

5.2 Alternate Pin Function Control Register

REGISTER 5-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — —

bit 7 bit 0

T1GSEL

— COG1FSEL COG1O1SEL COG1O0SEL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’.

bit 4 T1GSEL: Timer 1 Gate Input Pin Selection bit

1 = T1G function is on RA3 0 = T1G function is on RA4

bit 3 Unimplemented: Read as ‘0’.

bit 2 COG1FSEL: COG1 Fault Input Pin Selection bit

1 = COG1FLT is on RA3 0 = COG1FLT is on RA4

bit 1 COG1O1SEL: COG1 Output 1 Pin Selection bit

1 = COG1OUT1 is on RA4 0 = COG1OUT1 is on RA0

bit 0 COG1O0SEL: COG1 Output 0 Pin Selection bit

1 = COG1OUT0 is on RA5 0 = COG1OUT0 is on RA2

DS41576B-page 46 Preliminary  2011 Microchip Technology Inc.

5.3 PORTA and the TRISA Registers

PORTA is a 6-bit wide port with 5 bidirectional and 1 input-only pin. The corresponding data direction register is TRISA (Register 5-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’.

Example 5-1 shows how to initialize PORTA.

Reading the PORTA register (Register 5-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1.

The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’.

Note: The ANSEL register must be initialized to

configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt.

PIC12F752/HV752

TABLE 5-1: PORTA OUTPUT PRIORITY

Pin Name Function Priority

RA0 ICSPDAT

REFOUT DACOUT COG1OUT1 RA0

RA1 RA1

RA2 COG1OUT0

C1OUT C2OUT CCP1 RA2

RA3 None

RA4 CLKOUT

COG1OUT1 RA4

RA5 COG1OUT0

RA5

Note 1: Priority listed from highest to lowest.

2: Default function pin (see APFCON register). 3: Alternate function pin (see APFCON register).

(1)

(2)

(3)

5.3.1 PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Tab l e 5 - 1.

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input functions, such as comparator inputs, are not shown in the priority lists. These inputs are active when the peripheral is enabled and the input multiplexer for the pin is selected. The Analog mode, set with the ANSELA register, disables the digital input buffer thereby preventing excessive input current when the analog input voltage is between logic states. Digital output functions may control the pin when it is in Analog mode with the priority shown in Table 5-1.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 47

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5.4 PORTA Control Registers

REGISTER 5-2: PORTA: PORTA REGISTER

U-0 U-0 R/W-x/u R/W-x/u R-x/x R/W-x/u R/W-x/u R/W-x/u

— — RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RA<5:0>: PORTA I/O Value bits

1 = Port pin is > VIH 0 = Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O

pin values.

(1)

REGISTER 5-3: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1

— — TRISA5 TRISA4 TRISA3

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISA<5:0>: PORTA Tri-State Control bits

1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output

Note 1: TRISA3 always reads ‘1’.

(1)

TRISA2 TRISA1 TRISA0

REGISTER 5-4: LATA: PORTA DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u

— —LATA5LATA4— LATA2 LATA1 LATA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 LATA<5:4>: PORTA Output Latch Value bits

bit 3 Unimplemented: Read as ‘0’

bit 2-0 LATA<2:0>: PORTA Output Latch Value bits

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O

pin values.

DS41576B-page 48 Preliminary  2011 Microchip Technology Inc.

(1)

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5.5 Additional Pin Functions

Every PORTA pin on the PIC12F752 has an interrupton-change option and a weak pull-up option. The next three sections describe these functions.

5.5.1 ANSELA REGISTER

The ANSELA register (Register 5-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly.

The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

Note: The ANSELA bits default to the Analog

mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software.

5.5.2 WEAK PULL-UPS

Each of the PORTA pins, except RA3, has an individually configurable internal weak pull-up. Control bits WPUx enable or disable each pull-up. Refer to

off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the

bit of the OPTION_REG register). A weak pull-

RAPU up is automatically enabled for RA3 when configured as MCLR and disabled when RA3 is an I/O. There is no software control of the MCLR

pull-up.

5.5.3 INTERRUPT-ON-CHANGE

Each PORTA pin is individually configurable as an interrupt-on-change pin. Control bits IOCA enable or disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The ‘mismatch’ outputs of the last read are OR’d together to set the PORTA Change Interrupt Flag bit (IOCIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by:

a) Any read of PORTA AND Clear flag bit IOCIF.

This will end the mismatch condition;

b) Any write of PORTA AND Clear flag bit IOCIF

will end the mismatch condition;

A mismatch condition will continue to set flag bit IOCIF. Reading PORTA will end the mismatch condition and allow flag bit IOCIF to be cleared. The latch holding the last read value is not affected by a MCLR Reset. After these Resets, the IOCIF flag will continue to be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when any PORTA operation is being executed, then the IOCIF interrupt flag may not get set.

nor BOR

5.5.4 SLEW RATE CONTROL

Two of the PORTA pins, RA0 and RA2, are equipped with high current driver circuitry. The SLRCONA register provides reduced slew rate control to mitigate possible EMI radiation from these pins.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 49

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REGISTER 5-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ANSA<5:4>: Analog Select Between Analog or Digital Function on Pin RA<5:4> bits

1 = Analog input. Pin is assigned as analog input 0 = Digital I/O. Pin is assigned to port or special function.

bit 3 Unimplemented: Read as ‘0’

bit 2-0 ANSA<2:0> Analog Select Between Analog or Digital Function on Pin RA<2:0> bits

1 = Analog input. Pin is assigned as analog input. 0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-

change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

REGISTER 5-6: WPUA: WEAK PULL-UP PORTA REGISTER

(1)

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — WPU5 WPU4 WPU3 WPU2 WPU1 WPU0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPU<5:0>: Weak Pull-up Control bits

1 = Pull-up enabled 0 = Pull-up disabled

Note 1: Global RAPU

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). 3: The RA3 pull-up is enabled when configured as MCLR

as an input and reads as ‘0’.

must be enabled for individual pull-ups to be enabled.

in the Configuration Word, otherwise it is disabled

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REGISTER 5-7: SLRCONA: SLEW RATE CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0

— — — — —SLRA2 —SLRA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 SLRA2: Slew Rate Control bit

1 = Pin voltage slews at limited rate 0 = Pin voltage slews at maximum rate

bit 1 Unimplemented: Read as ‘0’

bit 0 SLRA0: Slew Rate Control bit

1 = Pin voltage slews at limited rate 0 = Pin voltage slews at maximum rate

Note 1: Global RAPU

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). 3: The RA3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled

as an input and reads as ‘0’.

must be enabled for individual pull-ups to be enabled.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 51

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REGISTER 5-8: IOCAP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAP<5:0>: Interrupt-on-Change Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will

be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin.

REGISTER 5-9: IOCAN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAN<5:0>: Interrupt-on-Change Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will

be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin.

REGISTER 5-10: IOCAF: INTERRUPT-ON-CHANGE FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAF<5:0>: Interrupt-on-Change Flag bits

1 = An enabled change was detected on the associated pin.

Set when IOCAPx = 1 and a rising edge was detected on RBx, or when IOCANx = 1 and a falling edge was detected on RAx.

0 = No change was detected, or the user cleared the detected change.

DS41576B-page 52 Preliminary  2011 Microchip Technology Inc.

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TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADCON0 ADFM VCFG CHS<3:0> GO/DONE

ADCON1

ANSELA

APFCON

CM1CON0

CM2CON0

CM1CON1

CM2CON1

DACCON0 DACEN

IOCAF

IOCAN

IOCAP

LATA

OPTION_REG

PORTA

SLRCONA

TRISA

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: TRISA3 always reads ‘1’.

— ADCS<2:0> — — — —

— — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 50

— — —T1GSEL— COG1FSEL COG1O1SEL COG1O0SEL 46

C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 127

C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 127

C1INTP C1INTN C1PCH<1:0> — — — C1NCH0 128

C2NTP C2INTN C2PCH<1:0> — — — C2NCH0 128

DACRNG DACOE — — DACPSS0 — — 11 8

— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 52

— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 52

— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 52

— —LATA5LATA4— L ATA2 LATA 1 LATA 0 48

RAPU INTEDG T0CS T0SE PSA PS<2:0> 19

— — RA5 RA4 RA3 RA2 RA1 RA0 48

— — — — —SLRA2 —SLRA051

— — TRISA5 TRISA4 TRISA3

(1)

TRISA2 TRISA1 TRISA0 48

Page

ADON 106

107

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NOTES:

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T0CKI

T0SE

TMR0

Watchdog

Timer

WDT

Time-out

PS<2:0>

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.

2: WDTE bit is in the Configuration Word register.

8-bit

Prescaler

FOSC/4

PSA

Sync

2 T

Shared Prescale

WDTE

LFINTOSC

(Figure 4-1)

2

PSA

6.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

Figure 6-1 is a block diagram of the Timer0 module.

6.1 Timer0 Operation

When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter.

6.1.1 8-BIT TIMER MODE

When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to ‘0’.

When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write.

Note: The value written to the TMR0 register

can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.

6.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION_REG register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 6-1: TIMER0 WITH SHARED PRESCALE BLOCK DIAGRAM

 2011 Microchip Technology Inc. Preliminary DS41576B-page 55

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BANKSEL TMR0 ; CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and

;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ;

; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32

CLRWDT ;Clear WDT and

;prescaler BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG ;

6.1.3 SOFTWARE PROGRAMMABLE PRESCALER

A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’.

There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module.

The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler.

When the prescaler is assigned to WDT, (PSA = 1), a CLRWDT instruction will clear the prescaler along with the WDT.

6.1.3.1 Switching Prescaler Between

Timer0 and WDT Modules

As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 6-1, must be executed.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0  WDT)

When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 6-2).

EXAMPLE 6-2: CHANGING PRESCALER

(WDT  TIMER0)

6.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register.

Note: The Timer0 interrupt cannot wake the pro-

cessor from Sleep since the timer is frozen during Sleep.

6.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 20.0 “Electrical Specifications”.

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000

001

010

011

100

101

110

111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

6.2 Option and Timer0 Control Register

REGISTER 6-1: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU INTEDG T0CS T0SE PSA PS<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RAPU

: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values in WPU register

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (F

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

OSC/4)

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMR0 Holding Register for the 8-bit Timer0 Register

INTCON GIE PEIE T0IE

OPTION_REG

TRISA

Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0

Note 1: TRISA3 always reads ‘1’.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 57

module.

* Page provides register information.

RAPU INTEDG T0CS T0SE PSA PS<2:0> 57

INTE IOCIE T0IF INTF IOCIF

— — TRISA5 TRISA4 TRISA3

(1)

TRISA2 TRISA1 TRISA0

Page

55*

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TMR1H TMR1L

T1CKPS<1:0>

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit TMR1IF on Overflow

TMR1

(2)

TMR1ON

Note 1: ST buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.

T1G

FOSC/4

Internal

Clock

T1CKI

TMR1CS<1:0>

(1)

Synchronize

(3)

det

Sleep input

TMR1GE

From Timer0

SYNCC1OUT

T1GPOL

T1GVAL

Single Pulse

Acq. Control

T1GSPM

T1GGO/DONE

T1GSS<1:0>

FOSC

Internal

Clock

Temperature Sense

SYNCC2OUT

Overflow

DENQ

T1GCON

Data Bus

det

Interrupt

TMR1GIF

T1CLK

FOSC/2

Internal

Clock

T1G_IN

TMR1ON

T1GTM

Oscillator

T1SYNC

TMR1CS1

CCP Special Event Trigger

7.0 TIMER1 MODULE WITH GATE CONTROL

The Timer1 module is a 16-bit timer/counter with the following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Selectable internal or external clock sources

• 2-bit prescaler

• Synchronous or asynchronous operation

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP)

• Selectable Gate Source Polarity

FIGURE 7-1: TIMER1 BLOCK DIAGRAM

• Gate Toggle mode

• Gate Single-pulse mode

• Gate Value Status

• Gate Event Interrupt

Figure 7-1 is a block diagram of the Timer1 module.

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7.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.

When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.

Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Ta bl e 7 - 1 displays the Timer1 enable selections.

TABLE 7-1: TIMER1 ENABLE

SELECTIONS

TMR1ON TMR1GE

00Off

01Off

10Always On

11Count Enabled

Timer1

Operation

7.2 Clock Source Selection

The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. Tab l e 7- 2 displays the clock source selections.

TABLE 7-2: CLOCK SOURCE

SELECTIONS

TMR1CS<1:0> Clock Source

11 Temperature Sense Oscillator

10 External Clocking on T1CKI Pin

01 System Clock (FOSC)

00 Instruction Clock (FOSC/4)

7.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples

OSC or FOSC/4 as determined by the Timer1

of F prescaler.

7.2.2 EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI.

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first incrementing rising edge (see Figure 7-2) after any one or more of the following conditions:

• Timer1 enabled after POR Reset

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low.

7.2.3 TEMPERATURE SENSE OSCILLATOR

When the Temperature Sense Oscillator source is selected, the TMR1H:TMR1L register pair will increment on multiples of the Temperature Sense Oscillator as determined by the Timer1 prescaler. The Temperature Sense Oscillator operates at 16 kHz typical.

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7.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.

7.4 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see

Section 7.4.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”).

Note: When switching from synchronous to

asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.

7.4.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads.

For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.

7.5 Timer1 Gate

Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate count enable.

Timer1 gate can also be driven by multiple selectable sources.

7.5.1 TIMER1 GATE COUNT ENABLE

The Timer1 gate is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 gate is configured using the T1GPOL bit of the T1GCON register.

When Timer1 Gate (T1G) input is active, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 gate input is inactive, no incrementing will occur and Timer1 will hold the current count. See Figure 7-3 for timing details.

TABLE 7-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL T1G Timer1 Operation

 00Counts  01Holds Count  10Holds Count  11Counts

7.5.2 TIMER1 GATE SOURCE SELECTION

The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register.

TABLE 7-4: TIMER1 GATE SOURCES

T1GSS Timer1 Gate Source

11 SYNCC2OUT

10 SYNCC1OUT

01 Overflow of Timer0

(TMR0 increments from FFh to 00h)

00 Timer1 Gate Pin

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7.5.2.1 T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry.

7.5.2.2 Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry.

7.5.2.3 C1OUT/C2OUT Gate Operation

The outputs from the Comparator C1 and C2 modules can be used as gate sources for the Timer1 module.

7.5.3 TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse.

The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 7-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured.

Note: Enabling Toggle mode at the same time

as changing the gate polarity may result in indeterminate operation.

7.5.5 TIMER1 GATE VALUE STATUS

When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared).

7.5.6 TIMER1 GATE EVENT INTERRUPT

When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized.

The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared).

7.5.4 TIMER1 GATE SINGLE-PULSE MODE

When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software.

Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/DONE timing details.

Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 7-6 for timing details.

bit in the T1GCON register must be set.

bit will automatically be

bit. See Figure 7-5 for

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T1CKI

TMR1 enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

7.6 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.

Note: The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before enabling interrupts.

7.7 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, the clock source can be used to increment the counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC

• TMR1CS bits of the T1CON register must be configured

• TMR1GE bit of the T1GCON register must be configured

The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).

bit of the T1CON register must be set

7.8 CCP Capture/Compare Time Base

The CCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode.

In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event.

In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger.

For more information, see Section 10.0 “Capture/

Compare/PWM Modules”.

7.9 CCP Special Event Trigger

When the CCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1.

Timer1 should be synchronized to the F the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed.

In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence.

For more information, see Section 12.2.5 “Special

Event Trigger”.

OSC/4 to utilize

FIGURE 7-2: TIMER1 INCREMENTING EDGE

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TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

TIMER1

N N + 1 N + 2 N + 3 N + 4

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

TIMER1

N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8

FIGURE 7-3: TIMER1 GATE COUNT ENABLE MODE

FIGURE 7-4: TIMER1 GATE TOGGLE MODE

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FIGURE 7-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

TIMER1

N N + 1 N + 2

T1GSPM

T1GGO/

DONE

Set by software

Cleared by hardware on falling edge of T1GVAL

Set by hardware on falling edge of T1GVAL

Cleared by software

Cleared by

software

TMR1GIF

Counting enabled on

rising edge of T1G

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TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

TIMER1

NN + 1

N + 2

T1GSPM

T1GGO/

DONE

Set by software

Cleared by hardware on falling edge of T1GVAL

Set by hardware on

falling edge of T1GVAL

Cleared by software

Cleared by

software

TMR1GIF

T1GTM

Counting enabled on

rising edge of T1G

N + 4

N + 3

FIGURE 7-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

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7.10 Timer1 Control Registers

REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

TMR1CS<1:0> T1CKPS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Temperature Sense Oscillator 10 = External clock from T1CKI pin (on the rising edge) 01 = Timer1 clock source is system clock (F 00 = Timer1 clock source is instruction clock (F

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value

bit 3 Reserved: Do not use.

bit 2 T

1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS<1:0> = 1X

1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (F

Reserved T1SYNC —TMR1ON

OSC)

OSC/4)

OSC)

TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.

bit 1 Unimplemented: Read as ‘0’

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

Clears Timer1 gate flip-flop

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REGISTER 7-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = This bit is ignored If TMR1ON = 1:

1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function

bit 6 T1GPOL: Timer1 Gate Polarity bit

1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 5 T1GTM: Timer1 Gate Toggle mode bit

1 = Timer1 Gate Toggle mode is enabled. 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4 T1GSPM: Timer1 Gate Single Pulse mode bit

1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled

bit 3 T1GGO/DONE

1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started

This bit is automatically cleared when T1GSPM is cleared.

bit 2 T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits

11 = SYNCC2OUT 10 = SYNCC1OUT 01 = Timer0 overflow output 00 = Timer1 gate pin

: Timer1 Gate Single-Pulse Acquisition Status bit

T1GVAL T1GSS<1:0>

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TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELA

APFCON

CCP1CON

INTCON GIE PEIE

PIE1

PIR1

PORTA

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 59*

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 59*

TRISA

T1CON TMR1CS<1:0> T1CKPS<1:0>

T1GCON

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

— — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 50

— — — T1GSEL — COG1SEL COG1O1SEL COG1O0SEL

— — DC1B<1:0> CCP1M<3:0> 83

T0IE INTE IOCIE T0IF INTF IOCIF 20

TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 21

TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 23

— — RA5 RA4 RA3 RA2 RA1 RA0 48

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 48

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

* Page provides register information.

Reserved

DONE

T1SYNC

T1GVAL T1GSS<1:0>

—

TMR1ON

Page

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NOTES:

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Comparator

TMR2 Output

Sets Flag

TMR2

Reset

Postscaler

Prescaler

PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

TOUTPS<3:0>

T2CKPS<1:0>

8.0 TIMER2 MODULE

The Timer2 module is an 8-bit timer with the following features:

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

See Figure 8-1 for a block diagram of Timer2.

8.1 Timer2 Operation

The clock input to the Timer2 module is the system instruction clock (F Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register.

The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented

The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register.

OSC/4). The clock is fed into the

The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh.

Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’.

The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when:

• A write to TMR2 occurs.

• A write to T2CON occurs.

• Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset).

Note: TMR2 is not cleared when T2CON is

written.

FIGURE 8-1: TIMER2 BLOCK DIAGRAM

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8.2 Timer2 Control Registers

REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS<3:0> TMR2ON T2CKPS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

INTCON GIE PEIE

PIE1

PIR1

PR2 Timer2 Module Period Register 71*

TMR2 Holding Register for the 8-bit TMR2 Register 71*

T2CON

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

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TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 21

TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 23

— TOUTPS<3:0> TMR2ON T2CKPS<1:0>

* Page provides register information.

T0IE INTE IOCIE T0IF INTF IOCIF

Page

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Comparator

HLTimer1 Output

Sets Flag bit HLTMR1IF

HLTMR1

Reset

Postscaler

Prescaler

HLTPR1

OSC/4

1:1 to 1:16

1:1, 1:4, 1:16

H1OUTPS<3:0>

H1CKPS<1:0>

Detect

H1FEREN

H1REREN

H1ERS<2:0>

Detect

CCP1 out

C1OUT C2OUT

‘0’ ‘0’

COG1OUT1

COG1OUT0

COG1FLT

000

111

H1ON

(to COG module)

9.0 HARDWARE LIMIT TIMER (HLT) MODULE

The Hardware Limit Timer (HLT) module is a version of the Timer2-type modules. In addition to all the Timer2type features, the HLT can be reset on rising and falling events from selected peripheral outputs.

The HLT primary purpose is to act as a timed hardware limit to be used in conjunction with asynchronous analog feedback applications. The external reset source synchronizes the HLTMR1 to an analog application.

In normal operation, the external reset source from the analog application should occur before the HLTMR1 matches the HLTPR1. This resets HLTMR1 for the next period and prevents the HLTimer1 Output from going active.

When the external reset source fails to generate a signal within the expected time, (allowing the HLTMR1 to match the HLTPR1), then the HLTimer1 Output becomes active.

FIGURE 9-1: HLTMR1 BLOCK DIAGRAM

The HLT module incorporates the following features:

• 8-bit Read-Write Timer Register (HLTMR1)

• 8-bit Read-Write Period register (HLTPR1)

• Software programmable prescaler:

-1:1

-1:4

-1:16

• Software programmable postscaler

- 1:1 to 1:16, inclusive

• Interrupt on HLTMR1 match with HLTPR1

• 8 selectable timer Reset inputs (5 reserved)

• Reset on rising and falling event

Refer to Figure 9-1 for a block diagram of the HLT.

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9.1 HLT Operation

The clock input to the HLT module is the system instruction clock (F each rising clock edge.

A 4-bit counter/prescaler on the clock input provides the following prescale options:

• Direct input

•Divide-by-4

•Divide-by-16

The prescale options are selected by the prescaler control bits, H1CKPS<1:0> of the HLT1CON0 register.

The value of HLTMR1 is compared to that of the Period register, HLTPR1, on each clock cycle. When the two values match,then the comparator generates a match signal as the HLTimer1 output. This signal also resets the value of HLTMR1 to 00h on the next clock rising edge and drives the output counter/postscaler (see

Section 9.2 “HLT Interrupt”).

The HLTMR1 and HLTPR1 registers are both directly readable and writable. The HLTMR1 register is cleared on any device Reset, whereas the HLTPR1 register initializes to FFh. Both the prescaler and postscaler counters are cleared on any of the following events:

• A write to the HLTMR1 register

• A write to the HLT1CON0 register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

• RESET Instruction

Reset

Note: HLTMR1 is not cleared when HLT1CON0 is

written.

OSC/4). HLTMR1 increments on

9.2 HLT Interrupt

The HLT can also generate an optional device interrupt. The HLTMR1 output signal (HLTMR1-to-HLTPR1 match) provides the input for the 4-bit counter/ postscaler. The overflow output of the postscaler sets the HLTMR1IF bit of the PIR1 register. The interrupt is enabled by setting the HLTMR1 Match Interrupt Enable bit, HLTMR1IE of the PIE1 register.

A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, H1OUTPS<3:0>, of the HLT1CON0 register.

9.3 Peripheral Resets

Resets driven from the selected peripheral output prevents the HLTMR1 from matching the HLTPR1 register and generating an output. In this manner, the HLT can be used as a hardware time limit to other peripherals.

In this device, the primary purpose of the HLT is to limit the COG PWM duty cycle. Normally, the COG operation uses analog feedback to determine the PWM duty cycle. The same feedback signal is used as an HLT Reset input. The HLTPR1 register is set to occur at the maximum allowed duty cycle. If the analog feedback to the COG exceeds the maximum time, then an HLTMR1-to-HLTPR1 match will occur and generate the output needed to limit the COG drive output.

The HLTMR1 can be reset by one of several selectable peripheral sources. Reset inputs include:

• CCP1 output

• Comparator 1 output

• Comparator 2 output

The Reset input is selected with the H1ERS<2:0> bits of the HLT1CON1 register.

HLTMR1 Resets are synchronous with the HLT clock. In other words, HLTMR1 is cleared on the rising edge of the HLT clock after the enabled Reset event occurs.

The Reset can be enabled to occur on the rising and falling input event. Rising and falling event enables are selected with the respective H1REREN and H1FEREN bits of the HLT1CON1 register. External Resets do not cause an HLTMR1 output event.

9.4 HLTimer1 Output

The unscaled output of HLTMR1 is available only to the COG module, where it is used as a selectable limit to the maximum COG period.

9.5 HLT Operation During Sleep

The HLT cannot be operated while the processor is in Sleep mode. The contents of the HLTMR1 register will remain unchanged while the processor is in Sleep mode.

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9.6 HLT Control Registers

REGISTER 9-1: HLT1CON0: HLT1 CONTROL REGISTER 0

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— H1OUTPS<3:0> H1ON H1CKPS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 H1OUTPS<3:0>: Hardware Limit Timer 1 Output Postscaler Select bits

bit 2 H1ON: Hardware Limit Timer 1 On bit

1 =Timer is on 0 =Timer is off

bit 1-0 H1CKPS<1:0>: Hardware Limit Timer 1 Clock Prescale Select bits

00 =Prescaler is 1 01 =Prescaler is 4 1x = Prescaler is 16

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REGISTER 9-2: HLT1CON1: HLT1 CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — H1ERS<2:0> H1FEREN H1REREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-2 H1ERS<2:0>: Hardware Limit Timer 1 Peripheral Reset Select bits

000 = CCP1 Out 001 =C1OUT 010 =C2OUT 011 =COG1FLT 100 =COG1OUT0 101 =COG1OUT1 110 = Reserved - ‘0’ input 111 = Reserved - ‘0’ input

bit 1 H1FEREN: Hardware Limit Timer 1 Falling Edge Reset Enable bit

1 = HLTMR1 will reset on the first clock after a falling edge of selected Reset source 0 = Falling edges of selected source have no effect

bit 0 H1REREN: Hardware Limit Timer 1 Rising Edge Reset Enable bit

1 = HLTMR1 will reset on the first clock after a rising edge of selected Reset source 0 = Rising edges of selected source have no effect

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH HLT

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCP1CON

CM1CON0 C1ON

CM1CON1

CM2CON0 C2ON

CM2CON1

INTCON GIE PEIE

PIE1

PIR1

HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Register 73*

HLTPR1 HLTMR1 Module Period Register 73*

HLT1CON0

HLT1CON1

Legend: — = unimplemented location, read as ‘0’. Shaded cells do not affect the HLT module operation.

* Page provides register information.

— — DC1B<1:0> CCP1M<3:0> 83

C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 127

C1INTP C1INTN C1PCH<1:0> — —

C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 127

C2INTP C2INTN C2PCH<1:0> — —

T0IE INTE IOCIE T0IF INTF IOCIF 20

TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 21

TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 23

— H1OUTPS<3:0> H1ON H1CKPS<1:0> 75

— — — H1ERS<2:0> H1FEREN H1REREN

— C1NCH0

— C2NCH0

128

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CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR2 register)

Capture Enable

CCP1M<3:0>

Prescaler

 1, 4, 16

and

Edge Detect

CCP1

System Clock (F

OSC)

BANKSEL CCP1CON ;Set Bank bits to point

;to CCP1CON CLRF CCP1CON ;Turn CCP1 module off MOVLW NEW_CAPT_PS ;Load the W reg with

;the new prescaler

;move value and CCP1 ON MOVWF CCP1CON ;Load CCP1CON with this

;value

10.0 CAPTURE/COMPARE/PWM MODULES

The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.

10.1 Capture Mode

Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCP1 pin, the 16-bit CCPR1H:CCPR1L register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR2 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value.

Figure 10-1 shows a simplified diagram of the Capture

operation.

10.1.1 CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit.

10.1.2 TIMER1 MODE RESOURCE

Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP1 module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.

See Section 7.0 “Timer1 Module with Gate Control” for more information on configuring Timer1.

10.1.3 SOFTWARE INTERRUPT MODE

When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE2 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR2 register following any change in Operating mode.

Note: Clocking Timer1 from the system clock

OSC) should not be used in Capture

(F mode. In order for Capture mode to recognize the trigger event on the CCP1 pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.

10.1.4 CCP1 PRESCALER

There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP1 module is turned off, or the CCP1 module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler. Example 10-1 demonstrates the code to perform this function.

EXAMPLE 10-1: CHANGING BETWEEN

CAPTURE PRESCALERS

Note: If the CCP1 pin is configured as an output,

a write to the port can cause a capture condition.

FIGURE 10-1: CAPTURE MODE

OPERATION BLOCK DIAGRAM

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10.1.5 CAPTURE DURING SLEEP

Capture mode depends upon the Timer1 module for proper operation. If the Timer1 clock input source is a clock that is not disabled during Sleep, Timer1 will continue to operate and Capture mode will operate during Sleep to wake the device. The T1CKI is an example of a clock source that will operate during Sleep.

When the input source to Timer1 is disabled during Sleep, such as the HFINTOSC, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state.

TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCP1CON

CCPR1L Capture/Compare/PWM Register x Low Byte (LSB)

CCPR1H Capture/Compare/PWM Register x High Byte (MSB)

INTCON GIE PEIE

PIE1

PIE2

PIR1

PIR2

T1CON TMR1CS<1:0> T1CKPS<1:0>

T1GCON

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TRISA

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.

* Page provides register information.

Note 1: TRISA3 always reads ‘1’.

— — DC1B<1:0> CCP1M<3:0>

T0IE INTE IOCIE T0IF INTF IOCIF

TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 21

— — C2IE C1IE — COG1IE — CCP1IE 22

TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 23

— — C2IF C1IF — COG1IF — CCP1IF 24

Reserved T1SYNC —TMR1ON

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

— — TRISA5 TRISA4 TRISA3

T1GVAL T1GSS<1:0>

(1)

TRISA2 TRISA1 TRISA0

59*

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CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCP1IF Interrupt Flag

(PIR2)

Match

TRIS

CCP1M<3:0>

Mode Select

Output Enable

CCP1

10.2 Compare Mode

Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPR1H:CCPR1L register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur:

• Toggle the CCP1 output

• Set the CCP1 output

• Clear the CCP1 output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. At the same time, the interrupt flag CCP1IF bit is set.

All Compare modes can generate an interrupt.

Figure 10-2 shows a simplified diagram of the

Compare operation.

FIGURE 10-2: COMPARE MODE

OPERATION BLOCK DIAGRAM

10.2.1 CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by clearing the associated TRIS bit.

Note: Clearing the CCP1CON register will force

the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch.

10.2.2 TIMER1 MODE RESOURCE

In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.

See Section 7.0 “Timer1 Module with Gate Control” for more information on configuring Timer1.

Note: Clocking Timer1 from the system clock

OSC) should not be used in Compare

mode. In order for Compare mode to recognize the trigger event on the CCP1 pin, TImer1 must be clocked from the instruction clock (F

OSC/4) or from an

external clock source.

10.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register).

10.2.4 SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

The CCP1 module does not assert control of the CCP1 pin in this mode.

The Special Event Trigger output of the CCP1 occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1.

TABLE 10-2: SPECIAL EVENT TRIGGER

Device CCP1

PIC12F752 PIC12HV752

Refer to Section 12.0 “Analog-to-Digital Converter

(ADC) Module” for more information.

CCP1

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit TMR1IF of the PIR1 register.

2: Removing the match condition by

changing the contents of the CCPR1H

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and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.

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10.2.5 COMPARE DURING SLEEP

The Compare mode is dependent upon the system clock (F down during Sleep mode, the Compare mode will not function properly during Sleep.

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

OSC) for proper operation. Since FOSC is shut

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCP1CON

CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB)

CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB)

INTCON GIE PEIE

PIE1 TMR1GIE

PIE2

PIR1 TMR1GIF

PIR2

T1CON TMR1CS<1:0> T1CKPS<1:0>

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TRISA

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

* Page provides register information.

Note 1: TRISA3 always reads ‘1’.

— — DC1B<1:0> CCP1M<3:0>

T0IE INTE IOCIE T0IF INTF IOCIF

ADIE — — — HLTMR1IE TMR2IE TMR1IE 20

— — C2IE C1IE — COG1IE — CCP1IE 20

ADIF — — — HLTMR1IF TMR2IF TMR1IF 20

— — C2IF C1IF — COG1IF — CCP1IF 20

Reserved T1SYNC —TMR1ON

T1GVAL T1GSS<1:0>

— — TRISA5 TRISA4 TRISA3

(1)

TRISA2 TRISA1 TRISA0

59*

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Period

Pulse Width

TMR2 = 0

TMR2 = CCPR1H:CCP1CON<5:4>

TMR2 = PR2

CCPR1L

CCPR1H

(2)

(Slave)

Comparator

TMR2

PR2

(1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer, toggle CCP1 pin and latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (F

OSC), or

2 bits of the prescaler, to create the 10-bit time base.

2: In PWM mode, CCPR1H is a read-only register.

TRIS

CCP1

Comparator

10.3 PWM Overview

Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined.

PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load.

The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied.

Figure 10-3 shows a typical waveform of the PWM

signal.

FIGURE 10-3: CCP1 PWM OUTPUT

SIGNAL

FIGURE 10-4: SIMPLIFIED PWM BLOCK

DIAGRAM

10.3.1 STANDARD PWM OPERATION

The standard PWM mode generates a Pulse-Width modulation (PWM) signal on the CCP1 pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers:

• PR2 registers

• T2CON registers

• CCPR1L registers

• CCP1CON registers

Figure 10-4 shows a simplified block diagram of PWM

operation.

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the CCP1 pin.

2: Clearing the CCP1CON register will

relinquish control of the CCP1 pin.

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PWM Period PR 21+4TOSC =

(TMR2 Prescale Value)

Note 1: T

OSC = 1/FOSC

Pulse Width CCPR1L:CCP1CON<5:4>



TOSC (TMR2 Prescale Value)

Duty Cycle Ratio

CCPRxL:CCPxCON<5:4>

4 PRx 1+

------------ ------------- ------------- ----------- ------------ ----------=

10.3.2 SETUP FOR PWM OPERATION

The following steps should be taken when configuring the CCP1 module for standard PWM operation:

1. Disable the CCP1 pin output driver by setting the associated TRIS bit.

2. Load the PR2 register with the PWM period value.

3. Configure the CCP1 module for the PWM mode by loading the CCP1CON register with the appropriate values.

4. Load the CCPR1L register and the DC1B<1:0> bits of the CCP1CON register, with the PWM duty cycle value.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the

PIR1 register. See Note below.

• Configure the T2CKPS bits of the T2CON

• Enable the Timer by setting the TMR2ON

bit of the T2CON register.

6. Enable PWM output pin:

• Wait until the Timer overflows and the

TMR2IF bit of the PIR1 register is set. See Note below.

• Enable the CCP1 pin output driver by clear-

ing the associated TRIS bit.

Note: In order to send a complete duty cycle and

period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored.

When TMR2 is equal to PR2, the following three events occur on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)

• The PWM duty cycle is latched from CCPR1L into CCPR1H.

Note: The Timer postscaler (see Section 8.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency.

10.3.4 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only.

Equation 10-2 is used to calculate the PWM pulse

width.

Equation 10-3 is used to calculate the PWM duty cycle

ratio.

EQUATION 10-2: PULSE WIDTH

10.3.3 PWM PERIOD

The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 10-1.

EQUATION 10-1: PWM PERIOD

DS41576B-page 82 Preliminary  2011 Microchip Technology Inc.

EQUATION 10-3: DUTY CYCLE RATIO

The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation.

The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (F the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.

When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see

Figure 10-4).

OSC), or 2 bits of

PIC12F752/HV752

10.4 CCP Control Registers

REGISTER 10-1: CCP1CON: CCP1 CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode: Unused

Compare mode: Unused

PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0 CCP1M<3:0>: CCP1 Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP1 module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved

DC1B<1:0> CCP1M<3:0>

0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge

1000 = Compare mode: initialize CCP1 pin low; set output on compare match (set CCP1IF) 1001 = Compare mode: initialize CCP1 pin high; clear output on compare match (set CCP1IF) 1010 = Compare mode: generate software interrupt only; CCP1 pin reverts to I/O state 1011 = Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D conversion

11xx = PWM mode

if A/D module is enabled)

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11.0 COMPLEMENTARY OUTPUT

GENERATOR (COG) MODULE

The primary purpose of the Complementary Output Generator (COG) is to convert a single output PWM signal into a two output complementary PWM signal. The COG can also convert two separate input events into a single or complementary PWM output.

The COG PWM frequency and duty cycle are determined by a rising event input and a falling event input. The rising event and falling event may be the same source. Sources may be synchronous or asynchronous to the COG_clock.

The rate at which the rising event occurs determines the PWM frequency. The time from the rising event input to the falling event input determines the duty cycle.

A selectable clock input is used to generate the phase delay, blanking and dead-band times.

A simplified block diagram of the COG is shown in

Figure 11-1.

The COG module has the following features:

• Selectable clock source

• Selectable rising event source

• Selectable falling event source

• Selectable edge or level event sensitivity

• Independent output enables

• Independent output polarity selection

•Phase delay

• Dead-band control with independent rising and falling event dead-band times

• Blanking control with independent rising and falling event blanking times

• Auto-shutdown control with:

- Selectable shutdown sources

- Auto-restart enable

- Auto-shutdown pin override control

11.1 Fundamental Operation

The COG generates a two output complementary PWM waveform from rising and falling event sources. In the simplest configuration, the rising and falling event sources are the same signal, which is a PWM signal with the desired period and duty cycle. The COG converts this single PWM input into a dual complementary PWM output. The frequency and duty cycle of the dual PWM output match those of the single input PWM signal. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time immediately after the PWM transition where neither output is driven. This is referred to as dead time and is covered in Section 11.5

“Dead-Band Control”.

A typical operating waveform, with dead band, generated from a single CCP1 input is signal is shown in Figure 11-2.

The COG can also generate a PWM waveform from a periodic rising event and a separate falling event. In this case, the falling event is usually derived from analog feedback within the external PWM driver circuit. In this configuration, high power switching transients may trigger a false falling event that needs to be blanked out. The COG can be configured to blank falling (and rising) event inputs for a period of time immediately following the rising (and falling) event drive output. This is referred to as input blanking and is covered in Section 11.6 “Blanking Control”.

It may be necessary to guard against the possibility of circuit faults. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in

Section 11.8 “Auto-shutdown Control”.

A feedback falling event arriving too late or not at all o can be terminated with auto-shutdown or by using one of the event inputs that is logically OR’d with the hardware limit timer (HLT). See Section 9.0 “Hardware

Limit Timer (HLT) Module” for more information about

the HLT.

The COG can be configured to operate in phase delayed conjunction with another PWM. The active drive cycle is delayed from the rising event by a phase delay timer. Phase delay is covered in more detail in

Section 11.7 “Phase Delay”.

A typical operating waveform, with phase delay and dead band, generated from a single CCP1 input is shown in Figure 11-3.

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DS41576B-page 86 Preliminary  2011 Microchip Technology Inc.

COG_clock

GxCS<1:0>

C1OUT

C2OUT

CCP1

GxRS0<2:0>

GxFS0<2:0>

GxOUT1SS

GxOUT0SS

COG1OUT0

COG1OUT1

Fosc

GxDBR<3:0>

GxDBF<3:0>

GxPOL0

GxPOL1

COGxFLT

GxASDSFLT

C1OUT

GxASDSC1

C2OUT

GxASDSC2

HLTimer1 output

GxASDSHLT

GxARSEN

Fosc/4

HFINTOSC

Phase

Dead Band

Cnt/R

Dead Band

Cnt/R

Blanking

Cnt/R

Delay

GxOE0

GxOE1

GxBLKR<3:0>

GxPH<3:0>

Blanking

Cnt/R

GxBLKF<3:0>

Write GxASDE Low

GxASDEAuto-shutdown source

Set Dominates

Write GxASDE High

Rising event source

Falling event source

HLTimer1 or C1OUT

HLTimer1 or C2OUT

HLTimer1 or CCP1

COGxFLT

HLTimer1 or COGxFLT

C1OUT

C2OUT

CCP1

HLTimer1 or C1OUT

HLTimer1 or C2OUT

HLTimer1 or CCP1

COGxFLT

HLTimer1 or COGxFLT

GxRSIM

GxFSIM

Reset Dominates

GxEN

FIGURE 11-1: SIMPLIFIED COG BLOCK DIAGRAM

PIC12F752/HV752

Falling Source Dead Band

Rising Source Dead Band

Falling Source Dead Band

COG_clock

CCP1

COGxOUT0

COGxOUT1

Source

Falling Source Dead

Rising Source Dead Band

Phase DelayFalling Source Dead Band

CCP1

COGxOUT0

COGxOUT1

COG_clock

Source

Band

FIGURE 11-2: TYPICAL COG OPERATION WITH CCP1

FIGURE 11-3: COG OPERATION WITH CCP1 AND PHASE DELAY

 2011 Microchip Technology Inc. Preliminary DS41576B-page 87

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Rising (CCP1)

Falling (C1OUT)

C1IN-

COGOUT

hyst

Edge Sensitive

Rising (CCP1)

Falling (C1OUT)

C1IN-

COGOUT

hyst

11.2 Clock Sources

The COG_clock is used as the reference clock to the various timers in the peripheral. Timers that use the COG_clock include:

• Rising and falling dead-band time

• Rising and falling blanking time

• Rising event phase delay

Clock sources available for selection include:

• 8 MHz HFINTOSC

• Instruction clock (Fosc/4)

• System clock (Fosc)

The clock source is selected with the GxCS<1:0> bits of the COGxCON0 register (Register 11-1).

11.3 Selectable Event Sources

The COG uses two independently selectable event sources to generate the complementary waveform:

• Rising event source

• Falling event source

Level or edge sensitive modes are available for each event input.

The rising event source is selected with the GxRS<2:0> bits and the mode is controlled with the GxRSIM bit. The falling event source is selected with the GxFS<2:0> bits and the mode is controlled with the GxFSIM bit. Selection and mode control bits for both sources are located in the COGxCON1 register (Register 11-2).

11.3.1 EDGE VS. LEVEL SENSING

Event input detection may be selected as level or edge sensitive. In general, events that are driven from a periodic source should be edge detected and events that are derived from voltage thresholds at the target circuit should be level sensitive. Consider the following two examples:

1. The first example is an application in which the period is determined by a 50% duty cycle clock and the COG output duty cycle is determined by a voltage level fed back through a comparator. If the clock input is level sensitive then duty cycles less than 50% will exhibit erratic operation.

2. The second example is similar to the first except that the duty cycle is close to 100%. The feedback comparator high-to-low transition trips the COG drive off but almost immediately the period source turns the drive back on. If the off cycle is short enough then the comparator input may not reach the low side of the hysteresis band precluding an output change. The comparator output stays low and without a high-to-low transition to trigger the edge sense then the drive of the COG output will be stuck in a constant drive-on condition. See Figure 11-4.

FIGURE 11-4: EDGE VS LEVEL SENSE

11.3.2 RISING EVENT

The rising event starts the PWM output active duty cycle period. The rising event is the low-to-high transition of the selected rising event source. When the phase delay and rising event dead-band time values are zero, the COGxOUT0 output starts immediately. Otherwise, the COGxOUT0 output is delayed. The rising event causes all the following actions:

• Start rising event phase delay counter (if enabled).

• Clear COGxOUT1 after phase delay.

• Start falling event input blanking (if enabled).

• Start dead-band counter (if enabled).

• Set COGxOUT0 output after dead-band counter expires.

11.3.3 FALLING EVENT

The falling event terminates the PWM output active duty cycle period. The falling event is the high-to-low transition of the selected falling event source. When the falling event dead-band time value is zero, the COGxOUT1 output starts immediately. Otherwise, the COGxOUT1 output is delayed. The falling event causes all the following actions:

• Clear COGxOUT0.

• Start rising event input blanking (if enabled).

• Start falling event dead-band counter (if enabled).

• Set COGxOUT1 output after dead-band counter expires.

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11.4 Output Control

Immediately after the COG module is enabled, the complementary drive is configured with COGxOUT0 drive cleared and COGxOUT1 drive active.

11.4.1 OUTPUT ENABLES

Each COG output pin has individual output enable controls. Output enables are selected with the GxOE0 and GxOE1 bits of the COGxCON0 register. When an output enable control is cleared, the module asserts no control over the pin. When an output enable is set, the override value or active PWM waveform is applied to the pin per the port priority selection.

The output pin enables are independent of the module enable bit, GxEN. When GxEN is cleared, the shutdown override levels are present on the COG output pins for which the output enables are active.

11.4.2 POLARITY CONTROL

The polarity of each COG output can be selected independently. When the output polarity bit is set, the corresponding output is active low. Clearing the output polarity bit configures the corresponding output as active high. However, polarity does not affect the override levels.

Output polarity is selected with the GxPOL0 and GxPOL1 bits of the COGxCON0 register.

11.5.1 RISING EVENT DEAD BAND

Rising event dead-band delays the turn-on of COGxOUT0 from when COGxOUT1 is turned off. The rising event dead-band time starts when the rising event output goes true.

The rising event output into the dead-band counter may be delayed by the phase delay. When the phase delay time is zero, the rising event output goes true coincident with the unblanked rising input event. When the phase delay time is not zero, the rising event output goes true at the completion of the phase delay time.

The rising event dead-band time is set by the value contained in the GxDBR<3:0> bits of the COGxDB register. When the value is zero, rising event dead band is disabled.

11.5.2 FALLING EVENT DEAD BAND

Falling event dead-band delays the turn-on of COGxOUT1 from when COGxOUT0 is turned off. The falling event dead-band time starts when the falling event output goes true. The falling event output goes true coincident with the unblanked falling input event.

The falling event dead-band time is set by the value contained in the GxDBF<3:0> bits of the COGxDB register. When the value is zero, falling event dead band is disabled.

11.5 Dead-Band Control

The dead-band control provides for non-overlapping PWM output signals to prevent shoot through current in the external power switches.

The COG contains two 4-bit dead-band counters. One dead-band counter is used for rising event dead-band control. The other is used for falling event dead-band control.

Dead band is timed by counting COG_clock periods from zero up to the value in the dead-band count register. Use Equation 11-1 to calculate dead-band times.

11.5.3 DEAD-BAND TIME UNCERTAINTY

When the rising and falling events that trigger the dead-band counters come from asynchronous inputs, it creates uncertainty in the dead-band time. The maximum uncertainty is equal to one COG_clock period. Refer to Equation 11-1 for more detail.

11.5.4 DEAD-BAND OVERLAP

There are two cases of dead-band overlap:

• Rising-to-falling

• Falling-to-rising

11.5.4.1 Rising-to-Falling Overlap

In this case, the falling event occurs while the rising event dead-band counter is still counting. When this happens, the COGxOUT0 drive is suppressed and the dead band extends by the falling event dead-band time. At the termination of the extended dead-band time, the COGxOUT1 drive goes true.

11.5.4.2 Falling-to-Rising Overlap

In this case, the rising event occurs while the falling event dead-band counter is still counting. When this happens, the COGxOUT1 drive is suppressed and the dead band extends by the rising event dead-band time. At the termination of the extended dead-band time, the COGxOUT0 drive goes true.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 89

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min

Count=

max

Count 1+

COG_clock

--------------------------=

uncertainty

maxTmin

–=

uncertainty

COG_clock

--------------------------=

Also:

Where:

T Count

Phase Delay GxPH<3:0>

Rising Dead Band GxDBR<3:0>

Falling Dead Band GxDBF<3:0>

Rising Event Blanking GxBLKR<3:0>

Falling Event Blanking GxBLKF<3:0>

COG_clock

11.6 Blanking Control

Input blanking is a function whereby the event inputs can be masked or blanked for a short period of time. This is to prevent electrical transients caused by the turn-on/off of power components from generating a false input event.

The COG contains two 4-bit blanking counters. The counters are cross coupled with the events they are blanking. The falling event blanking counter is used to blank rising input events and the rising event blanking counter is used to blank falling input events. Once started, blanking extends for the time specified by the corresponding blanking counter.

Blanking is timed by counting COG_clock periods from zero up to the value in the blanking count register. Use

Equation 11-1 to calculate blanking times.

11.6.1 RISING EVENT INPUT BLANKING

The falling event blanking counter inhibits the rising input from triggering a rising event. The falling event blanking time starts when the falling event output drive goes true.

The falling event blanking time is set by the value contained in the GxBLKF<3:0> bits of the COGxBLK register. Blanking times are calculated using the formula shown in Equation 11-1.

When the GxBLKF<3:0> value is zero, falling event blanking is disabled and the blanking counter output is true, thereby, allowing the event signal to pass straight through to the event trigger circuit.

11.7 Phase Delay

It is possible to delay the assertion of the rising event. This is accomplished by placing a non-zero value in COGxPH register. Refer to Register 11-6 and

Figure 11-3 for COG operation with CCP1 and phase

delay. The delay from the input rising event signal switching to the actual assertion of the events is calculated the same as the dead-band and blanking delays. Please see Equation 11-1.

When the COGxPH value is zero, phase delay is disabled and the phase delay counter output is true, thereby, allowing the event signal to pass straight through to complementary output driver flop.

11.7.1 CUMULATIVE UNCERTAINTY

It is not possible to create more than one COG_clock of uncertainty by successive stages. Consider that the phase delay stage comes after the blanking stage, the dead-band stage comes after either the blanking or phase delay stages, and the blanking stage comes after the dead-band stage. When the preceding stage is enabled, the output of that stage is necessarily synchronous with the COG_clock, which removes any possibility of uncertainty in the succeeding stage.

EQUATION 11-1: PHASE, DEAD-BAND,

AND BLANKING TIME CALCULATION

11.6.2 FALLING EVENT INPUT BLANKING

The rising event blanking counter inhibits the falling input from triggering a falling event. The rising event blanking time starts when the rising event output drive goes true.

The rising event blanking time is set by the value contained in the GxBLKR<3:0> bits of the COGxBLK register.

When the GxBLKR<3:0> value is zero, rising event blanking is disabled and the blanking counter output is true, thereby, allowing the event signal to pass straight through to the event trigger circuit.

11.6.3 BLANKING TIME UNCERTAINTY

When the rising and falling events that trigger the blanking counters are asynchronous to the COG_clock, it creates uncertainty in the blanking time. The maximum uncertainty is equal to one COG_clock period. Refer to Equation 11-1 and Example 11-1 for more detail.

DS41576B-page 90 Preliminary  2011 Microchip Technology Inc.

EXAMPLE 11-1: TIMER UNCERTAINTY

Given:

Therefore:

Count Ah 10d==

COG_Clock

8MHz=

uncertainty

COG_clock

--------------------------=

8MHz

---------------=

125ns=

Proof:

min

Count

COG_clock

--------------------------

125ns 10d= 1.25s=

max

Count 1+

COG_clock

--------------------------=

125ns 10d 1+=

1.375s=

Therefore:

uncertainty

maxTmin

–=

1.375s 1.25s–=

125ns=

PIC12F752/HV752

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11.8 Auto-shutdown Control

Auto-shutdown is a method to immediately override the COG output levels with specific overrides that allow for safe shutdown of the circuit.

The shutdown state can be either cleared automatically or held until cleared by software.

11.8.1 SHUTDOWN

The shutdown state can be entered by either of the following two mechanisms:

• Software generated

• External Input

11.8.1.1 Software Generated Shutdown

Setting the GxASDE bit of the COGxASD register will force the COG into the shutdown state.

When auto-restart is disabled, the shutdown state will persist as long as the GxASDE bit is set.

When auto-restart is enabled, the GxASDE bit will clear automatically and resume operation on the next rising event. See Figure 11-5.

11.8.1.2 External Shutdown Source

External shutdown inputs provide the fastest way to safely suspend COG operation in the event of a fault condition. When any of the selected shutdown inputs goes true, the output drive latches are reset and the COG outputs will immediately go to the selected override levels without software delay.

Any combination of four input sources can be selected to cause a shutdown condition. The four sources include:

• HLTimer1 output

• C2OUT (low true)

• C1OUT (low true)

• COG1FLT pin (low true)

Shutdown inputs are selected independently with bits <3:0> of the COGxASD register (Register 11-3).

11.8.2 PIN OVERRIDE LEVELS

The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDL0 and GxASDL1 bits of the COGxASD register (Register 11-3). GxASDL0 controls the GxOUT0 override level and GxASDL1 controls the GxOUT1 override level. The control bit logic level corresponds to the output logic drive level while in the shutdown state.

Note: The polarity control does not apply to the

override level.

11.8.3 AUTO-SHUTDOWN RESTART

After an auto-shutdown event has occurred, there are two ways to have the module resume operation:

• Software controlled

• Auto-restart

The restart method is selected with the GxARSEN bit of the COGxASD register. Waveforms of a software controlled automatic restart are shown in Figure 11-5.

11.8.3.1 Software Controlled Restart

When the GxARSEN bit of the COGxASD register is cleared, the COG must be restarted after an auto-shutdown event by software.

The COG will resume operation on the first rising event after the GxASDE bit is cleared. Clearing the shutdown state requires all selected shutdown inputs to be false, otherwise, the GxASDE bit will remain set.

11.8.3.2 Auto-Restart

When the GxARSEN bit of the COGxASD register is set then the COG will restart from the auto-shutdown state automatically.

The GxASDE bit will clear automatically and the COG will resume operation on the first rising event after all selected shutdown inputs go false.

Note: Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state cannot be cleared as long as the shutdown input level persists, except by disabling auto-shutdown,

DS41576B-page 92 Preliminary  2011 Microchip Technology Inc.

 2011 Microchip Technology Inc. Preliminary DS41576B-page 93

1 2 3 4 5

Next rising event

Cleared in software

Cleared in hardware

NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT

SOFTWARE CONTROLLED RESTART

AUTO-RESTART

CCP1

GxARSEN

Shutdown input

GxASDE

GxASDL0

GxASDL1

COGxOUT0

COGxOUT1

Operating State

FIGURE 11-5: AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT

SOURCE

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11.9 Buffer updates

Changes to the phase, dead band, and blanking count registers need to occur simultaneously during COG operation to avoid unintended operation that may occur as a result of delays between each register write. This is accomplished with the GxLD bit of the COGxCON0 register and double buffering of the phase, blanking, and dead-band count registers.

Before the COG module is enabled, writing the count registers loads the count buffers without need of the GxLD bit. However, when the COG is enabled, the count buffers updates are suspended after writing the count registers until after the GxLD bit is set. When the GxLD bit is set, the phase, dead band, and blanking register values are transferred to the corresponding buffers synchronous with COG operation. The GxLD bit is cleared by hardware when the transfer is complete.

11.10 Alternate Pin Selection

The COGxOUT0, COGxOUT1 and COGxFLT functions can be directed to alternate pins with control bits of the APFCON register. Refer to Register 5-1.

Note: The default COG outputs have high drive

strength capability, whereas the alternate outputs do not.

11.11 Operation During Sleep

The COG continues to operate in Sleep provided that the COG_clock, rising event, and falling event sources remain active.

The HFINTSOC remains active during Sleep when the COG is enabled and the HFINTOSC is selected as the COG_clock source.

11.12 Configuring the COG

The following steps illustrate how to properly configure the COG to ensure a synchronous start with the rising event input:

1. Configure the desired COGxFLT input,

COGxOUT0 and COGxOUT1 pins with the corresponding bits in the APFCON register.

2. Clear all ANSELA register bits associated with

pins that are used for COG functions.

3. Ensure that the TRIS control bits corresponding

to COGxOUT0 and COGxOUT1 are set so that both are configured as inputs. These will be set as outputs later.

4. Clear the GxEN bit, if not already cleared.

5. Set desired dead-band times with the COGxDB

6. Set desired blanking times with the COGxBLK

7. Set desired phase delay with the COGxPH

8. Setup the following controls in COGxASD

auto-shutdown register:

• Select desired shutdown sources.

• Select both output overrides to the desired levels (this is necessary, even if not using auto-shutdown because start-up will be from a shutdown state).

• Set the GxASDE bit and clear the GxARSEN bit.

9. Select the desired rising and falling event sources and input modes with the COGxCON1 register.

10. Configure the following controls in COGxCON0 register:

• Select the desired clock source

• Select the desired output polarities

• Set the output enables of the outputs to be

used.

11. Set the GxEN bit.

12. Clear TRIS control bits corresponding to COGxOUT0 and COGxOUT1 to be used, thereby configuring those pins as outputs.

13. If auto-restart is to be used, set the GxARSEN bit and the GxASDE will be cleared automatically. Otherwise, clear the GxASDE bit to start the COG.

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11.13 COG Control Registers

REGISTER 11-1: COGxCON0: COG CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

GxEN GxOE1 GxOE0 GxPOL1 GxPOL0 GxLD GxCS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxEN: COGx Enable bit

1 = Module is enabled 0 = Module is disabled

bit 6 GxOE1: COGxOUT1 Output Enable bit

1 = COGxOUT1 is available on associated I/O pin 0 = COGxOUT1 is not available on associated I/O pin

bit 5 GxOE0: COGxOUT0 Output Enable bit

1 = COGxOUT0 is available on associated I/O pin 0 = COGxOUT0 is not available on associated I/O pin

bit 4 GxPOL1: COGxOUT1 Output Polarity bit

1 = Output is inverted polarity 0 = Output is normal polarity

bit 3 GxPOL0: COGxOUT0 Output Polarity bit

1 = Output is inverted polarity 0 = Output is normal polarity

bit 2 GxLD: COGx Load Buffers bit

1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events 0 = Register to buffer transfer is complete

bit 1-0 GxCS<1:0>: COGx Clock Source Select bits

11 = Reserved 10 = 8 MHz HFINTOSC clock 01 = Instruction clock (Fosc/4) 00 = System clock (Fosc)

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REGISTER 11-2: COGxCON1: COG CONTROL REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

GxFSIM GxRSIM

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxFSIM: COGx Falling Source Input mode bit

1 = Input is edge sensitive 0 = Input is level sensitive

bit 6 GxRSIM: COGx Rising Source Input mode bit

1 = Input is edge sensitive 0 = Input is level sensitive

bit 5-3 GxFS<2:0>: COGx Falling Source Select bits

111 = COGxFLT or HLTimer1 110 = CCP1 or HLTimer1 101 = C2OUT or HLTimer1 100 = C1OUT or HLTimer1 011 =COGxFLT 010 = CCP1 001 =C2OUT 000 =C1OUT

bit 2-0 GxRS<2:0>: COGx Rising Source Select bits

111 = COGxFLT or HLTimer1 110 = CCP1 or HLTimer1 101 = C2OUT or HLTimer1 100 = C1OUT or HLTimer1 011 = COGxFLT 010 = CCP1 001 =C2OUT 000 =C1OUT

GxFS<2:0> GxRS<2:0>

DS41576B-page 96 Preliminary  2011 Microchip Technology Inc.

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REGISTER 11-3: COGxASD: COG AUTO-SHUTDOWN CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

GxASDE GxARSEN GxASDL1 GxASDL0 GxASDSHLT GxASDSC2 GxASDSC1 GxASDSFLT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxASDE: Auto-Shutdown Event Status bit

1 = COG is in the shutdown state 0 = COG is not in the shutdown state

bit 6 GxARSEN: Auto-Restart Enable bit

1 = Auto-restart is enabled 0 = Auto-restart is disabled

bit 5 GxASDL1: COGxOUT1 Auto-shutdown Override Level bit

1 =A logic ‘1’ is placed on COGxOUT1 when a shutdown input is true 0 =A logic ‘0’ is placed on COGxOUT1 when a shutdown input is true

bit 4 GxASDL0: COGxOUT0 Auto-shutdown Override Level bit

1 =A logic ‘1’ is placed on COGxOUT0 when a shutdown input is true 0 =A logic ‘0’ is placed on COGxOUT0 when a shutdown input is true

bit 3 GxASDSHLT: COG Auto-shutdown Source Enable bit 3

1 = COG is shutdown when HLTMR equals HLTPR is low 0 = HLTimer1 pin has no effect on shutdown

bit 2 GxASDSC2: COG Auto-shutdown Source Enable bit 2

1 = COG is shutdown when C2OUT is low 0 = C2OUT pin has no effect on shutdown

bit 1 GxASDSC1: COG Auto-shutdown Source Enable bit 1

1 = COG is shutdown when C1OUT is low 0 = C1OUT pin has no effect on shutdown

bit 0 GxASDSFLT: COG Auto-shutdown Source Enable bit 0

1 = COG is shutdown when COGxFLT pin is low 0 = COGxFLT pin has no effect on shutdown

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REGISTER 11-4: COGxDB: COG DEAD-BAND COUNT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

GxDBR<3:0> GxDBF<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-4 GxDBR<3:0>: Rising Event Dead-band Count Value bits

= Number of COG clock periods to delay primary output after rising event input

bit 3-0 GxDBF<3:0>: Falling Event Dead-band Count Value bits

= Number of COG clock periods to delay complementary output after falling event input

REGISTER 11-5: COGxBLK: COG BLANKING COUNT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

GxBLKR<3:0> GxBLKF<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-4 GxBLKR<3:0>: Rising Event Blanking Count Value bits

= Number of COGx clock periods to inhibit falling event input

bit 3-0 GxBLKF<3:0>: Falling Event Blanking Count Value bits

= Number of COGx clock periods to inhibit rising event input

REGISTER 11-6: COGxPH: COG PHASE COUNT REGISTER

U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 GxPH<3:0>: Rising Event Phase Delay Count Value bits

= Number of COG clock periods to delay rising edge event

GxPH<3:0>

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TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH COG

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELA

APFCON

COG1PH

COG1BLK G1BLKR<3:0> G1BLKF<3:0> 98

COG1DB G1DBR<3:0> G1DBF<3:0> 98

COG1CON0 G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD G1CS1 G1CS0 95

COG1CON1 G1FSIM G1RSIM G1FS<2:0> G1RS<2:0> 96

COG1ASD G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT 97

INTCON GIE PEIE

LATA

PIE2

PIR2

TRISA

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG. Note 1: Other (non Power-up) Resets include MCLR

2: See Configuration Word register (Register 17-1) for operation of all register bits.

— — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 50

— — —

— — — —

T0IE INTE IOCIE T0IF INTF IOCIF 20

— —LATA5LATA4 —LATA2LATA1 LATA0 48

— — C2IE C1IE —COG1IE— CCP1IE 22

— — C2IF C1IF —COG1IF— CCP1IF 24

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 48

T1GSEL — COG1FSEL COG1O1SEL COG1O0SEL 46

G1PH<3:0> 98

Reset and Watchdog Timer Reset during normal operation.

on Page

 2011 Microchip Technology Inc. Preliminary DS41576B-page 99

PIC12F752/HV752

NOTES:

DS41576B-page 100 Preliminary  2011 Microchip Technology Inc.

Datasheet PIC12F752, PIC12HV752 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE 1: PIC12F752/HV752 FEATURE SUMMARY

FIGURE 1: 8-PIN DIAGRAM, PIC12F752/HV752 (PDIP, SOIC, DFN)

TABLE 2: PIC12F752/HV752 PIN SUMMARY (PDIP, SOIC, DFN)

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC12F752/HV752 BLOCK DIAGRAM

TABLE 1-1: PIC12F752/HV752 PINOUT DESCRIPTION

2.0 MEMORY ORGANIZATION

FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F752/HV752

TABLE 2-1: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 0

TABLE 2-2: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 1

TABLE 2-3: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 2

TABLE 2-4: PIC12F752/HV752 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

REGISTER 2-1: STATUS: STATUS REGISTER

REGISTER 2-2: OPTION_REG: OPTION REGISTER

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

REGISTER 2-8: PCON: POWER CONTROL REGISTER

EXAMPLE 2-1: INDIRECT ADDRESSING

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F752/HV752

3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL

REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

REGISTER 3-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

EXAMPLE 3-1: FLASH PROGRAM READ

FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

FIGURE 3-2: BLOCK WRITES TO 1K FLASH PROGRAM MEMORY

FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION

EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

TABLE 3-2: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

4.0 OSCILLATOR MODULE

FIGURE 4-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

FIGURE 4-2: OSCILLATOR ENABLE

TABLE 4-1: OSCILLATOR DELAY EXAMPLES

REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER

REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

TABLE 4-3: SUMMARY OF CONFIGURATION WORD CLOCK SOURCES

5.0 I/O PORTS

EXAMPLE 5-1: INITIALIZING PORTA

REGISTER 5-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

TABLE 5-1: PORTA OUTPUT PRIORITY

REGISTER 5-2: PORTA: PORTA REGISTER

REGISTER 5-3: TRISA: PORTA TRI-STATE REGISTER

REGISTER 5-4: LATA: PORTA DATA LATCH REGISTER

REGISTER 5-5: ANSELA: PORTA ANALOG SELECT REGISTER

REGISTER 5-6: WPUA: WEAK PULL-UP PORTA REGISTER

REGISTER 5-7: SLRCONA: SLEW RATE CONTROL REGISTER

REGISTER 5-8: IOCAP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

REGISTER 5-9: IOCAN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

REGISTER 5-10: IOCAF: INTERRUPT-ON-CHANGE FLAG REGISTER

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

6.0 TIMER0 MODULE

FIGURE 6-1: TIMER0 WITH SHARED PRESCALE BLOCK DIAGRAM

REGISTER 6-1: OPTION_REG: OPTION REGISTER

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

7.0 TIMER1 MODULE WITH GATE CONTROL

FIGURE 7-1: TIMER1 BLOCK DIAGRAM

TABLE 7-4: TIMER1 GATE SOURCES

FIGURE 7-2: TIMER1 INCREMENTING EDGE

FIGURE 7-3: TIMER1 GATE COUNT ENABLE MODE

FIGURE 7-4: TIMER1 GATE TOGGLE MODE

FIGURE 7-5: TIMER1 GATE SINGLE-PULSE MODE

FIGURE 7-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER

REGISTER 7-2: T1GCON: TIMER1 GATE CONTROL REGISTER

TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

8.0 TIMER2 MODULE

FIGURE 8-1: TIMER2 BLOCK DIAGRAM

REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2