PIC12F629/675
Data Sheet
8-Pin FLASH-Based 8-Bit
CMOS Microcontrollers
2003 Microchip Technology Inc. DS41190C
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications. No
representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patents or other
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Use of Microchip’s products as critical components in life
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Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Accuron, dsPIC, dsPICDEM.net, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming,
ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net,
PowerCal, PowerInfo, PowerTool, rfPIC, rfLAB, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS41190C - page ii 2003 Microchip Technology Inc.
PIC12F629/675
8-Pin FLASH-Based 8-Bit CMOS Microcontroller
High Performance RISC CPU:
• Only 35 instructions to learn
- All single cycle instructions except branches
• Operating speed:
- DC - 20 MHz oscillator/clock input
- DC - 200 ns instruction cycle
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect, and Relative Addressing modes
Special Microcontroller Features:
• Internal and external oscillator options
- Precision Internal 4 MHz oscillator factory
calibrated to ±1%
- External Oscillator support for crystals and
resonators
-5µs wake-up from SLEEP, 3.0V, typical
• Power saving SLEEP mode
• Wide operating voltage range - 2.0V to 5.5V
• Industrial and Extended temperature range
• Low power Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Detect (BOD)
• Watchdog Timer (WDT) with independent
oscillator for reliable operation
• Multiplexed MCLR/Input-pin
• Interrupt-on-pin change
• Individual programmable weak pull-ups
• Programmable code protection
• High Endurance FLASH/EEPROM Cell
- 100,000 write FLASH endurance
- 1,000,000 write EEPROM endurance
- FLASH/Data EEPROM Retention: > 40 years
Low Power Features:
• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
-8.5µA @ 32 kHz, 2.0V, typical
-100µA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current
- 300 nA @ 2.0V, typical
• Timer1 oscillator current:
-4µA @ 32 kHz, 2.0V, typical
Peripheral Features:
• 6 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- One analog comparator
- Programmable on-chip comparator voltage
reference (CV
- Programmable input multiplexing from device
inputs
- Comparator output is externally accessible
• Analog-to-Digital Converter module (PIC12F675):
- 10-bit resolution
- Programmable 4-channel input
- Voltage reference input
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator, if INTOSC mode
selected
• In-Circuit Serial ProgrammingTM (ICSPTM) via
two pins
REF) module
Program
Device
PIC12F629 1024 64 128 6 – 1 1/1
PIC12F675 1024 64 128 6 4 1 1/1
* 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
2003 Microchip Technology Inc. DS41190C-page 1
Memory
FLASH
(words)
Data Memory
SRAM
(bytes)
EEPROM
(bytes)
I/O
10-bit A/D
(ch)
Comparators
Timers
8/16-bit
PIC12F629/675
Pin Diagrams
8-pin PDIP, SOIC, DFN-S
GP5/T1CKI/OSC1/CLKIN
GP4/T1G
/OSC2/CLKOUT
GP3/MCLR
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G
/OSC2/CLKOUT
GP3/MCLR
VDD
/VPP
VDD
/VPP
1
8
PIC12F629
2
7
3
6
45
1
8
PIC12F675
2
7
3
6
45
VSS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
VSS
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/V
GP2/AN2/T0CKI/INT/COUT
REF/ICSPCLK
DS41190C-page 2 2003 Microchip Technology Inc.
PIC12F629/675
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5
2.0 Memory Organization.................................................................................................................................................................. 7
3.0 GPIO Port ................................................................................................................................................................................. 19
4.0 Timer0 Module .......................................................................................................................................................................... 27
5.0 Timer1 Module with Gate Control ............................................................................................................................................. 30
6.0 Comparator Module .................................................................................................................................................................. 35
7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) ................................................................................................... 41
8.0 Data EEPROM Memory ............................................................................................................................................................ 47
9.0 Special Features of the CPU .................................................................................................................................................... 51
10.0 Instruction Set Summary ........................................................................................................................................................... 69
11.0 Development Support ............................................................................................................................................................... 77
12.0 Electrical Specifications ............................................................................................................................................................ 83
13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 105
14.0 Packaging Information ............................................................................................................................................................ 115
Appendix A: Data Sheet Revision History ......................................................................................................................................... 121
Appendix B: Device Differences ....................................................................................................................................................... 121
Appendix C: Device Migrations ......................................................................................................................................................... 122
Appendix D: Migrating from other PICmicro
Index ................................................................................................................................................................................................. 123
On-Line Support ................................................................................................................................................................................ 127
Systems Information and Upgrade Hot Line ..................................................................................................................................... 127
Reader Response ............................................................................................................................................................................. 128
Product Identification System ........................................................................................................................................................... 129
®
Devices ...................................................................................................................... 122
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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2003 Microchip Technology Inc. DS41190C-page 3
PIC12F629/675
NOTES:
DS41190C-page 4 2003 Microchip Technology Inc.
PIC12F629/675
1.0 DEVICE OVERVIEW
This document contains device specific information for
the PIC12F629/675. Additional information may be
found in the PICmicro
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this Data
FIGURE 1-1: PIC12F629/675 BLOCK DIAGRAM
Program
Bus
Internal
4 MHz
Oscillator
OSC1/CLKIN
OSC2/CLKOUT
T1G
TM
Mid-Range Reference Manual
FLASH
Program
Memory
1K x 14
14
Instruction Reg
Instruction
Decode &
Control
Timing
Generation
DD, VSS
V
13
Program Counter
8-Level Stack
Direct Addr
8
Power-up
Time r
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Time r
Brown-out
Detect
(13-bit)
Data Bus
RAM
File
Registers
64 x 8
9
Addr MUX
7
FSR Reg
STATUS Reg
3
ALU
8
W Reg
Sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
The PIC12F629 and PIC12F675 devices are covered
by this Data Sheet. They are identical, except the
PIC12F675 has a 10-bit A/D converter. They come in
8-pin PDIP, SOIC, and MLF-S packages. Figure 1-1
shows a block diagram of the PIC12F629/675
devices. Table 1-1 shows the Pinout Description.
8
GP0/AN0/CIN+
8
MUX
RAM
Addr
Indirect
Addr
GP1/AN1/CIN-/V
GP2/AN2/T0CKI/INT/COUT
GP3/MCLR
GP4/AN3/T1G/OSC2/CLKOUT
GP5/T1CKI/OSC1/CLKIN
(1)
REF
/VPP
T1CKI
T0CKI
VREF
Time r0 Timer1
Analog to Digital Converter
(PIC12F675 only)
CIN- CIN+ COUT
AN0 AN1 AN2 AN3
Note 1: Higher order bits are from STATUS register.
Analog
Comparator
and reference
EE DATA
128 bytes
8
EEPROM
EEADDR
DATA
2003 Microchip Technology Inc. DS41190C-page 5
PIC12F629/675
TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION
Name Function
GP0/AN0/CIN+/ICSPDAT GP0 TTL CMOS Bi-directional I/O w/ programmable pull-up and
AN0 AN A/D Channel 0 input
CIN+ AN Comparator input
ICSPDAT TTL CMOS Serial programming I/O
GP1/AN1/CIN-/VREF/
ICSPCLK
GP2/AN2/T0CKI/INT/COUT GP2 ST CMOS Bi-directional I/O w/ programmable pull-up and
GP3/MCLR/VPP GP3 TTL Input port w/ interrupt-on-change
GP4/AN3/T1G/OSC2/
CLKOUT
GP5/T1CKI/OSC1/CLKIN
VSS VSS Power Ground reference
VDD VDD Power Positive supply
Legend: Shade = PIC12F675 only
TTL = TTL input buffer, ST = Schmitt Trigger input buffer
GP1 TTL CMOS Bi-directional I/O w/ programmable pull-up and
AN1 AN A/D Channel 1 input
CIN- AN Comparator input
VREF AN External voltage reference
ICSPCLK ST Serial programming clock
AN2 AN A/D Channel 2 input
T0CKI ST TMR0 clock input
INT ST External interrupt
COUT CMOS Comparator output
MCLR ST Master Clear
VPP HV Programming voltage
GP4 TTL CMOS Bi-directional I/O w/ programmable pull-up and
AN3 AN A/D Channel 3 input
T1G ST TMR1 gate
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
GP5 TTL CMOS Bi-directional I/O w/ programmable pull-up and
T1CKI ST TMR1 clock
OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/RC oscillator connection
Input
Type
Output
Type
Description
interrupt-on-change
interrupt-on-change
interrupt-on-change
interrupt-on-change
interrupt-on-change
DS41190C-page 6 2003 Microchip Technology Inc.
PIC12F629/675
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F629/675 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h - 03FFh)
for the PIC12F629/675 devices is physically implemented. Accessing a location above these boundaries
will cause a wrap around within the first 1K x 14 space.
The RESET vector is at 0000h and the interrupt vector
is at 0004h (see Figure 2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F629
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
/675
13
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose registers and the Special Function registers. The Special
Function registers are located in the first 32 locations of
each bank. Register locations 20h-5Fh are General
Purpose registers, implemented as static RAM and are
mapped across both banks. All other RAM is
unimplemented and returns ‘0’ when read. RP0
(STATUS<5>) is the bank select bit.
• RP0 = 0 Bank 0 is selected
• RP0 = 1 Bank 1 is selected
Note: The IRP and RP1 bits STATUS<7:6> are
reserved and should always be maintained
as ‘0’s.
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F629/675 devices. Each register is accessed,
either directly or indirectly, through the File Select
Register FSR (see Section 2.4).
RESET Vector
Interrupt Vector
On-chip Program
Memory
000h
0004
0005
03FFh
0400h
1FFFh
2003 Microchip Technology Inc. DS41190C-page 7
PIC12F629/675
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
FIGURE 2-2: DATA MEMORY MAP OF
THE PIC12F629/675
File
Address
PCL
FSR
GPIO
PIR1
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
(2)
1Eh
(2)
1Fh
20h
Indirect addr.
OPTION_REG
EECON2
ADRESL
Indirect addr.
TMR0
STATUS
PCLATH
INTCON
TMR1L
TMR1H
T1CON
CMCON VRCON
ADRESH
ADCON0
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCAL
WPU
IOC
EEDATA
EEADR
EECON1
ANSEL
(2)
(1)
(2)
Address
(1)
File
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
General
Purpose
Registers
64 Bytes
5Fh
60h
7Fh
Bank 0
Unimplemented data memory locations, read as '0'.
1: Not a physical register.
2: PIC12F675 only.
DS41190C-page 8 2003 Microchip Technology Inc.
accesses
20h-5Fh
DFh
E0h
FFh
Bank 1
PIC12F629/675
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
00h INDF
01h TMR0 Timer0 Module’s Register xxxx xxxx 27
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17
03h STATUS
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 18
05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx 19
06h — Unimplemented — —
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 17
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 15
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 30
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 30
10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 32
11h — Unimplemented — —
12h — Unimplemented — —
13h — Unimplemented — —
14h — Unimplemented — —
15h — Unimplemented — —
16h — Unimplemented — —
17h — Unimplemented — —
18h — Unimplemented — —
19h CMCON —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH
1Fh ADCON0
(1)
Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 18,59
(2)
IRP
(3)
Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result xxxx xxxx 42
(3)
ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 43,59
RP1
COUT
(2)
RP0 TO PD Z DC C
—
CINV CIS CM2 CM1 CM0
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
Value on
POR, BOD
0001 1xxx 11
-0-0 0000 35
Page
2003 Microchip Technology Inc. DS41190C-page 9
PIC12F629/675
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
80h INDF
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12,28
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17
83h STAT US
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 18
85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 19
86h — Unimplemented — —
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 17
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 14
8Dh — Unimplemented — —
8Eh PCON — — — — — — POR BOD ---- --0x 16
8Fh — Unimplemented — —
90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 16
91h — Unimplemented — —
92h — Unimplemented — —
93h — Unimplemented — —
94h — Unimplemented — —
95h WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 20
96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 21
97h — Unimplemented — —
98h — Unimplemented — —
99h VRCON VREN —
9Ah EEDATA Data EEPROM Data Register 0000 0000 47
9Bh EEADR — Data EEPROM Address Register -000 0000 47
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 48
9Dh EECON2
9Eh ADRESL
9Fh ANSEL
(1)
(3)
Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 18,59
(2)
IRP
(1)
EEPROM Control Register 2 ---- ---- 48
(3)
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 42
— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 44,59
RP1
(2)
RP0 TO PD Z DC C 0001 1xxx 11
VRR
—
VR3 VR2 VR1 VR0
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
Value on
POR, BOD
0-0- 0000 40
Page
DS41190C-page 10 2003 Microchip Technology Inc.
PIC12F629/675
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the RESET status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
and PD bits are not
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any STATUS bits. For other instructions not
affecting any STATUS bits, see the “Instruction Set
Summary”.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12F629/675 and should
be maintained as clear. Use of these bits
is not recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS — STATUS REGISTER (ADDRESS: 03h OR 83h)
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0
bit 7 IRP: This bit is reserved and should be maintained as ‘0’
bit 6 RP1: This bit is reserved and should be maintained as ‘0’
bit 5 RP0: Register Bank Select bit (used for direct addressing)
0 = Bank 0 (00h - 7Fh)
1 = Bank 1 (80h - FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow,
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
the polarity is reversed.
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS41190C-page 11
PIC12F629/675
2.2.2.2 OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
• TMR0/WDT prescaler
• External GP2/INT interrupt
•TMR0
• Weak pull-ups on GPIO
REGISTER 2-2: OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION<3>). See
Section 4.4.
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS41190C-page 12 2003 Microchip Technology Inc.
PIC12F629/675
2.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO port change and
external GP2/INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 2-3: INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3 GPIE: Port Change Interrupt Enable bit
1 = Enables the GPIO port change interrupt
0 = Disables the GPIO port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0 GPIF: Port Change Interrupt Flag bit
1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)
0 = None of the GP5:GP0 pins have changed state
(1)
(2)
Note 1: IOC register must also be enabled to enable an interrupt-on-change.
2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and
should be initialized before clearing T0IF bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS41190C-page 13
PIC12F629/675
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4: PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIE ADIE — — CMIE — — TMR1IE
bit 7 bit 0
bit 7 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only)
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4 Unimplemented: Read as ‘0’
bit 3 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS41190C-page 14 2003 Microchip Technology Inc.
PIC12F629/675
2.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5: PIR1 — PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIF ADIF — — CMIF — — TMR1IF
bit 7 bit 0
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ‘0’
bit 3 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS41190C-page 15
PIC12F629/675
2.2.2.6 PCON Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Detect (BOD)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6: PCON — POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x
— — — — — — POR BOD
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR: Power-on Reset STATUS bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOD: Brown-out Detect STATUS bit
1 = No Brown-out Detect occurred
0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2.2.2.7 OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to
calibrate the internal 4 MHz oscillator. It contains 6 bits
to adjust the frequency up or down to achieve 4 MHz.
The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7: OSCCAL — OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — —
bit 7 bit 0
bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits
111111 = Maximum frequency
100000 = Center frequency
000000 = Minimum frequency
bit 1-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS41190C-page 16 2003 Microchip Technology Inc.
PIC12F629/675
2.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figure 2-3 shows how the PC is loaded on
a write to PCL (PCLATH<4:0> → PCH). The lower
example in Figure 2-3 shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3> →
PCH).
FIGURE 2-3: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
11
8
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
2.3.2 STACK
The PIC12F629/675 family has an 8-level deep x 13-bit
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the stack
pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL instruction is executed, or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
PCLATH
2.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When perform-
ing a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note “Implementing a Table Read"
(AN556).
2003 Microchip Technology Inc. DS41190C-page 17
PIC12F629/675
2.4 Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESSING
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actually accesses data pointed to by the File Select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no
operation (although STATUS bits may be affected). An
effective 9-bit address is obtained by concatenating the
NEXT clrf INDF ;clear INDF register
CONTINUE ;yes continue
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-4.
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F629/675
(1)
RP1
RP0 6
Bank Select Location Select
From Opcode
0
00 01 10 11
00h
(1)
IRP
Bank Select
180h
Indirect AddressingDirect Addressing
7
FSR Register
Location Select
0
Data
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
For memory map detail see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
Not Used
1FFh
DS41190C-page 18 2003 Microchip Technology Inc.
PIC12F629/675
3.0 GPIO PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
Note: Additional information on I/O ports may be
found in the PICmicro™ Mid-Range Reference Manual, (DS33023)
3.1 GPIO and the TRISIO Registers
GPIO is an 6-bit wide, bi-directional port. The corresponding data direction register is TRISIO. Setting a
TRISIO bit (= 1) will make the corresponding GPIO pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISIO bit (= 0) will
make the corresponding GPIO pin an output (i.e., put
the contents of the output latch on the selected pin).
The exception is GP3, which is input only and its
TRISIO bit will always read as ‘1’. Example 3-1 shows
how to initialize GPIO.
Reading the GPIO register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch. GP3 reads ‘0’ when MCLREN = 1.
The TRISIO register controls the direction of the
GP pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
Note: The ANSEL (9Fh) and CMCON (19h)
registers (9Fh) must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’. The ANSEL register is defined for
the PIC12F675.
EXAMPLE 3-1: INITIALIZING GPIO
bcf STATUS,RP0 ;Bank 0
clrf GPIO ;Init GPIO
movlw 07h ;Set GP<2:0> to
movwf CMCON ;digital IO
bsf STATUS,RP0 ;Bank 1
clrf ANSEL ;Digital I/O
movlw 0Ch ;Set GP<3:2> as inputs
movwf TRISIO ;and set GP<5:4,1:0>
;as outputs
3.2 Additional Pin Functions
Every GPIO pin on the PIC12F629/675 has an
interrupt-on-change option and every GPIO pin, except
GP3, has a weak pull-up option. The next two sections
describe these functions.
3.2.1 WEAK PULL-UP
Each of the GPIO pins, except GP3, has an individually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 3-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit
(OPTION<7>).
REGISTER 3-1: GPIO — GPIO REGISTER (ADDRESS: 05h)
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— —
bit 7 bit 0
bit 7-6: Unimplemented: Read as ’0’
bit 5-0: GPIO<5:0>: General Purpose I/O pin.
1 = Port pin is >VIH
0 = Port pin is <VIL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS41190C-page 19
GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
PIC12F629/675
REGISTER 3-2: TRISIO — GPIO TRISTATE REGISTER (ADDRESS: 85h)
U-0 U-0 R/W-x R/W-x R-1 R/W-x R/W-x R/W-x
— —
bit 7 bit 0
bit 7-6: Unimplemented: Read as ’0’
bit 5-0: TRISIO<5:0>: General Purpose I/O Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output.
Note: TRISIO<3> always reads 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
REGISTER 3-3: WPU — WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— — WPU5 WPU4 — WPU2 WPU1 WPU0
bit 7 bit 0
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 WPU<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 WPU<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISIO = 0).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS41190C-page 20 2003 Microchip Technology Inc.
PIC12F629/675
3.2.2 INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR'd
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of GPIO. This will end the
mismatch condition.
b) Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF interrupt flag may not get set.
REGISTER 3-4: IOC — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOC<5:0>: Interrupt-on-Change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be
recognized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS41190C-page 21
PIC12F629/675
3.3 Pin Descriptions and Diagrams
Each GPIO pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D, refer to the
appropriate section in this Data Sheet.
3.3.1 GP0/AN0/CIN+
Figure 3-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• an analog input to the comparator
3.3.2 GP1/AN1/CIN-/VREF
Figure 3-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
• as a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• an analog input to the comparator
• a voltage reference input for the A/D (PIC12F675
only)
FIGURE 3-1: BLOCK DIAGRAM OF GP0
AND GP1 PINS
Analog
Data Bus
WR
WPU
RD
WPU
WR
PORT
WR
TRISIO
RD
TRISIO
RD
PORT
WR
IOC
RD
IOC
D
CK
D
CK
D
CK
D
CK
Input Mode
Q
Q
GPPU
Q
Q
Q
Q
Analog
Input Mode
Q
Q
Q
Q
VDD
Weak
VDD
I/O pin
VSS
D
EN
D
Interrupt-on-Change
To Comparator
To A/D Converter
EN
RD PORT
DS41190C-page 22 2003 Microchip Technology Inc.
PIC12F629/675
3.3.3 GP2/AN2/T0CKI/INT/COUT
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from the comparator
FIGURE 3-2: BLOCK DIAGRAM OF GP2
Analog
Data Bus
WR
WPU
RD
WPU
WR
PORT
WR
TRISIO
RD
TRISIO
D
CK
D
CK
D
CK
Input Mode
Q
Q
GPPU
COUT
Enable
Q
Q
Q
Q
COUT
1
0
Analog
Input Mode
Analog
Input
Mode
VDD
Weak
VDD
I/O pin
VSS
3.3.4 GP3/MCLR/VPP
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset
FIGURE 3-3: BLOCK DIAGRAM OF GP3
Data Bus
RD
TRISIO
RD
PORT
D
WR
IOC
RD
IOC
Interrupt-on-Change
CK
RESET
VSS
Q
Q
MCLRE
MCLRE
Q
EN
Q
EN
RD PORT
I/O pin
SS
V
D
D
RD
PORT
Q
D
WR
IOC
RD
IOC
Interrupt-on-Change
CK
Q
To TMR0
To I N T
To A/D Converter
Q
EN
Q
EN
RD PORT
D
D
2003 Microchip Technology Inc. DS41190C-page 23
PIC12F629/675
3.3.5 GP4/AN3/T1G/OSC2/CLKOUT
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 3-4: BLOCK DIAGRAM OF GP4
Analog
Data Bus
WR
WPU
WPU
WR
PORT
WR
TRISIO
TRISIO
PORT
WR
IOC
IOC
Interrupt-on-Change
D
CK
RD
D
CK
D
CK
RD
RD
D
CK
RD
Q
Q
Q
Q
Q
Q
Q
Q
Input Mode
F
GPPU
OSC1
OSC/4
CLKOUT
Enable
INTOSC/
RC/EC
CLKOUT
Enable
Input Mode
CLK
Modes
Oscillator
Circuit
CLKOUT
Enable
1
0
(2)
Analog
Q
Q
(1)
VDD
Weak
VDD
I/O pin
VSS
D
EN
D
EN
3.3.6 GP5/T1CKI/OSC1/CLKIN
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 3-5: BLOCK DIAGRAM OF GP5
INTOSC
Data Bus
WPU
WPU
PORT
TRISIO
TRISIO
PORT
IOC
IOC
Interrupt-on-Change
WR
RD
WR
WR
RD
RD
WR
RD
D
CK
D
CK
D
CK
D
CK
Mode
TMR1LPEN
Q
Q
GPPU
Oscillator
Q
Q
Q
Q
Q
Q
OSC2
INTOSC
Mode
RD PORT
Circuit
Q
Q
(1)
VDD
Weak
VDD
I/O pin
VSS
(2)
D
EN
D
EN
To TMR1 T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
RD PORT
To TMR1 or CLKGEN
Note 1: Timer1 LP Oscillator enabled
2: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
DS41190C-page 24 2003 Microchip Technology Inc.
PIC12F629/675
TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
95h WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 --11 -111
96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000
9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by GPIO.
POR,
BOD
Value on all
other
RESETS
2003 Microchip Technology Inc. DS41190C-page 25
PIC12F629/675
NOTES:
DS41190C-page 26 2003 Microchip Technology Inc.
PIC12F629/675
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 4-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Note: Additional information on the Timer0
module is available in the PICmicro
Range Reference Manual, (DS33023).
4.1 Timer0 Operation
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
TM
Mid-
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin GP2/T0CKI. The incrementing edge is determined
by the source edge (T0SE) control bit
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
Note: Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
TM
PICmicro
Mid-Range Reference
Manual, (DS33023).
4.2 Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit. The interrupt can be masked
by clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before reenabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is
shut-off during SLEEP.
FIGURE 4-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT
(= FOSC/4)
0
1
1
T0CKI
pin
T0SE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
T0CS
Watchdog
Timer
WDTE
0
8-bit
Prescaler
1
PSA
PSA
8
PS0 - PS2
PSA
SYNC 2
Cycles
0
1
WDT
Time-out
0
Data Bus
8
TMR0
Set Flag bit T0IF
on Overflow
2003 Microchip Technology Inc. DS41190C-page 27
PIC12F629/675
4.3 Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2T
OSC (and
a small RC delay of 20 ns) and low for at least 2T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
REGISTER 4-1: OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS41190C-page 28 2003 Microchip Technology Inc.
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