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PIC12F635
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Datasheet PIC12F635, PIC16F636, PIC16F639 Datasheet

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PIC12F635/PIC16F636/639
Data Sheet
8/14-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
with nanoWatt Technology
*8-bit, 8-pin Devices Protecte d by Microchip’ s Low Pin Coun t Patent: U. S. Patent N o. 5,847,450. Additi onal U.S. and foreign patents and applications may be issued or pending.
© 2007 Microchip Technology Inc. DS41232D
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K
EELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfP IC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MX DEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC® DSCs, KEELOQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
®
code hopping devices, Serial
®
PIC12F635/PIC16F636/639
8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers
With nanoWatt Technology
High-Performance RISC CPU:
• Only 35 instructions to learn:
- All single-cycle instructions except branches
• Operating speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instr uction cycle
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range of 8 MHz to 125 kHz
- Software tunable
- Two-Speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for power savings
• Clock mode switching for low-power operation
• Power-Saving Sleep mode
• Wide operating voltage range (2.0V-5.5V)
• Industrial and Extended Temperature range
• Power-on Reset (POR)
• Wake-up Reset (WUR)
• Independent weak pull-up/pull-down resistors
• Programmable Low-Voltage Detect (PLVD)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with software control option
• Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable
• Multiplexed Master Clear with pull-up/input pin
• Programmable code protection (program and data independent)
• High-Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM Retention: > 40 years
Low-Power Features:
• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
-8.5μA @ 32 kHz, 2.0V, typical
-100μA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current:
-1μA @ 2.0V, typical
Peripheral Features:
• 6/12 I/O pins with individual dire ct ion contro l:
- High-current source/sink for direct LED drive
- Interrupt-on-change pin
- Individually programmable weak pull-ups/ pull-downs
- Ultra Low-Power Wake-up
• Analog Comparator module with:
- Up to tw o analog comparators
- Programmable On-chip Voltage Reference
REF) module (% of VDD)
(CV
- Comparator inputs and outputs externally accessible
• Timer0: 8-bit timer/counter with 8-bit programmable prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode selected
®
EELOQ
•K module
• In-Circuit Serial Programming™ (ICSP™) via two pins
compatible hardware Crypt ographic
Low-Frequency Analog Front-End Features (PIC16F639 only):
• Three input pins for 125 kHz LF input signals
• High input detection sensitivity (3mV
• Demodulated data, Carrier clock or RSSI output selection
• Input carrier frequency: 125 kHz, typical
• Input modulation frequency: 4 kHz, maximum
• 8 internal Configuration registers
• Bidirectional transponder communication (LF talk back)
• Programmable antenna tuning capac itance (up to 63 pF, 1 pF/step)
• Low standby current: 5 μA (with 3 channels enabled), typical
• Low operating current: 15 μA (with 3 channels enabled), typical
• Serial Peripheral Interface (SPI) with internal MCU and external devices
• Supports Battery Back-up mode and batteryless operation with external circuits
PP, typical)
© 2007 Microchip Technology Inc. DS41232D-page 1
PIC12F635/PIC16F636/639
Program Memory Data Memory
Device
PIC12F635 1024 64 128 6 1 N PIC16F636 2048 128 256 12 2 N PIC16F639 2048 128 256 12 2 Y
Note 1: Any references to PORT A, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively.
2: V
3: VSST is the grou n d r ef e re n ce vo l tage of t h e A na l og Fr on t -E nd s ec t ion ( PIC 1 6 F63 9 on l y) . VSST is treated
Flash (words) SRAM (bytes) EEPROM (bytes)
DDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in
this document unless ot herwise stated.
SS in this document unless otherwise stated.
as V
I/O Comparators
Low Frequency
Analog
Front-End
PIC12F635/PIC16F636/639
8-Pin Diagrams (PDIP, SOIC, DFN, DFN-S)
PDIP, SOIC
DFN, DFN-S
GP5/T1CKI/OSC1/CLKIN
GP4/T1G
GP5/T1CKI/OSC1/CLKIN
GP4/T1G
/OSC2/CLKOUT
GP3/MCLR
VDD
/OSC2/CLKOUT
GP3/MCLR
/VDD
/VPP
1 2
3 4
1 2
3 4
8 7
6
PIC12F635
5
PIC12F635
VSSVDD GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT
8 7 6 5
VSS GP0/CIN+/ICSPDAT/ULPWU GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT
TABLE 1: 8-PIN SUMMARY (PDIP, SOIC, DFN, DFN-S)
I/O Pin Comparators Timer Interrupts Pull-ups Basic
GP0 7 C1IN+ — IOC Y ICSPDAT/ULPWU GP1 6 C1IN- — IOC Y ICSPCLK GP2 5 C1OUT T0CKI INT/IOC Y —
(1)
GP3 GP4 3 — T1G IOC Y OSC2/CLKOUT
GP5 2 — T1CKI IOC Y OSC1/CLKIN
— 1 — — — — VDD —8———— VSS
Note 1: Input only.
4— — IOC Y
2: Only when pin is configured for external MCLR.
(2)
MCLR/VPP
© 2007 Microchip Technology Inc. DS41232D-page 3
PIC12F635/PIC16F636/639
14-Pin Diagram (PDIP, SOIC, TSSOP)
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G
/OSC2/CLKOUT
RA3/MCLR
RC4/C2OUT
/VPP RC5
RC3
1 2 3 4 5 6 7
14 13 12 11 10
PIC16F636
9 8
VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C2IN­RC2
REF/ICSPCLK
TABLE 2: 14-PIN SUMMARY (PDIP, SOIC, TSSOP)
I/O Pin Comparators Timer Interrupts Pull-ups Basic
RA0 13 C1IN+ — IOC Y ICSPDAT/ULPWU RA1 12 C1IN- — IOC Y VREF/ICSPCLK RA2 11 C1OUT T0CKI INT/IOC Y —
(1)
RA3 RA4 3 — T1G IOC Y OSC2/CLKOUT
RA5 2 — T1CKI IOC Y OSC1/CLKIN RC0 10 C2IN+ — — — — RC1 9 C2IN- — — — — RC2 8 — — — — — RC37———— — RC4 6 C2OUT — — — — RC55———— —
— 1 — — — — VDD —14———— VSS
Note 1: Input only.
4— — IOC Y
2: Only when pin is configured for external MCLR
.
(2)
MCLR/VPP
16-Pin Diagram
QFN
PIC12F635/PIC16F636/639
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
RA3/MCLR
/VPP RC5
VDD
16
1 2
PIC16F636
3 4
5
RC4/C2OUT
NCNCV
15
6
RC3
14
7
RC2
SS
13
12 11 10
8
RC1/C2IN-
RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V
RA2/T0CKI/INT/C1OUT
9
RC0/C2IN+
REF/ICSPCLK
TABLE 3: 16-PIN SUMMARY
I/O Pin Comparators Timer Interrupts Pull-ups Basic
RA0 12 C1IN+ — IOC Y ICSPDAT/ULPWU RA1 11 C1IN- — IOC Y VREF/ICSPCLK RA2 10 C1OUT T0CKI INT/IOC Y —
(1)
RA3 RA4 2 — T1G IOC Y OSC2/CLKOUT
RA5 1 — T1CKI IOC Y OSC1/CLKIN RC0 9 C2IN+ — — — — RC1 8 C2IN- — — — — RC2 7 — — — — — RC36———— — RC4 5 C2OUT — — — — RC54———— —
— 16 — — — — VDD —13———— VSS — 14 — — — — NC —15———— NC
Note 1: Input only.
3— — IOC Y
2: Only when pin is configured for external MCLR.
(2)
MCLR/VPP
© 2007 Microchip Technology Inc. DS41232D-page 5
PIC12F635/PIC16F636/639
20-Pin Diagram
SSOP
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR
/VPP RC5
RC4/C2OUT
RC3/LFDATA/RSSI/CCLK/SDIO
(3)
V
DDT
LCZ
LCY
1 2 3 4 5 6 7 8 9 10
20 19 18 17
16 15 14
PIC16F639
13 12 11
VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V
REF/ICSPCLK
RA2/TOCKI/INT/C1OUT RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT
(4)
VSST LCCOM LCX
TABLE 4: 20-PIN SUMMARY
I/O Pin Analog Front-End Comparators Timer Interrupts Pull-ups Basic
RA0 19 — C1IN+ — IOC Y ICSPDAT/ULPWU RA1 18 — C1IN- — IOC Y VREF/ICSPCLK RA2 17 — C1OUT T0CKI INT/IOC Y —
(1)
RA3
4— ——IOCY RA4 3 — — T1G IOC Y OSC2/CLKOUT RA5 2 — — T1CKI IOC Y OSC1/CLKIN RC0 16 — C2IN+ — — — — RC1 15 — C2IN- — — — CS RC2 14 ALERT — — — — SCLK RC3 7 LFDATA/RSSI — — — — CCLK/SDIO RC4 6 — C2OUT — — — — RC5 5 — — — — — —
— 8 — — — — — VDDT —13 — — ——— VSST — 11 LCX — — — — — —10 LCY — ——— — — 9 LCZ — — — — — — 12 LCCOM — — — — — — 1 — — — — — VDD —20 — — ——— VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR. 3: V
DDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in
this document unless ot herwise stated.
4: V
SST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated
as V
SS in this document unless otherwise stated.
(2)
MCLR/VPP
(3) (4)
PIC12F635/PIC16F636/639
Table of Contents
1.0 Device Overview.......................................................................................................................................................................... 9
2.0 Memory Organization................................................................................................................................................................. 17
3.0 Clock Sources............................................................................................................................................................................ 35
4.0 I/O Ports...................... .................................................... ........................................ ...................................................................47
5.0 Timer0 Module ........................................................................................................................................................................... 61
6.0 Timer1 Module with Gate Control............................................................................................................................................... 64
7.0 Comparator Module.................................................................. .... .. .... .. ......... .... .. .... ......... .......................................................... 71
8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 87
9.0 Data EEPROM Memory................................................ ........................................ ..................................................................... 91
10.0 K
11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 97
12.0 Special Features of the CPU......................... ........................... ........................................ ........................................................ 129
13.0 Instruction Set Summary.......................................................................................................................................................... 149
14.0 Development Support............................................................................................................................................................... 159
15.0 Electrical Specifications............................................................................................................................................................ 163
16.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................191
17.0 Packaging Information. ........................... ........................................ ..........................................................................................211
On-Line Support 223
Systems Information and Upgrade Hot Line..................................................................................................................................... 223
Reader Response............................................................................................................................................................................. 224
Appendix A: Data Sheet Revision History......................................................................................................................................... 225
Product Identification System........................................................................................................................................................... 231
Worldwide Sales and Service ...................................................... ........................... .......................................................................... 232
®
EELOQ
Compatible Cryptographic Module............................................................................................................................. 95
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
© 2007 Microchip Technology Inc. DS41232D-page 7
PIC12F635/PIC16F636/639
NOTES:
PIC12F635/PIC16F636/639

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the PIC12F635/PIC16F636/639 devices.

FIGURE 1-1: PIC12F635 BLOCK DIAGRAM

Program
Bus
Configuration
Flash
1K x 14
Program
Memory
14
Instruction Reg
13
Program Counter
8-level Stack
(13-bit)
Direct Addr
8
Block Diagrams and pinout descriptions of the devices are as follows:
• PIC12F635 (Figure 1-1, Table 1-1)
• PIC16F636 (Figure 1-2, Table 1-2)
• PIC16F639 (Figure 1-3, Table 1-3)
RAM Addr
7
Data Bus
RAM
64 bytes
File
Registers
Addr MUX
8
FSR Reg
STATUS Reg
9
Indirect
Addr
8
GPIO
GP0 GP1 GP2 GP3 GP4 GP5
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
T1G
T1CKI
T0CKI
Cryptographic
Instruction
Decode and
Control
Timing
Generation
8 MHz
Internal
Timer0 Timer1
Module
31 kHz
Internal
Oscillator
Low-Voltage Detect
MCLR
C1IN- C1IN+ C1OUT
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Programmable
Wake-up
Reset
VDD
VSS
1 Analog
Comparator
and Reference
3
8
MUX
ALU
W Reg
EEDAT
128 bytes
Data
EEPROM EEADDR
© 2007 Microchip Technology Inc. DS41232D-page 9
PIC12F635/PIC16F636/639

FIGURE 1-2: PIC16F636 BLOCK DIAGRAM

Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
8 MHz
Internal
Oscillator
Configuration
Flash
2K x 14
Program
Memory
14
Instruction Reg
Instruction
Decode and
Control
Timing
Generation
31 kHz
Internal
Oscillator
13
Program Counter
8-level Stack
(13-bit)
Direct Addr
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Programmable
Low-Voltage Detect
Wake-up
Reset
RAM Addr
7
3
8
Data Bus
RAM
128
bytes
File
Registers
Addr MUX
8
FSR Reg
STATUS Reg
ALU
W Reg
T1CKI
9
MUX
Indirect
Addr
T1G
8
PORTA
RA0 RA1 RA2 RA3 RA4 RA5
PORTC
RC0 RC1 RC2 RC3 RC4 RC5
VDD
MCLR
T0CKI
Timer0 Timer1
Cryptographic
Module
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
2 Analog Comparators
and Reference
VSS
EEDAT
256 bytes
Data
EEPROM
EEADDR
PIC12F635/PIC16F636/639

FIGURE 1-3: PIC16F639 BLOCK DIAGRAM

OSC1/CLKIN
OSC2/CLKOUT
T0CKI
Configuration
Flash 2K x 14 Program
Memory
Program
Bus
8 MHz
Internal
Oscillator
14
Instruction Reg
Instruction
Decode and
Control
Timing
Generation
31 kHz Internal
Oscillator
Timer0 Timer1
13
Program Counter
8-level Stack
(13-bit)
Direct Addr
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Programmable
Low-voltage Detect
Wake-up
Reset
VDD
MCLR
RAM Addr
7
3
8
VSS
Data Bus
RAM
128
bytes
File
Registers
(1)
9
Addr MUX
8
FSR Reg
STATUS Reg
MUX
ALU
W Reg
T1CKI T1G
Indirect
Addr
8
PORTA
PORTC
VDDT
SST
V
LCCOM
RA0 RA1 RA2 RA3 RA4 RA5
RC0 RC1 RC2 RC3 RC4 RC5
125 kHz
Analog Front-End
(AFE)
LCX
LCY LCZ
KEELOQ Module
2 Analog
Comparators
and Reference
C1IN- C1IN+ C1OUT C2IN-
C2IN+ C2OUT
EEDAT
256 bytes
DATA
EEPROM
EEADDR
© 2007 Microchip Technology Inc. DS41232D-page 11
PIC12F635/PIC16F636/639

TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS

Name Function
GP0/C1IN+/ICSPD AT/ULPWU GP0 TTL — General purpose I/O. Individually controlled
C1IN+ AN — Comparator 1 input – positive.
ICSPDAT TTL CMOS Serial programming data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
GP1/C1IN-/ICSPCLK GP1 TTL CMOS General purpose I/O. Individually controlled
C1IN- AN — Comparator 1 input – negative.
ICSPCLK ST — Serial programming clock.
GP2/T0CKI/INT/C1OUT GP2 ST CMOS General purpose I/O. Individually controlled
T0CKI ST — External clock for Timer0.
INT ST — External interrupt.
C1OUT — CMOS Comparator 1 output.
GP3/MCLR
GP4/T1G
GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O. Individually controlled
DD VDD D — Power supply for microcontroller.
V V
SS VSS D — Ground reference for microcontroller.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct
/VPP GP3 TTL — General purpose input. Individually controlled
MCLR
PP HV — Programming voltage.
V
/OSC2/CLKOUT GP4 TTL CMOS General purpose I/O. Individually controlled
T1G
OSC2 — XTAL XTAL connection.
CLKOUT — CMOS T
T1CKI ST — Timer1 clock.
OSC1 XTAL — XTAL connection.
CLKIN ST — T
HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XT AL = Crystal
Input
Type
Output
Type
interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.
interrupt-on-change. Individually enabled pull-up/pull-down.
interrupt-on-change. Individually enabled pull-up/pull-down.
interrupt-on-change.
ST — Master Clear Reset. Pull-up enabled when configured as MCLR.
interrupt-on-change. Individually enabled pull-up/pull-down.
ST — Timer1 gate.
OSC/4 reference clock.
interrupt-on-change. Individually enabled pull-up/pull-down.
OSC reference clock.
Description
PIC12F635/PIC16F636/639

TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS

Name Function
RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL — General purpose I/O. Individually controlled
C1IN+ AN — Comparator 1 input – positive.
ICSPDAT TTL CMOS Serial programming data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/C1IN-/V
RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled
RA3/MCLR
RA4/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/C2IN+ RC0 TTL CMOS General purpose I/O.
RC1/C2IN- RC1 TTL CMOS General purpose I/O.
RC2 RC2 TTL CMOS General purpose I/O. RC3 RC3 TTL CMOS General purpose I/O. RC4/C2OUT RC4 TTL CMOS General purpose I/O.
RC5 RC5 TTL CMOS General purpose I/O.
DD VDD D — Power supply for microcontroller.
V V
SS VSS D — Ground reference for microcontroller.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled
C1IN- AN — Comparator 1 input – negative.
REF AN — External voltage reference
V
ICSPCLK ST — Serial progra mm ing clock.
T0CKI ST — External clock for Timer0.
INT ST — External interrupt.
C1OUT — CMOS Comparator 1 output.
/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-change.
MCLR
V
/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
T1G
OSC2 — XTAL XTAL connection.
CLKOUT — CMOS T
T1CKI ST — Timer1 clock. OSC1 XTAL — XTAL connection.
CLKIN ST — T
C2IN+ AN — Comparator 1 input – positive.
C2IN- AN — Comparator 1 input – negative.
C2OUT — CMOS Comparator 2 output.
HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XT AL = Crystal
Input
Type
PP HV — Programming voltage.
Output
Type
interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.
interrupt-on-change. Individually enabled pull-up/pull-down.
interrupt-on-change. Individually enabled pull-up/pull-down.
ST — Mast er Clear Reset. Pull-up enabled when configured as MCLR.
Individually enabled pull-up/pull-down.
ST — Timer1 gate.
OSC/4 reference clock.
Individually enabled pull-up/pull-down.
OSC reference clock.
Description
© 2007 Microchip Technology Inc. DS41232D-page 13
PIC12F635/PIC16F636/639
TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS
Name Function
LCCOM LCCOM AN — Common reference for analog inputs. LCX LCX AN — 125 kHz analog X channel input. LCY LCY AN — 125 kHz analog Y channel input. LCZ LCZ AN — 125 kHz analog Z channel input. RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL — General purpose I/O. Individually controlled interrupt-on-change.
C1IN+ AN — Comparator1 input – positive.
ICSPDAT TTL CMOS Serial Programming Data IO.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/C1IN-/V
RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.
RA3/MCLR
RA4/T1G
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
RC0/C2IN+ RC0 TTL CMOS General purpose I/O.
RC1/C2IN-/CS
RC2/SCLK/ALERT
Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct
REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
C1IN- AN — Comparator1 input – negative.
REF AN — External voltage reference
V
ICSPCLK ST — Serial Programming Clock.
T0CKI ST — External clock for Timer0.
INT ST — External Interrupt.
C1OUT — CMOS Comparator1 output.
/VPP
/OSC2/CLKOUT
HV = High Voltage ST = Schmitt Trigger input with CMOS levels OD = Open Drain TTL = TTL compatible input XTAL = Crystal
RA3 TTL
MCLR
V
PP HV — Programming voltage.
RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
T1G
OSC2 — XTAL XTAL connection.
CLKOUT — CMOS T
T1CKI ST — Timer1 clock.
OSC1 XTAL — XTAL connection.
CLKIN ST — T
C2IN+ AN — Comparator1 input – positive.
RC1 TTL CMOS General purpose I/O.
C2IN- AN — Comparator1 input – negative.
CS
RC2 TTL CMOS General purpose I/O.
SCLK TTL — Digital clock input for SPI communication.
ALERT
Input
Type
Output
Type
Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.
Individually enabled pull-up/pull-down.
Individually enabled pull-up/pull-down.
General purpose input. Individually controlled
—
interrupt-on-change.
ST —
ST — Timer1 gate.
TTL — Chip select input for SPI communication with internal pull-up
— OD Output with internal pull-up resistor for AFE error signal.
Master Clear Reset. Pull-up enabled when configured as MCLR
Individually enabled pull-up/pull-down.
OSC reference clock.
Individually enabled pull-up/pull-down.
OSC/4 reference clock.
resistor.
Description
.
PIC12F635/PIC16F636/639
TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS (CONTINUED)
Name Function
RC3/LFDATA/RSSI/CCLK/SDO RC3 TTL CMOS General purpose I/O.
LFDATA — CMOS Digital output representation of analog input signal to LC pins.
RSSI — Current Received signal strength indicator. Analog current that is
CCLK — — Carrier clock output.
SDIO TTL CMOS Input/Output for SPI communication.
RC4/C2OUT RC4 TTL CMOS General purpose I/O.
C2OUT — CMOS Comparator2 output.
RC5 RC5 TTL CMOS General purpose I/O.
DDT VDDT D — Power supply for Analog Front-End. In this document, VDDT is
V
SST VSST D — Ground reference for Analog Front-End. In this document, VSST is
V
V
DD VDD D — Power supply for microcontroller. SS VSS D — Ground reference for microcontroller.
V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct
HV = High Voltage ST = Schmitt Trigger input with CMOS levels OD = Open Drain TTL = TTL compatible input XTAL = Crystal
Input
Type
Output
Type
Description
proportional to input amplitude.
treated the same as V
treated the same as V
DD, unless otherwise stated.
SS, unless otherwise stated.
© 2007 Microchip Technology Inc. DS41232D-page 15
PIC12F635/PIC16F636/639
NOTES:
PIC12F635/PIC16F636/639

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization
The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh, for the PIC12F635) and 2K x 14 (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs, implemented as static RAM for the PIC16F636/639. For the PIC12F635, reg ister locat ions 4 0h throug h 7Fh are GPRs implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. RP0 of the STATUS register is the bank select bit.
RP1
RP0
00→ Bank 0 is selected 01→ Bank 1 is selected 10→ Bank 2 is selected 11→ Bank 3 is selected
FIGURE 2-1: PROGRAM MEMOR Y M AP AND
STAC K OF THE PIC12F635
PC<12:0>
CALL, RETURN RETFIE, RETLW
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
Access 0-3FFh
13
0000h
0004h 0005h
03FFh 0400h
1FFFh
FIGURE 2-2: PROGRAM MEMORY MAP AND
ST AC K OF T HE PIC16F636/639
PC<12:0>
CALL, RETURN RETFIE, RETLW
Stack Level 1
13
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
Access 0-7FFh
© 2007 Microchip Technology Inc. DS41232D-page 17
0000h
0004h 0005h
07FFh 0800h
1FFFh
PIC12F635/PIC16F636/639
2.2.1 GENERAL PURPOSE REGISTER
The register file is organized as 64 x 8 for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select R egister, FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Figure 2-1). These registers are static RAM.
The special re gisters can be classifi ed into two sets: core and peripheral. The Special Function Registers associated with the “c ore” are des cribed in this sect ion. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
PIC12F635/PIC16F636/639

FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS

File File File File Address Address Address Address
Indirect addr.
(1)
00h Indirect addr.
TMR0 01h OPTION_REG 81h 101h 181h
PCL 02h PCL 82h 102h 182h
STATUS 03h STATUS 83h 103h 183h
FSR 04h FSR 84h 104h 184h
GPIO 05h TRISIO 85h 105h 185h
06h 86h 106h 186h 07h 87h 107h 187h 08h 88h 108h 188h
09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh
PIR1 0Ch PIE1 8Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh T1CON 10h OSCTUNE 90h CRCON 110h 190h
11h 91h CRDAT0 12h 92h CRDAT1 13h 93h CRDAT2 14h LVDCON 94h CRDAT3 15h WPUDA 95h 115h 195h 16h IOCA 96h 116h 196h 17h WDA 97h 117h 197h
WDTCON 18h
CMCON0 19h VRCON 99h 119h 199h CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah
1Bh EEADR 9Bh 11Bh 19Bh 1Ch EECON1 9Ch 11Ch 19Ch 1Dh EECON2 1Eh 9Eh 11Eh 19Eh 1Fh 9Fh 11Fh 19Fh 20h
(1)
80h Accesses
00h-0Bh
100h Accesses
80h-8Bh
10Ch 18Ch
10Fh 18Fh
(2)
111h 191h
(2)
112h 192h
(2)
113h 193h
(2)
114h 194h
98h 118h 198h
(1)
9Dh 11Dh 19Dh
A0h 120h 1A0h
180h
3Fh
General
40h Purpose Register
64 Bytes
Accesses
7Fh FFh 17Fh 1FFh
70h-7Fh
EFh 16Fh 1EFh F0h Accesses
70h-7Fh
170h Accesses
Bank 0
1F0h
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
®
2: CRDA T<3:0> registers are K
“K registers. T he “K
EELOQ
®
Encoder License Agreement” regarding implementation of the module and access to related
EELOQ
EELOQ
®
Encoder Lice nse Agre emen t” ma y be ac cess ed thr oug h the Micr ochi p web site
located at www .m ic roc hi p.c om /K
© 2007 Microchip Technology Inc. DS41232D-page 19
hardware peripheral rel ated registers and requ ire the execution of the
EELOQ or by contacting your local Microchip Sales Representative.
PIC12F635/PIC16F636/639

FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS

File File File File Address Address Address Address
Indirect addr.
(1)
00h Indirect addr.
TMR0 01h OPTION_REG 81h 101h 181h
PCL 02h PCL 82h 102h 182h
STATUS 03h ST ATUS 83h 103h 183h
FSR 04h FSR 84h 104h 184h
PORTA 05h TRISA 85h 105h 185h
06h 86h 106h 186h
PORTC 07h TRISC 87h 107h 187h
08h 88h 108h 188h
09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh
PIR1 0Ch PIE1 8Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h CRCON 110h
11h 91h CRDAT0
12h 92h CRDAT1
13h 93h CRDAT2
14h LVDCON 94h CRDAT3
15h WPUDA 95h 115h 195h
16h IOCA 96h 116h 196h
17h WDA 97h 117h 197h
WDTCON 18h 98h 118h 198h
CMCON0 19h VRCON 99h CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah
1Bh EEADR 9Bh 11Bh 19Bh
1Ch EECON1 9Ch 11Ch 19Ch
1Dh EECON2
1Eh 9Eh 11Eh 19Eh
1Fh 9Fh 11Fh 19Fh
General Purpose Register
96 Bytes
20h General
Purpose Register
32 Bytes
Accesses
7Fh FFh 17Fh 1FFh
70h-7Fh
Bank 0Bank 1Bank 2Bank 3
(1)
80h Accesses
00h-0Bh
100h Accesses
80h-8Bh
10Ch 18Ch
(2)
111h 191h
(2)
112h 192h
(2)
113h 193h
(2)
114h 194h
119h 199h
(1)
9Dh 11Dh 19Dh
A0h
120h 1A0h
BFh C0h
EFh 16Fh 1EFh F0h Accesses
70h-7Fh
170h Accesses
Bank 0
180h
190h
1F0h
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: CRDAT<3:0> registers are K
“K registers. T he “K
EELOQ
®
Encoder License Agreement” regarding implementation of the module and access to related
EELOQ
located at www.m ic roc hip.c om /K
EELOQ hardware peripheral rel ated reg is ters and require the execution o f the
®
Encoder License Agreement” may be accessed through the Microchip web site
EELOQ or by contacting your local Microchip Sales Representative.
PIC12F635/PIC16F636/639

TABLE 2-1: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory
01h TMR0 T imer0 Module Register xxxx xxxx 61,137 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 32,137 03h STATUS IRP RP1 RP0 TO 04h FSR Indirect Data Me mory Address Pointer xxxx xxxx 32,137 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 64,137 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 64,137
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, Note 1: Other (non Power-up) Resets include MCLR
2: MCLR
(not a physical register)
PD ZDC C0001 1xxx 26,137
— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xx00 47,137
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 32,137
EEIF LVDIF CRIF —C1IFOSFIF—TMR1IF000- 00-0
TMR1CS TMR1ON 0000 0000 68,137
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 144,137 —COUT— CINV CIS CM2 CM1 CM0 -0-0 0000 79,137 — — — — — — T1GSS CMSYNC ---- --10 82,137
shaded = unimplemente d
and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mis-
match exists.
Reset and Watchdog Timer Reset during normal operation.
Value on
POR/BOR/
WUR
xxxx xxxx 32,137
(2)
0000 000x
Page
28,137 30,137
© 2007 Microchip Technology Inc. DS41232D-page 21
PIC12F635/PIC16F636/639

TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr N a m e Bit 7 B i t 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0
Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000
83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE —C1IEOSFIE—TMR1IE000- 00-0 8Dh — Unimplemented — —
8Eh PCON 8Fh OSCCON — IRCF2 IRCF1 IRCF0 O STS HTS LTS SCS -110 q000 36,137 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 40,137 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT 9Bh EEADR 9Ch EECON1 9Dh EECON 2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---­9Eh — Unimplemented — — 9Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
Note 1: Other (non Power-up) Resets include MCLR
(2)
shaded = unimplemented
2: GP3 pull-up is enabled when pin is configured as MCLR
3: MCLR
again if the mismatch exists.
(not a physical register)
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000
— — ULPWUE SBOREN WUR —PORBOR --01 q-qq 31,137
(2)
— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -000 --00 -000 — — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 — — W DA5 WDA4 — WDA2WDA1WDA0--11 -111 --11 -111
—VRR—VR3VR2VR1VR00-0- 0000 0-0- 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
— — — — WRERR WREN W R RD ---- x000 ---- q000
Reset and Watchdog Timer Res et during normal operation.
in the Configuration Word register.
and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set
POR/BOR/
xxxx xxxx
(3)
0000 000x
Value on
Page
WUR
32,137
63,137 32,137 26,137 32,137
32,137 28,137
29,137
PIC12F635/PIC16F636/639

TABLE 2-3: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory
01h TMR0 Timer0 Module Register xxxx xxxx 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000
03h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xx00 48,137 06h — Unimplemented — — 07h PORTC 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 EEIF LVDIF CRIF C2IF C1IF OSFIF —TMR1IF0000 00-0 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 1Ah CMCON1 — — — — — — T1GSS C2SYNC ---- --10 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
Note 1: Other (non Power-up) Resets include MCLR
2: MCLR
(not a physical register)
— — RC5 RC4 RC3 RC2 RC1 RC0 --xx xx00 57,137
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000
shaded = unimplemented
Reset and Watchdog Timer Reset during normal operation.
and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
POR/BOR/
xxxx xxxx
(2)
0000 000x
Val ue on
Page
WUR
32,137
61,137 32,137
26,137 32,137
32,137 28,137 30,137
64,137 64,137
68,137
144,137
79,137 82,137
© 2007 Microchip Technology Inc. DS41232D-page 23
PIC12F635/PIC16F636/639

TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 82h PCL Pr ogram Count er’s (PC) Least Significant Byte 0000 0000
83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 86h — Unimplemented — — 87h TRISC 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE C2IE C1IE OSFIE —TMR1IE0000 00-0 8Dh — Unimplemented — —
8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDA T4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 9Ch EECON1 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---­9Eh — Unimplemented — — 9Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
Note 1: Other (non Power-up) Resets include MCLR
(2)
shaded = unimplemented
2: RA3 pull-up is enabled when pin is configured as MCLR
3: MCLR
again if the mismatch exists.
(not a physical register)
— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000
— — ULPWUE SBOREN WUR —PORBOR --01 q-qq --0u u-uu — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 x000 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
(2)
— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -000 --00 -000 — — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 — — WDA5 WDA4 — WDA2 WDA1 WDA 0 --11 -111 --11 -111
—VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
— — — — WRERR WREN WR RD ---- x000 ---- q000
Reset and Watchdog Timer Res et during normal operation.
in the Configuration Word register.
and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
POR/BOR/
xxxx xxxx
(3)
0000 000x
Value on
Page
WUR
32,137
63,137 32,137 26,137 32,137
32,137 28,137
29,137
PIC12F635/PIC16F636/639

TABLE 2-5: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 2 10Ch — Unimplemented — — 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplement ed — —
110h CRCON GO/DONE 111h CRDAT0 112h CRDAT1 113h CRDAT2 114h CRDAT3 115h — Unimplemented — — 116h — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
Note 1: Other (non Power-up) Resets include MCLR
2: CRDAT<3:0> registers are K
(2)
Cryptographic Data Register 0 0000 0000 0000 0000
(2)
Cryptographic Data Register 1 0000 0000 0000 0000
(2)
Cryptographic Data Register 2 0000 0000 0000 0000
(2)
Cryptographic Data Register 3 0000 0000 0000 0000
shaded = unimplemented
Encoder License Agreement” regarding implementation of the module and access to related registers. The “K Encoder License Agreement” may be accessed through the Microchip web site located at www.microchip.com/K or by contacting your local Microchip Sales Representative.
ENC/DEC — — — — CRREG1 CRREG0 00-- --00 00-- --00
Reset and Watchdog Timer Reset during normal operation.
hardware peripheral related registers and require the execution of the “KEELOQ
EELOQ
®
Value on
POR/BOR/
WUR
Page
EELOQ
EELOQ
© 2007 Microchip Technology Inc. DS41232D-page 25
PIC12F635/PIC16F636/639
2.2.2.1 STATUS Register
The STATUS register, shown i n Re gis t er2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (GPR and SFR)
The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destin ation may be di fferent than intended.
and PD bits are not
For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affect­ing any Status bit s , s ee Section13.0 “Instruction Set
Summary”
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in subtraction.
REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
(1)
(1)
C
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh)
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
bit 0 C: Carry/Borrow
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
(1)
(1)
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, t his bit i s loaded with eithe r the high -order or low -order bit of the source register.
PIC12F635/PIC16F636/639
2.2.2.2 OPTION Register
The OPTION register is a readable and writable register which contains various control bits to configure:
• TMR0/WDT prescaler
• External RA2/INT interrupt
•TMR0
• Weak pull-up/pull-downs on PORTA
REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION register to ‘1’. See Section 5.1.3 “Software Programmable Prescaler”.
bit 7 RAPU
: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on R A2/T0CKI pi n 0 = Internal instruction cycle clock (F
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 001 010 011 100 101 110 111
1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
OSC/4)
1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128
© 2007 Microchip Technology Inc. DS41232D-page 27
PIC12F635/PIC16F636/639
2.2.2.3 INTCON Register
The INTCON register is a readable and writable register which co nt ains th e vari ous e nable and fl ag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regard less of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RAIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts 0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enab le bit
1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt
bit 4 INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt
bit 3 RAIE: PORTA Change Interrupt Enable bit
1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow
bit 1 INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur
bit 0 RAIF: PORTA Change Interrupt Flag bit
1 = When at least one of the PORTA general purpose I/O pins changed state (must be cleared in
software)
0 = None of the PORTA general purpose I/O pins have changed state
(2)
(1,3)
(1,3)
T0IF
(2)
INTF RAIF
Note 1: IOCA register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
3: Includes ULPWU interrupt.
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