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Datasheet PIC12F609, PIC12F615, PIC12F617, PIC12HV609, PIC12HV615 Datasheet

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PIC12F609/615/617
PIC12HV609/615
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
2010 Microchip Technology Inc. DS41302D
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC
32
logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
PIC12F609/615/617/12HV609/615
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU:

• Only 35 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instru ction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable f requency: 4 M Hz or 8 MHz
• Power-Saving Sleep mode
• Vo ltage Range:
- PIC12F609/615/617: 2.0V to 5.5V
- PIC12HV609/615: 2.0V to user defined maximum (see note)
• Industrial and Extend ed Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR)
• Watchdog Timer (WDT) with independent Oscillator for Reliable Operation
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• High Endurance Flash:
- 100,000 write Flash endurance
- Flash retention: > 40 y ears
• Self Read/ Write Program Memory (PIC12F617 only)

Low-Power Features:

• Standby Current:
- 50 nA @ 2.0V, typical
• Operating Current:
-11A @ 32 kHz, 2.0V, typical
-260A @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
-1A @ 2.0V, typical Note: Voltage across the shunt regulator should
not exceed 5V.

Peripheral Features:

• Shunt Voltage Regulator (PIC12HV609/615 only):
- 5 volt regulation
- 4 mA to 50 mA shunt range
• 5 I/O Pins and 1 Input Only
• High Current Source/Sink for Direct LED Drive
- Interrupt-on-pin change or pins
- Individually programmable weak pull-ups
• Analog Compar ator module with:
- One analog comparator
- Programmable on-chip voltage reference (CV
REF) module (% of VDD)
- Comparator inputs and output externally accessible
- Built-In Hysteresis (software selectable)
• Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode selected
- Option to use system clock as Timer1
TM
• In-Circuit Serial Prog ram ming Pins
PIC12F615/617/HV615 ONLY:
• Enhanced Capture, Compare, PWM module:
- 16-bit Capture, max. resolution 12.5 ns
- Compare, max. resolution 200 ns
- 10-bit PWM with 1 or 2 output channels, 1
output channel programmable “dead time,” max. frequency 20 kHz, auto-shutdown
• A/D Converter:
- 10-bit resolution and 4 channels, samples
internal voltage references
• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler
(ICSPTM) via Two
2010 Microchip Technology Inc. DS41302D-page 3
PIC12F609/615/617/12HV609/615
1 2
3 4
5
6
7
8
PIC12F609/
HV609
V
SS
GP0/CIN+/ICSPDAT GP1/CIN0-/ICSPCLK GP2/T0CKI/INT/COUT
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/CIN1-/T1G
/OSC2/CLKOUT
GP3/MCLR
/VPP
Program
Device
PIC12F609 1024 64 PIC12HV609 1024 64 PIC12F615 1024 64 PIC12HV615 1024 64 PIC12F617 2048 128 YES 5 4 1 YES 2/1 2.0V-5.5V
Memory
Flash
(words)
Data Memory
SRAM (bytes)
Self Read/
Self Write
— — — —
— —
Timers
8/16-bit
1/1 2.0V-5.5V 1/1 2.0V-user defined
Volt age Range
10-bit A/D
I/O
(ch)
50 1 50 1 5 4 1 YES 2/1 2.0V-5.5V 5 4 1 YES 2/1 2.0V-user defined
Comparators ECCP

8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)

TABLE 1: PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
I/O Pin Comparators Timer Interrupts Pull-ups Basic
GP0 7 CIN+ — IOC Y ICSPDAT GP1 6 CIN0- — IOC Y ICSPCLK GP2 5 COUT T0CKI INT/IOC Y —
GP3
(1)
4—
—
IOC Y GP4 3 CIN1- T1G IOC Y OSC2/CLKOUT GP5 2 — T1CKI IOC Y OSC1/CLKIN
— 1 — — — — VDD —8— ——— VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR
.
(2)
MCLR/VPP
PIC12F609/615/617/12HV609/615
1 2
3 4
5
6
7
8
PIC12F615/
617/HV615
V
SS
GP0/AN0/CIN+/P1B/ICSPDA T GP1/AN1/CIN0- /V
REF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
VDD
GP5/T1CKI/P1A*/OSC1/CLKIN
GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT
GP3/T1G
*/MCLR/VPP
* Alternate pin function.

8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)

T ABLE 2: PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
I/O Pin Analog
GP0 7 AN0 CIN+ — P1B IOC Y ICSPDAT GP1 6 AN1 CIN0- — — IOC Y ICSPCLK/V GP2 5 AN2 COUT T0CKI CCP1/P1A INT/IOC Y —
(1)
GP3 GP4 3 AN3 CIN1- T1G P1B* IOC Y OSC2/CLKOUT GP5 2 — — T1CKI P1A* IOC Y OSC1/CLKIN
— 1 — — — — — — VDD —8 — — — — — — VSS
Note 1: Input only.
4— — T1G*— IOCY
* Alternate pin function.
2: Only when pin is configured for external MCLR.
Comparator
s
Timer CCP Interrupts Pull-ups Basic
(2)
MCLR/VPP
REF
2010 Microchip Technology Inc. DS41302D-page 5
PIC12F609/615/617/12HV609/615
Table of Contents
1.0 Device Overview .........................................................................................................................................................................7
2.0 Memory Organization..................................................................................................................................... ........................... 11
3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................................................................................. 27
4.0 Oscillator Module .......................................................................................................................................................................37
5.0 I/O Port ...................................................................................................................................................................................... 43
6.0 Timer0 Module .......................................................................................................................................................................... 53
7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57
8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65
9.0 Comparator Module ................................................................................................................................................................... 67
10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) ...............................................................................79
11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ............... 89
12.0 Special Features of the CPU ........................................ ......................... ......................... ......................................................... 107
13.0 Voltage Regulator .................................................................................................................................................................... 127
14.0 Instruction Set Summ a ry ............................................. ............. ......................... ............ .........................................................129
15.0 Development Support ................................................................... .... .. .... .. ......... .. .... .. .... ......................................................... 139
16.0 Electrical Specifications ........................................................................................................................................................... 143
17.0 DC and AC Characteristics Graphs and Tables ......................................................................................................................171
18.0 Packaging Information ............................ ............. ............ ............. ......................... ................................................................. 195
Appendix A: Data Sheet Revision History ......................................................................................................................................... 203
Appendix B: Migrating from other PIC
Index ..................................................................... .. .. ....... .. .... .. .. .. .... ..... .. .... .. .. .. .... ............................................................................ 205
The Microchip Web Site .............................................. ............. ............. ............ ................................................................................209
Customer Change Notification Service .............................................................................................................................................209
Customer Support .............................................................................................................................................................................209
Reader Response .............................................................................................................................................................................210
Product Identification System ............................................................................................................................................................211
Worldwide Sales and Service ................ .......................... ......................... ......................... ............................................................... 212
®
Devices ................ ............ ............. ......................... ......................... .......................... .......... 203
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best docum entation possible to ensure s ucce ssf ul use of y our M icrochip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

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PIC12F609/615/617/12HV609/615
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
GPIO
8
8
8
3
8-Level Stack
64 Bytes
1K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR
VSS
Brown-out
Reset
Timer0 Timer1
GP0 GP1 GP2 GP3 GP4 GP5
Analog Comparator
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
and Reference
T1G
VDD
Block
CIN+
CIN0-
CIN1-
COUT
Comparator Voltage Reference
Absolute Voltage Reference
Shunt Regulator
(PIC12HV609 only)

1.0 DEVICE OVERVIEW

The PIC12F609/615/617/12HV609/615 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC, MSOP and DFN packages.

FIGURE 1-1: PIC12F609/HV609 BLOCK DIAGRAM

Block Diagrams and pinout descriptions of the devices are as follows:
• PIC12F609/HV609 (Figure 1-1, Table 1-1)
• PIC12F615/617/HV615 (Figure 1-2, Table 1-2)
2010 Microchip Technology Inc. DS41302D-page 7
PIC12F609/615/617/12HV609/615
Flash
Program Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
GPIO
8
8
8
3
8-Level Stack
64 Bytes and
1K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR
VSS
Brown-out
Reset
Timer0 Timer1
GP0 GP1 GP2 GP3 GP4 GP5
Analog Comparator
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
VREF
and Reference
T1G
VDD
Timer2
Block
Shunt Regulator
(PIC12HV615 only)
Analog-To-Digital Converter
AN0
AN1
AN2
AN3
CIN+
CIN0-
CIN1-
COUT
ECCP
CCP1/P1A
P1B
P1A*
P1B*
Comparator Voltage Reference
Absolute Voltage Reference
* Alternate pin function. ** For the PIC12F617 only.
T1G*
2K X 14**
and
128 Bytes**

FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM

PIC12F609/615/617/12HV609/615

T ABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION

Name Function
GP0/CIN+/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN+ AN — Comparator non-inverting input
ICSPDAT ST CMOS Serial Programming Data I/O
GP1/CIN0-/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN0- AN — Comparator inverting input
ICSPCLK ST — Serial Programming Clock
GP2/T0CKI/INT/COUT GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-change
T0CKI ST — Timer0 clock input
INT ST — External Interrupt
COUT — CMOS Comparator output
GP3/MCLR
GP4/CIN1-/T1G CLKOUT
GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
DD VDD Power — Positive supply
V
SS VSS Power — Ground reference
V Legend: AN=Analog input or output CMOS= CMOS compatible input or output HV= High Voltage
/VPP GP3 TTL — General purpose input with interrupt-on-change
MCLR
PP HV — Programming voltage
V
/OSC2/
ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL=Crystal
GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN1-
T1G
OSC2 — XTAL Crystal/Resonator
CLKOUT — CMOS F
T1CKI ST — Timer1 clock input OSC1 XTAL — Crystal/Resonator
CLKIN ST — External clock input/RC oscillator connection
Input
Type
Output
Type
ST — Master Clear w/internal pull-up
AN — Comparator inverting input ST — Timer1 gate (count enable)
OSC/4 output
Description
2010 Microchip Technology Inc. DS41302D-page 9
PIC12F609/615/617/12HV609/615

TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION

Name Function
GP0/AN0/CIN+/P1B/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
AN0 AN — A/D Channel 0 input
CIN+ AN — Comparator non-inverting input
P1B — CMOS PWM output
ICSPDAT ST CMOS Serial Programming Data I/O
GP1/AN1/CIN0-/V
GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A
GP3/T1G
GP4/AN3/CIN1-/T1G CLKOUT
GP5/T1CKI/P1A*/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
V V
Legend: AN=Analog input or output CMOS= C MO S com patible input or output HV= High Voltage
*/MCLR/VPP GP3 TTL — General purpose input with interrupt-on-change
DD VDD Power — Positive supply SS VSS Power — Ground reference
* Alternate pin function.
REF/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
AN1 AN — A/D Channel 1 input
CIN0- AN — Comparator inverting input
REF AN — External Voltage Reference for A/D
V
ICSPCLK ST — Serial Programming Clock
GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-
AN2 AN — A/D Channel 2 input
T0CKI ST — Timer0 clock input
INT ST — External Interrupt COUT — CMOS Comparator output CCP1 ST CMOS Capture input/Compare input/PWM output
P1A — CMOS PWM output
T1G
MCLR
V
PP HV — Programming voltage
/P1B*/OSC2/
ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL=Crystal
GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
AN3 AN — A/D Channel 3 input
CIN1-
T1G
P1B* — CMOS PWM output, alternate pin
OSC2 — XTAL Crystal/Resonator
CLKOUT — CMOS F
T1CKI ST — Timer1 clock input
P1A* — CMOS PWM output, alternate pin OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection
Input
Type
* ST — Timer1 gate (count enable), alternate pin
Output
Type
change
change
change
ST — Master Clear w/internal pull-up
change
AN — Comparator inverting input ST — Timer1 gate (count enable)
OSC/4 output
change
Description
PIC12F609/615/617/12HV609/615
PC<12:0>
13
0000h
0004h 0005h
03FFh 0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN RETFIE, RETLW
Stack Level 2
Wraps to 0000h-03FFh
PC<12:0>
13
0000h
0004h 0005h
07FFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN RETFIE, RETLW
Stack Level 2
Page 0
On-Chip
Program
Memory
Wraps to 0000h-07FFh
0800h 1FFFh

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F609/615/617/12HV609/615 has a 13-bit program counter capable of addressing an 8K x 14 program memory spa ce. Only the first 1K x 14 (0000h­03FFh) for the PIC12F609/615/12HV609/615 is physically implemented. For the PIC12F617, the first 2K x 14 (0000h-07FFh) is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space for PIC12F609/615/12HV609/615 devices, and within the first 2K x 14 space for the PIC12F617 device. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE PIC12F609/615/12HV609/615
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE PIC12F617

2.2 Data Memory Organization

The data memory (see Figure 2-3) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. For the PIC12F617, the register locations 20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general purpose registers implemented as S tatic RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. The RP0 bit of the STATUS register is the bank select bit.
RP0
0 Bank 0 is selected 1 Bank 1 is selected
Note: The IRP and RP1 bits of the STATUS
register are reserved and should always be maintained as ‘0’s.
2010 Microchip Technology Inc. DS41302D-page 11
PIC12F609/615/617/12HV609/615
Indirect Addr.
(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH INTCON
PIR1
TMR1L
TMR1H
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
7Fh
Bank 0
Unimplemented data memory locations, rea d as ‘0’.
Note 1: Not a physical register.
General
File
Address
File
Address
WPU
IOC
Indirect Addr.
(1)
OPTION_REG
PCL
STAT US
FSR
TRISIO
PCLATH INTCON
PIE1
PCON
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
A0h
FFh
Bank 1
ANSEL
Accesses 70h-7Fh
F0h
VRCON
CMCON0
OSCTUNE
40h
3Fh
CMCON1
EFh
T1CON
Purpose
Registers
64 Bytes
Accesses 70h-7Fh
6Fh 70h

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file is organized as 64 x 8 in the PIC12F609/615/12HV609/615, and as 128 x 8 in the PIC12F617. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM.
The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
FIGURE 2-3: DATA MEMORY MAP OF
THE PIC12F609/HV609
PIC12F609/615/617/12HV609/615
Indirect Addr.
(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L TMR1H T1CON
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
7Fh
Bank 0
Unimplemented data memory locations, rea d as ‘0’.
Note 1: Not a physical register.
2: Used for the PIC12F617 only.
File
Address
File
Address
WPU
IOC
Indirect Addr.
(1)
OPTION_REG
PCL
STAT US
FSR
TRISIO
PCLATH INTCON
PIE1
PCON
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
A0h
FFh
Bank 1
ADRESH ADCON0
ADRESL
ANSEL
Accesses 70h-7Fh
F0h
TMR2
T2CON
CCPR1L CCPR1H
CCP1CON
PWM1CON
ECCPAS
VRCON
CMCON0
OSCTUNE
PR2
40h
3Fh
CMCON1
EFh
APFCON
General Purpose
Registers
64 Bytes
Accesses 70h-7Fh
6Fh 70h
PMCON1
(2)
PMCON2
(2)
PMADRL
(2)
PMADRH
(2)
PMDATL
(2)
PMDATH
(2)
General
Purpose
Registers
96 Bytes from
20h-7Fh
(2)
Unimplemented for PIC12F615/HV615
General
Purpose
Registers
32 Bytes
(2)
Unimplemented for
PIC12F615/HV615
BFh
C0h
FIGURE 2-4: DATA MEMORY MAP OF
THE PIC12F615/617/HV615
2010 Microchip Technology Inc. DS41302D-page 13
PIC12F609/615/617/12HV609/615
TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 115 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 115 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 115 03h STA TUS IRP 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 115 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 115 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h VRCON CMVREN 1Ah CMCON0 CMON COUT CMOE CMPOL 1Bh — — — — — 1Ch CMCON1 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —
Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: Read only register.
(1)
— — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 115
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 115
— — — —CMIF— —TMR1IF---- 0--0 22, 115
— — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 73, 116
(1)
RP1
— VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116
RP0 TO PD ZDCC0001 1xxx 18, 115
TMR1CS TMR1ON 0000 0000 62, 115
—CMR—CMCH0000 -0-0 72, 116
Value on
POR, BOR
Page
PIC12F609/615/617/12HV609/615
TABLE 2-2: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 116 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116 03h STA TUS IRP 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 116 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h TMR2 12h T2CON 13h CCPR1L 14h CCPR1H 15h 16h
17h ECCPAS
18h — Unimplemented — — 19h VRCON CMVREN 1Ah CMCON0 CMON COUT CMOE CMPOL 1Bh — — — — — 1Ch CMCON1 1Dh — Unimplemented — — 1Eh 1Fh ADCON0
Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
(3)
(3)
(3) (3)
CCP1CON PWM1CON
ADRESH
2: Read only register. 3: PIC12F615/617/HV615 only.
(3)
(3)
(3)
(2, 3)
(3)
(1)
— — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 116
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116
— ADIF CCP1IF —CMIF—TMR2IFTMR1IF-00- 0-00 22, 116
Timer2 Module Register 0000 0000 65, 116
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 66, 116 Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 90, 116 Capture/Compare/PWM Register 1 High Byte XXXX XXXX 90, 116
P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 89, 116
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 105,
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 102,
— — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 73, 116
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 85, 116
ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 84, 116
(1)
RP1
— VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116
RP0 TO PD ZDCC0001 1xxx 18, 116
TMR1CS TMR1ON 0000 0000 62, 116
—CMR—CMCH0000 -0-0 72, 116
Value on
POR, BOR
Page
116
116
2010 Microchip Technology Inc. DS41302D-page 15
PIC12F609/615/617/12HV609/615
TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 81h OPTION_RE
G 82h PCL Pro gr am Coun ter’s (PC) Least Significant Byte 0000 0000 25, 116 83h STATUS IRP 84h FSR Indirect Dat a Memory Address Pointer xxxx xxxx 25, 116 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 8Ch PIE1 8Dh — Unimplemented — — 8Eh PCON 8Fh — Unimplemented — — 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU 96h IOC 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ANSEL
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
(2)
2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: MCLR
exists.
4: TRISIO3 always reads as ‘1’ since it is an input only pin.
GPPU
— — TRISIO5 TRISIO4 TRISIO3
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116
— — — —CMIE— —TMR1IE---- 0--0 21, 116
— — — — — —PORBOR ---- --qq 23, 116
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116
— —WPU5WPU4— WPU2 WPU1 WPU0 --11 -111 46, 116 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116
— — — —ANS3— ANS1 ANS0 ---- 1-11 45, 117
and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
INTEDG T0CS
(1)
RP1
(1)
RP0 TO PD ZDCC0001 1xxx 18, 116
T0SE PSA PS2 PS1 PS0 1111 1111 19, 116
(4)
TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116
Value on
POR, BOR
(3)
0000 0000 20, 116
Page
PIC12F609/615/617/12HV609/615
T ABLE 2-4: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 81h OPTION_REG GPPU 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116 83h STATUS IRP 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 8Ch PIE1 8Dh — Unimplemented — — 8Eh PCON 8Fh — Unimplemented — — 90h OSCTUNE 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 65, 116 93h APFCON 94h — Unimplemented — — 95h WPU 96h IOC 97h — Unimplemented — — 98h PMCON1 99h PMCON2 9Ah PMADRL 9Bh PMADRH 9Ch PMDATL 9Dh PMDATH 9Eh ADRESL 9Fh ANSEL
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
(2)
(7) (7)
Program Memory Control Register 2 (not a physical register). ---- ---- —
(7)
PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 28
(7)
(7)
PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 28
(7)
(5, 6)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 85, 117
2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: MCLR
4: TRISIO3 always reads as ‘1’ since it is an input only pin. 5: Read only register. 6: PIC12F615/617/ H V6 15 onl y. 7: PIC12F617 only.
and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116
(1)
— — TRISIO5 TRISIO4 TRISIO3
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116
— ADIE CCP1IE —CMIE— TMR2IE TMR1IE -00- 0-00 21, 116
— — — — — —PORBOR ---- --qq 23, 116
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116
— — — T1GSEL — — P1BSEL P1ASEL ---0 --00 21, 116
— —WPU5WPU4 — WPU2 WPU1 WPU0 --11 -111 46, 116 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116
— — — — — WREN WR RD ---- -000 29
— — — — — PMADRH2 PMADRH1 PMADRH0 ---- -000 28
— — Pr ogr am Memo ry Data Regis ter H igh By te. --00 0000 28
— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 45, 117
RP1
(1)
RP0 TO PD ZDCC0001 1xxx 18, 116
(4)
TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116
Value on
POR, BOR
(3)
0000 0000 20, 116
Page
2010 Microchip Technology Inc. DS41302D-page 17
PIC12F609/615/617/12HV609/615
2.2.2.1 STATUS Register
The STATUS registe r, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (RAM) The STATUS register can be the destination for any
instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as des tination may be different than intended.
For example, CLRF STATUS, will clea r the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).
and PD bits are not
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 14.0
“Instruction Set Summary”.
Note 1: Bits IRP and RP1 of the STATUS register
are not used by the PIC12F609/615/617/ 12HV609/615 and should be maintained as clear. Use of these bits is not recom­mended, since this may affect upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respe ctively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1: STATUS: STATUS REGISTER
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h – FFh) 0 = Bank 0 (00h – 7Fh)
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Borrow
bit 0 C: Carry/Borrow
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is
reversed.
1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow
second operand. For rotate (RRF, RLF) instructi ons, this bit is loaded with either the high-orde r or low-o rder bit of the source register.
, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
PIC12F609/615/617/12HV609/615
000 001 010 011 100 101 110 111
1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128
BIT VALUE TIMER0 RATE WDT RATE
2.2.2.2 OPTION Register
The OPTION register is a readable and writable register, which contains various control bits to configure:
• Timer0/WDT prescaler
• External GP2/INT interrupt
•Timer0
• Weak pull-ups on GPIO
REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
INTEDG T0CS T0SE PSA PS2 PS1 PS0
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 6.1.3 “Software Programmable Prescaler”.
bit 7 GPPU
: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin 0 = Internal in struction cycle clock (F
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transit ion on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
OSC/4)
2010 Microchip Technology Inc. DS41302D-page 19
PIC12F609/615/617/12HV609/615
2.2.2.3 INTCON Register
The INTCON register is a readable and writable register , which c ontains the various en able and fl ag bits for TMR0 register ove rflo w, GPIO change and external GP2/INT pin interrupts.
Note: Interrupt flag bits are set w hen an in terrupt
condition occurs, regar dless of the st ate of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts 0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interru pt Enab le bit
1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt
bit 4 INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt
bit 3 GPIE: GPIO Change Interrupt Enable bit
1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit
1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow
bit 1 INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur
bit 0 GPIF: GPIO Change Interrupt Flag bit
1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software) 0 = None of the GPIO <5:0> pins have changed state
(1)
(2)
Note 1: IOC register must also be enabled.
2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
PIC12F609/615/617/12HV609/615
2.2.2.4 PI E1 Register
The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register2-4.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
—ADIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt 0 = Disables the ADC interrupt
bit 5 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt
bit 4 Unimplemented: Read as ‘0’ bit 3 CMIE: Compara tor Interrupt Enable bit
1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt
bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
(1)
CCP1IE
(1)
—CMIE —TMR2IE
(1)
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
(1)
(1)
(1)
TMR1IE
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
2010 Microchip Technology Inc. DS41302D-page 21
PIC12F609/615/617/12HV609/615
2.2.2.5 PIR1 Register
The PIR1 register cont ain s the P eriphera l Interr upt flag bits, as shown in Register 2-5.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
—ADIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started
bit 5 CCP1IF: CCP1 Interrupt Flag bit
Capture mod e:
1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred
Compare mode
1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed (must be cleared in software)
0 = Comparator output has not changed
bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match has not occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 register overflowed (must be cleared in software)
0 = Timer1 has not overflowed
(1)
CCP1IF
:
:
(1)
—CMIF —TMR2IF
(1)
(1)
Note: Interrupt flag bi ts are set when an interrupt
condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt f lag bits ar e cle ar prior to enabling an interrupt.
(1)
(1)
TMR1IF
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
PIC12F609/615/617/12HV609/615
2.2.2.6 PCON Regi st er
The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a:
• Power-on Reset (POR
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR The PCON register also contro ls the software enabl e of
the BOR The PCON register bits are shown in Register 2-6.
.
REGISTER 2-6: PCON: POWER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — —PORBOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
)
Reset
(1)
bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR
bit 0 BOR
Note 1: Reads as ‘0’ if Brown-out Reset is disabled.
: Power-on Reset Status bit
1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
2010 Microchip Technology Inc. DS41302D-page 23
PIC12F609/615/617/12HV609/615
2.2.2.7 APFCON Register (PIC12F615/617/HV615 only)
The Alternate Pin Function Control (APFC ON) reg ister is used to steer specific peripheral input and output functions between different pins. For this device, the P1A, P1B and Timer1 Gate functions can be moved between different pins.
The APFCON register bits are shown in Register 2-7.
REGISTER 2-7: APFCON:ALTERNATE PIN FUNCTION REGISTER
U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
— — — T1GSEL — — P1BSEL P1ASEL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1GSEL: TMR1 Input Pin Select bit
1 = T1G function is on GP3/T1G 0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B
bit 3-2 Unimplemented: Read as ‘0’ bit 1 P1BSEL: P1B Output Pin Select bit
1 = P1B function is on GP4/AN3/CIN1-/T1G 0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT
bit 0 P1ASEL: P1A Output Pin Select bit
1 = P1A function is on GP5/T1CKI/P1A 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
(2)
/MCLR/VPP
(2)
(2)
/OSC2/CLKOUT
(2)
/P1B
/OSC2/CLKOUT
/OSC1/CLKIN
(1)
Note 1: PIC12F615/617/HV615 only.
2: Alternate pin function.
PIC12F609/615/617/12HV609/615
PC
12 8 7 0
5
PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
OPCODE <10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
MOVLW 0x40 ;initialize pointer MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer BTFSS FSR,7 ;all done? GOTO NEXT ;no clear next
CONTINUE ;yes continue

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The lo w byte comes from the PCL register, which is a readable and writable register . The hig h byte (PC<12:8>) is not directl y readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS

2.3.2 STACK

The PIC12F609/615/617/12HV609/615 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the S ta ck Pointer i s not rea dable or writa ble. The PC is PUSHed onto the stack when a CALL instruction is execute d or an interrupt ca uses a branc h. The stack is POPed in the even t of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
The stack operat es as a circular buf fer . This means th at after the st ack ha s been PUSHed eight time s, th e nin th push overwrites th e valu e that was s tore d from the firs t push. The tenth pus h ov erwr i tes the se co nd push (and so on).
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

2.4 Indirect Addressing, INDF and FSR Registers

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This a llow s the entire contents of the program counter to be changed by writing the desired up per 5 bit s to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.
A computed GOTO is accomplish ed by adding an of fs et to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program b ranch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table.
For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556).
The INDF register is not a physica l register . Addr essing the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-6.
A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIR ECT ADDRES SING

2010 Microchip Technology Inc. DS41302D-page 25
PIC12F609/615/617/12HV609/615
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
2: Accesses in this area are mirrored back into Bank 0 and Bank 1.
Data Memory
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1
(1)
RP0 6
0
From Opcode
IRP
(1)
File Select Register
7
0
Bank Select
Location Select
00 01 10 11
180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
NOT USED
(2)
For memory map detail, see Figure 2-3.

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615

PIC12F609/615/617/12HV609/615

3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY)

The Flash program memory is readable and writable during normal operation (full V is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5). There are six SFRs used to read and write this memory:
•PMCON1
•PMCON2
•PMDATL
•PMDATH
• PMADRL
• PMADRH
When interfacing the program memory block, the PMDA T L and PMDATH registers form a two-byte word which holds the 14-bit data for read/write, and the PMADRL and PMADRH registers form a two-byte word which holds the 13-bit address of the Flash loca­tion being accessed. These devices have 2K words of program Flash with an address range from 0000h to 07FFh.
The program memory allows single word read and a by four word write. A four word write automatically erases the row of the location and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump r ated to oper ate over the vo ltage range of the device for byte or word operations.
When the device is code-protected, the CPU may continue to read and write the Flash program memory.
Depending on the settings of the Flash Program Memory Enable (WRT<1:0>) bits, the device may or may not be able to write certain blocks of the program memory, however, reads of the prog ram memory are allowed.
When the Flash program memory Code Protection
) bit in the Configuration Word register is enabled,
(CP the program memory is code-protected, and the device programmer (ICSP™) cannot access data or program memory.
DD range). This memory

3.1 PMADRH and PMADRL Registers

The PMADRH and PMADRL registers can address up to a maximum of 8K words of program memory.
When selecting a program address value, the Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register.

3.2 PMCON1 and PMCON2 Registers

PMCON1 is th e control regi ster for the da ta program memory accesses.
Control bits RD and WR initiate read and write, respectiv ely. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation.
The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear.
PMCON2 is not a physical regis ter. Reading PMCON2 will read all ‘0’s. The PMCON2 register is used exclusively in the Flash memory write sequence.
2010 Microchip Technology Inc. DS41302D-page 27
PIC12F609/615/617/12HV609/615

REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMDATL7 PM DATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PMDATL<7:0>: 8 Least Significant Address bits to Write or Read from Program Memory

REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation

REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDATH<5:0>: 6 Most Significant Data bits from Program Memory

REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PMADRH2 PMADRH1 PMA DRH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 3 Unimplemented: Read as ‘0’ bit 2-0 PMADRH<2:0>: Specifies the 3 Most Significant Address bits or high bits for program memory reads.
PIC12F609/615/617/12HV609/615

REGISTER 3-5: PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h)

U-1 U-0 U-0 U-0 U-0 R/W-0 R/S-0 R/S-0
— — — — —WRENWR RD
bit 7 bit 0
bit 7 Unimplemented: Read as ‘1’ bit 6-3 Unimplemented: Read as ‘0’ bit 2 WREN: Program Memory Write Enable bit
1 = Allows write cycles 0 = Inhibits write to the EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle to program memory. (The bit is cleared by hard w are whe n w rit e is co mplete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle to the Flash memory is complete
bit 0 RD: Read Control bit
1 = Initiates a program memory read (The read t ak es on e cycle. The RD is c lea red i n h ard w are; th e RD bi t
can only be set (not cleared) in software).
0 = Does not initiate a Flash memory read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
2010 Microchip Technology Inc. DS41302D-page 29
PIC12F609/615/617/12HV609/615
BANKSEL PM_ADR ; Change STATUS bits RP1:0 to select bank with PMADRL MOVLW MS_PROG_PM_ADDR ; MOVWF PMADRH ; MS Byte of Program Address to read MOVLW LS_PROG_PM_ADDR ; MOVWF PMADRL ; LS Byte of Program Address to read BANKSEL PMCON1 ; Bank to containing PMCON1 BSF PMCON1, RD ; PM Read
NOP ; First instruction after BSF PMCON1,RD executes normally
NOP ; Any instructions here are ignored as program
; memory is read in second cycle after BSF PMCON1,RD
; BANKSEL PMDATL ; Bank to containing PMADRL MOVF PMDATL, W ; W = LS Byte of Program PMDATL MOVF PMDATH, W ; W = MS Byte of Program PMDATL

3.3 Reading the Flash Program Memory

To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memo ry Flash con troller wi ll use the s econd instruction cycle af te r to read the dat a. Thi s caus es the second instruction immediately following the “
PMCON1,RD
” instruction to be ignored. The data is available in the very next cycle in the PMDATL and PMDATH registers; it can be read as two bytes in the following instructions. PMDATL and PMDATH regis­ters will hold this value until another read or until it is written to by the user (during a write operation).

EXAMPLE 3-1: FLASH PROGRAM READ

BSF
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