Datasheet PIC12F609, PIC12F615, PIC12F617, PIC12HV609, PIC12HV615 Datasheet

PIC12F609/615/617

PIC12HV609/615

Data Sheet

8-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.

 2010 Microchip Technology Inc. DS41302D

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC

logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

DS41302D-page 2  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU:

• Only 35 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instru ction cycle

• Interrupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable f requency: 4 M Hz or 8 MHz

• Power-Saving Sleep mode

• Vo ltage Range:

- PIC12F609/615/617: 2.0V to 5.5V

- PIC12HV609/615: 2.0V to user defined maximum (see note)

• Industrial and Extend ed Temperature Range

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Reset (BOR)

• Watchdog Timer (WDT) with independent Oscillator for Reliable Operation

• Multiplexed Master Clear with Pull-up/Input Pin

• Programmable Code Protection

• High Endurance Flash:

- 100,000 write Flash endurance

- Flash retention: > 40 y ears

• Self Read/ Write Program Memory (PIC12F617 only)

Low-Power Features:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operating Current:

-11A @ 32 kHz, 2.0V, typical

-260A @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

-1A @ 2.0V, typical Note: Voltage across the shunt regulator should

not exceed 5V.

Peripheral Features:

• Shunt Voltage Regulator (PIC12HV609/615 only):

- 5 volt regulation

- 4 mA to 50 mA shunt range

• 5 I/O Pins and 1 Input Only

• High Current Source/Sink for Direct LED Drive

- Interrupt-on-pin change or pins

- Individually programmable weak pull-ups

• Analog Compar ator module with:

- One analog comparator

- Programmable on-chip voltage reference (CV

REF) module (% of VDD)

- Comparator inputs and output externally accessible

- Built-In Hysteresis (software selectable)

• Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Gate (count enable)

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode selected

- Option to use system clock as Timer1

• In-Circuit Serial Prog ram ming Pins

PIC12F615/617/HV615 ONLY:

• Enhanced Capture, Compare, PWM module:

- 16-bit Capture, max. resolution 12.5 ns

- Compare, max. resolution 200 ns

- 10-bit PWM with 1 or 2 output channels, 1

output channel programmable “dead time,” max. frequency 20 kHz, auto-shutdown

• A/D Converter:

- 10-bit resolution and 4 channels, samples

internal voltage references

• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

(ICSPTM) via Two

 2010 Microchip Technology Inc. DS41302D-page 3

PIC12F609/615/617/12HV609/615

1 2

3 4

PIC12F609/

HV609

GP0/CIN+/ICSPDAT GP1/CIN0-/ICSPCLK GP2/T0CKI/INT/COUT

VDD

GP5/T1CKI/OSC1/CLKIN

GP4/CIN1-/T1G

/OSC2/CLKOUT

GP3/MCLR

/VPP

Program

Device

PIC12F609 1024 64 PIC12HV609 1024 64 PIC12F615 1024 64 PIC12HV615 1024 64 PIC12F617 2048 128 YES 5 4 1 YES 2/1 2.0V-5.5V

Memory

Flash

(words)

Data Memory

SRAM (bytes)

Self Read/

Self Write

— — — —

— —

Timers

8/16-bit

1/1 2.0V-5.5V 1/1 2.0V-user defined

Volt age Range

10-bit A/D

I/O

(ch)

50 1 50 1 5 4 1 YES 2/1 2.0V-5.5V 5 4 1 YES 2/1 2.0V-user defined

Comparators ECCP

8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)

TABLE 1: PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)

I/O Pin Comparators Timer Interrupts Pull-ups Basic

GP0 7 CIN+ — IOC Y ICSPDAT GP1 6 CIN0- — IOC Y ICSPCLK GP2 5 COUT T0CKI INT/IOC Y —

GP3

(1)

4—

—

IOC Y GP4 3 CIN1- T1G IOC Y OSC2/CLKOUT GP5 2 — T1CKI IOC Y OSC1/CLKIN

— 1 — — — — VDD —8— ——— VSS

Note 1: Input only.

2: Only when pin is configured for external MCLR

(2)

MCLR/VPP

DS41302D-page 4  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

1 2

3 4

PIC12F615/

617/HV615

GP0/AN0/CIN+/P1B/ICSPDA T GP1/AN1/CIN0- /V

REF/ICSPCLK

GP2/AN2/T0CKI/INT/COUT/CCP1/P1A

VDD

GP5/T1CKI/P1A*/OSC1/CLKIN

GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT

GP3/T1G

*/MCLR/VPP

* Alternate pin function.

8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)

T ABLE 2: PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)

I/O Pin Analog

GP0 7 AN0 CIN+ — P1B IOC Y ICSPDAT GP1 6 AN1 CIN0- — — IOC Y ICSPCLK/V GP2 5 AN2 COUT T0CKI CCP1/P1A INT/IOC Y —

(1)

GP3 GP4 3 AN3 CIN1- T1G P1B* IOC Y OSC2/CLKOUT GP5 2 — — T1CKI P1A* IOC Y OSC1/CLKIN

— 1 — — — — — — VDD —8 — — — — — — VSS

Note 1: Input only.

4— — T1G*— IOCY

* Alternate pin function.

2: Only when pin is configured for external MCLR.

Comparator

Timer CCP Interrupts Pull-ups Basic

(2)

MCLR/VPP

REF

 2010 Microchip Technology Inc. DS41302D-page 5

PIC12F609/615/617/12HV609/615

Table of Contents

1.0 Device Overview .........................................................................................................................................................................7

2.0 Memory Organization..................................................................................................................................... ........................... 11

3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................................................................................. 27

4.0 Oscillator Module .......................................................................................................................................................................37

5.0 I/O Port ...................................................................................................................................................................................... 43

6.0 Timer0 Module .......................................................................................................................................................................... 53

7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57

8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65

9.0 Comparator Module ................................................................................................................................................................... 67

10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) ...............................................................................79

11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ............... 89

12.0 Special Features of the CPU ........................................ ......................... ......................... ......................................................... 107

13.0 Voltage Regulator .................................................................................................................................................................... 127

14.0 Instruction Set Summ a ry ............................................. ............. ......................... ............ .........................................................129

15.0 Development Support ................................................................... .... .. .... .. ......... .. .... .. .... ......................................................... 139

16.0 Electrical Specifications ........................................................................................................................................................... 143

17.0 DC and AC Characteristics Graphs and Tables ......................................................................................................................171

18.0 Packaging Information ............................ ............. ............ ............. ......................... ................................................................. 195

Appendix A: Data Sheet Revision History ......................................................................................................................................... 203

Appendix B: Migrating from other PIC

Index ..................................................................... .. .. ....... .. .... .. .. .. .... ..... .. .... .. .. .. .... ............................................................................ 205

The Microchip Web Site .............................................. ............. ............. ............ ................................................................................209

Customer Change Notification Service .............................................................................................................................................209

Customer Support .............................................................................................................................................................................209

Reader Response .............................................................................................................................................................................210

Product Identification System ............................................................................................................................................................211

Worldwide Sales and Service ................ .......................... ......................... ......................... ............................................................... 212

Devices ................ ............ ............. ......................... ......................... .......................... .......... 203

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best docum entation possible to ensure s ucce ssf ul use of y our M icrochip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

DS41302D-page 6  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

Flash

Program

Memory

Data Bus

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

GPIO

8-Level Stack

64 Bytes

1K X 14

(13-Bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR

VSS

Brown-out

Reset

Timer0 Timer1

GP0 GP1 GP2 GP3 GP4 GP5

Analog Comparator

T0CKI

INT

T1CKI

Configuration

Internal

Oscillator

and Reference

T1G

VDD

Block

CIN+

CIN0-

CIN1-

COUT

Comparator Voltage Reference

Absolute Voltage Reference

Shunt Regulator

(PIC12HV609 only)

1.0 DEVICE OVERVIEW

The PIC12F609/615/617/12HV609/615 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC, MSOP and DFN packages.

FIGURE 1-1: PIC12F609/HV609 BLOCK DIAGRAM

Block Diagrams and pinout descriptions of the devices are as follows:

• PIC12F609/HV609 (Figure 1-1, Table 1-1)

• PIC12F615/617/HV615 (Figure 1-2, Table 1-2)

 2010 Microchip Technology Inc. DS41302D-page 7

PIC12F609/615/617/12HV609/615

Flash

Program Memory

Data Bus

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

GPIO

8-Level Stack

64 Bytes and

1K X 14

(13-Bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR

VSS

Brown-out

Reset

Timer0 Timer1

GP0 GP1 GP2 GP3 GP4 GP5

Analog Comparator

T0CKI

INT

T1CKI

Configuration

Internal

Oscillator

VREF

and Reference

T1G

VDD

Timer2

Block

Shunt Regulator

(PIC12HV615 only)

Analog-To-Digital Converter

AN0

AN1

AN2

AN3

CIN+

CIN0-

CIN1-

COUT

ECCP

CCP1/P1A

P1B

P1A*

P1B*

Comparator Voltage Reference

Absolute Voltage Reference

* Alternate pin function. ** For the PIC12F617 only.

T1G*

2K X 14**

and

128 Bytes**

FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM

DS41302D-page 8  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

T ABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION

Name Function

GP0/CIN+/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change

CIN+ AN — Comparator non-inverting input

ICSPDAT ST CMOS Serial Programming Data I/O

GP1/CIN0-/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change

CIN0- AN — Comparator inverting input

ICSPCLK ST — Serial Programming Clock

GP2/T0CKI/INT/COUT GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-change

T0CKI ST — Timer0 clock input

INT ST — External Interrupt

COUT — CMOS Comparator output

GP3/MCLR

GP4/CIN1-/T1G CLKOUT

GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change

DD VDD Power — Positive supply

SS VSS Power — Ground reference

V Legend: AN=Analog input or output CMOS= CMOS compatible input or output HV= High Voltage

/VPP GP3 TTL — General purpose input with interrupt-on-change

MCLR

PP HV — Programming voltage

/OSC2/

ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL=Crystal

GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change

CIN1-

T1G

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS F

T1CKI ST — Timer1 clock input OSC1 XTAL — Crystal/Resonator

CLKIN ST — External clock input/RC oscillator connection

Input

Type

Output

Type

ST — Master Clear w/internal pull-up

AN — Comparator inverting input ST — Timer1 gate (count enable)

OSC/4 output

Description

 2010 Microchip Technology Inc. DS41302D-page 9

PIC12F609/615/617/12HV609/615

TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION

Name Function

GP0/AN0/CIN+/P1B/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN0 AN — A/D Channel 0 input

CIN+ AN — Comparator non-inverting input

P1B — CMOS PWM output

ICSPDAT ST CMOS Serial Programming Data I/O

GP1/AN1/CIN0-/V

GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A

GP3/T1G

GP4/AN3/CIN1-/T1G CLKOUT

GP5/T1CKI/P1A*/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

V V

Legend: AN=Analog input or output CMOS= C MO S com patible input or output HV= High Voltage

*/MCLR/VPP GP3 TTL — General purpose input with interrupt-on-change

DD VDD Power — Positive supply SS VSS Power — Ground reference

* Alternate pin function.

REF/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN1 AN — A/D Channel 1 input

CIN0- AN — Comparator inverting input

REF AN — External Voltage Reference for A/D

ICSPCLK ST — Serial Programming Clock

GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN2 AN — A/D Channel 2 input

T0CKI ST — Timer0 clock input

INT ST — External Interrupt COUT — CMOS Comparator output CCP1 ST CMOS Capture input/Compare input/PWM output

P1A — CMOS PWM output

T1G

MCLR

PP HV — Programming voltage

/P1B*/OSC2/

ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL=Crystal

GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN3 AN — A/D Channel 3 input

CIN1-

T1G

P1B* — CMOS PWM output, alternate pin

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS F

T1CKI ST — Timer1 clock input

P1A* — CMOS PWM output, alternate pin OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection

Input

Type

* ST — Timer1 gate (count enable), alternate pin

Output

Type

change

ST — Master Clear w/internal pull-up

change

AN — Comparator inverting input ST — Timer1 gate (count enable)

OSC/4 output

change

Description

DS41302D-page 10  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

PC<12:0>

0000h

0004h 0005h

03FFh 0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

Stack Level 2

Wraps to 0000h-03FFh

PC<12:0>

0000h

0004h 0005h

07FFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN RETFIE, RETLW

Stack Level 2

Page 0

On-Chip

Program

Memory

Wraps to 0000h-07FFh

0800h 1FFFh

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F609/615/617/12HV609/615 has a 13-bit program counter capable of addressing an 8K x 14 program memory spa ce. Only the first 1K x 14 (0000h03FFh) for the PIC12F609/615/12HV609/615 is physically implemented. For the PIC12F617, the first 2K x 14 (0000h-07FFh) is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space for PIC12F609/615/12HV609/615 devices, and within the first 2K x 14 space for the PIC12F617 device. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC12F609/615/12HV609/615

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK FOR THE PIC12F617

2.2 Data Memory Organization

The data memory (see Figure 2-3) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. For the PIC12F617, the register locations 20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general purpose registers implemented as S tatic RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. The RP0 bit of the STATUS register is the bank select bit.

RP0

0  Bank 0 is selected 1  Bank 1 is selected

Note: The IRP and RP1 bits of the STATUS

 2010 Microchip Technology Inc. DS41302D-page 11

PIC12F609/615/617/12HV609/615

Indirect Addr.

(1)

TMR0

PCL

STATUS

FSR

GPIO

PCLATH INTCON

PIR1

TMR1L

TMR1H

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h

7Fh

Bank 0

Unimplemented data memory locations, rea d as ‘0’.

Note 1: Not a physical register.

General

File

Address

File

Address

WPU

IOC

Indirect Addr.

(1)

OPTION_REG

PCL

STAT US

FSR

TRISIO

PCLATH INTCON

PIE1

PCON

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

A0h

FFh

Bank 1

ANSEL

Accesses 70h-7Fh

F0h

VRCON

CMCON0

OSCTUNE

40h

3Fh

CMCON1

EFh

T1CON

Purpose

Registers

64 Bytes

Accesses 70h-7Fh

6Fh 70h

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file is organized as 64 x 8 in the PIC12F609/615/12HV609/615, and as 128 x 8 in the PIC12F617. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM.

The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

FIGURE 2-3: DATA MEMORY MAP OF

THE PIC12F609/HV609

DS41302D-page 12  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

Indirect Addr.

(1)

TMR0

PCL

STATUS

FSR

GPIO

PCLATH

INTCON

PIR1

TMR1L TMR1H T1CON

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h

7Fh

Bank 0

Unimplemented data memory locations, rea d as ‘0’.

Note 1: Not a physical register.

2: Used for the PIC12F617 only.

File

Address

File

Address

WPU

IOC

Indirect Addr.

(1)

OPTION_REG

PCL

STAT US

FSR

TRISIO

PCLATH INTCON

PIE1

PCON

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

A0h

FFh

Bank 1

ADRESH ADCON0

ADRESL

ANSEL

Accesses 70h-7Fh

F0h

TMR2

T2CON

CCPR1L CCPR1H

CCP1CON

PWM1CON

ECCPAS

VRCON

CMCON0

OSCTUNE

PR2

40h

3Fh

CMCON1

EFh

APFCON

General Purpose

Registers

64 Bytes

Accesses 70h-7Fh

6Fh 70h

PMCON1

(2)

PMCON2

(2)

PMADRL

(2)

PMADRH

(2)

PMDATL

(2)

PMDATH

(2)

General

Purpose

Registers

96 Bytes from

20h-7Fh

(2)

Unimplemented for PIC12F615/HV615

General

Purpose

Registers

32 Bytes

(2)

Unimplemented for

PIC12F615/HV615

BFh

C0h

FIGURE 2-4: DATA MEMORY MAP OF

THE PIC12F615/617/HV615

 2010 Microchip Technology Inc. DS41302D-page 13

PIC12F609/615/617/12HV609/615

TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 115 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 115 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 115 03h STA TUS IRP 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 115 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 115 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h VRCON CMVREN 1Ah CMCON0 CMON COUT CMOE CMPOL 1Bh — — — — — 1Ch CMCON1 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —

Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: Read only register.

(1)

— — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 115

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 115

— — — —CMIF— —TMR1IF---- 0--0 22, 115

— — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 73, 116

(1)

RP1

— VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116

RP0 TO PD ZDCC0001 1xxx 18, 115

TMR1CS TMR1ON 0000 0000 62, 115

—CMR—CMCH0000 -0-0 72, 116

Value on

POR, BOR

Page

DS41302D-page 14  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

TABLE 2-2: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 116 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116 03h STA TUS IRP 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 116 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h TMR2 12h T2CON 13h CCPR1L 14h CCPR1H 15h 16h

17h ECCPAS

18h — Unimplemented — — 19h VRCON CMVREN 1Ah CMCON0 CMON COUT CMOE CMPOL 1Bh — — — — — 1Ch CMCON1 1Dh — Unimplemented — — 1Eh 1Fh ADCON0

Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(3)

(3) (3)

CCP1CON PWM1CON

ADRESH

2: Read only register. 3: PIC12F615/617/HV615 only.

(3)

(2, 3)

(3)

(1)

— — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 116

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116

— ADIF CCP1IF —CMIF—TMR2IFTMR1IF-00- 0-00 22, 116

Timer2 Module Register 0000 0000 65, 116

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 66, 116 Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 90, 116 Capture/Compare/PWM Register 1 High Byte XXXX XXXX 90, 116

P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 89, 116

PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 105,

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 102,

— — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 73, 116

Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 85, 116

ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 84, 116

(1)

RP1

— VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116

RP0 TO PD ZDCC0001 1xxx 18, 116

TMR1CS TMR1ON 0000 0000 62, 116

—CMR—CMCH0000 -0-0 72, 116

Value on

POR, BOR

Page

116

 2010 Microchip Technology Inc. DS41302D-page 15

PIC12F609/615/617/12HV609/615

TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 81h OPTION_RE

G 82h PCL Pro gr am Coun ter’s (PC) Least Significant Byte 0000 0000 25, 116 83h STATUS IRP 84h FSR Indirect Dat a Memory Address Pointer xxxx xxxx 25, 116 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 8Ch PIE1 8Dh — Unimplemented — — 8Eh PCON 8Fh — Unimplemented — — 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU 96h IOC 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ANSEL

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(2)

2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: MCLR

exists.

4: TRISIO3 always reads as ‘1’ since it is an input only pin.

GPPU

— — TRISIO5 TRISIO4 TRISIO3

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116

— — — —CMIE— —TMR1IE---- 0--0 21, 116

— — — — — —PORBOR ---- --qq 23, 116

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116

— —WPU5WPU4— WPU2 WPU1 WPU0 --11 -111 46, 116 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116

— — — —ANS3— ANS1 ANS0 ---- 1-11 45, 117

and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch

INTEDG T0CS

(1)

RP1

(1)

RP0 TO PD ZDCC0001 1xxx 18, 116

T0SE PSA PS2 PS1 PS0 1111 1111 19, 116

(4)

TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116

Value on

POR, BOR

(3)

0000 0000 20, 116

Page

DS41302D-page 16  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

T ABLE 2-4: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 81h OPTION_REG GPPU 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116 83h STATUS IRP 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 8Ch PIE1 8Dh — Unimplemented — — 8Eh PCON 8Fh — Unimplemented — — 90h OSCTUNE 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 65, 116 93h APFCON 94h — Unimplemented — — 95h WPU 96h IOC 97h — Unimplemented — — 98h PMCON1 99h PMCON2 9Ah PMADRL 9Bh PMADRH 9Ch PMDATL 9Dh PMDATH 9Eh ADRESL 9Fh ANSEL

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(2)

(7) (7)

Program Memory Control Register 2 (not a physical register). ---- ---- —

(7)

PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 28

(7)

PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 28

(7)

(5, 6)

Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 85, 117

2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: MCLR

4: TRISIO3 always reads as ‘1’ since it is an input only pin. 5: Read only register. 6: PIC12F615/617/ H V6 15 onl y. 7: PIC12F617 only.

and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch

exists.

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116

(1)

— — TRISIO5 TRISIO4 TRISIO3

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116

— ADIE CCP1IE —CMIE— TMR2IE TMR1IE -00- 0-00 21, 116

— — — — — —PORBOR ---- --qq 23, 116

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116

— — — T1GSEL — — P1BSEL P1ASEL ---0 --00 21, 116

— —WPU5WPU4 — WPU2 WPU1 WPU0 --11 -111 46, 116 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116

— — — — — WREN WR RD ---- -000 29

— — — — — PMADRH2 PMADRH1 PMADRH0 ---- -000 28

— — Pr ogr am Memo ry Data Regis ter H igh By te. --00 0000 28

— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 45, 117

RP1

(1)

RP0 TO PD ZDCC0001 1xxx 18, 116

(4)

TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116

Value on

POR, BOR

(3)

0000 0000 20, 116

Page

 2010 Microchip Technology Inc. DS41302D-page 17

PIC12F609/615/617/12HV609/615

2.2.2.1 STATUS Register

The STATUS registe r, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM) The STATUS register can be the destination for any

instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as des tination may be different than intended.

For example, CLRF STATUS, will clea r the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

and PD bits are not

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 14.0

“Instruction Set Summary”.

Note 1: Bits IRP and RP1 of the STATUS register

are not used by the PIC12F609/615/617/ 12HV609/615 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respe ctively, in subtraction. See the SUBLW and SUBWF instructions for examples.

REGISTER 2-1: STATUS: STATUS REGISTER

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h – FFh) 0 = Bank 0 (00h – 7Fh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Borrow

bit 0 C: Carry/Borrow

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is

reversed.

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow

second operand. For rotate (RRF, RLF) instructi ons, this bit is loaded with either the high-orde r or low-o rder bit of the source register.

DS41302D-page 18  2010 Microchip Technology Inc.

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

PIC12F609/615/617/12HV609/615

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

BIT VALUE TIMER0 RATE WDT RATE

2.2.2.2 OPTION Register

The OPTION register is a readable and writable register, which contains various control bits to configure:

• Timer0/WDT prescaler

• External GP2/INT interrupt

•Timer0

• Weak pull-ups on GPIO

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG T0CS T0SE PSA PS2 PS1 PS0

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 6.1.3 “Software Programmable Prescaler”.

bit 7 GPPU

: GPIO Pull-up Enable bit

1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on GP2/T0CKI pin 0 = Internal in struction cycle clock (F

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transit ion on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

OSC/4)

 2010 Microchip Technology Inc. DS41302D-page 19

PIC12F609/615/617/12HV609/615

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register , which c ontains the various en able and fl ag bits for TMR0 register ove rflo w, GPIO change and external GP2/INT pin interrupts.

Note: Interrupt flag bits are set w hen an in terrupt

condition occurs, regar dless of the st ate of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overflow Interru pt Enab le bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: GP2/INT External Interrupt Enable bit

1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt

bit 3 GPIE: GPIO Change Interrupt Enable bit

1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit

1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow

bit 1 INTF: GP2/INT External Interrupt Flag bit

1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur

bit 0 GPIF: GPIO Change Interrupt Flag bit

1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software) 0 = None of the GPIO <5:0> pins have changed state

(1)

(2)

Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

DS41302D-page 20  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

2.2.2.4 PI E1 Register

The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register2-4.

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

—ADIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 4 Unimplemented: Read as ‘0’ bit 3 CMIE: Compara tor Interrupt Enable bit

1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt

bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

(1)

CCP1IE

(1)

—CMIE —TMR2IE

(1)

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

(1)

TMR1IE

Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.

 2010 Microchip Technology Inc. DS41302D-page 21

PIC12F609/615/617/12HV609/615

2.2.2.5 PIR1 Register

The PIR1 register cont ain s the P eriphera l Interr upt flag bits, as shown in Register 2-5.

REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

—ADIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Interrupt Flag bit

1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started

bit 5 CCP1IF: CCP1 Interrupt Flag bit

Capture mod e:

1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred

Compare mode

1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator output has changed (must be cleared in software)

0 = Comparator output has not changed

bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1 = Timer2 to PR2 match occurred (must be cleared in software)

0 = Timer2 to PR2 match has not occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Timer1 register overflowed (must be cleared in software)

0 = Timer1 has not overflowed

(1)

CCP1IF

(1)

—CMIF —TMR2IF

(1)

Note: Interrupt flag bi ts are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt f lag bits ar e cle ar prior to enabling an interrupt.

(1)

TMR1IF

Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.

DS41302D-page 22  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

2.2.2.6 PCON Regi st er

The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR The PCON register also contro ls the software enabl e of

the BOR The PCON register bits are shown in Register 2-6.

REGISTER 2-6: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

)

Reset

(1)

bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR

bit 0 BOR

Note 1: Reads as ‘0’ if Brown-out Reset is disabled.

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

 2010 Microchip Technology Inc. DS41302D-page 23

PIC12F609/615/617/12HV609/615

2.2.2.7 APFCON Register (PIC12F615/617/HV615 only)

The Alternate Pin Function Control (APFC ON) reg ister is used to steer specific peripheral input and output functions between different pins. For this device, the P1A, P1B and Timer1 Gate functions can be moved between different pins.

The APFCON register bits are shown in Register 2-7.

U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0

— — — T1GSEL — — P1BSEL P1ASEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1GSEL: TMR1 Input Pin Select bit

1 = T1G function is on GP3/T1G 0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B

bit 3-2 Unimplemented: Read as ‘0’ bit 1 P1BSEL: P1B Output Pin Select bit

1 = P1B function is on GP4/AN3/CIN1-/T1G 0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT

bit 0 P1ASEL: P1A Output Pin Select bit

1 = P1A function is on GP5/T1CKI/P1A 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A

(2)

/MCLR/VPP

(2)

/OSC2/CLKOUT

(2)

/P1B

/OSC2/CLKOUT

/OSC1/CLKIN

(1)

Note 1: PIC12F615/617/HV615 only.

2: Alternate pin function.

DS41302D-page 24  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

12 8 7 0

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

MOVLW 0x40 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer BTFSS FSR,7 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The lo w byte comes from the PCL register, which is a readable and writable register . The hig h byte (PC<12:8>) is not directl y readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0>  PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3>  PCH).

FIGURE 2-5: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.2 STACK

The PIC12F609/615/617/12HV609/615 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the S ta ck Pointer i s not rea dable or writa ble. The PC is PUSHed onto the stack when a CALL instruction is execute d or an interrupt ca uses a branc h. The stack is POPed in the even t of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operat es as a circular buf fer . This means th at after the st ack ha s been PUSHed eight time s, th e nin th push overwrites th e valu e that was s tore d from the firs t push. The tenth pus h ov erwr i tes the se co nd push (and so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

2.4 Indirect Addressing, INDF and FSR Registers

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This a llow s the entire contents of the program counter to be changed by writing the desired up per 5 bit s to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

A computed GOTO is accomplish ed by adding an of fs et to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program b ranch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table.

For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556).

The INDF register is not a physica l register . Addr essing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-6.

A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIR ECT ADDRES SING

 2010 Microchip Technology Inc. DS41302D-page 25

PIC12F609/615/617/12HV609/615

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

2: Accesses in this area are mirrored back into Bank 0 and Bank 1.

Data Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1

(1)

RP0 6

From Opcode

IRP

(1)

File Select Register

Bank Select

Location Select

00 01 10 11

180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

NOT USED

(2)

For memory map detail, see Figure 2-3.

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615

DS41302D-page 26  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY)

The Flash program memory is readable and writable during normal operation (full V is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5). There are six SFRs used to read and write this memory:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

• PMADRL

• PMADRH

When interfacing the program memory block, the PMDA T L and PMDATH registers form a two-byte word which holds the 14-bit data for read/write, and the PMADRL and PMADRH registers form a two-byte word which holds the 13-bit address of the Flash location being accessed. These devices have 2K words of program Flash with an address range from 0000h to 07FFh.

The program memory allows single word read and a by four word write. A four word write automatically erases the row of the location and writes the new data (erase before write).

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump r ated to oper ate over the vo ltage range of the device for byte or word operations.

When the device is code-protected, the CPU may continue to read and write the Flash program memory.

Depending on the settings of the Flash Program Memory Enable (WRT<1:0>) bits, the device may or may not be able to write certain blocks of the program memory, however, reads of the prog ram memory are allowed.

When the Flash program memory Code Protection

) bit in the Configuration Word register is enabled,

(CP the program memory is code-protected, and the device programmer (ICSP™) cannot access data or program memory.

DD range). This memory

3.1 PMADRH and PMADRL Registers

The PMADRH and PMADRL registers can address up to a maximum of 8K words of program memory.

When selecting a program address value, the Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register.

3.2 PMCON1 and PMCON2 Registers

PMCON1 is th e control regi ster for the da ta program memory accesses.

Control bits RD and WR initiate read and write, respectiv ely. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear.

PMCON2 is not a physical regis ter. Reading PMCON2 will read all ‘0’s. The PMCON2 register is used exclusively in the Flash memory write sequence.

 2010 Microchip Technology Inc. DS41302D-page 27

PIC12F609/615/617/12HV609/615

REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMDATL7 PM DATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMDATL<7:0>: 8 Least Significant Address bits to Write or Read from Program Memory

REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation

REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDATH<5:0>: 6 Most Significant Data bits from Program Memory

REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PMADRH2 PMADRH1 PMA DRH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 3 Unimplemented: Read as ‘0’ bit 2-0 PMADRH<2:0>: Specifies the 3 Most Significant Address bits or high bits for program memory reads.

DS41302D-page 28  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

REGISTER 3-5: PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h)

U-1 U-0 U-0 U-0 U-0 R/W-0 R/S-0 R/S-0

— — — — —WRENWR RD

bit 7 bit 0

bit 7 Unimplemented: Read as ‘1’ bit 6-3 Unimplemented: Read as ‘0’ bit 2 WREN: Program Memory Write Enable bit

1 = Allows write cycles 0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycle to program memory. (The bit is cleared by hard w are whe n w rit e is co mplete. The

WR bit can only be set (not cleared) in software.)

0 = Write cycle to the Flash memory is complete

bit 0 RD: Read Control bit

1 = Initiates a program memory read (The read t ak es on e cycle. The RD is c lea red i n h ard w are; th e RD bi t

can only be set (not cleared) in software).

0 = Does not initiate a Flash memory read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

 2010 Microchip Technology Inc. DS41302D-page 29

PIC12F609/615/617/12HV609/615

BANKSEL PM_ADR ; Change STATUS bits RP1:0 to select bank with PMADRL MOVLW MS_PROG_PM_ADDR ; MOVWF PMADRH ; MS Byte of Program Address to read MOVLW LS_PROG_PM_ADDR ; MOVWF PMADRL ; LS Byte of Program Address to read BANKSEL PMCON1 ; Bank to containing PMCON1 BSF PMCON1, RD ; PM Read

NOP ; First instruction after BSF PMCON1,RD executes normally

NOP ; Any instructions here are ignored as program

; memory is read in second cycle after BSF PMCON1,RD

; BANKSEL PMDATL ; Bank to containing PMADRL MOVF PMDATL, W ; W = LS Byte of Program PMDATL MOVF PMDATH, W ; W = MS Byte of Program PMDATL

3.3 Reading the Flash Program Memory

To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memo ry Flash con troller wi ll use the s econd instruction cycle af te r to read the dat a. Thi s caus es the second instruction immediately following the “

PMCON1,RD

” instruction to be ignored. The data is available in the very next cycle in the PMDATL and PMDATH registers; it can be read as two bytes in the following instructions. PMDATL and PMDATH registers will hold this value until another read or until it is written to by the user (during a write operation).

EXAMPLE 3-1: FLASH PROGRAM READ

BSF

DS41302D-page 30  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,RD

Executed here

INSTR (PC + 1)

Executed here

NOP

Executed here

PC PC + 1 PMADRH,PMADRL PC+3 PC + 5

Flash ADDR

RD bit

INSTR (PC)

PMDATH,PMDATL

INSTR (PC + 3)

PC + 3 PC + 4

INSTR (PC + 4)

INSTR (PC + 1)

INSTR (PC - 1)

Executed here

INSTR (PC + 3)

Executed here

INSTR (PC + 4)

Executed here

Flash DATA

PMDATH

PMDATL

PMRHLT

FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

 2010 Microchip Technology Inc. DS41302D-page 31

PIC12F609/615/617/12HV609/615

3.4 Writing the Flash Program

Memory

A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory.

Flash program memory must be written in four-word blocks. See Figure 3-2 and Figure 3-3 for more details. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where PMADRL<1:0> = 00. All block writes to program memory are done as 16-word erase by fourword write operations. The write operation is edgealigned and cannot occur across boundaries.

To write program data, it must first be loaded into the buffer registers (see Figure 3-2). This is accomplished by first writing the de stina tio n addres s to PMAD RL and PMADRH and then writing the data to PMDATL and PMDATH. After the address and data have been set up, then the following sequence of events must be executed:

1. Write 55h, then AAh, to PMCON2 (Flash

programmi ng sequence).

2. Set the WR control bit of the PMC ON1 re gis ter. All four buffer register locations should be written to

with correct data. If less than four words are being written to in the block of four words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the PMDATL and PMDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed.

To transfer data from the buffer registers to the program memory, the PMADRL and PMADRH must point to the last location in the four-word block (PMADRL<1:0> =

11). Then the following sequence of events must be executed:

1. Write 55h, then AAh, to PMCON2 (Flash pro-

gramming sequence).

2. Set contro l bit WR of t he PMCON1 reg ister to

begin the write operation.

The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (000, 001, 010, 011). When the write is performed on the last word (PMADRL<1:0> = 11), a block of sixteen words i s automatica lly eras ed and t he cont ent of t he fou r-word buffer registers are written into the program memory.

After the “BSF PMCON1,WR” inst r uct i on , th e p roc es so r requires two cycles to set up the erase/write operation. The user must pla ce two NOP instructions after the WR bit is set. Since data is being written to bu ff er regis ters, the writing of the first three words of the block appears to occur immediately. The processor will halt internal operations for the typical 4 ms, only during the cycle in

which the erase takes place (i.e., the last word of the sixteen-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the four-word write cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. The above sequence must be repeated for the higher 12 words.

3.5 Protection Against Spurious Write

There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is clea red. Als o, the Powe r-up Timer (64 ms duration) prevents program memory writes.

The write initiate sequence and the WREN bit help prevent an accidental write during brown-out, power glitch or software malfunction.

3.6 Operation During Code-Protect

When the device is code-protected, the CPU is able to read and write unscrambled data to the program memory. The test mode access is disabled.

3.7 Operation During Write Protect

When the program memory is write-protected, the CPU can read and execute from the program memory. The portions of program memory that are write protected can b e mo difie d by t he C PU us in g the P MCO N registers, but the protected program memory cannot be modified using ICSP mode.

DS41302D-page 32  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

14 14 14

Program Memory

Buffer Register

PMADRL<1:0> = 00

Buffer Register

PMADRL<1:0> = 01

Buffer Register

PMADRL<1:0> = 10

Buffer Register

PMADRL<1:0> = 11

PMDATLPMDATH

First word of block to be written

If at a new row

to Flash automatically after this word is written

are transferred

Flash are erased, then four buffers

sixteen words of

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,WR

Executed here

INSTR (PC + 1)

Executed here

PC + 1

Flash

INSTR

PMDATH,PMDATL

INSTR (PC+3)

INSTR

NOP

Executed here

Flash

PMWHLT

WR bit

Processor halted PM Write Time

PMADRH,PMADRL

PC + 3 PC + 4

INSTR (PC + 3)

Executed here

ADDR

DAT A

Memory

Location

ignored

read

PC + 2

INSTR (PC+2)

(INSTR (PC + 2)

NOP

Executed here

(PC)

(PC + 1)

FIGURE 3-2: BLOCK WRITES TO 2K FLASH PROGRAM MEMORY

FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION

 2010 Microchip Technology Inc. DS41302D-page 33

PIC12F609/615/617/12HV609/615

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This write routine assumes the following: ; A valid starting address (the least significant bits = '00') ; is loaded in ADDRH:ADDRL ; ADDRH, ADDRL and DATADDR are all located in data memory ; BANKSEL PMADRH MOVF ADDRH,W ; Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVF DATAADDR,W ; Load initial data address MOVWF FSR ;

LOOP MOVF INDF,W ; Load first data byte into lower

MOVWF PMDATL ; INCF FSR,F ; Next byte MOVF INDF,W ; Load second data byte into upper MOVWF PMDATH ; INCF FSR,F ; BANKSEL PMCON1 BSF PMCON1,WREN ; Enable writes BCF INTCON,GIE ; Disable interrupts (if using) BTFSC INTCON,GIE ; See AN576 GOTO $-2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Required Sequence MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write 0AAh BSF PMCON1,WR ; Set WR bit to begin write NOP ; Required to transfer data to the buffer NOP ; registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts (comment out if not using interrupts) BANKSEL PMADRL MOVF PMADRL, W INCF PMADRL,F ; Increment address ANDLW 0x03 ; Indicates when sixteen words have been programmed SUBLW 0x03 ; 0x0F = 16 words

; 0x0B = 12 words ; 0x07 = 8 words

; 0x03 = 4 words BTFSS STATUS,Z ; Exit on a match, GOTO LOOP ; Continue if more data needs to be written

An example of the complete four-word write sequence is shown in Example 3-2. The initial address is loaded into the PMADRH and PMADRL register pair; the eight words of data are loaded using indirect addressing.

EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY

DS41302D-page 34  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PMCON1 PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----

PMADRL PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 0000 0000 PMADRH PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 0000 0000 PMDATH Legend: x = unknown , u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

—

— — —

— — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0 --00 0000 --00 0000

Shaded cells are not used by Program Memory module.

— — — —WRENWR RD---- -000 ---- -000

— —

PMADRH2 PMADRH1 PM A DRH0 ---- -000 ---- -000

Value on

POR, BOR

Value on

all other

Resets

 2010 Microchip Technology Inc. DS41302D-page 35

PIC12F609/615/617/12HV609/615

NOTES:

DS41302D-page 36  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

(CPU and Peripherals)

OSC1

OSC2

Sleep

External Oscillator

LP, XT, HS, RC, RCIO, EC

System Clock

MUX

FOSC<2:0>

(Configuration Word Register)

Internal Oscillator

INTOSC

8 MHz

Postscaler

4 MHz

INTOSC

IOSCFS<7>

4.0 OSCILLATOR MODULE

The Oscillator mod ule can be c onfigured in one of eig ht clock modes.

4.1 Overview

The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applicati ons while maximiz ing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the Oscillator module.

Clock sources can be configured from external oscillators, quartz cryst al resonators , ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured with a choice of two selectable speeds: internal or external system clock source.

3. EC – External clock w ith I/O on OSC2/C LKOUT.

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode.

6. HS – High Gain Crystal or Ceramic Resonator mode.

7. RC – External Resistor-Capacitor (RC) with

OSC/4 output on OSC2/CLKOUT.

8. RCIO – External Resistor-C apacitor (RC) with I/O on OSC2/CLKOUT.

9. INTOSC – Internal oscillator with F on OSC2 and I/O on OSC1/CLKIN.

10. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT.

Clock Source modes are configured by the FO SC<2:0> bits in the Configuration Word register (CONFIG). The Internal Oscillator module provides a selectable system clock mode of either 4 MHz (Postscaler) or 8 MHz (INTOSC).

FIGURE 4-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

OSC/4 output

 2010 Microchip Technology Inc. DS41302D-page 37

PIC12F609/615/617/12HV609/615

OSC1/CLKIN

OSC2/CLKOUT

(1)

I/O

Clock from Ext. System

PIC

MCU

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

4.2 Clock Source Modes

Clock Source modes can be classified as external or internal.

• External Clock m odes rely on e xternal c ircui try fo r the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two selectable clock frequencies: 4 MHz and 8 MHz

The system clock can be selected between extern al or internal clock sources via the FOSC<2:0> bits of the Configuration Word register.

4.3 External Clock Modes

4.3.1 OSCILLATOR START-UP TIMER (OST)

If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator o r ce ramic res onator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 4-1.

TABLE 4-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR INTOSC 125 kHz to 8 MHz Oscillator Warm-Up Delay (T Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)

4.3.2 EC MODE

The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 4-2 shows the pin connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

MCU design is fully

WARM)

FIGURE 4-2: EXTERNAL CLOCK (EC)

MODE OPERATION

DS41302D-page 38  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Quartz

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

F varies with the Oscillator mode

selected (typically between 2 M to 1 0 M.

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

Ceramic

(1)

OSC1/CLKIN

(2)

Sleep

To Internal Logic

PIC® MCU

(3)

Resonator

OSC2/CLKOUT

4.3.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figu re 4-3). The mode selects a low , medium or high gain setting of the internal inverteramplifier to support v arious resonato r types and spee d.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. T his mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medi um of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonato rs that req uire a hi gh drive setting.

Figure 4-3 and Figure 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively.

FIGURE 4-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

Note 1: Quartz cryst al characterist ics vary acco rding

to type, package and manufacturer. The user should consult the manu facturer data sheets for sp ecifi catio ns an d reco mmen ded application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, refer ence

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

and PIC®

Devices” (DS00826)

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

FIGURE 4-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

 2010 Microchip Technology Inc. DS41302D-page 39

PIC12F609/615/617/12HV609/615

OSC2/CLKOUT

(1)

CEXT

REXT

PIC® MCU

OSC1/CLKIN

OSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  R

EXT  100 k, 3-5V

EXT > 20 pF, 2-5V

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2: Output depends upon R C or RCIO Clock

mode.

I/O

(2)

4.3.4 EXT ERN AL RC MODES

The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 4-5 shows the external RC mode connections.

FIGURE 4-5: EXTERNAL RC MODES

4.4 Internal Clock Modes

The Oscillator module provides a selectable system clock source of either 4 MHz or 8 MHz. The selectable frequency is configured through the IOSCFS bit of the Configuration Word.

The frequency of the int ernal oscillator can be trim me d with a calibration value in the OSCTUNE register.

4.4.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is progra mmed usi ng the osc illator selectio n or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 12.0 “Special Features of the CPU” for more information.

In INTOSC mode, OSC1/CLKIN i s available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator fre quency div ided by 4. The C LKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O.

In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance The user also needs to take into account variation due

to tolerance of external RC components used.

DS41302D-page 40  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

4.4.1.1 OSCTUNE Register

The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-1).

The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number.

When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

REGISTER 4-1: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximum frequency 01110 =

•

00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 =

•

• 10000 = Minimum frequency

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CONFIG OSCTUNE

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR

 2010 Microchip Technology Inc. DS41302D-page 41

(2)

IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word register (Register 12-1) for operation of all register bits.

Val ue on

POR, BOR

Val ue on

all other

Resets

(1)

PIC12F609/615/617/12HV609/615

NOTES:

DS41302D-page 42  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

BANKSEL GPIO ; CLRF GPIO ;Init GPIO BANKSEL ANSEL ; CLRF ANSEL ;digital I/O, ADC clock

;setting ‘don’t care’ MOVLW 0Ch ;Set GP<3:2> as inputs MOVWF TRISIO ;and set GP<5:4,1:0>

;as outputs

5.0 I/O PORT

There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In gen eral, when a periphe ral is enabled, the associated pin may not be used as a general purpose I/O pin.

5.1 GPIO and the TRISIO Registers

GPIO is a 6-bit wide p ort wi th 5 bi directio nal an d 1 inp utonly pin. The corresponding data direction register is TRISIO (Register 5-2). Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., disable the output driver). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., enables output driver and puts the content s of the output l atch on the selected pin). The exception is GP3, which is input only and its TRIS bit will always read as ‘1’. Example 5- 1 shows how to initi ali ze G PIO .

Note: GPIO = PORTA

TRISIO = TRISA

Reading the GPIO register (Register 5-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘0’ when MCLRE = 1.

The TRISIO register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO register are maintained set when using the m as analog inputs. I/O pin s co nfigure d a s ana log i nput a lways read ‘0’.

Note: The ANSEL register must be initialized to

configure an analog channel as a digital input. Pins configu red as analo g inputs will read ‘0’ and cannot generate an interrupt.

EXAMPLE 5-1: INITIA LI ZING GPIO

REGISTER 5-1: GPIO: GPIO REGISTER

U-0 U-0 R/W-x R/W-x R- x R/W-x R/W-x R/W-x

— — GP5 GP4 GP3 GP2 GP1 GP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GP<5:0>: GPIO I/O Pin bit

1 = GPIO pin is > V 0 = GPIO pin is < VIL

 2010 Microchip Technology Inc. DS41302D-page 43

PIC12F609/615/617/12HV609/615

REGISTER 5-2: TRISIO: GPIO TRI-STATE REGISTER

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISIO<5:0>: GPIO Tri-State Control bit

1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output

Note 1: TRISIO<3> always reads ‘1’.

2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

5.2 Additional Pin Functions

Every GPIO pin on the PIC12F609/615/617/12HV609/ 615 has an interrupt-on-c hange option and a weak pullup option. The next three sections describe these functions.

5.2.1 ANSEL REGISTER

The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digi t al read s on the pi n to be read as ‘0’ and allow analog functions on the pin to operate correctly.

The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

5.2.2 WEAK PULL-UPS

Each of the GPIO pins, exce pt GP3, has an individuall y configurable internal weak pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 5-5. Each weak pull-up is automatically turned off when the port pin is c onfigured as an out put. The pull-ups are disabled on a Power-on Reset by the GPPU OPTION register). A weak pull-up is automatically enabled for GP3 when configured as MCLR and disabled when GP3 is an I/O. There is no software control of the MCLR

pull-up.

bit of the

For enabled interrupt-on-change pins, the values are compared with the old value latch ed on the last rea d of GPIO. The ‘mismatch’ o utputs of t he last read are OR’d together to set the GPIO Change Interrupt Flag bit (GPIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by:

a) Any read of GPIO AND Clear flag bit GPIF. This

will end the mismatch condit ion ; OR

b) Any write of GPIO AND Clear flag bit GPIF will

end the mismatch condition;

A mismatch condition will continue to set flag bit GPIF. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the last read value is not affected by a MCLR Reset. After these res ets , the GPIF fl ag will contin ue to be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when any GPIO operation is being executed, then the GPIF interru pt flag may not get set.

nor BOR

5.2.3 INTERRUPT-ON-CHANGE

Each GPIO pin is individually configurable as an interrupt-on-change pin. Control bits IOCx enable or disable the interrupt function for each pin. Refer to Register5-6. The interrupt-on-change is disabled on a Power-on Reset.

DS41302D-page 44  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

REGISTER 5-3: ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609)

U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1

— — — —ANS3— ANS1 ANS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS3: Analog Select Between Ana l og or Di gital Func tion on Pi n GP 4

1 = Analog input. Pin is assigned as analog input 0 = Digital I/O. Pin is assigned to port or special function.

bit 2 Unimplemented: Read as ‘0’ bit 1 ANS1: Analog Select Between Analog or Digital Function on Pin GP1

1 = Analog input. Pin is assigned as analog input . 0 = Digital I/O. Pin is assigned to port or special function.

bit 0 ANS0: Analog Select Between Analog or Digital Function on Pin GP0

0 = Digital I/O. Pin is assigned to port or special function. 1 = Analog input. Pin is assigned as analog input .

(1)

Note 1: Setting a pin to an analo g input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-

change if available. The cor re sponding TRIS bit must be s et to Input mode in order to allow exte rn al control of the voltage on the pin.

REGISTER 5-4: ANSEL: ANALOG SELECT REGISTER (PIC12F615/617/HV615)

U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R /W-1 R/W-1

— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits

OSC/2

000 = F

OSC/8

001 = F 010 = F

OSC/32 RC (clock derived from a dedicated internal oscillator = 500 kHz max)

x11 = F 100 = F

OSC/4 OSC/16

101 = F 110 = F

OSC/64

bit 3-0 ANS<3:0>: Analog Select B et wee n Anal og or Di gital Func ti on on Pins GP4, GP 2, GP1 , GP0 , r es pe ct iv el y.

1 = Analog input. Pin is assigned as analog input 0 = Digital I/O. Pin is assigned to port or special function.

(1)

Note 1: Setting a pin to an analo g input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-

change if available. The cor re sponding TRIS bit must be s et to Input mode in order to allow exte rn al control of the voltage on the pin.

 2010 Microchip Technology Inc. DS41302D-page 45

PIC12F609/615/617/12HV609/615

REGISTER 5-5: WPU: WEAK PULL-UP GPIO REGISTER

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WPU5 WPU4 — WPU2 WPU1 WPU0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits

1 = Pull-up enabled 0 = Pull-up disabled

bit 3 WPU<3>: Weak Pull-up Register bit bit 2-0 WPU<2:0>: Weak Pull-up Control bits

1 = Pull-up enabled 0 = Pull-up disabled

(3)

Note 1: Global GPPU

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). 3: The GP3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled

as an input and reads as ‘0’.

4: WPU<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

must be enabled for individual pull-ups to be enabled.

REGISTER 5-6: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOC<5:0>: Interrupt-on-change GPIO Control bit

1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOC<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

DS41302D-page 46  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

VDD

VSS

VDD

Weak

RD GPIO

WR IOC

IOC

Interrupt-on-

To Comparator

Analog

(1)

Input Mode

GPPU

Analog

(1)

Input Mode

Change

WPU

Data Bus

WPU

GPIO

TRISIO

GPIO

Note 1: Comparator mode and ANSEL determines Analog Input mode.

2: Set has priority over Reset. 3: PIC12F615/617/HV615 only.

To A/D Converter

(3)

I/O Pin

(2)

From other GP<5:0> pins (GP0)

Write ‘0’ to GBIF

GP<5:2, 0> pins (GP1)

5.2.4 PIN DESCRIPTIONS AND DIAGRAMS

Each GPIO pin is multiplexed with other functions. The pins and thei r c ombined functions a r e bri efl y de sc ribe d here. For specific inf ormation about indi vidual function s such as the Comparator or the ADC, refer to the appropriate section in this data sheet.

5.2.4.1 GP0/AN0

(1)

/CIN+/P1B

(1)

/ICSPDAT

Figure 5-1 shows the diagram for this pin. T he GP0 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

(1)

• an analog non-inverting input to the comparator

• a PWM output

(1)

• In-Circuit Serial Programming data

FIGURE 5-1: BLOCK DIAGRAM OF GP<1:0>

5.2.4.2 GP1/AN1

(1)

/CIN0-/VREF

(1)

/ICSPCLK

Figure 5-1 shows the diagram for this pin. T he GP1 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

(1)

• an analog inverting input to the comparator

• a voltage reference input for the ADC

(1)

• In-Circuit Serial Programming clock

Note 1: PIC12F615/617/HV615 only.

 2010 Microchip Technology Inc. DS41302D-page 47

PIC12F609/615/617/12HV609/615

VDD

VSS

VDD

Weak

RD GPIO

WR IOC

IOC

Interrupt-on-

To INT

Analog

(1)

Input Mode

GPPU

Analog

(1)

Input Mode

Change

WPU

Data Bus

WPU

GPIO

TRISIO

GPIO

Note 1: Comparator mode and ANSEL determines Analog Input mode.

2: Set has priority over Reset. 3: PIC12F615/617/HV615 only.

To A/D Converter

(3)

I/O Pin

(2)

From other GP<5:3, 1:0> pins

Write ‘0’ to GBIF

C1OE

Enable

To Timer0

5.2.4.3 GP2/AN2 CCP1

(1)

/T0CKI/INT/COUT/

(1)

/P1A

(1)

Figure 5-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

(1)

• the clock input for TMR0

• an external edge triggered interrupt

• a digital output from Comparator

• a Capture input/Compare inp ut/PW M output

• a PWM output

(1)

FIGURE 5-2: BLOCK DIAGRAM OF GP2

Note 1: PIC12F615/617/HV615 only.

DS41302D-page 48  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

VSS

Data Bus

RD GPIO

GPIO

IOC

Reset

MCLRE

TRISIO

VSS

MCLRE

VDD

Weak

MCLRE

Input

Interrupt-on-

Change

(1)

From other

Write ‘0’ to GBIF

Note 1: Set has priority over Reset

GP<5:4, 2:0> pins

5.2.4.4 GP3/T1G

(1, 2)

/MCLR/VPP

Figure 5-3 shows the diagram for this pin. T he GP3 pin is configurable to function as one of the following:

• a general purpose input

• a Timer1 gate (count enable), alternate pin

(1, 2)

• as Master Clear Reset with weak pull-up

Note 1: Alternate pin function.

2: PIC12F615/617/HV615 only.

FIGURE 5-3: BLOCK DIAGRAM OF GP3

 2010 Microchip Technology Inc. DS41302D-page 49

PIC12F609/615/617/12HV609/615

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPU

GPIO

TRISIO

WR IOC

IOC

OSC/4

To A/D Converter

(5)

Oscillator

Circuit

OSC1

CLKOUT

Enable

Analog

(3)

Input Mode

GPPU

RD GPIO

To T1G

INTOSC/

RC/EC

(2)

CLK

(1)

Modes

CLKOUT

Enable

Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable.

2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC12F615/617/HV615 only.

I/O Pin

Interrupt-on-

Change

(4)

From other

Write ‘0’ to GBIF

GP<5, 3:0> pins

5.2.4.5 GP4/AN3 P1B

(2)

(1, 2)

/CIN1-/T1G/

/OSC2/CLKOUT

Figure 5-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

(2)

• Comparator inverting input

• a Timer1 gate (count enable)

FIGURE 5-4: BLOCK DIAGRAM OF GP4

• PWM output, alternate pin

• a crystal/reso na tor con nection

• a clock output

Note 1: Alternate pin function.

2: PIC12F615/61 7/HV615 onl y.

(1, 2)

DS41302D-page 50  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

VDD

VSS

VDD

Weak

Data Bus

WPU

GPIO

TRISIO

IOC

To Timer1

INTOSC

Mode

RD GPIO

INTOSC

Mode

GPPU

OSC2

Note 1: Timer1 LP Oscillator enabled.

2: Set has priority over Reset.

TMR1LPEN

(1)

Oscillator

Circuit

I/O Pin

Interrupt-on-

Change

(2)

From other

GP<4:0> pins

Write ‘0’ to GBIF

5.2.4.6 GP5/T1CKI/P1A

(1, 2)

/OSC1/CLKIN

Figure 5-5 shows the diagram for this pin. T he GP5 pin is configurable to function as one of the following:

• a general purpose I/O

• a Timer1 clock input

• PWM output, alternate pin

(1, 2)

• a crystal/resonator connection

• a clock input

FIGURE 5-5: BLOCK DIAGRAM OF GP5

Note 1: Alternate pin function.

2: PIC12F615/617/HV615 only.

 2010 Microchip Technology Inc. DS41302D-page 51

PIC12F609/615/617/12HV609/615

TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSEL CMCON0 INTCON GIE IOC

OPTION_REG GPPU GPIO TRISIO WPU T1CON CCP1CON APFCON

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO. Note 1: PIC12F615/617/HV615 only.

(1)

— ADCS2

CMON COUT CMOE CMPOL —CMR—CMCH0000 -0-0 0000 -0-0

— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --u0 u000 — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 — — WPU5 WPU4 WPU3 WPU2 WPU1 WPU0 --11 1111 --11 -111

T1GINV TMR1GE TICKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000

— — — T1GSEL — — P1BSEL P1ASEL ---0 --00 ---0 --00

(1)

PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

ADCS1

(1)

ADCS0

(1)

ANS3 ANS2

(1)

ANS1 ANS0 -000 1111 -000 1111

Value on

POR, BOR

Value on all other

Resets

DS41302D-page 52  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

T0CKI

T0SE

TMR0

Watchdog

Timer

WDT

Time-out

PS<2:0>

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: WDTE bit is in the Configuration Word register.

8-bit

Prescaler

FOSC/4

PSA

Sync

2 T

6.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/c ounter with the following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow Figure 6-1 is a block diagram of the Timer0 module.

6.1 Timer0 Operation

When used as a timer, the Timer0 module can be use d as either an 8-bit timer or an 8-bit counter.

6.1.1 8-BIT TIMER MODE

When used as a timer, the Timer0 module will increment every instruction cyc le (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to ‘0’.

When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write.

Note: The value written to th e TMR0 regis ter can

be adjusted, in order to ac count for th e two instruction cycle delay when TMR0 is written.

6.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

 2010 Microchip Technology Inc. DS41302D-page 53

PIC12F609/615/617/12HV609/615

BANKSEL TMR0 ; CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and

;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ;

; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32

CLRWDT ;Clear WDT and

;prescaler BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG ;

6.1.3 SOFTWARE PROGRAMMABLE PRESCALER

A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlle d by the PSA bit o f the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’.

There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via th e PS<2:0> bits of the OPTION regi ster . In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module.

The prescaler is not readable or writable. When assigned to the Tim er0 module, all instructions w riting to the TMR0 register will clear the prescaler .

When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.

6.1.3.1 Switching Prescaler Between

Timer0 and WDT Modules

As a result of hav ing the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changin g th e presca le r ass ig nme nt fro m Timer0 to the WDT module, the instr uction sequence shown in Example 6-1, must be executed.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0  WDT)

When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 6-2).

EXAMPLE 6-2: CHANGIN G PRESCA LER

(WDT  TIMER0)

6.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register.

Note: The Timer0 interrupt cannot wake the

processor from Sleep since the timer is frozen dur ing Sleep.

6.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK

When Timer0 is in Coun ter mo de, t he synchronizatio n of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler ou tput on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 16.0 “Electrical Specifications”.

DS41302D-page 54  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

BIT VALUE TMR0 RATE WDT RATE

REGISTER 6-1: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GPPU

: GPIO Pull-up Enable bit

1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin 0 = Internal in struction cycle clock (FOSC/4)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE OPTION_REG TRISIO Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0

 2010 Microchip Technology Inc. DS41302D-page 55

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

module.

Value on

POR, BOR

INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x

Value on

all other

Resets

PIC12F609/615/617/12HV609/615

NOTES:

DS41302D-page 56  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

7.0 TIMER1 MODULE WITH GATE CONTROL

The Timer1 module is a 16-bit timer/counter with the following features:

• 16-bit timer/counter reg ister p air (TMR1 H:TMR1 L)

• Programmable internal or external clock source

• 3-bit prescaler

• Optional LP oscillator

• Synchronous or asynchronous operation

• Timer1 gate (count enable) via comparator or

T1G

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with ECCP)

• Comparator output synchronization to Timer1

clock

Figure 7-1 is a block diagram of the Timer1 module.

7.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.

When used with an interna l clock so urce, the module i s a timer. When used with an ext ernal cl ock sou rce, t he module can be used as either a timer or counter.

7.2 Clock Source Selection

The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source

OSC/4. When TMR1CS = 1, the clock source is

is F supplied externally.

Clock Source TMR1CS T1ACS

OSC/4 00

FOSC 01 T1CKI pin 1x

 2010 Microchip Technology Inc. DS41302D-page 57

PIC12F609/615/617/12HV609/615

TMR1H TMR1L

Oscillator

T1SYNC

T1CKPS<1:0>

OSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit TMR1IF on Overflow

TMR1

(2)

TMR1GE

TMR1ON

T1OSCEN

COUT

T1GSS

T1GINV

To Comparator Module Timer1 Clock

TMR1CS

OSC2/T1G

OSC1/T1CKI

Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.

2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: Alternate pin function.

5: PIC12F615/617/HV615 only.

(1)

INTOSC

Without CLKOUT

T1ACS

OSC

T1GSEL

(2)

GP3/T1G

(4, 5)

Synchronize

(3)

det

FIGURE 7-1: TIMER1 BLOCK DIAGRAM

DS41302D-page 58  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

7.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples

CY as determined by the Timer1 prescaler.

of T

7.2.2 EXT ERN AL CLOCK SOURCE

When the external clock source is selected, the Timer1 module may work as a timer or a counter.

When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously.

If an external clock oscillator is needed (and the microcontroller is us ing the INTOS C without CLKOUT), Timer1 can use the LP oscillator as a clock source.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions:

• Timer1 is enabled after POR or BOR Reset

• A write to TMR1H or TMR1L

• T1CKI is high when Timer1 is disabled and when

Timer1 is re-enabled T1CKI is low. See Figure 7-2.

7.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cl eared upon a write to TMR1H or TMR1L.

7.4 Timer1 Oscillator

A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON regi ster. The oscillator will continue to run during Sleep.

The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer 1 can use th is mode on ly when the primary system clock is derived from the internal oscillator or when in LP osci llator m ode. The us er must provide a software time delay to ensure proper oscillator start-up.

TRISIO5 and TRISIO4 bits are set when the Timer1 oscillator is ena bled. GP 5 and GP 4 bit s read as ‘0’ an d TRISIO5 and TRISIO4 bits read as ‘1’.

7.5 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 7.5.1 “Reading and Writing

Timer1 in Asynchronous Counter Mode”).

Note: When switching from synchronous to

asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment.

Note: In asynchronous counter mode or when

using the interna l oscillat or and T1ACS= 1, Timer1 ca n no t be used as a tim e base for the capture or compare modes of the ECCP module (for PIC12F615/617/ HV615 only).

7.5.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running from an external asyn chronous cl ock will e nsure a valid read (taken care of in hardware). However, the user should keep in mind that rea ding t he 1 6-bit ti mer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads.

For writes, it is recommend ed that th e user s imply sto p the timer and write the desired values. A write contention may occ ur by w ritin g to th e timer regist ers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TTMR1L register pair.

Note: The oscillator requires a start-up and

stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.

 2010 Microchip Technology Inc. DS41302D-page 59

PIC12F609/615/617/12HV609/615

7.6 Timer1 Gate

Timer1 gate source is software configurable to be the

pin (or the alternate T1G pin) or the output of the

T1G Comparator. This allows the device to directly time external events using T1G or analog events using the Comparator. See the CMCON1 Register (Register 9-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com).

Note: TMR1GE bi t of the T1CON register must

be set to use either T1G Timer1 gate source . See Register 9-2 for more informat ion on selecting th e Timer1 gate source.

Timer1 gate can be in verted using the T1GINV bit of the T1CON register , wh ether it originate s from the T1G pin or the Comparator output. This configures Timer1 to measure either the active-high or active-low time between ev ents.

or COUT as the

7.7 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over , the T i mer1 in terrupt fl ag bit of th e PIR1 regis ter is set. To enable the interrupt on rollover, you must set these bits:

• Timer1 interrupt enable bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note: The TMR1H:TTMR1L register p air and th e

TMR1IF bit should be cleared before enabling interrupts.

7.9 ECCP Capture/Compare Time Base (PIC12F615/617/HV615 only)

The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode.

In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event.

In Compare mode, an event is trigge red when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger.

For more information, see Section 11.0 “Enhanced

Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)”.

7.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in Asynchronous Count er mode. In this mode, a n external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute

the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).

DS41302D-page 60  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

T1CKI = 1 when TMR1 Enabled

T1CKI = 0 when TMR1 Enabled

Note 1: Arrows indicate counter increments.

2: I n Counter mode, a falling edge must be re gistered by the counter prior to the first incr ementing rising edge of

the clock.

7.10 ECCP Special Event Trigger (PIC12F615/617/HV615 only)

If a ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L register pair ef fe cti ve ly bec omes the period register for Timer1.

Timer1 should be sync hronized to the F the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed.

In the event that a write to TMR1H or TMR 1L coincide s with a Special Event Trigger from the ECCP, the write will take precedence.

FIGURE 7-2: TIMER1 INCREMENTING EDGE

OSC to utilize

For more information, see Section 11.0 “Enhanced

Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)”.

7.1 1 Comparator Synchronization

The same cl ock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module.

When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator chang es.

For more information, see Section 9.0 “Comparator Module”.

 2010 Microchip Technology Inc. DS41302D-page 61

PIC12F609/615/617/12HV609/615

7.12 Timer1 Control Register

The Timer1 Control register (T1CON), shown in Register 7-1, is used to control Timer1 and select the various features of the Timer1 module.

REGISTER 7-1: T1CON: TIMER 1 CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

T1GINV

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

TMR1GE

(2)

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 T1GINV: Timer1 Gate Invert bit

1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 6 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0: This bit is ignored If TMR1ON =

1 = Timer1 is on if Timer1 gate is active 0 = Timer1 is on

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off

For all other system clock modes: This bit is ignored. LP oscillator is disabled.

bit 2 T1SYNC

TMR1CS =

1 = Do not synchronize external clock inp ut 0 = Synchronize external clock input

TMR1CS = This bit is ignored. Timer1 uses the internal clock

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (F

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

: Timer1 External Clock Input Synchronization Control bit

OSC/4) or system clock (FOSC)

(1)

(2)

(3)

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G

3: See T1ACS bit in CMCON1 register.

DS41302D-page 62  2010 Microchip Technology Inc.

pin or COUT, as selected by the T1GSS bit of the CMCON1

PIC12F609/615/617/12HV609/615

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(1)

APFCON CMCON0 CMON COUT CMCON1 INTCON GIE PEIE PIE1 PIR1 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Note 1: PIC12F615/617/HV615 only.

— — — T1GSEL — — P1BSEL P1 ASEL ---0 --00 ---0 --00

CMOE CMPOL —CMR —CMCH0000 -0-0 0000 -0-0

— — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 ---0 0-10

T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x — ADIE — ADIF

(1) (1)

CCP1IE

CCP1IF

(1)

— CMIE — TMR2IE

(1)

— CMIF — TMR2IF

(1)

TMR1IE -00- 0-00 -00- 0-00

(1)

TMR1IF -00- 0-00 -00- 0-00

TMR1CS TMR1ON 0000 0000 uuuu uuuu

Value on

POR, BOR

Value on

all other

Resets

 2010 Microchip Technology Inc. DS41302D-page 63

PIC12F609/615/617/12HV609/615

NOTES:

DS41302D-page 64  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

Comparator

TMR2

Sets Flag

TMR2

Output

Reset

Postscaler

Prescaler

PR2

OSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

TOUTPS<3:0>

T2CKPS<1:0>

8.0 TIMER2 MODULE (PIC12F615/617/HV615 ONLY)

The Timer2 module is an 8-bit timer with the following features:

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

See Figure 8-1 for a block diagram of Timer2.

8.1 Timer2 Operation

The clock input to the Timer2 module is the system instruction clock (F Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescal er is the n use d to increment the TMR2 register.

The values of T MR2 and PR2 are co nstan tly comp ared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented

The match output of the Timer2/PR2 comparator is then fed into th e T i mer2 post sca ler. The postscaler has postscale op tions of 1 :1 to 1:16 i nclusiv e. The out put of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register.

OSC/4). The clock is fed into the

The TMR2 and PR2 registers are both fully readable and writable . On any Re set, th e TMR2 regis ter is set to 00h and the PR2 register is set to FFh.

Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned of f by clearing the TMR2ON bit to a ‘0’.

The Timer2 prescale r is co ntro lle d by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when:

• A write to TMR2 occurs.

• A write to T2CON occurs.

• Any device Reset oc curs (Power-on Rese t, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset).

Note: TMR2 is not cleared when T2CON is

written.

FIGURE 8-1: TIMER2 BLOCK DIAGRAM

 2010 Microchip Technology Inc. DS41302D-page 65

PIC12F609/615/617/12HV609/615

REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE PIE1 PIR1

(1)

PR2 TMR2 T2CON

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note 1: For PIC12F615/617/HV615 only.

DS41302D-page 66  2010 Microchip Technology Inc.

— ADIE — ADIF

Timer2 Module Period Register 1111 1111 1111 1111

(1)

Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000

(1)

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

(1) (1)

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 CCP1IE CCP1IF

(1) (1)

— CMIE —TMR2IE — CMIF —TMR2IF

(1)

TMR1IE -00- 0-00 -00- 0-00

(1)

TMR1IF -00- 0-00 -00- 0-00

Value on

POR, BOR

Value on

all other

Resets

PIC12F609/615/617/12HV609/615

–

VIN+ V

IN-

Output

VIN+

VIN-

Note: The black areas of the output of the

comparator represents the uncertainty due to input offsets and response time.

CMOE

MUX

CMPOL

CMON

(1)

CMCH

From Timer1

Clock

Note 1: When CMON = 0, the comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (F

OSC).

3: Q1 is held high during Sleep mode. 4: Output shown for reference only. See I/O port pin diagram for more details.

RD_CMCON0

Q3*RD_CMCON0

Set CMIF

Reset

CMV

IN-

CMV

IN+

GP1/CIN0-

GP4/CIN1-

CMSYNC

CMPOL

Data Bus

MUX

COUT

(4)

To PWM Auto-Shutdown

To Timer1 Gate

CMR

MUX

GP0/CIN+

MUX

CVREF

CMVREN

FixedRef

CMV

REF

SYNCCMOUT

9.0 COMPARATOR MODULE

The comparator can be used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative ma gnitudes. The comparat or is a very useful mixed signal building block because it provides analog functionality independent of the program execution. The Analog Comparator module includes the following features:

• Programmable input section

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

•PWM shutdown

• Time r1 gate (co unt ena ble )

• Output synchronization to Timer1 clock input

• Programmable voltage reference

• User-enable Comp arator Hysteresis

9.1 Comparator Overview

The comparator is shown in Figure 9-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at V

IN+ is less

than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at

IN-, the output of the comparat or is a digit al high le vel.

FIGURE 9-1:SINGLE COMPARATOR

FIGURE 9-2: COMPARATOR SIMPLIFIED BLOCK DIAGRAM

 2010 Microchip Technology Inc. DS41302D-page 67

PIC12F609/615/617/12HV609/615

RS < 10K

5 pF

VDD

VT  0.6V

RIC

ILEAKAGE ±500 nA

AIN

Legend: CPIN = Input Capa citance

LEAKAGE = Leakage Current at the pin due to various junctions

IC = Interconnect Resistance

S = Source Impe dance

A = Analog Voltage

T = Threshold Voltage

To Comparator

9.2 Analog Input Connection Considerations

A simplified circuit for an analog input is shown in Figure 9-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to V analog input, therefore , must be between V If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward bi ased and a latch-up may occur.

A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener dio de, should hav e very little leakage current to minimize inaccuracies introduced.

FIGURE 9-3: ANALOG INPUT MODEL

DD and VSS. The

SS and VDD.

Note 1: When reading a GPIO register, all pins

configured as anal og inp uts will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to consume more current than is specified.

DS41302D-page 68  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

9.3 Comparator Control

The comparator has two control and Configuration registers: CMCON0 and CMCON1. The CMCON1 register is used for controlling the interaction with Timer1 and simultaneously reading the comparator output.

The CMCON0 register (Register9-1) contain the control and Status bits for the following:

• Enable

• Input selection

• Reference selection

•Output selection

• Output polarity

9.3.1 COMPARATOR ENABLE

Setting the CMON bit of the CMCON0 register enables the comparator for operation. Clearing the CMON bit disables the comparator for minimum current consumption.

9.3.2 COMPARATOR INPUT SELECTION

The CMCH bit of the CMCON0 register directs one of four analog input pins to the comp arator inverting i nput.

Note: To use CIN+ and CIN- pins as analog

inputs, the appropriate bits must be set in the ANSEL register and the corres ponding TRIS bits must al so be set to dis able the output drivers.

9.3.3 COMPARATOR REFERENCE SELECTION

Setting the CMR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. See Section 9.10 “Comparator Voltage Reference” for more information on the internal voltage reference module.

9.3.5 COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register. Clearing CMPOL results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 9-1.

T ABLE 9-1: OUTPUT STATE VS. INPUT

CONDITIONS

Input Conditions CMPOL COUT

CMV

IN- > CMVIN+ 00

CMVIN- < CMVIN+ 01

IN- > CMVIN+ 11

CMV CMVIN- < CMVIN+ 10

Note: COUT refers to both the register bit and

output pin.

9.4 Comparator Response Time

The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference volta ge. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See Section 16.0 “Electrical Specifications” for more details.

9.3.4 COMPARATOR OUTPUT SELECTION

The output of the comparator can be monitored by reading either the COUT bit of the CMCON0 register . In order to make the output available for an external connection, the following conditions must be true:

• CMOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CMON bit of the CMCON0 register must be set.

Note 1: The CMOE bit overrides the PORT data

latch. Setting the CMON has no impact on the port override.

2: The internal output of the comparator is

latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.

 2010 Microchip Technology Inc. DS41302D-page 69

PIC12F609/615/617/12HV609/615

Q1 Q3 CIN+ COUT Set CMIF (edge) CMIF

TRT

reset by software

Q1 Q3 CIN+ COUT Set CMIF (edge) CMIF

TRT

reset by software

cleared by CMCON0 read

9.5 Comparator Interrupt Operation

The comparator interrupt flag can be set whenever there is a chang e in the o utput val ue of the compa rator . Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 9-4 and Figure 9-5). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latc h of the mism atch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. At this point the two mismatch latches have opposite output levels which is detected by the exclusive-or gate and fed to the interrupt circuitry. The mismatch condition persists until either the CMCON0 register is read or the comparator outp ut returns to the previous state.

Note 1: A write operation to the CMCON0 reg ister

will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle.

2: Comparator interrupts will operate

correctly regardless of the state of CMOE.

The comparator interrupt is set by the mismatch edge and not the mismatch level. This means that the interrupt flag can be res et w ithout the ad dition al st ep of reading or writing the CMCON0 register to clear the mismatch regi sters. Wh en the mism atch regis ters are cleared, an interrup t will oc cur upon the compara tor’s return to the previous state, otherwise no interrupt will be generated.

Software will need to maintain information about the status of the comparator output, as read from the CMCON1 register, to determine the actual change that has occurred.

The CMIF bit of the PIR1 register is the Comparator Interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a '1' to this register, an interrupt can be generated.

The CMIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CMIF bit of the PIR1 register wil l still b e set i f an inte rrupt cond ition occurs.

FIGURE 9-4: COMPARATOR

INTERRUPT TIMING W/O CMCON0 READ

FIGURE 9-5: COMPARATOR

INTERRUPT TIMING WITH CMCON0 READ

Note 1: If a change in the CMCON0 register

(COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF of the PIR1 register interrupt flag may not get set.

2: When a compar ator is fir st e nabled, bias

circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupt s.

DS41302D-page 70  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

9.6 Operation During Sleep

The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 16.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by clearing the CMON bit of the CMCON0 register.

A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, th e CMIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the SLEEP instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine.

9.7 Effects of a Reset

A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state.

 2010 Microchip Technology Inc. DS41302D-page 71

PIC12F609/615/617/12HV609/615

REGISTER 9-1: CMCON0: COMPARATOR CONTROL REGISTER 0

R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0

CMON COUT CMOE CMPOL — CMR — CMCH

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CMON: Comparator Enable bit

1 = Comparator is enabled 0 = Comparator is disabled

bit 6 COUT: Comparator Output bit

If C1POL = COUT = 0 when CMVIN+ > CMVIN- COUT = 1 when CMV If C1POL = COUT = 1 when CMVIN+ > CMVIN- COUT = 0 when CMV

bit 5 CMOE: Comparat or Output Enable bit

1 = COUT is present on the COUT pin 0 = COUT is internal only

bit 4 CMPOL: Comparator Output Polarity Select bit

1 = COUT logic is inverted 0 = COUT logic is not inverted

bit 3 Unimplemented: Read as ‘0’ bit 2 CMR: Comparator Reference Select bit (non-inverting input)

1 = CMVIN+ connects to CM VREF output 0 = CMV

bit 1 Unimplemented: Read as ‘0’ bit 0 CMCH: Comparator C1 Channel Select bit

0 = CMVIN- pin of the Comparator connects to CIN0- 1 = CMV

1 (inverted polarity):

IN+ < CMVIN-

0 (non-inverted polarity):

IN+ < CMVIN-

(1)

IN+ connects to CIN+ pin

IN- pin of the Comparator connects to CIN1-

Note 1: Comparator output requires the following three conditions: CMOE = 1, CMON = 1 and corr espon ding p ort

TRIS bit = 0.

DS41302D-page 72  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

9.8 Comparator Gating Timer1

This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator. This requires that Timer1 is on and gating is enabled. See Section 7.0 “Timer1 Module with Gate Control” for details.

It is recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment.

9.9 Synchronizing Comparat or Output to Timer1

The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the fa llin g edge of t he Timer1 clock sou rce. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock s ource and Timer1 increme nts on the risi ng edge of its c lock source. See the Compar ator Block Diagra m (Figure 9-

2) and the Timer1 Bloc k Diagram (Figure 7-1) for more

information.

REGISTER 9-2: CMCON1: COMPARATOR CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-0

— — — T1ACS CMHYS — T1GSS CMSYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1ACS: Timer1 Alternate Clock Select bit

1 = Timer 1 Clock Source is System Clock (F 0 = Timer 1 Clock Source is Instruction Clock (F

bit 3 CMHYS: Comparator Hysteresis Select bit

1 = Comparator Hysteresis enabled 0 = Comparator Hysteresis disabled

bit 2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer 1 Gate Source is comparator output

bit 0 CMSYNC: Comparator Output Synchronization bit

1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous

Note 1: Refer to Section 7.6 “Timer1 Gate”.

2: Refer to Figure 9-2.

OSC)

(1)

OSC\4)

(2)

 2010 Microchip Technology Inc. DS41302D-page 73

PIC12F609/615/617/12HV609/615

VRR 1 (low range):=

VRR 0 (high range):=

REF (VDD/4) + =

REF (VR<3:0>/24) VDD=

(VR<3:0> V

DD/32)

9.10 Comparator Voltage Reference

The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available:

• Independent from Comparator operation

• 16-level voltage range

• Output clamped to V

• Ratiometric with VDD

• Fixed Reference (0.6) The VRCON register (Register 9-3) controls the

Voltage Reference module shown in Register 9-6.

9.10.1 INDEPENDENT OPERATION

The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference.

9.10.2 OUTPUT VOLTAGE SELECTION

The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register.

The CVREF output voltage is determined by the

following equations:

EQUATION 9-1: CVREF OUTPUT VOLTAGE

9.10.3 OUTPUT CLAMPED TO VSS

The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows:

• FVREN = 0 This allows the comparator to detect a zero-crossing

while not consuming additional CV

REF module current.

9.10.4 OUTPUT RATIOMETRIC TO VDD

The comparator voltage reference is VDD d erived and therefore, the CV

DD. The tested absolute accur acy of the Comparator

V Voltage Reference can be found in Section 16.0 “Electrical Specificat ions”.

REF output changes with fluctuations in

9.10.5 FIXED VOLTAGE REFERENCE

The fixed volta ge reference is independent o f VDD, with a nominal output volt age of 0.6V. This reference can be enabled by setting the FVREN bit of the VRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active.

9.10.6 FIXED VOLTAGE REFERENCE STABILIZATION PERIOD

When the Fixed V o lta ge Refe rence mo dule is enable d, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See Section 16.0 “Electrical Specifications” for the minimum delay requirement.

The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 9-6.

9.10.7 VOLTAGE REFERENCE SELECTION

Multiplexers on the output of the Voltage Reference module enable selection of either the CV voltage reference for use by the comparators.

Setting the CMVREN bit of the VRCON register enables current to flow in the CV and selects the CV ator. Clearing the CMVREN bit selec ts the fi xed voltag e for use by the Comparator.

When the CMVREN bit is cleared, current flow in the

REF voltag e divide r is disabl ed mini mizing the pow er

CV drain of the voltage reference peripheral.

REF voltage for use by the Compar-

REF or fixed

REF voltage divider

DS41302D-page 74  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

VRR

VR<3:0>

(1)

Analog

8RRR RR

16 Stages

VDD

MUX

Fixed Voltage

CMVREN

REF

(1)

Reference

FVREN

Sleep HFINTOSC enable

0.6V

FixedRef

To Comparators and ADC Module

Note 1: Care should be taken to ensure CV

REF remains within the comparator common mode input range. See

Section 16.0 “Electrical Specifications” for more detail.

FIGURE 9-6: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

 2010 Microchip Technology Inc. DS41302D-page 75

PIC12F609/615/617/12HV609/615

REGISTER 9-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CMVREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— VRR FVREN VR3 VR2 VR1 VR0

bit 7 CMVREN: Comparator Voltage Reference Enable bit

1 = CVREF circuit powered on and routed to CVREF input of the Comparator 0 = 0.6 Volt constant reference routed to CV

bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CV

1 = Low range 0 = High range

bit 4 FVREN: 0.6V Reference Enable bit

1 = Enabled 0 = Disabled

bit 3-0 VR<3:0>: Comparator Voltage Reference CV

When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

Note 1: When CMVREN is low, the CVREF circuit is powered down and do es not contribute to IDD current.

2: When CMVREN is low and the FVREN bit is low, the CVREF signal should provide Vss to the comparator.

REF Range Selection bit

(2)

REF input of the Comparator

REF Value Selection bits (0  VR<3:0>  15)

(1, 2)

DS41302D-page 76  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

–

VIN+

IN-

Output

Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time.

VH-

H+

VIN-

V+

IN+

Output

(Without Hysteresis)

Output

(With Hyste resis)

9.11 Comparator Hysteresis

Each comparator has built-in hysteresis that is user enabled by setting the CMHYS bit of the CMCON1 register . The hystere sis feature can hel p filter noise an d reduce multiple com parator outpu t transitions wh en the output is changing state.

FIGURE 9-7: COMPARATOR HYSTERESIS

Figure 9-7 shows the relationship between the analog input levels and di gital output of a com p a rator with and without hysteresis. The output of the comparator changes from a low sta te to a hi gh s t ate only wh en the analog voltage at V hysteresis threshold (V comparator changes from a high state to a low state only when the analog voltage at V lower hysteresis threshold (V

IN+ rises above the upper

H+). The output of the

IN+ falls below the

H-).

 2010 Microchip Technology Inc. DS41302D-page 77

PIC12F609/615/617/12HV609/615

TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND

VOLTAGE REFERENCE MODULES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSEL CMCON0 CMON COUT CMOE CMPOL CMCON1 INTCON GIE PEIE PIE1 PIR1 GPIO TRISIO VRCON CMVREN

Legend:

— ADCS2

— — — T1ACS CMHYS — T1GSS CM SYNC 0000 0000 0000 0000

— ADIE — ADIF — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

(1)

(1) (1)

— VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 0-00 0000

(1)

ADCS1

T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x

(1)

CCP1IE

(1)

CCP1IF

(1)

ADCS0

—CMIE— TMR2IE —CMIF— TMR2IF

ANS3 ANS2

—CMR —CMCH0000 -000 0000 -000

(1)

ANS1 ANS0 -000 1111 -000 1111

(1) (1)

Note 1: For PIC12F615/617/HV615 only .

TMR1IE -00- 0-00 -00- 0-00 TMR1IF -00- 0-00 -00- 0-00

Value on

POR, BOR

Value on all other

Resets

DS41302D-page 78  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

GP0/AN0

A/D

GP1/AN1/VREF

GP2/AN2

REF

VDD

VREF

ADON

GO/DONE

VCFG = 1

VCFG = 0

CHS

VSS

0.6V Reference

1.2V Reference

GP4/AN3

ADRESH ADRESL

ADFM

0 = Left Justify 1 = Right Justify

000 001 010 011 100 101 110

10.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC12F615/617/HV615 ONLY)

The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH).

The ADC voltage reference is software selectable to either V pins.

The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wak e-up the device from Sleep.

Figure 10-1 shows the block diagram of the ADC.

FIGURE 10-1: ADC BLOCK DIAGRAM

DD or a voltage appli ed to the ex ternal reference

Note: The ADRESL and ADRESH registers are

Read Only.

 2010 Microchip Technology Inc. DS41302D-page 79

PIC12F609/615/617/12HV609/615

10.1 ADC Configuration

When configuring and using the ADC the following functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Results formatting

10.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding port section for more information.

Note: Analog voltages on any pin that is defined

as a digital input may cause the input buffer to conduct excess current.

10.1.2 CHANNEL SELECTION

The CHS bits of the ADCON0 regi ster determ ine which channel is connected to the sample and hold circuit.

When changing channels, a delay is required before starting the next conversion. Refer to Section 10.2 “ADC Operation” for more information.

10.1.3 ADC VOLTAGE REFERENCE

The VCFG bit of the ADCON0 register prov ides contro l of the positive voltage reference. The positive voltage reference can be either V source. The negative voltage reference is always connected to the ground reference.

DD or an external voltage

10.1.4 CONVERSION CLOCK

The source of the conversion clock is software selectable via the ADCS bits of the ANSEL register. There are seven possible clock options:

OSC/2

•F

OSC/4

•FOSC/8

•FOSC/16

•F

OSC/32

•FOSC/64

•FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as

AD. One full 10-bit con ve r si on requ ire s 11 T AD periods

T as shown in Figure10-3.

For correct conversion, the appropriate T must be met. See A/D conversion requirements in Section 16.0 “Electrical Specifications” for more information. Table 10-1 gives examples of appropriate ADC clock selections.

Note: Unless using the FRC, any changes in the

system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.

AD specification

DS41302D-page 80  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9

Set GO/DONE bit

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

b9 b8 b7 b6 b5 b4 b3 b2

TAD10 TAD11

b1 b0

TCY to TAD

Conversion Starts

ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input

TABLE 10-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)

ADC Clock Period (T

ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz

OSC/2 000 100 ns

FOSC/4 100 200 ns

OSC/8 001 400 ns

F FOSC/16 101 800 ns FOSC/32 010 1.6 s4.0 s 8.0 s FOSC/64 110 3.2 s 8.0 s

FRC x11 2-6 s

Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.

2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the F

conversion will be performed during Sleep.

AD) Device Frequency (FOSC)

(2) (2) (2) (2)

(1,4)

(2)

250 ns 500 ns

1.0 s

(2)

500 ns

(2)

1.0 s

2.0 s 8.0 s

2.0 s4.0 s 16.0 s

(3)

(1,4)

2-6 s

RC clock source is only recommended if the

16.0 s

2-6 s

(1,4)

(2)

(3)

2.0 s

4.0 s

32.0 s

64.0 s

2-6 s

(3)

(3) (3) (3)

(1,4)

FIGURE 10-2: ANALOG-TO-DIGITAL CONVERSION T

AD CYCLES

10.1.5 INTERRUPTS

The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is th e ADIF bit in the PIR1 register . The ADC inte rrupt en able i s the AD IE bit in the PIE1 register. The ADIF bit must be cleared in software.

Note: The ADIF bit is set at the completion of

every conversion, regardless of whether or not the ADC interrupt is enabled.

This interrupt can be generated while the device is operating or while in Sle ep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is al w ays exe cu ted . If the user is att em ptin g to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrup t Service Routine.

Please see Section 10.1.5 “Interrupts” for more information.

 2010 Microchip Technology Inc. DS41302D-page 81

PIC12F609/615/617/12HV609/615

10.1.6 RESULT FORMATTING

The 10-bit A/D conversion res ult can be suppl ied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format.

Figure 10-4 shows the two output formats.

FIGURE 10-3: 10-BIT A/D CONVERSION RESULT FORMAT

ADRESH ADRESL

(ADFM = 0)MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

10.2 ADC Operation

10.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion.

Note: The GO/DONE bit should not be set in the

same instruction that turns on the ADC. Refer to Section 10.2.6 “A/D Conver- sion Procedure”.

10.2.2 COMPLETION OF A CONVERSION

When the convers ion is complet e, the ADC module will:

• Clear the GO/DONE

• Set the ADIF flag bit

• Update the ADRESH:ADR ESL registers with new conversion result

10.2.3 TERMINATING A CONVERSION

If a conversi on must be ter min ated bef ore co mplet ion , the GO/DONE ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the prev ious conversi on. Additionally, a 2 T sition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel.

AD delay is required before anothe r acqui-

bit

bit can be cleared in software. The

MSB LSB

10.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option. When the FRC clock source is selected, the ADC waits one ad ditional instructi on before star ting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set.

When the ADC clock source is something other than

RC, a SLEEP instruction causes the present

F conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.

10.2.5 SPECIAL EVENT TRIGGER

The ECCP Special Ev ent Trigger allow s peri odic A DC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero.

Using the Special Event Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met.

See Section 11.0 “Enhanced Capture/Compare/

PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)” for more

information.

Note: A device Reset forces all registers to their

Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.

DS41302D-page 82  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL TRISIO ; BSF TRISIO,0 ;Set GP0 to input BANKSEL ANSEL ; MOVLW B’01110001’ ;ADC Frc clock, IORWF ANSEL ; and GP0 as analog BANKSEL ADCON0 ; MOVLW B’10000001’ ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;Store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space

10.2.6 A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to perform an Analog-to-Digital conversion:

1. Configure Port:

• Disable pin output driver (See TRIS register)

• Configure pin as analog

2. Configure the ADC module:

• Select ADC conversion cl ock

• Configure voltage reference

• Select ADC input channel

• Select result format

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt

4. Wait the required acquisition time

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC co nver si on t o c ompl ete by one of the following:

• Polling the GO/DONE

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result

8. Clear the ADC interru pt flag (requi red if interru pt is enabled).

(1)

bit

(2)

EXAMPLE 10-1: A/D CONVERSION

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep and resume in-line code execution.

2: See Section 10.3 “A/D Acquisition

Requirements”.

 2010 Microchip Technology Inc. DS41302D-page 83

PIC12F609/615/617/12HV609/615

10.2.7 ADC REGISTER DEFINITIONS

The following registers are used to control the operation of the ADC.

REGISTER 10-1: ADCON0: A/D CONTROL REGISTER 0

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justified 0 = Left justified

bit 6 VCFG: Voltage Refe ren ce bit

REF pin

1 = V 0 = V

bit 5 Unimplemented: Read as ‘0’ bit 4-2 CHS<2:0>: Analog Channel Select bits

000 = Channel 00 (AN0) 001 = Channel 01 (AN1) 010 = Channel 02 (AN2) 011 = Channel 03 (AN3) 100 = CV 101 = 0.6V Reference 110 = 1.2V Reference 111 = Reserved. Do not use.

bit 1 GO/DONE

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled 0 = ADC is disabled and consumes no operating current

REF

: A/D Conversion Status bit

Note 1: When the CHS<2:0> bits change to select the 1.2V or 0.6V reference, the reference output voltage will

have a transient. If the Comparator module uses this 0.6V reference voltage, the comparator output may momentarily change state due to the transient.

DS41302D-page 84  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

REGISTER 10-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY)

R-x R-x R-x R-x R-x R -x R-x R-x

ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES <9:2> : ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 10-3: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY)

R-x R-x U-0 U-0 U-0 U-0 U-0 U-0

ADRES1 ADRES0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— — — — — —

bit 7-6 ADRES <1:0> : ADC Result Register bits

Lower 2 bits of 10-bit conversion result

bit 5-0 Unimplem ented: Read as ‘0’

REGISTER 10-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY)

U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x

— — — — — — ADRES9 ADRES8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplem ented: Read as ‘0’ bit 1-0 ADRES <9:8> : ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 10-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY)

R-x R-x R-x R-x R-x R -x R-x R-x

ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES <7:0> : ADC Result Register bits

Lower 8 bits of 10-bit conversion result

 2010 Microchip Technology Inc. DS41302D-page 85

PIC12F609/615/617/12HV609/615

TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=

AMP TC TCOFF++=

2µs T

C Temperature - 25°C0.05µs/°C++=

TC CHOLD RIC RSS RS++ ln(1/2047)–=

10pF 1k



7k10k



++– ln(0.0004885)=

1.37

= µs

ACQ 2µs 1.37µs 50°C- 25°C0.05µs/°C++=

4.67µs=

VAPPLIED 1e

Tc–

-------- -

–







VAPPLIED 1

2047

----------- -

–





VAPPLIED 1

2047

----------- -

–





VCHOLD=

VAPPLIED 1e

TC–

--------- -

–







VCHOLD=

;[1] VCHOLD charged to within 1/2 lsb

;[2] V

CHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for T

C can be approximated with the following equations:

Solving for T

Therefore:

Temperature 50°C and external impedance of 10k



5.0V V DD=

Assumptions:

10.3 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge holding capacitor (C charge to the input channel voltage level. The Analog Input model is shown in Figure 10-4. The source impedance (R impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (V

The maximum recommended impedance for analog sources is 10 k. As the source impedance is

decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed),

EQUATION 10-1: ACQUISITION TIME EXAMPLE

HOLD) must be allowed to fully

S) and the internal sampling switch (RSS)

DD), see Figure 10-4.

an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 10-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum er ror allow ed for the ADC to meet its specified resolution.

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

HOLD) is not discharged after each conversion.

DS41302D-page 86  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

CPIN

ANx

5 pF

VT = 0.6V

T = 0.6V

LEAKAGE

RIC  1k

Sampling Switch

Rss

HOLD = 10 pF

SS/VREF-

Sampling Switch

5V 4V 3V 2V

567891011

(k)

± 500 nA

Legend: CPIN

VT I LEAKAGE

RIC SS C

HOLD

= Input Capacitance = Threshold Voltage

= Leakage current at the pin due to = Interconnect Resistance

= Sampling Switch = Sample/Hold Capacitance

various junctions

RSS

3FFh 3FEh

ADC Output Code

3FDh 3FCh

004h 003h 002h 001h 000h

Full-Scale

3FBh

1 LSB ideal

SS/VREF-

Zero-Scale Transition

DD/VREF+

Transition

1 LSB ideal

Full-Scale Range

Analog Input Voltage

FIGURE 10-4: ANALOG INPUT MODEL

FIGURE 10-5: ADC TRANSFER FUNCTION

 2010 Microchip Technology Inc. DS41302D-page 87

PIC12F609/615/617/12HV609/615

TABLE 10-2: SUMMARY OF ASSOCIATED ADC REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0

ADCON0 ANSEL ADRESH ADRESL GPIO INTCON GIE PEIE PIE1 PIR1 TRISIO

(1)

ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000

—

(1,2)

A/D Result Register High Byte xxxx xxxx uuuu uuuu

(1,2)

A/D Result Register Low Byte xxxx xxxx uuuu uuuu

ADCS2

(1)

ADCS1

(1)

ADCS0

(1)

ANS3 ANS2

(1)

ANS1 ANS0 -000 1111 -000 1111

— — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 --x0 x000

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 —ADIE —ADIF

(1) (1)

CCP1IE

CCP1IF

(1)

— CMIE — TMR2IE

(1)

— CMIF — TMR2IF

(1)

TMR1IE -00- 0-00 -00- 0-00

(1)

TMR1IF -00- 0-00 -00- 0-00

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note 1: For PIC12F615/617/HV615 only.

2: Read Only Register.

Val ue on

POR, BOR

Value on all other

Resets

DS41302D-page 88  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

11.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTOSHUTDOWN AND DEAD BAND) MODULE (PIC12F615/617/

event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle.

Table 11-1 shows the timer resources required by the ECCP module.

HV615 ONLY)

The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The Compare mode allows the user to trigger an external

REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER

R/W-0

P1M

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

U-0

—

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

T ABLE 11-1: ECCP MODE – TIMER

RESOURCES REQUIRED

ECCP Mode Timer Resource

Capture Timer1

Compare Timer1

PWM Timer2

bit 7 P1M: PWM Output Configuration bits

f CCP1M<3:2> = 00, 01, 10:

I x = P1A assigned as Capture/Compare input; P1B assigned as port pins If CCP1M<3:2> = 11:

0 = Single output; P1A modulated; P1B assigned as port pins 1 = Half-Bridge output; P1A, P1B modulated with dead-band control

bit 6 Unimplemented: Read as ‘0’

bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode: Unused. Compare mode: Unused. PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0 CCP1M<3:0>: ECCP Mode Se lec t bits

0000 =Capture/Compare/PWM off (resets ECCP module) 0001 =Unused (reserved) 0010 =Compare mode, toggle output on match (CCP1IF bit is set) 0011 =Unused (reserved) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCP1IF bit is set) 1001 =Compare mode, clear output on match (CCP1IF bit is set) 1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 =Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2 and starts

an A/D conversion, if the ADC module is enabled)

1100 =PWM mode; P1A active-high; P1B active-high 1101 =PWM mode; P1A active-high; P1B active-low 1110 =PWM mode; P1A active-low; P1B active-high 1111 =PWM mode; P1A active-low; P1B active-low

 2010 Microchip Technology Inc. DS41302D-page 89

PIC12F609/615/617/12HV609/615

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR1 register)

Capture Enable

CCP1CON<3:0>

Prescaler

 1, 4, 16

and

Edge Detect

CCP1

System Clock (F

OSC)

BANKSEL CCP1CON ;Set Bank bits to point

;to CCP1CON CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler

; move value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this

; value

11. 1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 regi ster when an event occu rs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge When a capture i s m ade, the I nterrupt Re quest Flag bit

CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old capture d value is overwri tten by the new captured value (see Figure 11-1).

11.1.1 CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit.

Note: If the CCP1 pin is configured as an o utput,

a write to the port can cause a capture condition.

11.1.2 TIMER1 MODE SELECTION

Timer1 must be running in T im er mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.

11.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt en able bit o f the PIE1 re gister clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode.

11.1.4 CCP PRESCALER

There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. A ny Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected op eration, turn the mo dule off by clearing the CCP1CON register before changing the prescaler (see Example 11-1).

FIGURE 11-1: CAPTURE MODE

OPERATION BLOCK DIAGRAM

EXAMPLE 11-1: CHANGING BETWEEN

CAPTURE PRESCALERS

DS41302D-page 90  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0

CCP1CON CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H C apture/Com pare/PW M Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE PIE1 PIR1 T1CON T1G INV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TRISIO

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture. Note 1: For PIC12F615/617/HV615 only.

P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP 1M0 0-00 0000 0-00 0000

T0IE INTE GPIE T0IF INTF GPIF — ADIE — ADIF

— —TRISIO5TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

(1)

CCP1IE CCP1IF

(1)

— CMIE — TMR2IE

(1)

— CMIF — TMR2IF

(1)

TMR1IE -00- 0-00 -00- 0-00

(1)

TMR1IF -00- 0-00 -00- 0-00

TMR1CS TMR1ON

Value on

POR, BOR

0000 0000 0000 0000

0000 0000 uuuu uuuu

Value on

all other

Resets

 2010 Microchip Technology Inc. DS41302D-page 91

PIC12F609/615/617/12HV609/615

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCP1IF Interrupt Flag

(PIR1)

Match

TRIS

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

• Clear TMR1H and TMR1L registers.

• NOT set interrupt flag bit TMR1IF of the PIR1 register.

• Set the GO/DONE

bit to start the ADC conversion.

CCP1

11.2 Compare Mode

In Compare mo de, th e 16- bit CC PR1 re gist er va lue is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may:

• Toggle the CCP1 output.

• Set the CCP1 output.

• Clear the CCP1 output.

• Generate a Special Event Trigger.

• Generate a Software Interrupt. The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt.

FIGURE 11-2: COMPARE MODE

OPERATION BLOCK DIAGRAM

11.2.2 TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.

11.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register).

11.2.4 SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled The CCP1 module does not assert contro l of the CCP 1

pin in this mode (see the CCP1CON register). The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next risi ng edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1.

11.2.1 CCP1 PIN CONFIGURATION

The user must configure the C CP 1 pin a s an out put b y clearing the associated TRIS bit.

Note: Clearing the CCP1CON register will force

the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit TMRxIF of the PIR1 register.

2: Removing the match condition by

changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the T imer1 Res et, will preclud e the Reset from occurring.

DS41302D-page 92  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCP1CON CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE PIE1 PIR1 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Compare. Note 1: For PIC12F615/617/HV615 only.

P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP 1M0 0-00 0000 0-00 0000

T0IE INTE GPIE T0IF INTF GPIF — ADIE — ADIF

— —TRISIO5TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

(1) (1)

CCP1IE CCP1IF

(1)

— CMIE — TMR2IE

(1)

— CMIF — TMR2IF

(1)

TMR1IE -00- 0-00 -00- 0-00

(1)

TMR1IF -00- 0-00 -00- 0-00

TMR1CS TMR1ON

Value on

POR, BOR

0000 0000 0000 0000

0000 0000 uuuu uuuu

Value on

all other

Resets

 2010 Microchip Technology Inc. DS41302D-page 93

PIC12F609/615/617/12HV609/615

CCPR1L

CCPR1H

(2)

(Slave)

Comparator

TMR2

PR2

(1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer2, toggle CCP1 pin and latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (F

OSC), or

2 bits of the prescaler, to create the 10-bit time base.

2: In PWM mode, CCPR1H is a read-only register.

TRIS

CCP1

Comparator

Period

Pulse Width

TMR2 = 0

TMR2 = CCPRxL:CCPxCON<5:4>

TMR2 = PR2

11.3 PWM Mode

The PWM mode gene rates a Pulse-Width Mod ulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers:

•PR2

•T2CON

• CCPR1L

• CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP

module produces up to a 10 -bit resol ution PWM output on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT dat a latch, the TRIS for that pin m ust be cleared to enable the CCP1 pin output driver.

Note: Clearing the CCP1CON register will

relinquish CCP1 control of the CCP1 pin.

Figure 11-3 shows a simplified block diagram of PWM operation.

Figure 11-4 shows a typical waveform of the PWM signal.

For a step-by-step proc edure on how t o set up the CC P module for PWM operation, see Section 11.3.7 “Setup for PWM Operation”.

The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle).

FIGURE 11-4: CCP PWM OUTPUT

FIGURE 11-3: SIMPLIFIED PWM BLOCK

DIAGRAM

DS41302D-page 94  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

PWM Period PR21+4TOSC =

(TMR2 Pre scale Value)

Pulse Width CCPR1L:CCP1CON<5:4>



OSC



(TMR2 Pre scale Value)

Duty Cycle Ratio

CCPR1L:CCP1CON<5:4>

4PR2 1+

-----------------------------------------------------------------------=

Resolution

4PR2 1+log

2log

------------------------------------------ bits=

11.3.1 PWM PERIOD

The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation11-1.

EQUATION 11-1: PWM PERIOD

When TMR2 is eq ual to PR2, the followi ng three ev ents occur on the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)

• The PWM duty cycle is latched from CCPR1L i nto CCPR1H.

Note: The Timer2 postscaler (see Section 8.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency.

11.3.2 PW M DUTY CYCL E

The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only.

Equation 11-2 is used to calculate the PWM pulse width.

Equation 11-3 is used to calculate the PWM duty cy cl e ratio.

EQUATION 11-2: PULSE WIDTH

EQUATION 11-3: DUTY CYCLE RATIO

The CCPR1H register and a 2-bit internal latch are used to double buf fer the PWM duty cycle. Thi s doubl e buffering is essential for glitchless PWM operation.

The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (F the prescaler, to create the 10-bit time ba se. The system clock is used if the Timer2 prescaler is s et to 1:1.

When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP 1 pin is cleared (see Fig ure 11-

3).

OSC), or 2 bits of

11.3.3 PW M RES O LUTION

The resolutio n determine s the number of availabl e duty cycles for a giv en period. F or example, a 10-bit resol ution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 di sc re te duty cycles.

The maximum PWM resolution is 10 bits when PR2 is

255. The resolution is a function of the PR2 register value as shown by Equation 11-4.

EQUATION 11- 4: PWM RESOLUTION

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will remain unchanged.

TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 11-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5

 2010 Microchip Technology Inc. DS41302D-page 95

OSC = 20 MHz)

OSC = 8 MHz)

PIC12F609/615/617/12HV609/615

11.3.4 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment and the state of the module will not cha nge. If the CCP1 pin is driving a value , it wi ll cont inue to d rive th at valu e. When the device wak es up, TMR2 wil l continue from its previous state.

11.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY

The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 4.0 “Oscillator Module” for additional details.

11.3.6 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the CCP registers to their Reset states.

11.3.7 SETUP FOR PWM OPERATION

The following steps should be taken when configuring the CCP module for PWM operation:

1. Disable the PWM pin (CCP1) output drivers by setting the associated TRIS bit.

2. Set the PWM period by loa ding the PR2 register .

3. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values.

4. Set the PWM duty cycle by loading the CCPR1L register and DC1B bits of the CCP1CON register.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the PIR1 register.

• Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register.

• Enable Timer2 by setting the TMR2ON bit of the T2CON register.

6. Enable PWM ou tput af ter a n ew PWM cycle has started:

• Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set).

• Enable the CCP1 pin output driver by clearing the associated TRIS bit.

DS41302D-page 96  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers

CCP1<1:0>

Clear Timer2, toggle PWM pin and latch duty cycle

* Alternate pin function.

Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.

TRISIO2

CCP1/P1A

Output

Controller

P1M<1:0>

CCP1M<3:0> 4

PWM1CON

CCP1/P1A

P1B

TRISIO5

CCP1/P1A*

P1ASEL

(APFCON<0>)

TRISIO0

P1B

TRISIO4

P1B*

P1BSEL

(APFCON<1>)

11. 4 PWM (Enhanced Mode)

The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes:

• Single PWM

• Half-Bridge PWM To select an Enhanced PWM mode, the P1M bits of the

CCP1CON register must be set appropriately.

The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately.

Table 11-6 shows the pin assignments for each Enhanced PWM mode.

Figure 11-5 shows an example of a simplified block diagram of the Enhanced PWM module.

Note: To prevent the generation of an

incomplete waveform when the PWM is first enabled, the ECCP module wait s until the start of a new PWM period before generating a PWM signal.

FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIA GRAM O F THE E NH ANCED PWM MO DE

Note 1: The TRIS register value for each PWM output must be configured appropriately.

2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.

TABLE 11-6: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

ECCP Mode P1M<1:0> CCP1/P1A P1B

Single 00 Yes Half-Bridge 10 Yes Yes

 2010 Microchip Technology Inc. DS41302D-page 97

(1)

Yes

(1)

PIC12F609/615/617/12HV609/615

Period

Signal

PR2+1

P1M<1:0>

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inactive

P1D Modulated

Pulse Width

(Single Output)

(Half-Bridge)

Delay

(1)

Delay

(1)

Relationships:

• Period = 4 * T

OSC * (PR2 + 1) * (TMR2 Prescale Va lue)

• Pulse Width = T

OSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

• Delay = 4 * T

OSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay

mode”).

Period

Signal

PR2+1

P1M<1:0>

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inactive

P1D Modulated

Pulse Width

(Single Output)

(Half-Bridge)

Delay

(1)

Delay

(1)

Relationships:

• Period = 4 * T

OSC * (PR2 + 1) * (TMR2 Prescale Value)

• Pulse Width = T

OSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

• Delay = 4 * T

OSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay

mode”).

FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

DS41302D-page 98  2010 Microchip Technology Inc.

PIC12F609/615/617/12HV609/615

Period

Pulse Width

(1)

P1A

(2)

P1B

(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TM R2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

P1A

P1B

FET Driver

Load

FET Driver

V+

Load

FET Driver

P1A

P1B

Standard Half-Bridge Circuit (“Push-Pull”)

Half-Bridge Output Driving a Full-Bridge Circuit

11.4.1 HALF-BRIDGE MODE

In Half-Bridge mode, two p ins are used as outputs to drive push-pull loads. The PWM outp ut sign al is output on the CCP1/P1A pin, whil e the complementary PWM output signal is output on the P1B pin (see Figure 11-8).

Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs.

FIGURE 11-8: EXAMPLE OF HALF-

This mode can be used for Half-Bridge applications, as shown in Figure 11-9, or for Full-Bridge applications, where four power switch es are being modulated with two PWM signals.

In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in HalfBridge power devices. The value of the PDC<6:0> bits of the PWM1CON register sets the number of instruction cycles before the output is dr iven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See

Section 11.4.6 “Programmable Dead-Band Delay mode” for more details of the dead-band delay

operations.

FIGURE 11-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS

BRIDGE PWM OUTPUT

 2010 Microchip Technology Inc. DS41302D-page 99

PIC12F609/615/617/12HV609/615

11.4.2 START-UP CONSIDERATIONS

When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins.

Note: When the microcontroller is released from

Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devi ces in the OFF state until the microcontroller drives the I/O pins with the p roper signal l evels or activates the PWM output(s).

The CCP 1M<1:0> bits of the CC P1CON register allow the user to choose whe the r th e P WM output si gna ls are active-high or acti ve-low for e ach PWM out put pin (P 1A and P1B). The PWM outp ut polarit ies must be sele cted before the PWM pin output drivers are enabled. Changing the polarity con figuration while the PWM pin output drivers are enable is no t recommended since it may result in damage to the application circuits.

The P1A and P1B output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanc ed PWM modes must be enabled in the prop er Output mode and comp lete a full PWM cycle before configuring the PWM pin output drivers. The completi on of a full PWM cycle is in dicated by the TMR2IF bit of t he PIR1 regi ster being se t as the second PWM period begins.

11.4.3 OPERATION DURING SLEEP

When the device is placed in sleep, the allocated timer will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state.

DS41302D-page 100  2010 Microchip Technology Inc.

Datasheet PIC12F609, PIC12F615, PIC12F617, PIC12HV609, PIC12HV615 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance RISC CPU:

Special Microcontroller Features:

Low-Power Features:

Peripheral Features:

8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)

8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC12F609/HV609 BLOCK DIAGRAM

FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM

T ABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION

TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

2.2 Data Memory Organization

2.2.1 GENERAL PURPOSE REGISTER FILE

2.2.2 SPECIAL FUNCTION REGISTERS

TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

TABLE 2-2: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

T ABLE 2-4: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

REGISTER 2-1: STATUS: STATUS REGISTER

REGISTER 2-2: OPTION_REG: OPTION REGISTER

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

REGISTER 2-6: PCON: POWER CONTROL REGISTER

2.3 PCL and PCLATH

2.3.2 STACK

2.4 Indirect Addressing, INDF and FSR Registers

2.3.1 MODIFYING PCL

EXAMPLE 2-1: INDIR ECT ADDRES SING

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615

3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY)

3.1 PMADRH and PMADRL Registers

3.2 PMCON1 and PMCON2 Registers

REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA REGISTER

REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS REGISTER

REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

REGISTER 3-5: PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h)

3.3 Reading the Flash Program Memory

EXAMPLE 3-1: FLASH PROGRAM READ

FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

3.5 Protection Against Spurious Write

3.6 Operation During Code-Protect

3.7 Operation During Write Protect

FIGURE 3-2: BLOCK WRITES TO 2K FLASH PROGRAM MEMORY

FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION

EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY

4.0 OSCILLATOR MODULE

4.1 Overview

FIGURE 4-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

4.2 Clock Source Modes

4.3 External Clock Modes

4.3.1 OSCILLATOR START-UP TIMER (OST)

TABLE 4-1: OSCILLATOR DELAY EXAMPLES

4.3.2 EC MODE

4.3.3 LP, XT, HS MODES

4.3.4 EXT ERN AL RC MODES

FIGURE 4-5: EXTERNAL RC MODES

4.4 Internal Clock Modes

4.4.1 INTOSC AND INTOSCIO MODES

REGISTER 4-1: OSCTUNE: OSCILLATOR TUNING REGISTER

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

5.0 I/O PORT

5.1 GPIO and the TRISIO Registers

EXAMPLE 5-1: INITIA LI ZING GPIO

REGISTER 5-1: GPIO: GPIO REGISTER

REGISTER 5-2: TRISIO: GPIO TRI-STATE REGISTER

5.2 Additional Pin Functions

5.2.1 ANSEL REGISTER

5.2.2 WEAK PULL-UPS