Datasheet PIC12LF1840, PIC12F1840 Datasheet

PIC12(L)F1840

Data Sheet

8-Pin Flash Microcontrollers

with nanoWatt XLP Technology

 2011 Microchip Technology Inc. Preliminary DS41441B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-183-4

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41441B-page 2 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

8-Pin Flash Microcontrollers with nanoW att XLP Technology

High-Performance RISC CPU:

• Only 49 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 32 MHz oscillator/clock input

- DC – 125 ns instruction cycle

• Interrupt Capability with Automatic Context
Saving

• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Struc ture:

• Precision 32 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%, typical

- Software selectable frequencies range of

31 kHz to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• Four Crystal modes up to 32 MHz

• Three External Clock modes up to 32 MHz

• 4X Phase Lock Loop (PLL)

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

• Two-Speed Oscillator Start-up

• Reference Clock module:

- Programmable clock output frequency and

duty-cycle

Special Microcontroller Features:

• Full 5.5V Operation – PIC12F1840

• 1.8V-3.6V Operation – PIC12LF1840

• Self-Reprogrammable under Software Control

• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)

• Programmable Brown-out Reset (BOR)

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming™ (ICSP™) via
two pins

• In-Circuit Debug (ICD) via Two Pins

• Enhanced Low-Voltage Programming (LVP)

• Operating Voltage Range:

- 2.3V-5.5V (PIC12F1840)

- 1.8V-3.6V (PIC12LF1840)

• Programmable Code Protection

• Power-Saving Sleep mode

Low-Power Features:

• Standby Current (PIC12LF1840):

- 20 nA @ 1.8V, typical

• Operating Current (PIC12LF1840):

-34A @ 1 MHz, 1.8V, typical

• Low-Power Watchdog Timer Current
(PIC12LF1840):

- 300 nA @ 1.8V, typical

Analog Features:

• Analog-to-Digital Converter (ADC) module:

- 10-bit resolution, 4 channels

- Conversion available during Sleep

• Analog Comparator module:

- One rail-to-rail analog comparator

- Power mode control

- Software controllable hysteresis

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive

and negative reference selection

Peripheral Highlight s:

• 5 I/O Pins and 1 Input Only Pin:

- High current sink/source 25 mA/25 mA

- Programmable weak pull-ups

- Programmable interrupt-on-change pins

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated, low-power 32 kHz oscillator driver

• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler

• Enhanced CCP (ECCP) module:

- Software selectable time bases

- Auto-shutdown and auto-restart

- PWM steering

• Master Synchronous Serial Port (MSSP) with SPI

2

CTM with:

and I

- 7-bit address masking

- SMBus/PMBus

• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

• Capacitive Sensing (CPS) module (mTouch

- 4 input channels

TM

compatibility

TM

):

 2011 Microchip Technology Inc. Preliminary DS41441B-page 3

PIC12(L)F1840

Peripheral Features (Continued):

• Data Signal Modulator module:

- Selectable modulator and carrier sources

•SR Latch:

- Multiple Set/Reset input options

- Emulates 555 Timer applications

PIC12(L)F1840 Family Types

Program

Memory

Device

Words

PIC12LF1840 4K 25625664412/111—1Yes
PIC12F1840 4K 256 256 6 4 4 1 2/1 1 1 — 1 Yes

Note 1: One pin is input only.

Data

Memory

SRAM

(bytes)

(1)

(bytes)

Data EEPROM

I/O’s

Comparators

CapSense (ch)

10-bit ADC (ch)

Timers (8/16-bit)

MSSP

EUSART

SR Latch

ECCP (Full-Bridge)

ECCP (Half-Bridge)

DS41441B-page 4 Preliminary  2011 Microchip Technology Inc.

 2011 Microchip Technology Inc. Preliminary DS41441B-page 5

PDIP, SOIC, DFN

1

2

3

4

8

7

6

5

VDD

RX

(1)

/DT

(1)

/CCP1

(1)

/P1A

(1)

/SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5

MDCIN2/T1G

(1)

/P1B

(1)

/TX

(1)

/CK

(1)

/SDO

(1)

/CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4

MCLR

/VPP/T1G

(1)

/SS

(1)

/RA3

V

SS

RA0/AN0/CPS0/C1IN+/DACOUT/TX

(1)

/CK

(1)

/SDO

(1)

/SS

(1)

/P1B

(1)

/MDOUT/ICSPDAT

RA1/AN1/CPS1/V

REF/C1IN0-/SRI/RX

(1)

/DT

(1)

/SCL/SCK/MDMIN/ICSPCLK

RA2/AN2/CPS2/C1OUT/SRQ/T0CKI/CCP1

(1)

/P1A

(1)

/FLT0/SDA/SDI/INT/MDCIN1

Note 1: Pin function is selectable via the APFCON register.

PIC12(L)F1840

FIGURE 1: 8-PIN DIAGRAM FOR PIC12(L)F1840

TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1840)

I/O

A/D

Reference

8-Pin PDIP/SOIC/DFN

RA0

RA1

RA2

RA3

RA4

RA5

VDD

VSS

7 AN0 DACOUT CPS0 C1IN+ — — P1B

6AN1 VREF CPS1 C1IN0- SRI — — RX

5 AN2 — CPS2 C1OUT SRQ T0CKI CCP1

4—————T1G

3 AN3 — CPS3 C1IN1- — T1G

2 — — — — SRNQ T1CKI

1 — — — — — — — — — — — — VDD

8————————————VSS

Note 1: Pin function is selectable via the APFCON register.

Cap Sense

Basic

ICDDAT

ICPCLK

PIC12(L)F1840

P1A

ECCP

(1)

(1)

(1)

EUSART

(1)

TX

(1)

CK

(1)
(1)

DT

— SDA

Comparator

SR Latch

Timers

SDO

SS

SCL
SCK

SDI

MSSP

(1)

Interrupt

(1)

IOC MDOUT Y ICSPDAT

Modulator

Pull-up

IOC MDMIN Y ICSPCLK

INT/

MDCIN1 Y —

IOC

FLT0

(1)

——

SS

(1)

IOC — Y

MCLR

VPP

(1)

T1OSO

P1B

(1)

TX
CK

(1)
(1)

SDO

(1)

IOC MDCIN2 Y OSC2

CLKOUT

CLKR

(1)

CCP1

(1)

T1OSI

P1A

(1)

RX

(1)

DT

— IOC — Y OSC1

CLKIN

PIC12(L)F1840

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13

3.0 Memory Organization ................................................................................................................................................................. 15

4.0 Device Configuration .................................................................................................................................................................. 41

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 47

6.0 Reference Clock Module ............................................................................................................................................................ 57

7.0 Resets ........................................................................................................................................................................................ 69

8.0 Interrupts .................................................................................................................................................................................... 77

9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 89

10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 93

11.0 Data EEPROM and Flash Program Memory Control ................................................................................................................. 97

12.0 I/O Ports ................................................................................................................................................................................... 111

13.0 Interrupt-on-Change ................................................................................................................................................................. 119

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 123

15.0 Temperature Indicator .............................................................................................................................................................. 125

16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 127

17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 141

18.0 SR Latch................................................................................................................................................................................... 145

19.0 Comparator Module.................................................................................................................................................................. 151

20.0 Timer0 Module ......................................................................................................................................................................... 159

21.0 Timer1 Module ......................................................................................................................................................................... 163

22.0 Timer2 Modules........................................................................................................................................................................ 175

23.0 Data Signal Modulator (DSM) .................................................................................................................................................. 179

24.0 Capture/Compare/PWM Module .............................................................................................................................................. 189

25.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 211

26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 267

27.0 Capacitive Sensing (CPS) Module ........................................................................................................................................... 295

28.0 In-Circuit Serial Programming

29.0 Instruction Set Summary.......................................................................................................................................................... 307

30.0 Electrical Specifications............................................................................................................................................................ 321

31.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 355

32.0 Development Support............................................................................................................................................................... 357

33.0 Packaging Information.............................................................................................................................................................. 361

Appendix A: Revision History............................................................................................................................................................. 371

Appendix B: Device Differences......................................................................................................................................................... 371

Index .................................................................................................................................................................................................. 371

The Microchip Web Site..................................................................................................................................................................... 379

Customer Change Notification Service .............................................................................................................................................. 379

Customer Support .............................................................................................................................................................................. 379

Reader Response .............................................................................................................................................................................. 380

Product Identification System............................................................................................................................................................. 381

™ (ICSP™) ................................................................................................................................ 303

DS41441B-page 6 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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 2011 Microchip Technology Inc. Preliminary DS41441B-page 7

PIC12(L)F1840

NOTES:

DS41441B-page 8 Preliminary  2011 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC12(L)F1840 are described within this data sheet.
They are available in 8-pin packages. Figure 1-1 shows a
block diagram of the PIC12(L)F1840 devices. Ta b le 1 -2
shows the pinout descriptions.

Reference Ta bl e 1- 1 for peripherals available per
device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC12F/LF1840

ADC ●
Capacitive Sensing (CPS) Module ●
Data EEPROM ●
Digital-to-Analog Converter (DAC) ●
Digital Signal Modulator (DSM) ●
EUSART ●
Fixed Voltage Reference (FVR) ●
SR Latch ●
Capture/Compare/PWM Modules

ECCP1 ●

Comparators

C1 ●

Master Synchronous Serial Ports

MSSP ●

Timers

Timer0 ●
Timer1 ●
Timer2 ●

PIC12(L)F1840

 2011 Microchip Technology Inc. Preliminary DS41441B-page 9

PIC12(L)F1840

PORTA

EUSART

Comparators

MSSP

Timer1Timer0

ECCP1

ADC

10-Bit

SR

Latch

Note 1: See applicable chapters for more information on peripherals.

2: See Tab l e 1 - 1 for peripherals available on specific devices.

CPU

Program

Flash Memory

EEPROM

RAM

Timing

Generation

INTRC

Oscillator

MCLR

(Figure 2-1)

Modulator

CapSense

Clock

CLKR

Reference

DAC

FVR

OSC1/CLKIN

OSC2/CLKOUT

FIGURE 1-1: PIC12(L )F 1840 BLOCK DIAGRAM

DS41441B-page 10 Preliminary  2011 Microchip Technology Inc.

T ABLE 1-2: PIC12(L)F1840 PINOUT DESCRIPTION

Input

Name Function

Type

Output

Type

PIC12(L)F1840

Description

RA0/AN0/CPS0/C1IN+/
DACOUT/TX

(1)

SS

(1)

/CK

(1)

/P1B

/MDOUT/ICSPDAT/

(1)

/SDO

ICDDAT

(1)

/

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

CPS0 AN — Capacitive sensing input 0.

C1IN+ AN — Comparator C1 positive input.

DACOUT — AN Digital-to-Analog Converter output.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

SDO — CMOS SPI data output.

SS

ST — Slave Select input.

P1B — CMOS PWM output.

MDOUT — CMOS Modulator output.

ICSPDAT ST CMOS ICSP™ Data I/O.

RA1/AN1/CPS1/V

(1)

SRI/RX

/DT

REF/C1IN0-/

(1)

/SCL/SCK/

MDMIN/ICSPCLK/ICDCLK

RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

CPS1 AN — Capacitive sensing input 1.

REF AN — A/D and DAC Positive Voltage Reference input.

V

C1IN0- AN — Comparator C1 negative input.

SRI ST — SR Latch input.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

2

SCL I

C™ OD I2C™ clock.

SCK ST CMOS SPI clock.

MDMIN ST — Modulator source input.

ICSPCLK ST — Serial Programming Clock.

RA2/AN2/CPS2/C1OUT/SRQ/
T0CKI/CCP1

(1)

/P1A

(1)

/FLT0/

SDA/SDI/INT/MDCIN1

RA2 ST CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

CPS2 AN — Capacitive sensing input 2.

C1OUT — CMOS Comparator C1 output.

SRQ — CMOS SR Latch non-inverting output.

T0CKI ST — Timer0 clock input.

CCP1 ST CMOS Capture/Compare/PWM 1.

P1A — CMOS PWM output.

FLT0 ST — ECCP Auto-Shutdown Fault input.

2

SDA I

C™ OD I2C™ data input/output.

SDI CMOS — SPI data input.

INT ST — External interrupt.

MDCIN1 ST — Modulator Carrier Input 1.

(1)

(1)

/T1G

RA3/SS

/VPP/MCLR RA3 TTL — General purpose input.

SS

ST — Slave Select input.

T1G ST — Timer1 Gate input.

PP HV — Programming voltage.

V

MCLR

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I

ST — Master Clear with internal pull-up.

2

C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).

 2011 Microchip Technology Inc. Preliminary DS41441B-page 11

PIC12(L)F1840

TABLE 1-2: PIC12(L)F1840 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

RA4/AN3/CPS3/OSC2/
CLKOUT/T1OSO/C1IN1-/CLKR/

(1)

(1)

(1)

SDO
T1G

/CK

(1)

/MDCIN2

/TX

/P1B

(1)

/

RA4 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

CPS3 AN — Capacitive sensing input 3.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS F

T1OSO XTAL XTAL Timer1 oscillator connection.

C1IN1- AN — Comparator C1 negative input.

CLKR — CMOS Clock Reference output.

SDO — CMOS SPI data output.

CK ST CMOS USART synchronous clock.

TX — CMOS USART asynchronous transmit.

P1B — CMOS PWM output.

T1G ST — Timer1 Gate input.

MDCIN2 ST — Modulator Carrier Input 2.

RA5/CLKIN/OSC1/T1OSI/
T1CKI/SRNQ/P1A

(1)

/RX

(1)

DT

(1)

/CCP1

(1)

RA5 TTL CMOS General purpose I/O.

/

CLKIN CMOS — External clock input (EC mode).

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

T1OSI XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

SRNQ — CMOS SR Latch inverting output.

P1A — CMOS PWM output.

CCP1 ST CMOS Capture/Compare/PWM 1.

DT ST CMOS USART synchronous data.

RX ST — USART asynchronous input.

DD VDD Power — Positive supply.

V

V

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).

Type

Output

Type

OSC/4 output.

Description

2

C™ = Schmitt Trigger input with I2C

DS41441B-page 12 Preliminary  2011 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 8.5 “Automatic Context Saving”,
for more information.

PIC12(L)F1840

2.2 16-Level Stack with Overflow and Underflow

These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under­flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft­ware Reset. See Section 3.4 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one data pointer for all memory. When an
FSR points to program memory, there is 1 additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary” for more

details.

 2011 Microchip Technology Inc. Preliminary DS41441B-page 13

PIC12(L)F1840

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

V

DD

8

8

Brown-out

Reset

12

3

VSS

Internal

Oscillator

Block

Configuration

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr

7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

15

Data Bus

8

14

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr

7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

V

DD

8

8

3

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory

RAM

FSR regFSR reg

FSR1 Reg

15

15

MUX

15

Program Memory

Read (PMR)

12

FSR regFSR reg

BSR Reg

5

FIGURE 2-1: CORE BLOCK DIAGRAM

DS41441B-page 14 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

3.0 MEMORY ORGANIZATION

There are three types of memory in PIC12(L)F1840
devices: Data Memory, Program Memory and Data
EEPROM Memory

• Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

- Device Memory Maps

- Special Function Registers Summary

• Data EEPROM memory

Note 1: The Data EEPROM Memory and the

(1)

.

(1)

method to access Flash memory through
the EECON registers is described in

Section 11.0 “Data EEPROM and Fl ash
Program Memory Control”.

The following features are associated with access and
control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC12(L)F1840 family. Accessing a
location above these boundaries will cause a
wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC12(L)F1840 4, 096 0FFFh

 2011 Microchip Technology Inc. Preliminary DS41441B-page 15

PIC12(L)F1840

PC<14:0>

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh
1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

constants

BRW ;Add Index in W to

;program counter to

;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR
PIC12(L)F1840

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in pro­gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very sim­ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

DS41441B-page 16 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

constants

RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by set­ting bit 7 of the FSRxH register and reading the match­ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro­gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access­ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a
location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2.1 CORE REGISTERS

The core registers contain the registers that directly
affect the basic operation of the PIC12(L)F1840. These
registers are listed below:

• INDF0

• INDF1

•PCL

•STATUS

•FSR0 Low

• FSR0 High

•FSR1 Low

• FSR1 High

• BSR

•WREG

•PCLATH

• INTCON

Note: The core registers are the first 12

addresses of every data memory bank.

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

 2011 Microchip Technology Inc. Preliminary DS41441B-page 17

PIC12(L)F1840

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in
subtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

TO

PD ZDC

(1)

(1)

C

bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

(1)

bit

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

bit

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

DS41441B-page 18 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

0Bh
0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The registers asso­ciated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory
bank.

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all
banks.

FIGURE 3-2: BANKED MEMORY

PARTITIONING

3.2.5 DEVICE MEMORY MAPS

The memory maps for the device family are as shown
in Table 3-2.

TABLE 3-2: MEMORY MAP TABLES

Device Banks Table No.

PIC12(L)F1840 0-7 Table 3-3

8-23 Table 3-4

24-31 Table 3-5

31 Table 3-6

 2011 Microchip Technology Inc. Preliminary DS41441B-page 19

DS41441B-page 20 Preliminary  2011 Microchip Technology Inc.

TABLE 3-3: PIC12(L)F1840 MEMORY MAP, BANKS 0-7

PIC12(L)F1840

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0
001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1
002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL
003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS
004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L
005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H
006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L
007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H
008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR
009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG
00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH
00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch
00Dh
00Eh
00Fh
010h
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h
013h
014h
015h TMR0 095h OPTION 115h CMOUT 195h EECON1 215h SSPCON 295h CCP1AS 315h
016h

017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh CPSCON0 09Eh ADCON1 11Eh
01Fh CPSCON1 09Fh

020h

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh
070h 0F0h

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

— 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh —
—08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh—
—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
—090h—110h—190h—210h—290h— 310h — 390h —

—093h—113h— 193h EEDATL 213h SSPMASK 293h CCP1CON 313h — 393h
—094h—114h— 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h — 394h

TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h
TMR1H 097h WDTCON 117h FVRCON 197h VREGCON
T1CON 098h OSCTUNE 118h DACCON0 198h

T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h

TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah

PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh

—11Fh— 19Fh BAUDCON 21Fh —29Fh—31Fh—39Fh

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

120h

170h

General
Purpose
Register
96 Bytes

0A0h

0BFh

— 19Ch SPBRGH 21Ch

—

General
Purpose
Register

80 Bytes

Accesses

70h – 7Fh

19Eh TXSTA 21Eh

1A0h

Unimplemented

Read as ‘0’

1F0h

(1)

—218h—298h

Accesses

70h – 7Fh

217h SSPCON3 297h — 317h — 397h —

—
—
—
—

—29Eh—31Eh

220h

Unimplemented

Read as ‘0’

270h

Accesses

70h – 7Fh

299h
29Ah
29Bh
29Ch

2A0h

2F0h

— 30Ch — 38Ch —

— 391h IOCAP
— 392h IOCAN

— 395h
— 396h —

—
—
—
—
—

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

318h
319h
31Ah
31Bh
31Ch

320h

36Fh 3EFh
370h

—
—
—
—39Bh—
— 39Ch MDCON
—
—

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

398h
399h
39Ah CLKRCON

39Dh
39Eh

3A0h

3F0h

IOCAF

—
—

—
—

MDSRC
MDCARL
MDCARH

Unimplemented

Read as ‘0’

Accesses

70h – 7Fh

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Available only on PIC12F1840.

 2011 Microchip Technology Inc. Preliminary DS41441B-page 21

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

x00h

INDF0

x80h

INDF0

x00h

INDF0

x80h

INDF0

x00h

INDF0

x80h

INDF0

x00h

INDF0

x80h

INDF0

x01h

INDF1

x81h

INDF1

x01h

INDF1

x81h

INDF1

x01h

INDF1

x81h

INDF1

x01h

INDF1

x81h

INDF1

x02h

PCL

x82h

PCL

x02h

PCL

x82h

PCL

x02h

PCL

x82h

PCL

x02h

PCL

x82h

PCL

x03h

STATUS

x83h

STATUS

x03h

STATUS

x83h

STATUS

x03h

STATUS

x83h

STATUS

x03h

STATUS

x83h

STATUS

x04h

FSR0L

x84h

FSR0L

x04h

FSR0L

x84h

FSR0L

x04h

FSR0L

x84h

FSR0L

x04h

FSR0L

x84h

FSR0L

x05h

FSR0H

x85h

FSR0H

x05h

FSR0H

x85h

FSR0H

x05h

FSR0H

x85h

FSR0H

x05h

FSR0H

x85h

FSR0H

x06h

FSR1L

x86h

FSR1L

x06h

FSR1L

x86h

FSR1L

x06h

FSR1L

x86h

FSR1L

x06h

FSR1L

x86h

FSR1L

x07h

FSR1H

x87h

FSR1H

x07h

FSR1H

x87h

FSR1H

x07h

FSR1H

x87h

FSR1H

x07h

FSR1H

x87h

FSR1H

x08h

BSR

x88h

BSR

x08h

BSR

x88h

BSR

x08h

BSR

x88h

BSR

x08h

BSR

x88h

BSR

x09h

WREG

x89h

WREG

x09h

WREG

x89h

WREG

x09h

WREG

x89h

WREG

x09h

WREG

x89h

WREG

x0Ah

PCLATH

x8Ah

PCLATH

x0Ah

PCLATH

x8Ah

PCLATH

x0Ah

PCLATH

x8Ah

PCLATH

x0Ah

PCLATH

x8Ah

PCLATH

x0Bh

INTCON

x8Bh

INTCON

x0Bh

INTCON

x8Bh

INTCON

x0Bh

INTCON

x8Bh

INTCON

x0Bh

INTCON

x8Bh

INTCON

x0Ch

—

x8Ch

—

x0Ch

—

x8Ch

—

x0Ch

—

x8Ch

—

x0Ch

—

x8Ch

—

x0Dh

—

x8Dh

—

x0Dh

—

x8Dh

—

x0Dh

—

x8Dh

—

x0Dh

—

x8Dh

—

x0Eh

—

x8Eh

—

x0Eh

—

x8Eh

—

x0Eh

—

x8Eh

—

x0Eh

—

x8Eh

—

x0Fh

—

x8Fh

—

x0Fh

—

x8Fh

—

x0Fh

—

x8Fh

—

x0Fh

—

x8Fh

—

x10h

—

x90h

—

x10h

—

x90h

—

x10h

—

x90h

—

x10h

—

x90h

—

x11h

—

x91h

—

x11h

—

x91h

—

x11h

—

x91h

—

x11h

—

x91h

—

x12h

—

x92h

—

x12h

—

x92h

—

x12h

—

x92h

—

x12h

—

x92h

—

x13h

—

x93h

—

x13h

—

x93h

—

x13h

—

x93h

—

x13h

—

x93h

—

x14h

—

x94h

—

x14h

—

x94h

—

x14h

—

x94h

—

x14h

—

x94h

—

x15h

—

x95h

—

x15h

—

x95h

—

x15h

—

x95h

—

x15h

—

x95h

—

x16h

—

x96h

—

x16h

—

x96h

—

x16h

—

x96h

—

x16h

—

x96h

—

x17h

—

x97h

—

x17h

—

x97h

—

x17h

—

x97h

—

x17h

—

x97h

—

x18h

—

x98h

—

x18h

—

x98h

—

x18h

—

x98h

—

x18h

—

x98h

—

x19h

—

x99h

—

x19h

—

x99h

—

x19h

—

x99h

—

x19h

—

x99h

—

x1Ah

—

x9Ah

—

x1Ah

—

x9Ah

—

x1Ah

—

x9Ah

—

x1Ah

—

x9Ah

—

x1Bh

—

x9Bh

—

x1Bh

—

x9Bh

—

x1Bh

—

x9Bh

—

x1Bh

—

x9Bh

—

x1Ch

—

x9Ch

—

x1Ch

—

x9Ch

—

x1Ch

—

x9Ch

—

x1Ch

—

x9Ch

—

x1Dh

—

x9Dh

—

x1Dh

—

x9Dh

—

x1Dh

—

x9Dh

—

x1Dh

—

x9Dh

—

x1Eh

—

x9Eh

—

x1Eh

—

x9Eh

—

x1Eh

—

x9Eh

—

x1Eh

—

x9Eh

—

x1Fh

—

x9Fh

—

x1Fh

—

x9Fh

—

x1Fh

—

x9Fh

—

x1Fh

—

x9Fh

—

x20h

Unimplemented

Read as ‘0’

xA0h

Unimplemented

Read as ‘0’

x20h

Unimplemented

Read as ‘0’

xA0h

Unimplemented

Read as ‘0’

x20h

Unimplemented

Read as ‘0’

xA0h

Unimplemented

Read as ‘0’

x20h

Unimplemented

Read as ‘0’

xA0h

Unimplemented

Read as ‘0’

x6Fh xEFh x6Fh xEFh x6Fh xEFh x6Fh xEFh
x70h

Accesses
70h – 7Fh

xF0h

Accesses

70h – 7Fh

x70h

Accesses

70h – 7Fh

xF0h

Accesses

70h – 7Fh

x70h

Accesses

70h – 7Fh

xF0h

Accesses

70h – 7Fh

x70h

Accesses

70h – 7Fh

xF0h

Accesses

70h – 7Fh

x7Fh

xFFh x7Fh

xFFh x7Fh xFFh x7Fh xFFh

TABLE 3-4: PIC12(L)F1840 MEMORY MAP, BANKS 8-23

PIC12(L)F1840

DS41441B-page 22 Preliminary  2011 Microchip Technology Inc.

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0
C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1
C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL
C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS
C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L
C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H
C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L
C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H
C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR
C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG
C0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATH
C0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCON
C0Ch

—C8Ch—D0Ch—D8Ch—E0Ch—E8Ch—F0Ch—F8Ch

See Tab l e 3 - 6 for
register mapping

details

C0Dh

—C8Dh—D0Dh—D8Dh—E0Dh—E8Dh—F0Dh—F8Dh

C0Eh

—C8Eh—D0Eh—D8Eh—E0Eh—E8Eh—F0Eh—F8Eh

C0Fh

—C8Fh—D0Fh—D8Fh—E0Fh—E8Fh—F0Fh—F8Fh

C10h

—C90h—D10h—D90h—E10h—E90h—F10h—F90h

C11h

—C91h—D11h—D91h—E11h—E91h—F11h—F91h

C12h

—C92h—D12h—D92h—E12h—E92h—F12h—F92h

C13h

—C93h—D13h—D93h—E13h—E93h—F13h—F93h

C14h

—C94h—D14h—D94h—E14h—E94h—F14h—F94h

C15h

—C95h—D15h—D95h—E15h—E95h—F15h—F95h

C16h

—C96h—D16h—D96h—E16h—E96h—F16h—F96h

C17h

—C97h—D17h—D97h—E17h—E97h—F17h—F97h

C18h

—C98h—D18h—D98h—E18h—E98h—F18h—F98h

C19h

—C99h—D19h—D99h—E19h—E99h—F19h—F99h

C1Ah

—C9Ah—D1Ah—D9Ah—E1Ah—E9Ah—F1Ah—F9Ah

C1Bh

—C9Bh—D1Bh—D9Bh—E1Bh—E9Bh—F1Bh—F9Bh

C1Ch

—C9Ch—D1Ch—D9Ch—E1Ch—E9Ch—F1Ch—F9Ch

C1Dh

—C9Dh—D1Dh—D9Dh—E1Dh—E9Dh—F1Dh—F9Dh

C1Eh

—C9Eh—D1Eh—D9Eh—E1Eh—E9Eh—F1Eh—F9Eh

C1Fh

—C9Fh—D1Fh—D9Fh—E1Fh—E9Fh—F1Fh—F9Fh

C20h

Unimplemented

Read as ‘0’

CA0h

Unimplemented

Read as ‘0’

D20h

Unimplemented

Read as ‘0’

DA0h

Unimplemented

Read as ‘0’

E20h

Unimplemented

Read as ‘0’

EA0h

Unimplemented

Read as ‘0’

F20h

Unimplemented

Read as ‘0’

FA0h

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h

Accesses
70h – 7Fh

CF0h

Accesses

70h – 7Fh

D70h

Accesses

70h – 7Fh

DF0h

Accesses

70h – 7Fh

E70h

Accesses

70h – 7Fh

EF0h

Accesses

70h – 7Fh

F70h

Accesses

70h – 7Fh

FF0h

Accesses

70h – 7Fh

CFFh

CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-5: PIC12(L)F1840 MEMORY MAP, BANKS 24-31

PIC12(L)F1840

PIC12(L)F1840

Legend: = Unimplemented data memory locations,

read as ‘0’.

Bank 31

FA0h

FE3h

Unimplemented

Read as ‘0’

FE4h

STATUS_SHAD

FE5h

WREG_SHAD

FE6h

BSR_SHAD

FE7h

PCLATH_SHAD

FE8h

FSR0L_SHAD

FE9h

FSR0H_SHAD

FEAh

FSR1L_SHAD

FEBh

FSR1H_SHAD

FECh

—

FEDh

STKPTR

FEEh

TOSL

FEFh

TOSH

T ABLE 3-6: PIC12(L)F1840 MEMORY MAP,

BANK 31

3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY

The Special Function Register Summary for the device
family are as follows:

Device Bank(s) Page No.

0 24

1 25

2 26

3 27

PIC12(L)F1840

4 28

5 29

6 30

7 31

8-30 32

31 33

 2011 Microchip Technology Inc. Preliminary DS41441B-page 23

PIC12(L)F1840

TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

(1)

000h

001h

002h

003h

004h

005h

006h

007h

008h

009h

00Ah

00Bh

00Ch PORTA

00Dh

00Eh

00Fh

010h
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 OSFIF

013h

014h
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS1 TMR1CS0 T1CKPS<1:0> T1OSCEN T1SYNC

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111

01Ch T2CON

01Dh

01Eh CPSCON0 CPSON CPSRM

01Fh CPSCON1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Note 1: These registers can be addressed from any bank.

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(1)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(1)

WREG Working Register 0000 0000 uuuu uuuu

(1)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: PIC12F1840 only.

(not a physical register)

(not a physical register)

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx

— C1IF EEIF BCL1IF — — — 0-00 0--- 0-00 0---

—TMR1ON0000 00-0 uuuu uu-u

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

DONE

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

— — CPSRNG<1:0> CPSOUT T0XCS 00-- 0000 00-- 0000

— — — — — — CPSCH<1:0> ---- --00 ---- --00

Value on

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41441B-page 24 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

080h

081h

082h

083h

084h

085h

086h

087h

088h

089h

08Ah

08Bh

08Ch TRISA

08Dh

08Eh

08Fh

090h
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE

093h

094h

095h

096h PCON STKOVF STKUNF

097h WDTCON

098h OSCTUNE

099h OSCCON SPLLEN IRCF<3:0>
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1 ADFM ADCS<2:0>

09Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Note 1: These registers can be addressed from any bank.

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(1)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(1)

WREG Working Register 0000 0000 uuuu uuuu

(1)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

OPTION_REG

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: PIC12F1840 only.

(not a physical register)

(not a physical register)

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

— C1IE EEIE BCL1IE — — — 0-00 0--- 0-00 0---

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111

— —RMCLRRI POR BOR 00-- 11qq qq-- qquu
— — WDTPS<4:0> SWDTEN --01 0110 --01 0110
— — TUN<5:0> --00 0000 --00 0000

—SCS<1:0>0011 1-00 0011 1-00

— CHS<4:0>

— —

GO/DONE

ADPREF<1:0>

ADON -000 0000 -000 0000

Value on

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

0000 --00 0000 --00

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41441B-page 25

PIC12(L)F1840

TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

(1)

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch LATA

10Dh

10Eh

10Fh

110h

111h CM1CON0 C1ON C1OUT C1OE C1POL

112h CM1CON1 C1INTP C1INTN C1PCH<1:0>

113h

114h

115h CMOUT

116h BORCON SBOREN
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

118h DACCON0 DACEN DACLPS DACOE

119h DACCON1
11Ah SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000

11Bh SRCON1 SRSPE SRSCKE

11Ch

11Dh APFCON RXDTSEL SDOSEL SSSEL

11Eh

11Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Note 1: These registers can be addressed from any bank.

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(1)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(1)

WREG Working Register 0000 0000 uuuu uuuu

(1)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: PIC12F1840 only.

(not a physical register)

(not a physical register)

— —LATA5LATA4—LATA2LATA1LATA0--xx -xxx --uu -uuu

— C1SP C1HYS C1SYNC 0000 -100 0000 -100
— — — C1NCH 0000 ---0 0000 ---0

— — — — — — —MC1OUT---- ---0 ---- ---0

— — — — — — BORRDY 1--- ---q u--- ---u

— DACPSS<1:0> — — 000- 00-- 000- 00--

— — — DACR<4:0> ---0 0000 ---0 0000

Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E 0000 0000 0000 0000

--- T1GSEL TXCKSEL P1BSEL CCP1SEL 000- 0000 000- 0000

Value on

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41441B-page 26 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

(1)

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch ANSELA

18Dh

18Eh

18Fh

190h
191h EEADRL EEPROM/Program Memory Address Register Low Byte 0000 0000 0000 0000

192h EEADRH
193h EEDATL EEPROM/Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h EEDATH
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000

197h VREGCON

198h
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Note 1: These registers can be addressed from any bank.

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(1)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(1)

WREG Working Register 0000 0000 uuuu uuuu

(1)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: PIC12F1840 only.

(not a physical register)

(not a physical register)

— — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111

— EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000

— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

(2)

— — — — — —VREGPMReserved ---- --01 ---- --01

— SCKP BRG16 —WUEABDEN01-0 0-00 01-0 0-00

Value on

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41441B-page 27

PIC12(L)F1840

TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 4

(1)

200h

201h

202h

203h

204h

205h

206h

207h

208h

209h

20Ah

20Bh

20Ch WPUA

20Dh

20Eh

20Fh

210h
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111

214h SSP1STAT SMP CKE D/A
215h SSP1CON1 WCOL SSP1OV SSP1EN CKP SSP1M<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h

219h

21Ah

21Bh

21Ch

21Dh

21Eh

21Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Note 1: These registers can be addressed from any bank.

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(1)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(1)

WREG Working Register 0000 0000 uuuu uuuu

(1)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: PIC12F1840 only.

(not a physical register)

(not a physical register)

— — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111

PSR/WUA BF 0000 0000 0000 0000

Value on

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41441B-page 28 Preliminary  2011 Microchip Technology Inc.

PIC12(L)F1840

TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 5

(1)

280h

281h

282h

283h

284h

285h

286h

287h

288h

289h

28Ah

28Bh

28Ch

28Dh

28Eh

28Fh

290h
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000
294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000
295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000

296h PSTR1CON

297h

298h

299h

29Ah

29Bh

29Ch

29Dh

29Eh

29Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Note 1: These registers can be addressed from any bank.

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(1)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(1)

WREG Working Register 0000 0000 uuuu uuuu

(1)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: PIC12F1840 only.

(not a physical register)

(not a physical register)

— — — STR1SYNC Reserved Reserved STR1B STR1A ---0 rr01 ---0 rr01

Value on

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

 2011 Microchip Technology Inc. Preliminary DS41441B-page 29

PIC12(L)F1840

TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 6

(1)

300h

301h

302h

303h

304h

305h

306h

307h

308h

309h

30Ah

30Bh

30Ch

30Dh

30Eh

30Fh

310h

311h

312h

313h

314h

315h

316h

317h

318h

319h

31Ah

31Bh

31Ch

31Dh

31Eh

31Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Note 1: These registers can be addressed from any bank.

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS — — —TOPD ZDCC---1 1000 ---q quuu

(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

(1)

BSR — — — BSR<4:0> ---0 0000 ---0 0000

(1)

WREG Working Register 0000 0000 uuuu uuuu

(1)

PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

(1)

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

— Unimplemented — —

Shaded locations are unimplemented, read as ‘0’.

2: PIC12F1840 only.

(not a physical register)

(not a physical register)

Value on

POR, BOR

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

Value on all

other

Resets

DS41441B-page 30 Preliminary  2011 Microchip Technology Inc.