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Datasheet PIC12F1571, PIC12F1572, PIC12LF1571, PIC12LF1572 Datasheet

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PIC12(L)F1571/2

8-Pin MCU with High Precision 16-bit PWMs

Description:
PIC12(L)F1571/2 microcontrollers combine the capabilities of 16-bit PWMs with Analog to suit a variety of applications. These devices deliver three 16-bit PWMs with independent timers for applications where high resolution is needed, such as LED lighting, stepper motors, power supplies and other general purpose applications. The core independent peripherals (16-bit PWMs, Complementary Waveform Generator), Enhanced Universal Synchronous Asynchronous Receiver Transceiver (EUSART) and Analog (ADCs, Comparator and DAC) enable closed loop feedback and communication for use in multiple market segments. The EUSART peripheral enables the communication for applications such as LIN.
Core Features:
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Two 8-Bit Timers
• One 16-Bit Timer
• Three additional 16-Bit Timers available using the 16-Bit PWMs
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Low-Power Brown-out Reset (LPBOR)
• Programmable Watchdog Timer (WDT) up to 256s
• Programmable Code Protection
Memory:
• Up to 2 KW Flash Program Memory
• Up to 256 Bytes Data SRAM Memory
• Direct, Indirect and Relative Addressing modes
Operating Characteristics:
• Operating Voltage Range:
- 1.8V to 3.6V (PIC12LF1571/2)
- 2.3V to 5.5V (PIC12F1571/2)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
• Internal Voltage Reference module
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
Digital Peripherals:
• 16-Bit PWM:
- Three 16-bit PWMs with independent timers
- Multiple output modes (standard, center aligned, set and toggle on register match)
- User settings for phase, duty cycle, period, offset and polarity
- 16-bit timer capability
- Interrupts generated based on timer matches with offset, duty cycle, period and phase reg­isters
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Multiple signal sources
• Enhanced Universal Synchronous Asynchronous Receiver Transceiver (EUSART):
- Supports LIN applications
Device I/O Port Features:
- Six I/Os
- Individually selectable weak pull-ups
- Interrupt-on-change pins option with
edge-selectable option
Low-Power Features:
• Sleep mode: 20 nA @ 1.8V, typical
• Watchdog Timer: 260 nA @ 1.8V, typical
• Operating Current:
- 30 uA/MHz @ 1.8V, typical
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 1
PIC12(L)F1571/2
Analog Peripherals:
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to four external channels
- Conversion available during Sleep
• Comparator:
- Low-Power/High-Speed modes
- Fixed Voltage Reference at (non)inverting input(s)
- Comparator outputs externally accessible
- Synchronization with Timer1 clock source
- Software hysteresis enable
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels
PIC12(L)F1571/2 FAMILY TYPES
Clocking Structure:
• 16 MHz Internal Oscillator Block:
- ±1% at calibration temperature
- Selectable frequency range from 31 kHz to 16 MHz
• External Oscillator Block with:
- Resonator modes up to 20 MHz
- Two external clock modes up to 32 MHz
• Fail-Safe Clock Monitor
• Two-Speed Oscillator Start-up
• Digital Oscillator Input available
Package:
• 8-pin PDIP, SOIC, MSOP, DFN
Device
(Kwords)
Data Sheet Index
Program Memory Flash
PIC12(L)F1571 A 112862/4 PIC12(L)F1572 A 2 256 6 2/4
Note 1: I – Debugging integrated on chip.
2: Three additional 16-bit timers available when not using the 16-bit PWM outputs.
Data Sheet Index: (Unshaded devices are described in this document.)
A DS40001723 PIC12(L)F1571/2 Data Sheet, 8-Pin Flash, 8-bit MCU with High-Precision 16-bit PWM.
Data SRAM (bytes)
I/O Pins
8-Bit/16-Bit Timers
(2)
(2)
Comparators
134110I 1 3 4 1 1 1 I
16-Bit PWM
10-Bit ADC (ch)
CWG
5-Bit DAC
EUSART
(1)
Debug
DS40001723B-page 2 Preliminary 2013-2014 Microchip Technology Inc.

PIN DIAGRAMS

Note: See Table 1 for location of all peripheral functions.
1
2
3
4
8
7
6
5
VDD
RA5
RA3/MCLR
/VPP
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RA4
PIC12(L)F1571
PIC12(L)F1572
Pin Diagram – 8-Pin PDIP, SOIC, DFN, MSOP
PIC12(L)F1571/2

TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1571/2)

(2)
I/O
RA0 7 AN0 DAC1OUT C1IN+ — PWM2 TX
RA1 6 AN1 VREF+ C1IN0- — PWM1 RX
RA2 5 AN2 — C1OUT T0CKI PWM3 — CWG1FLT
RA3 4 — — — T1G
RA4 3 AN3 — C1IN1- T1G PWM2
RA5 2 — — — T1CKI PWM1
VDD 1 — — — — — — — — — VDD
Vss 8 — — — — — — — — — VSS
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.
2: PIC12(L)F1572 only.
ADC
8-Pin PDIP/SOIC/MSOP/DFN
Reference
Comparator
Timers
(1)
PWM
— — — IOC Y
(1)
(1)
TX CK
RX DT
CK
DT
EUSART
(2) (2)
(2) (2)
(1,2) (1,2)
(1,2) (1,2)
CWG
CWG1B IOC Y ICSPDAT
— IOC Y ICSPCLK
CWG1A
(1)
CWG1B
(1)
CWG1A
Interrupt
IOC INT
IOC Y CLKOUT
IOC Y CLKIN
Pull-up
Y —
Basic
ICDDAT
ICDCLK
MCLR
VPP
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 3
PIC12(L)F1571/2

TABLE OF CONTENTS

1.0 Device Overview .......................................................................................................................................................................... 6
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 10
3.0 Memory Organization ................................................................................................................................................................. 12
4.0 Device Configuration.................................................................................................................................................................. 39
5.0 Oscillator Module........................................................................................................................................................................ 44
6.0 Resets ........................................................................................................................................................................................ 56
7.0 Interrupts .................................................................................................................................................................................... 64
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 77
9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 80
10.0 Flash Program Memory Control ................................................................................................................................................. 84
11.0 I/O Ports ................................................................................................................................................................................... 100
12.0 Interrupt-On-Change ................................................................................................................................................................ 109
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 113
14.0 Temperature Indicator Module ................................................................................................................................................. 116
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 118
16.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 132
17.0 Comparator Module.................................................................................................................................................................. 135
18.0 Timer0 Module ......................................................................................................................................................................... 142
19.0 Timer1 Module with Gate Control............................................................................................................................................. 145
20.0 Timer2 Module ......................................................................................................................................................................... 156
21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 159
22.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 187
23.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 212
24.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 224
25.0 Instruction Set Summary .......................................................................................................................................................... 226
26.0 Electrical Specifications............................................................................................................................................................ 240
27.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 264
28.0 Development Support............................................................................................................................................................... 265
29.0 Packaging Information.............................................................................................................................................................. 269
Appendix A: Data Sheet Revision History .......................................................................................................................................... 282
The Microchip Web Site..................................................................................................................................................................... 283
Product Identification System............................................................................................................................................................. 284
DS40001723B-page 4 Preliminary 2013-2014 Microchip Technology Inc.
PIC12(L)F1571/2
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 5
PIC12(L)F1571/2

1.0 DEVICE OVERVIEW

The PIC12(L)F1571/2 are described within this data sheet. The block diagram of these devices are shown in
Figure 1-1, the available peripherals are shown in Table 1-1, and the pinout descriptions are shown in Table 1-2.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC12(L)F1571
PIC12(L)F1572
Analog-to-Digital Converter (ADC) ●● Complementary Wave Generator
(CWG) Digital-to-Analog Converter (DAC) ●● Enhanced Universal
Synchronous/Asynchronous Receiver/Transmitter (EUSART)
Fixed Voltage Reference (FVR) ●● Temperature Indicator ●● Comparators
PWM Modules
PWM1 ●● PWM2 ●● PWM3 ●●
Timers
Timer0 ●● Timer1 ●● Timer2 ●●
●●
●
C1 ● ●
DS40001723B-page 6 Preliminary 2013-2014 Microchip Technology Inc.

FIGURE 1-1: PIC12(L)F1571/2 BLOCK DIAGRAM

() y
CLKOUT
CLKIN
RAM
CPU
(Note 3)
Timing
Generation
INTRC
Oscillator
MCLR
Program
Flash Memory
FVR
ADC
10-bit
Temp
Indicator
TMR0TMR1TMR2
PWM1PWM2PWM3CWG1
PORTA
Rev. 10-000039E
9/12/2013
DACC1
EUSART
(4)
Note 1: See applicable chapters for more information on peripherals.
2: See Table 1-1 for peripherals available on specific devices. 3: See Figure 2-1. 4: PIC12(L)F1572 only.
PIC12(L)F1571/2
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 7
PIC12(L)F1571/2

TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION

Input
Name Function
Typ e
Output
Typ e
Description
RA0/AN0/C1IN+/DACOUT/
(2)
(2)
/CK
TX
/CWG1B/PWM2/
ICSPDAT/ICDDAT
RA0
AN0 ADC Channel input.
C1IN+ Comparator positive input.
General purpose I/O.
DACOUT Digital-to-Analog Converter output.
TX USART asynchronous transmit.
(3) (4)
CK USART synchronous clock.
CWG1B CWG complementary output.
PWM2 PWM output.
ICSPDAT ICSP™ Data I/O.
ICDDAT In-Circuit Debug data.
RA1/AN1/V DT
REF+/C1IN0-/RX
(2)
/PWM1/ICSPCLK/ICDCLK
(2)
/
RA1
General purpose I/O.
AN1 ADC Channel input.
REF+ ADC Voltage Reference input.
V
C1IN0- Comparator negative input.
RX USART asynchronous input.
(3) (4)
DT USART synchronous data.
PWM1 PWM output.
ICSPCLK ICSP Programming Clock.
ICDCLK In-Circuit Debug Clock.
RA2/AN2/C1OUT/T0CKI/ CWG1FLT
/CWG1A/PWM3/INT
RA2
AN2 ADC Channel input.
General purpose I/O.
C1OUT Comparator output.
T0CKI Timer0 clock input.
CWG1FLT
(3) (4)
Complementary Waveform Generator Fault input.
CWG1A CWG complementary output.
PWM3 PWM output.
INT External interrupt.
RA3/V
PP/T1G
/MCLR RA3
PP Programming voltage.
V
General purpose input with IOC and WPU.
(3) (4)
(1)
T1G Timer1 Gate input.
Master Clear with internal pull-up.
General purpose I/O.
RA4/AN3/C1IN1-/T1G/TX CK
(1,2)
/CWG1B
(1)
/PWM2
CLKOUT
(1,2)
(1)
MCLR
/
/
RA4
AN3 ADC Channel input.
C1IN1- Comparator negative input.
T1G Timer1 Gate input.
TX USART asynchronous transmit.
(3) (4)
CK USART synchronous clock.
CWG1B CWG complementary output.
PWM2 PWM output.
CLKOUT F
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
OSC/4 output.
2
C™ = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.
2: PIC12(L)F1572 only. 3: Input type is selected by the port. 4: Output type is selected by the port.
DS40001723B-page 8 Preliminary 2013-2014 Microchip Technology Inc.
PIC12(L)F1571/2
TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function
(1,2)
RA5/T1CKI/RX
(1)
CWG1A
DD VDD Power — Positive supply.
V
SS VSS Power — Ground reference.
V
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.
/PWM1
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels
2: PIC12(L)F1572 only. 3: Input type is selected by the port. 4: Output type is selected by the port.
/DT
(1)
/CLKIN
(1,2)
/
RA5
T1CKI Timer1 clock input.
RX USART asynchronous input.
DT USART synchronous data.
CWG1A CWG complementary output.
PWM1 PWM output.
CLKIN External clock input (EC mode).
Typ e
(3) (4)
Output
Typ e
General purpose I/O.
Description
2
C™ = Schmitt Trigger input with I2C
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 9
PIC12(L)F1571/2
15
15
15
15
8
8
8
12
14
7
5
3
Program Counter
MUX
Addr MUX
16-Level Stack
(15-bit)
Program Memory
Read (PMR)
Instruction Reg
Configuration
FSR0 Reg
FSR1 Reg
BSR Reg
STATUS Reg
RAM
WReg
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Instruction
Decode and
Control
Timing
Generation
Internal
Oscillator
Block
ALU
Flash
Program
Memory
MUX
Data Bus
Program
Bus
Direct Addr
Indirect
Addr
RAM Addr
CLKIN
CLKOUT
V
DD VSS
Rev. 10-000055A
7/30/2013
12
12

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

FIGURE 2-1: CORE BLOCK DIAGRAM

• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
DS40001723B-page 10 Preliminary 2013-2014 Microchip Technology Inc.

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section7.5 “Automatic Context Saving”, for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under­flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a soft­ware Reset. See section Section3.4 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See
Section3.5 “Indirect Addressing” for more details.
PIC12(L)F1571/2

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See
Section25.0 “Instruction Set Summary” for more
details.
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 11
PIC12(L)F1571/2

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:
• Program Memory
- Configuration Words
-Device ID
-User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (See
Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address
PIC12(L)F1571 1,024 3FFh PIC12(L)F1572 2,048 7FFh
DS40001723B-page 12 Preliminary 2013-2014 Microchip Technology Inc.
PIC12(L)F1571/2
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
Page 0
Rollover to Page 0
Rollover to Page 0
0000h
0004h 0005h
03FFh
0400h
7FFFh
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
Rev. 10-000040D
7/30/2013
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
Page 0
Rollover to Page 0
Rollover to Page 0
0000h
0004h 0005h
07FFh 0800h
7FFFh
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
Rev. 10-000040C
7/30/2013
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR PIC12(L)F1571
FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR PIC12(L)F1572
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 13
PIC12(L)F1571/2
constants
BRW ;Add Index in W to
;program counter to
;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3
my_function
;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W
constants
RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3
my_function
;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.1.1 READING PROGRAM MEMORY AS DATA
There are two methods of accessing constants in pro­gram memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.
3.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by set­ting bit 7 of the FSRxH register and reading the match­ing INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the pro­gram memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates access­ing the program memory via an FSR.
The HIGH operator will set bit<7> if a label points to a location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
The BRW instruction makes this type of table very sim­ple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.
DS40001723B-page 14 Preliminary 2013-2014 Microchip Technology Inc.
PIC12(L)F1571/2
Addresses BANKx
x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR
x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section3.5 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank.
3.2.1 CORE REGISTERS
The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta b l e 3 -2 . For detailed information, see Tab le 3 -9 .

TABLE 3-2: CORE REGISTERS

2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 15
PIC12(L)F1571/2
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to
Section25.0 “Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in subtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TO
PD ZDC
(1)
(1)
C
bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit Carry/Digit Borrow
bit 0 C: Carry/Borrow
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred
: Power-Down bit
1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
(1)
(1)
DS40001723B-page 16 Preliminary 2013-2014 Microchip Technology Inc.
PIC12(L)F1571/2
Memory Region7-bit Bank Offset
00h
0Bh
0Ch
1Fh
20h
6Fh
7Fh
70h
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
General Purpose RAM
(80 bytes maximum)
Common RAM
(16 bytes)
Rev. 10-000041A
7/30/2013
3.2.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appro­priate peripheral chapter of this data sheet.
3.2.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See
Section3.5.2 “Linear Data Memory” for more
information.
3.2.4 COMMON RAM
There are 16 bytes of common RAM accessible from all banks.
FIGURE 3-3: BANKED MEMORY
PARTITIONING
3.2.5 DEVICE MEMORY MAPS
The memory maps for PIC12(L)F1571/2 are as shown in Table 3-3 through Tab l e 3 - 8 .
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 17
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 18

TABLE 3-3: PIC12(L)F1571 MEMORY MAP, BANK 0-7

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta bl e 3 -2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA 00Dh 00Eh 00Fh 010h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h 013h PIR3 093h PIE3 113h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h
06Fh 070h
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
— 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh — —08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh— —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh— —090h—110h—190h—210h—290h
—094h—114h
TMR1L 096h PCON 116h BORCON 196h PMCON2 216h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h T1CON 098h OSCTUN E 118h
T1GCON 099h OSCCON 119h
TMR2 09Ah OSCSTAT 11Ah
PR2 09BhADRESL11Bh
T2CON 09Ch ADRESH 11Ch
— 09Dh ADCON0 11Dh APFCON 19Dh — —
General
Purpose Register 80 Bytes
Common RAM
080h
Core Registers
(Ta bl e 3 -2 )
09Eh ADCON1 11Eh
09Fh ADCON2 11Fh
0A0h
General Purpose
Register 0BFh 0C0h
0EFh
0F0h
48 Bytes
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
100h
120h
16Fh 1EFh 26Fh 2EFh
170h
Core Registers
(Table 3-2)
— —
DACCON0 DACCON1
—19Ah—21Ah—29Ah—31Ah—39Ah— —19Bh—21Bh—29Bh—31Bh — 19Ch — 21Ch — 29Ch — 31Ch
— —19Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
180h
Core Registers
(Table 3-2)
193h PMDATL 213h 194h PMDATH 214h
198h 199h
19Eh
1A0h
1F0h
—218h —219h—299h— 319h — 399h —
— — —
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
200h
21Dh 21Eh 21Fh
220h
270h
Core Registers
(Table 3-2)
— — — — — — — —
— — —
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
280h
291h 292h 293h 294h 295h 296h 297h 298h
29Dh 29Eh 29Fh
2A0h
2F0h
Core Registers
(Table 3-2)
— — — — — — — 316h — 396h — 317h — 397h — — 318h — 398h —
— — —
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
300h
Core Registers
(Table 3-2)
310h 311h 312h 313h 314h 315h
31Dh 31Eh 31Fh
320h
36Fh 3EFh 370h
— 390h — — — — — —
— — — — —
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
380h
391h IOCAP 392h IOCAN 393h 394h 395h
39Bh 39Ch 39Dh 39Eh 39Fh
3A0h
3F0h
Core Registers
(Table 3-2)
IOCAF
Unimplemented
Read as ‘0’
Common RAM
(Accesses 70h – 7Fh)
— — —
— — — — —
PIC12(L)F1571/2
DS40001723B-page 19 Preliminary 2013-2014 Microchip Technology Inc.

TABLE 3-4: PIC12(L)F1572 MEMORY MAP, BANK 0-7

PIC12(L)F1571/2
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta bl e 3 -2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA 00Dh 00Eh 00Fh 010h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h 013h PIR3 093h PIE3 113h 014h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h
06Fh 070h
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
— 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh — —08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh— —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh— —090h—110h—190h—210h—290h
—094h—114h— 194h PMDATH 214h
TMR1L 096h PCON 116h BORCON 196h PMCON2 216h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h T1CON 098h OSCTUNE 118h
T1GCON 099h OSCCON 119h
TMR2 09Ah OSCSTAT 11Ah
PR2 09BhADRESL11Bh
T2CON 09Ch ADRESH 11Ch
— 09Dh ADCON0 11Dh APFCON 19Dh — —
General
Purpose Register 80 Bytes
Common RAM
080h
Core Registers
(Ta bl e 3 -2 )
09Eh ADCON1 11Eh
09Fh ADCON2 11Fh
0A0h
General Purpose Register 80 Bytes
0EFh
0F0h
Accesses 70h – 7Fh
100h
120h
16Fh 1EFh 26Fh 2EFh
170h
Core Registers
(Table 3-2)
— 193h PMDATL 213h
DACCON0 DACCON1
—19Ah —19Bh — 19Ch
— —19Fh
General Purpose Register 80 Bytes
Accesses
70h – 7Fh
180h
198h 199h
19Eh
1A0h
1F0h
Core Registers
(Table 3-2)
—218h RCREG TXREG SPBRG
SPBRGH
RCSTA TXSTA
BAUDCON
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
200h
Core Registers
(Table 3-2)
— — — — — — —
— 219h 21Ah —29Ah—31Ah—39Ah— 21Bh —29Bh—31Bh 21Ch — 29Ch — 31Ch
21Dh 21Eh 21Fh
220h
270h
—299h— 319h — 399h —
—
—
—
Unimplemented
Read as ‘0’
Accesses 70h – 7Fh
280h
291h 292h 293h 294h 295h 296h 297h 298h
29Dh 29Eh 29Fh
2A0h
2F0h
Core Registers
(Table 3-2)
— — — — — — — 316h — 396h — 317h — 397h — — 318h — 398h —
— — —
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
300h
Core Registers
(Table 3-2)
310h 311h 312h 313h 314h 315h
31Dh 31Eh 31Fh
320h
36Fh 3EFh 370h
— 390h — — — — — —
— — — — —
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
380h
391h IOCAP 392h IOCAN 393h 394h 395h
39Bh 39Ch 39Dh 39Eh 39Fh
3A0h
3F0h
Core Registers
(Table 3-2)
IOCAF
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
— — —
— — — — —
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 20

TABLE 3-5: PIC12(L)F1571/2 MEMORY MAP, BANK 8-23

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh
420h
Core Registers
(Ta bl e 3 -2 )
— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh— —48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh— —490h—510h—590h—610h—690h— 710h — 790h — —491h—511h—591h—611h— 691h CWG1DBR 711h — 791h — —492h—512h—592h—612h— 692h CWG1DBF 712h — 792h — —493h—513h—593h—613h— 693h CWG1CON0 713h — 793h — —494h—514h—594h—614h— 694h CWG1CON1 714h — 794h — —495h—515h—595h—615h— 695h CWG1CON2 715h — 795h — —496h—516h—596h—616h—696h— 716h — 796h — —497h—517h—597h—617h—697h— 717h — 797h — —498h—518h—598h—618h—698h— 718h — 798h — —499h—519h—599h—619h—699h— 719h — 799h — —49Ah—51Ah—59Ah—61Ah—69Ah—71Ah—79Ah— —49Bh—51Bh—59Bh—61Bh—69Bh—71Bh—79Bh— — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch — — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh — —49Eh—51Eh—59Eh—61Eh—69Eh—71Eh—79Eh— —49Fh—51Fh—59Fh—61Fh—69Fh—71Fh—79Fh—
480h
48Bh
4A0h
Core Registers
(Ta bl e 3 -2 )
500h
50Bh
520h
Core Registers
(Table 3-2)
580h
58Bh
5A0h
Core Registers
(Table 3-2)
600h
60Bh
620h
Core Registers
(Table 3-2)
680h
68Bh
6A0h
Core Registers
(Table 3-2)
700h
70Bh
720h
Core Registers
(Table 3-2)
780h
78Bh
7A0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h
Accesses 70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
4F0h
Unimplemented
Read as ‘0’
Accesses 70h – 7Fh
570h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
5F0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
670h
Unimplemented
Read as ‘0’
Accesses 70h – 7Fh
6F0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
770h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
7F0h
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
Core Registers
(Ta bl e 3 -2 ) 80Bh 80Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 870h
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Accesses 70h – 7Fh
880h
88Bh 88Ch
8F0h
Core Registers
(Ta bl e 3 -2 )
Unimplemented
Read as ‘0’
Accesses 70h – 7Fh
900h
90Bh 90Ch
970h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
980h
98Bh 98Ch
9EFh
9F0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
A00h
A0Bh A0Ch
A6Fh A70h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses 70h – 7Fh
A80h
A8Bh A8Ch
AEFh AF0h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
B00h
B0Bh B0Ch
B6Fh B70h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
B80h
B8Bh B8Ch
BEFh BF0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
PIC12(L)F1571/2
DS40001723B-page 21 Preliminary 2013-2014 Microchip Technology Inc.
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta bl e 3 -2 )
C80h
C8Bh
Core Registers
(Ta bl e 3 -2 )
D00h
D0Bh
Core Registers
(Ta bl e 3 -2 )
D80h
D8Bh
Core Registers
(Ta bl e 3 -2 )
E00h
E0Bh
Core Registers
(Ta bl e 3 -2 )
E80h
E8Bh
Core Registers
(Ta bl e 3 -2 )
F00h
F0Bh
Core Registers
(Ta bl e 3 -2 )
F80h
F8Bh
Core Registers
(Ta bl e 3 -2 )
C0Ch
—C8Ch—D0Ch—D8Ch
See Tab l e 3- 7 for
register mapping
details
E0Ch
—E8Ch—F0Ch—F8Ch
See Tab l e 3- 8 for register mapping
details
C0Dh —C8Dh—D0Dh—E0Dh—E8Dh—F0Dh— C0Eh
—C8Eh—D0Eh—E0Eh—E8Eh—F0Eh—
C0Fh
—C8Fh—D0Fh—E0Fh—E8Fh—F0Fh—
C10h
—C90h—D10h—E10h—E90h—F10h—
C11h
—C91h—D11h—E11h—E91h—F11h—
C12h
—C92h—D12h—E12h—E92h—F12h—
C13h
—C93h—D13h—E13h—E93h—F13h—
C14h
—C94h—D14h—E14h—E94h—F14h—
C15h
—C95h—D15h—E15h—E95h—F15h—
C16h
—C96h—D16h—E16h—E96h—F16h—
C17h
—C97h—D17h—E17h—E97h—F17h—
C18h
—C98h—D18h—E18h—E98h—F18h—
C19h
—C99h—D19h—E19h—E99h—F19h—
C1Ah
—C9Ah—D1Ah—E1Ah—E9Ah—F1Ah—
C1Bh
—C9Bh—D1Bh—E1Bh—E9Bh—F1Bh—
C1Ch
—C9Ch—D1Ch—E1Ch—E9Ch—F1Ch—
C1Dh
—C9Dh—D1Dh—E1Dh—E9Dh—F1Dh—
C1Eh
—C9Eh—D1Eh—E1Eh—E9Eh—F1Eh—
C1Fh
—C9Fh—D1Fh—E1Fh—E9Fh—F1Fh—
C20h
Unimplemented
Read as ‘0’
CA0h
Unimplemented
Read as ‘0’
D20h
Unimplemented
Read as ‘0’
E20h
Unimplemented
Read as ‘0’
EA0h
Unimplemented
Read as ‘0’
F20h
Unimplemented
Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh C70h
Accesses
70h – 7Fh
CF0h
Accesses 70h – 7Fh
D70h
Accesses
70h – 7Fh
DF0h
Accesses
70h – 7Fh
E70h
Accesses
70h – 7Fh
EF0h
Accesses
70h – 7Fh
F70h
Accesses
70h – 7Fh
FF0h
Accesses
70h – 7Fh
CFFh
CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

TABLE 3-6: PIC12(L)F1571/2 MEMORY MAP, BANK 24-31

PIC12(L)F1571/2
PIC12(L)F1571/2
Bank 31
D8Ch — D8Dh
—
D8Eh
PWMEN
D8Fh
PWMLD
D90h
PWMOUT
D91h
PWM1PHL
D92h
PWM1PHH
D93h
PWM1DCL
D94h
PWM1DCH
D95h
PWM1PRL
D96h
PWM1PRH
D97h
PWM1OFL
D98h
PWM1OFH
D99h
PWM1TMRL
D9Ah
PWM1TMRH
D9Bh
PWM1CON
D9Ch
PWM1IE
D9Dh
PWM1IR
D9Eh
PWM1CLKCON
D9Fh
PWM1LDCON
DA0h
PWM1OFCON
DA1h
PWM2PHL
DA2h
PWM2PHH
DA3h
PWM2DCL
DA4h
PWM2DCH
DA5h
PWM2PRL
DA6h
PWM2PRH
DA7h
PWM2OFL
DA8h
PWM2OFH
DA9h
PWM2TMRL
DAAh
PWM2TMRH
DABh
PWM2CON
DACh
PWM2IE
DADh
PWM2IR
DAEh
PWM2CLKCON
DAFh
PWM2LDCON
DB0h
PWM2OFCON
DB1h
PWM3PHL
DB2h
PWM3PHH
DB3h
PWM3DCL
DB4h
PWM3DCH
DB5h
PWM2PRL
DB6h
PWM3PRH
DB7h
PWM3OFL
DB8h
PWM3OFH
DB9h
PWM3TMRL
DBAh
PWM3TMRH
DBBh
PWM3CON
DBCh
PWM3IE
DBDh
PWM3IR
DBEh
PWM3CLKCON
DBFh
PWM3LDCON
DC0h
PWM3OFCON
DC1h
—
DEFh
Legend: = Unimplemented data memory locations,
read as ‘0’.
Bank 31
F8Ch
FE3h
Unimplemented
Read as ‘0’
FE4h
STATUS_SHAD
FE5h
WREG_SHAD
FE6h
BSR_SHAD
FE7h
PCLATH_SHAD
FE8h
FSR0L_SHAD
FE9h
FSR0H_SHAD
FEAh
FSR1L_SHAD
FEBh
FSR1H_SHAD
FECh
—
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Legend: = Unimplemented data memory locations,
read as ‘0’.
TABLE 3-7: PIC12(L)F1571/2 MEMORY
MAP, BANK 27
TABLE 3-8: PIC12(L)F1571/2 MEMORY
MAP, BANK 31
DS40001723B-page 22 Preliminary 2013-2014 Microchip Technology Inc.
PIC12(L)F1571/2
3.2.6 CORE FUNCTION REGISTERS SUMMARY
The Core Function registers listed in Ta bl e 3 -9 can be addressed from any Bank.

TABLE 3-9: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0-31
x00h or
INDF0
x80h
x01h or
INDF1
x81h
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)
— — —TOPD ZDCC---1 1000 ---q quuu
— — —BSR<4:0>---0 0000 ---0 0000
— Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
Shaded locations are unimplemented, read as ‘0’.
Val ue o n
POR, BOR
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on all
other Resets
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 23
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 24

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Valu e o n
POR, BOR
Bank 0
00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx
00Dh
00Eh
00Fh
010h
011h PIR1 TMR1GIF ADIF RCIF
012h PIR2
013h PIR3
014h
015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON
01Dh
01Eh
01Fh
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— —C1IF — — — — — --0- ---- --0- ----
— PWM3IF PWM2IF PWM1IF — — — — -000 ---- -000 ----
— Unimplemented — —
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
(2)
TXIF
(2)
— —TMR2IFTMR1IF0000 --00 0000 --00
—TMR1ON0000 00-0 uuuu uu-u
DONE
T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
Bank 1
08Ch TRISA — — TRISA5 TRISA4 —
08Dh
08Eh
08Fh
090h
091h PIE1 TMR1GIE ADIE RCIE
092h PIE2
093h PIE3
094h
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only.
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— —C1IE — — — — — --0- ---- --0- ----
— PWM3IE PWM2IE PWM1IE — — — — -000 ---- -000 ----
— Unimplemented — —
2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.
(2)
TXIE
(2)
(2)
— —TMR2IETMR1IE0000 --00 0000 --00
TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Value on
all other
Resets
PIC12(L)F1571/2
DS40001723B-page 25 Preliminary 2013-2014 Microchip Technology Inc.
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
095h
096h PCON STKOVF STKUNF
097h WDTCON
098h OSCTUNE
099h OSCCON SPLLEN IRCF<3:0>
09Ah OSCSTAT
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0
09Eh ADCON1 ADFM ADCS<2:0>
09Fh ADCON2 TRIGSEL<3:0>
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu
— —WDTPS<4:0>SWDTEN--01 0110 --01 0110
— — TUN<5:0> --00 0000 --00 0000
—SCS<1:0>0011 1-00 0011 1-00
— PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS -0q0 0q00 -qqq qqqq
— CHS<4:0>
— —
— — — — 0000 ---- 0000 ----
GO/DONE
ADPREF<1:0>
ADON -000 0000 -000 0000
Valu e o n
POR, BOR
0000 --00 0000 --00
Value on
all other
Resets
PIC12(L)F1571/2
Bank 2
10Ch LATA — —LATA5LATA4 — LATA2 L ATA1 LATA0 --xx -xxx --uu -uuu
10Dh
10Eh
10Fh
110h
111h CM1CON0 C1ON C1OUT C1OE C1POL
112h CM1CON1 C1INTP C1INTN C1PCH<1:0>
113h
114h
115h CMOUT
116h BORCON SBOREN BORFS
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN DACLPS DACOE
119h DACCON1
11A h
11C h
11Dh APFCON RXDTSEL CWGASEL CWGBSEL
11Eh
11Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only.
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— C1SP C1HYS C1SYNC 0000 -100 0000 -100
— C1NCH<2:0> 0000 -000 0000 -000
— Unimplemented — —
— Unimplemented — —
— — — — — — —MC1OUT---- ---0 ---- ---0
— — — — — BORRDY 10-- ---q uu-- ---u
— DACPSS<1:0> — — 000- 00-- 000- 00--
— — — DACR<4:0> ---0 0000 ---0 0000
to
— Unimplemented — —
— T1GSEL TXCKSEL P2SEL P1SEL 000- 0000 000- 0000
— Unimplemented — —
— Unimplemented — —
2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 26
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Valu e o n
POR, BOR
Bank 3
18Ch ANSELA — — —ANSA4— ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
18Dh
18Eh
18Fh
190h
191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH
193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH
195h PMCON1
196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON
198h
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only.
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
(2)
—
Flash Program Memory Address Register High Byte 1000 0000 1000 0000
— — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
(2)
—
(1)
— Unimplemented — —
2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.
——— — — —VREGPMReserved ---- --01 ---- --01
CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Value on
all other
Resets
PIC12(L)F1571/2
DS40001723B-page 27 Preliminary 2013-2014 Microchip Technology Inc.
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 4
20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
20Dh
20Eh
21Fh
— Unimplemented — —
to
— Unimplemented — —
Valu e o n
POR, BOR
Value on
all other
Resets
PIC12(L)F1571/2
Bank 5
28Ch ODCONA — — ODA5 ODA4 — ODA2 ODA1 ODA0 --11 -111 --11 -111
28Dh
to
29Fh
— Unimplemented — —
Bank 6
30Ch SLRCONA — — SLRA5 SLRA4 — SLRA2 ODAA1 ODAA0 --11 -111 --11 -111
30Dh
to
31Fh
— Unimplemented — —
Bank 7
38Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111
38Dh
to
390h
391h IOCAP
392h IOCAN
393h IOCAF
394h
39Fh
— Unimplemented — —
— — IOCAP5 IOCAP4 IOCAP3
— — IOCAN5 IOCAN4 IOCAN3
— — IOCAF5 IOCAF4 IOCAF3
to
— Unimplemented — —
IOCAP2 IOCAP1 IOCAP0
IOCAN2 IOCAN1 IOCAN0
IOCAF2 IOCAF1 IOCAF0
--00 0000 --00 0000
--00 0000 --00 0000
--00 0000 --00 0000
Bank 8
40Ch
to
41Fh
— Unimplemented — —
Bank 9
48Ch
49Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only.
— Unimplemented — —
to
2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 28
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 10
50Ch
51Fh
— Unimplemented — —
to
Bank 11
58Ch
to
59Fh
— Unimplemented — —
Bank 12
60Ch
61Fh
— Unimplemented — —
to
Bank 13
68Ch
to
690h
691h CWG1DBR
692h CWG1DBF
693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA
694h CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0>
695h CWG1CON2 G1ASE G1ARSEN
696h
69Fh
— Unimplemented — —
— —CWG1DBR<5:0>--00 0000 --00 0000
— —CWG1DBF<5:0>--xx xxxx --xx xxxx
— —G1CS00000 0--0 0000 0--0
— G1IS<2:0> 0000 -000 0000 -000
— — — G1ASDC1 G1ASDSFLT — 00-- -00- 00-- -00-
to
— Unimplemented — —
Banks 14-26
x0Ch/ x8Ch — x1Fh/ x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only.
— Unimplemented — —
2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.
Valu e o n
POR, BOR
Value on
all other
Resets
PIC12(L)F1571/2
DS40001723B-page 29 Preliminary 2013-2014 Microchip Technology Inc.
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Valu e o n
POR, BOR
Value on
all other
Resets
PIC12(L)F1571/2
Bank 27
D8Ch — Unimplemented — —
D8Dh
D8Eh PWMEN
D8Fh PWMLD
D90h PWMOUT
D91h PWM1PHL PH<7:0> xxxx xxxx uuuu uuuu
D92h PWM1PHH PH<15:8> xxxx xxxx uuuu uuuu
D93h PWM1DCL DC<7:0> xxxx xxxx uuuu uuuu
D94h PWM1DCH DC<15:8> xxxx xxxx uuuu uuuu
D95h PWM1PRL PR<7:0> xxxx xxxx uuuu uuuu
D96h PWM1PRH PR<15:8> xxxx xxxx uuuu uuuu
D97h PWM1OFL OF<7:0> xxxx xxxx uuuu uuuu
D98h PWM1OFH OF<15:8> xxxx xxxx uuuu uuuu
D99h PWM1TMRL TMR<7:0> xxxx xxxx uuuu uuuu
D9Ah PWM1TMRH TMR<15:8> xxxx xxxx uuuu uuuu
D9Bh PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL PWM1MODE<1:0>
D9Ch PWM1IE
D9Dh PWM1IR
D9Eh PWM1CLKCON
D9Fh PWM1LDCON PWM1LDA PWM1LDT
DA0h PWM1OFCON
DA1h PWM2PHL PH<7:0> xxxx xxxx uuuu uuuu
DA2h PWM2PHH PH<15:8> xxxx xxxx uuuu uuuu
DA3h PWM2DCL DC<7:0> xxxx xxxx uuuu uuuu
DA4h PWM2DCH DC<15:8> xxxx xxxx uuuu uuuu
DA5h PWM2PRL PR<7:0> xxxx xxxx uuuu uuuu
DA6h PWM2PRH PR<15:8> xxxx xxxx uuuu uuuu
DA7h PWM2OFL OF<7:0> xxxx xxxx uuuu uuuu
DA8h PWM2OFH OF<15:8> xxxx xxxx uuuu uuuu
DA9h PWM2TMRL TMR<7:0> xxxx xxxx uuuu uuuu
DAAh PWM2TMRH TMR<15:8> xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only.
— Unimplemented — —
— — — — — PWM3EN_A PWM2EN_A PWM1EN_A ---- -000 ---- -000
— — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A ---- -000 ---- -000
— — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A ---- -000 ---- -000
— — 0000 00-- 0000 00--
— — — — PWM1OFIE PWM1PHIE PWM1DCIE PWM1PRIE ---- 000 ---- 000
— — — — PWM1OFIF PWM1PHIF PWM1DCIF PWM1PRIF ---- 000 ---- 000
— PWM1PS<2:0> — — PWM1CS<1:0> -000 -000 -000 --00
— — — —PWM1LDS<1:0>00-- -000 00-- --00
— PWM1OFM<1:0> PWM1OFO — —PWM1OFS<1:0>-000 -000 -000 --00
2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.
2013-2014 Microchip Technology Inc. Preliminary DS40001723B-page 30
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DABh PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL PWM2MODE<1:0> — — 0000 00-- 0000 00--
DACh PWM2IE
DADh PWM2IR
DAEh PWM2CLKCON
DAFh PWM2LDCON PWM2LDA PWM2LDT
DB0h PWM2OFCON
DB1h PWM3PHL PH<7:0> xxxx xxxx uuuu uuuu
DB2h PWM3PHH PH<15:8> xxxx xxxx uuuu uuuu
DB3h PWM3DCL DC<7:0> xxxx xxxx uuuu uuuu
DB4h PWM3DCH DC<15:8> xxxx xxxx uuuu uuuu
DB5h PWM3PRL PR<7:0> xxxx xxxx uuuu uuuu
DB6h PWM3PRH PR<15:8> xxxx xxxx uuuu uuuu
DB7h PWM3OFL OF<7:0> xxxx xxxx uuuu uuuu
DA8h PWM3OFH OF<15:8> xxxx xxxx uuuu uuuu
DA9h PWM3TMRL TMR<7:0> xxxx xxxx uuuu uuuu
DBAh PWM3TMRH TMR<15:8> xxxx xxxx uuuu uuuu
DBBh PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL PWM3MODE<1:0>
DBCh PWM3IE
DBDh PWM3IR
DBEh PWM3CLKCON
DBFh PWM3LDCON PWM3LDA PWM3LDT
DC0h PWM3OFCON
— — — — PWM2OFIE PWM2PHIE PWM2DCIE PWM2PRIE ---- 000 ---- 000
— — — — PWM2OFIF PWM2PHIF PWM2DCIF PWM2PRIF ---- 000 ---- 000
— PWM2PS<2:0> — — PWM2CS<1:0> -000 -000 -000 --00
— — — —PWM2LDS<1:0>00-- -000 00-- --00
—PWM2OFM<1:0>PWM2OFO— —PWM2OFS<1:0>-000 -000 -000 --00
— — 0000 00-- 0000 00--
— — — — PWM3OFIE PWM3PHIE PWM3DCIE PWM3PRIE ---- 000 ---- 000
— — — — PWM3OFIF PWM3PHIF PWM3DCIF PWM3PRIF ---- 000 ---- 000
— PWM3PS<2:0> — — PWM3CS<1:0> -000 -000 -000 --00
— — — —PWM3LDS<1:0>00-- -000 00-- --00
—PWM3OFM<1:0>PWM3OFO— —PWM3OFS<1:0>-000 -000 -000 --00
Valu e o n
POR, BOR
Bank 28-30
58Ch
59Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only.
— Unimplemented — —
to
2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.
Value on
all other
Resets
PIC12(L)F1571/2
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