Page 1
Features
Master/Slave clock selection in a backplane application
160 MHz operation (typical)
100ps duty cycle distortion (typical)
50ps channel to channel skew (typical)
3.3V power supply design
Glitch-free power on at CLKI/O pins
Low Power design (16mA @ 3.3V static)
Accepts small swing (300mV typical) differential signal levels
Industrial temperature operating range (40°C to +85°C)
Available in 24-pin TSSOP Packaging (L)
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
General Description
PI90LVB16 is a six-channel LVTTL clock distribution driver with 50
picosecond channel-to-channel skew. It translates one BLVDS
(Bus Low-Voltage Differential Signaling) input signal into six LVTTLcompatible output signals for distribution to adjacent chips on the
same board. The PI90LVB16 accepts BLVDS (300mV typical) differential input levels, and translates them to 3V CMOS output levels.
The 160MHz PI90LVB16 can be the master clock, driving inputs of
other clock I/O pins in a multipoint environment. It can also drive
the BLVDS backplane with a separate channel acting as a return/
source LVTTL clock source. The master/slave clock selection of the
driving source is controlled by the CrdCLKIN and the DE pins. An
output enable pin OE, when high, forces all CLK
A backplane clock distribution network must be able to drive many
transmission line stubs. The Bus LVDS feature of the PI90LVB16 is
ideal for driving data transfers in large, high-performance backplane
system applications. The device can be used as a source synchronous driver to distribute clock signals within data and telecommunications systems.
pins high.
OUT
Driver Mode Truth Table
tupnItuptuO
EOEDKLCdrC
NI
+O/IKLCO/IKLCKLC
LL L L H L
LL H H L H
HL L L H H
HL H H L H
HH X Z Z H
Function Diagram
OE
CLKI/0+
CLKI/0–
R
Delay
D
Receive Mode Truth Table
tupnI
TUO
EOEDKLCdrC
NI
HH X X H
LH X DIV ≥ V70.0H
LH X DIV ≤ V70.0L
L = Low Logic State; H = High Logic State; X = Irrelevant
Z = High Impedance
CLK
OUT0
CLK
OUT1
MUX
CLK
OUT5
)O/IKLC()+O/IKLC(KLC
tuptuO
TUO
DE
CrdCLK
IN
1
PS8536A 05/21/01
Page 2
Connection Diagram
GND
V
GNDA
CLKI/0+
CLKI/0–
GNDA
CrdCLK
GND
OE
NC
CCA
NC
DE
1
2
3
4
5
24-Pin
6
7
8
9
IN
10
11
12
L
TSSOP Package Pin Description
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
24
V
CC
23
CLK
OUT0
22
GND
21
CLK
OUT1
20
V
CC
19
CLK
OUT2
18
GND
17
CLK
OUT3
16
V
CC
15
CLK
OUT4
14
GND
13
CLK
OUT5
emaNniP#niPepyTnoitpircseD
+O/IKLC6O/I.tupnikcolclaitnereffidehtfoedis)evitisoP(eurT
O/IKLC7O/I.tupnikcolclaitnereffidehtfoedis)evitageN(yratnemelpmoC
EO2I KLCllasecrofnipsiht,hgiHnehW.woLevitcasinipsiht;EO
KLC
TUO
V
CC
ED11I KLCdraCehtselbanenipsiht,woLnehW.woLevitcasinipsiht;ED
KLCdnasnipO/IKLC
V
CC
KLC
TUO
KLCdrC
NI
V
CC
9I
32,12,91,71,51,31O .stuptuo)SOMC(kcolcdereffuBxiS
42,02,61rewoPVCCVgolanA;
ACC
DNG22,81,41,21,1dnuorGDNG
TUO
,woLnehW.hgiHnip
O/IKLCehttaDIVroNIKLCdrCehtrehtieybdenimretedsietatscigolsnip
otecivedpullupkaewasahnipsihT.nipEDehttalevelcigolehtottcepserhtiwsnip
KLCllaneht,gnitaolfsiEOfI.
TUO
TUO
KLCehtfoetatsehtenimreteddnastupni
TUO
.hgiHeblliwsnip
NI
ehtotlangis
erasnipO/IKLCeht,etatS-3sirevirDehthgiHnehW.
otecivedpullupkaewasahnipsihT.snip
.etatS-3erasnipO/IKLCllaneht,gnitaolfsiEDfI.
.)levelLTTrolevelSOMC(draCmorfkcolctupnI
VmorfetarapesyllanretnI(
CC
VrehtiE.deriuqergnicneuqesrewoplaicepsoN.)seilppusrewop
Vro
ACC
etarapesesuroyllanretxetcennoc,
ebnac
CC
.seilppusrewophtobylppaylsuoenatlumisro,tsrifdeilppa
V
ACC
4rewoPVgolanA
ADNG8,5dnuorG
CN01,3
ACC
VmorfetarapesyllanretnI(
CC
VrehtiE.deriuqergnicneuqesrewoplaicepsoN.)seilppus
Vro
ACC
CC
rewopetarapesesuroyllanretxetcennoc,
deilppaebnac
.seilppusrewophtobylppaylsuoenatlumisro,tsrif
.yllanretxedetcennocebtsumdnuorGmorfetarapesyllanretnI(dnuorGgolanA
.stcennoCoN
2
PS8536A 05/21/01
Page 3
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Absolute Maximum Ratings
Supply Voltage Range, V
CC
(1)
..................................................................................... 0.3V to +4V
Enable Input Voltage (DE, OE, CrdCLKIN) .............................................. 0.3V to +4V
Voltage (CLK
) ............................................................... 0.3V to (VCC + 0.3V)
OUT
Voltage (CLKI/O±) ............................................................... 0.3V to (VCC + 0.3V)
Driver Short Circuit Current ....................................................................... momentary
Receiver Short Circuit Current .................................................................. momentary
Maximum Package Power Dissipation at +25°C
TSSOP Package ................................................................................... 1500mW
Derate TSSOP Package ..................................................... 8.2mW/°C above +25°C
θ
........................................................................................................................................... 95°C/W
JA
θ
........................................................................................................................................... 30°C/W
JC
Storage Temperature Range ............................................................. 65°C to +150°C
Lead Temperature Range (Soldering, 4s) ........................................................... 260°C
ESD Ratings: HBM
CLK
CDM
OUT(05)
(2)
.................................................................................................................................. >1000V
Machine Model
(2)
.................................................................................................................. 9kV
.......................................................................................................................... ≥ 2kV
(2)
............................................................................................................... >200V
Recommended Operating Conditions
Min. Typ. Max Units
Supply Voltage (V
CC)
CrdCLKIN, DE, OE Input Voltage 0 V
Operating Free Air Temperature (TA) 40 24 +85 °C
+3.0 +3.3 +3.6 V
CC
V
3
PS8536A 05/21/01
Page 4
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed
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V
HT
V
LT
RMCV
I
NI
V
R1HO
V
R2HO
V
R1LO
V
R2LO
I
RHDO
I
RLDO
)5(
egnaR
KLC
TUO
hgiHdlohserhTtupnI
woLdlohserhTtupnI 0753
tnerruCtupnI
tnerruCtuptuO
egatloVhgiHtuptuOI,Vm052=DIV
egatloVhgiHtuptuOI,Vm052=DIV
egatloVwoLtuptuO
egatloVwoLtuptuO
cimanyD
)6(
egatloVedoMnommoC
V
NI
I
LO
I
LO
VotVO=
CC
HO
HO
V,Vm052+=DIV
V,Vm052=DIV
kaep-ot-kaepVm052=DIV V
V=ED,
CC
V=EO,
,
CC
Vm05±V2.1=tupnIrehtO
Am0.1=
Am6=V
Vm052=DIV,Am0.1=
Vm052=DIV,Am6=
V=
TUO
TUO
V1
CC
V1=
(3,4)
KLC
5257
Vm
,+O/IKLC
O/IKLC
2/
DI
V
8.2
V
2/
DI
015±01+Aµ
V
2.09.2
CC
6.05.2
CC
V
40.01.0
TUO
022.04.0
614243
Am
41525.73
V
HI
V
LI
I
HI
egatloVhgiHtupnI
egatloVwoLtupnI DNG8.0
V
tnerruChgiHtupnI
V=
NI
CC
V4.2ro
,EO,ED
KLCdrC
NI
0.2V
646
CC
V
ED,EO
LI
I
DRCNI
V
LC
tnerruCwoLtupnI
tnerruCtupnI
V
NI
V
NI
I
pmalCegatloVtupnI
TUO
ylppuSdaoLoN
I
CC
tnerruC
,delbanEstuptuO
deilppADIVoN
KLCdrC
NI
KLC
TUO
ylppuSdaoLoN
tnerruC
1CC
,delbanEstuptuO
nommoCrevoDIV
KLCdrC
NI
KLC
TUO
V4.0roDNG=
VotV0=
CC
V=EO,
CC
Am5.1=,ED,EO
,V0=ED=EO
V=
CC
,DNGro
nepO=)±(O/IKLC
tiucriCnepO=)5:0(
V=ED,DNG=EO
,
CC
V=
CC
,DNGro
)V572.2MCVV521.0(Vm052=DIV
tiucriCnepO=)5:0(
021102+
KLCdrC
NI
KLCdrC
NI
55
8.0V
AµI
01
V
CC
6
AmI
egnaRegatloV
,V0=EO=ED
I
DCC
tnerruC
ylppuSdedaoLrevirD
KLCdrC
V=
NI
CC
R
5.73= Ω +O/IKLCneewteb
L
KLC,O/IKLCdna
,DNGro
TUO
tiucriCnepO=)5:0(
6112
4
PS8536A 05/21/01
Page 5
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
DC Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specifice
lobmySretemaraPsnoitidnoCniP.niM.pyT.xaMstinU
V
∆V
V
∆V
V
V
I
I
I
DO
DO
SO
SO
DHO
DLO
D1SO
D2SO
D3SO
egatloV
VrevirD
DO
egnahC
egnahCedutitluM
)6(
tnerruCtiucriC
laitnereffiDtuptuOrevirD
edutingaM
egatloVtesffOrevirD 1.1 52.15.1V
R
5.73= Ω 5erugiF,
L
V0=ED
egatloVtesffOrevirD
hgiHtuptuOrevirD 4.18.1
woLtuptuOrevirD 8.050.1
trohSlaitnereffiDrevirD
KLCdrC
V=
NI
CC
,DNGro
V0=ED,)rehtegotdetrohsstuptuo(,V0=DOV
KLCdrC
trohSlaitnereffiDrevirD
)6(
VottnerruCtiucriC
CC
NI
KLCdrC
V=
NI
CC
V=+O/IKLC,V0=ED,DNG=
CC
V=O/IKLC,V0=ED,
CC
d
(3,4)
052053054
Vm
202
102Vm
V
,+O/IKLC
O/IKLC
31±71±
1171
Am
0171
KLCdrC
V=
NI
I
D4SO
I
D5SO
I
FFO
tnerruC
trohSlaitnereffiDrevirD
)6(
DNGottnerruCtiucriC
egakaeLffOrewoP
KLCdrC
V
CC
CC
NI
V,nepOroV0=
DEILPPA
+O/IKLC,V0=ED,
V0
=
O/IKLC,V0=ED,DNG=
V0
=
V6.3=02±Aµ
Switching Characteristics
Differential Receiver Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed
lobmySretemaraPsnoitidnoC.niM.pyT
t
RDLHP
t
RDHLP
t
R1KS
t
R2KS
t
R3KS
t
RHLT
t
RLHT
t
REOHLP
t
REOLHP
f
XAM
)01(
noitrotsiDelcyCytuD
,wekseslup LHPtHLPt 5004
egdEemaS;wekSlennahC-ot-lennahC
)21(
wekStraP-ot-traP
)9(
hgiH-ot-woLemiTnoitisnarT
)9(
woL-ot-hgiHemiTnoitisnarT
)51(
ycneuqerFgnitarepOmumixaM
KLC.woLothgiHyaleDnoitagaporPlaitnereffiD
O/I
KLC.hgiHotwoLyaleDnoitagaporPlaitnereffiD
O/I
)11(
)%08ot%02(,0.14.14.2
)%02ot%08(,0.13.14.2
KLCotEO(hgiH-ot-woLyaleDnoitagaporP
)
TUO
KLCotEO(woL-ot-hgiHyaleDnoitagaporP
)0.11.22.3
TUO
KLCot
TUO
KLCot
TUO
C
L
C
L
(7,8)
5171
5171
)1(
.xaMstinU
3.16.28.3
sn
3.16.28.3
Fp51=
Vm052=DIV
508
sp
2&1serugiF
DBT
sn
Fp51=
0.11.22.3
4&3serugiF
001061zHM
5
PS8536A 05/21/01
Page 6
Switching Characteristics
Differential Driver Timing Requuirements
(Over supply voltage and operating temperature ranges, unless otherwise specificed
lobmySretemaraPsnoitidnoC.niM.pyT
(7,8)
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
)1(
.xaMstinU
t
DDLHP
t
DDHLP
t
drCLHP
t
drCHLP
t
D1KS
t
D2KS
t
DHLT
t
DLHT
t
DZHP
t
DZLP
t
DHZP
t
DLZP
f
XAM
KLCdrC
NI
KLCdrC
NI
wekSlaitnereffiD t
KLCot
TUO
KLCot
TUO
)31(
t
HLP
LHP
)41(
wekStraP-ot-traPlaitnereffiD
)9(
emiTnoitisnarTlaitnereffiD
)9(
emiTnoitisnarTlaitnereffiD
)51(
ycneuqerFgnitarepOmumixaM
)%08ot%02(,2.053.056.0
)%02ot%08(,2.053.056.0
KLCdrC.woLothgiHyaleDnoitagaporPlaitnereffiD
otO/IKLC
NI
KLCdrC.hgiHotwoLyaleDnoitagaporPlaitnereffiD
otO/IKLC0.13.12.2
NI
woLothgiHyaleDnoitagaporP
hgiHotwoLyaleDnoitagaporP0.28.25.4
O/IKLCotED.etatS-3otwoLemiTnoitisnarT
O/IKLCotED.etatS-3otwoLemiTnoitisnarT 6.2
O/IKLCotED.hgiH-ot-etatS-3emiTnoitisnarT 3.4
O/IKLCotED.woL-ot-etatS-3emiTnoitisnarT 6.3
C
L
R
L
C
L
C
L
V
C
L
R
L
Fp51=
0.15.12.2
5.73= Ω
7&6serugiF
Fp51=
0.28.25.4
9&8serugiF
006sp
Fp51=
DBT
7&6serugiF
NI
VotV0=
CC
6.2
Fp51=
5.73= Ω
11&01serugiF
001061zHM
Notes:
1. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. These ratings
are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of
device operation.
2. ESD Rating: ESD qualification is performed per the following: HBM (1.5kΩ, 100pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All V
pins connected together, all ground pins connected together.
3. Current into device pins are defined as positive. Current out of device pins defined as negative. All voltages are referenced to ground except
VID, VOD, VTH, and VTL
4. All typicals are given for: VCC = +3.3V and TA = +25°C.
5. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 02V to 2.2VAVID up to VCC-0V may be applied
between the CLKI/O+ and CLKI/O inputs, with the Common Mode set to VCC/2.
6. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
7. CL includes probe and fixture capacitance.
8. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50Ω, tr = 1ns, tf = 1ns (10%90%). To ensure fastest
propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
In general, the faster the input edge rate, the better the AC performance,
9. All device output transition times are based on characterization measurements and are guaranteed by design.
10. t
is the difference in receiver propagation delay t
SKIR
PLH-tPHL
of one device, and is the duty cycle distortion of the output at any given
temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage and temperature.
11. t
is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction.
SK2R
This parameter is guaranteed by design and characterization.
12. t
part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction.
SK3R
This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t
defined as Max-Min differential propagation delay. This parameter is guaranteed by design and characterization.
13. t
14. t
is the difference in driver propagation delay t
SK1D
part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This
SK2D
PLH-tPHL
and is the duty cycle distortion of the CLKI/O outputs.
specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t
SK2D
defined as Max-Min differential propagation delay.
15. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle,
VOL(max) 0.4V, VOH(min) 2.7V, Load - 7pF (stray plus probes).
SK3R
is
CC
is
sn
sn
6
PS8536A 05/21/01
Page 7
Parameter Measurement Information
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
CLKI/0+
Generator
CLKI/0–
50
W
D.U.T .
CLK
OUT
C
L
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
CLKI/0–
CLKI/0+
t
PLHDR
V
= 250mV
ID
t
PHLDR
80% 80%
+1.35V
+1.10V
V
OH
VCC/2 VCC/2
CLK
OUT
t
TLHR
Generator waveform for all test unless otherwise specificed: f = 25MHz, 50% Duty Cycle, Z0 = 50W, t
t
THLR
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
7
20% 20%
V
OL
= 1ns
THL
PS8536A 05/21/01
Page 8
Parameter Measurement Information
Test
Point
Generator
50
W
0.95V
1.2V
0.95V
OE
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Test
Point
–
CLK
+
C
L
OUT
OE
CLK
OUT
S1– = 0.95V
S1+ = 1.2V
CLK
OUT
S1– = 0.95V
S1+ = 1.2V
Figure 3. Output Enable (OE) Test Circuit
50%
t
50%
PHLOER
50%
t
PLHOER
50%
V
0V
V
V
V
CC
OH
OL
OH
Figure 4. Output Enable (OE) Delay Waveforms
8
PS8536A 05/21/01
Page 9
Parameter Measurement Information
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
2V
0.8V
CrdCLK
RL/2 = 18.75
D
R
/2 = 18.75
L
W
V
OS
W
DE
Figure 5. Differential Driver DC Test
C
L
R
DE
D
C
L
IN
Figure 6. Driver Propagation Delay Test Circuit
V
OD
L
50%
CrdCLK
IN
t
PLHCrd
t
PHLCrd
CLKI/0–
0 Differential
CLKI/0+
t
PHLDR
V
DIFF= [CLKI/)+] – [CLKI/)–]
80%
0 Differential
80%
20% 20%
t
TLHDD
t
THLDD
Figure 7. Driver Propagation Delay and Transition Time Waveforms
9
V
V
V
CC
0V
OH
OL
PS8536A 05/21/01
Page 10
Parameter Measurement Information
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
CrdCLK
IN
Generator D.U.T.
C
50
W
Figure 8. CrdCLKIN Propagation Delay Time Test Circuit
V
CC
CLK
CLK
IN
0V
OUT
50%
50%
50%
50%
CLK
OUT
L
V
OH
t
PLHCrd
t
PHLCrd
Figure 9. CrdCLKIN Propagation Delay Time Waveforms
10
V
OL
PS8536A 05/21/01
Page 11
Parameter Measurement Information
V
CC
0V
Generator
Pulse
CrdCLK
IN
DE
Figure 10. Driver 3-State Test Circuit
D
50
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
C
L
C
L
W
RL/2
1.2V
RL/2
DE
CLKI/O+ (CrdCLKIN - L)
CLKI/O– (CrdCLK
CLKI/O+ (CrdCLK
CLKI/O– (CrdCLK
IN
IN
IN
- H)
-H)
- L)
50%
t
PLZD
50% 50%
t
PHZD
50%
Figure 11. Driver 3-State Waveforms
50%
t
PZLD
t
PZhD
V
CC
0V
1.2V
V
OL
V
OH
1.2V
11
PS8536A 05/21/01
Page 12
24-Pin TSSOP (L) Package
24
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
.169
.177
1
.0256
BSC
0.65
.303
.311
7.7
7.9
.007
.012
0.19
0.30
.002
.006
4.3
4.5
.047
1.20
Max
0.05
0.15
X.XX
X.XX
0.45
0.75
.252
BSC
SEATING
PLANE
DENOTES CONTROLLING
DIMENSIONS IN MILLIMETERS
6.4
.018
.030
.004
.008
0.09
0.20
Ordering Information
edoCgniredrOemaNegakcaPepyTegakcaPegnaRgnitarepO
L61BVL09IP42LPOSSTnip-42C°58otC°04
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
12
PS8536A 05/21/01
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